[deliverable/linux.git] / drivers / spi / spi-tegra.c

/*
 * Driver for Nvidia TEGRA spi controller.
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *     Erik Gilling <konkers@android.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/delay.h>

#include <linux/spi/spi.h>

#include <mach/dma.h>

#define SLINK_COMMAND		0x000
#define   SLINK_BIT_LENGTH(x)		(((x) & 0x1f) << 0)
#define   SLINK_WORD_SIZE(x)		(((x) & 0x1f) << 5)
#define   SLINK_BOTH_EN			(1 << 10)
#define   SLINK_CS_SW			(1 << 11)
#define   SLINK_CS_VALUE		(1 << 12)
#define   SLINK_CS_POLARITY		(1 << 13)
#define   SLINK_IDLE_SDA_DRIVE_LOW	(0 << 16)
#define   SLINK_IDLE_SDA_DRIVE_HIGH	(1 << 16)
#define   SLINK_IDLE_SDA_PULL_LOW	(2 << 16)
#define   SLINK_IDLE_SDA_PULL_HIGH	(3 << 16)
#define   SLINK_IDLE_SDA_MASK		(3 << 16)
#define   SLINK_CS_POLARITY1		(1 << 20)
#define   SLINK_CK_SDA			(1 << 21)
#define   SLINK_CS_POLARITY2		(1 << 22)
#define   SLINK_CS_POLARITY3		(1 << 23)
#define   SLINK_IDLE_SCLK_DRIVE_LOW	(0 << 24)
#define   SLINK_IDLE_SCLK_DRIVE_HIGH	(1 << 24)
#define   SLINK_IDLE_SCLK_PULL_LOW	(2 << 24)
#define   SLINK_IDLE_SCLK_PULL_HIGH	(3 << 24)
#define   SLINK_IDLE_SCLK_MASK		(3 << 24)
#define   SLINK_M_S			(1 << 28)
#define   SLINK_WAIT			(1 << 29)
#define   SLINK_GO			(1 << 30)
#define   SLINK_ENB			(1 << 31)

#define SLINK_COMMAND2		0x004
#define   SLINK_LSBFE			(1 << 0)
#define   SLINK_SSOE			(1 << 1)
#define   SLINK_SPIE			(1 << 4)
#define   SLINK_BIDIROE			(1 << 6)
#define   SLINK_MODFEN			(1 << 7)
#define   SLINK_INT_SIZE(x)		(((x) & 0x1f) << 8)
#define   SLINK_CS_ACTIVE_BETWEEN	(1 << 17)
#define   SLINK_SS_EN_CS(x)		(((x) & 0x3) << 18)
#define   SLINK_SS_SETUP(x)		(((x) & 0x3) << 20)
#define   SLINK_FIFO_REFILLS_0		(0 << 22)
#define   SLINK_FIFO_REFILLS_1		(1 << 22)
#define   SLINK_FIFO_REFILLS_2		(2 << 22)
#define   SLINK_FIFO_REFILLS_3		(3 << 22)
#define   SLINK_FIFO_REFILLS_MASK	(3 << 22)
#define   SLINK_WAIT_PACK_INT(x)	(((x) & 0x7) << 26)
#define   SLINK_SPC0			(1 << 29)
#define   SLINK_TXEN			(1 << 30)
#define   SLINK_RXEN			(1 << 31)

#define SLINK_STATUS		0x008
#define   SLINK_COUNT(val)		(((val) >> 0) & 0x1f)
#define   SLINK_WORD(val)		(((val) >> 5) & 0x1f)
#define   SLINK_BLK_CNT(val)		(((val) >> 0) & 0xffff)
#define   SLINK_MODF			(1 << 16)
#define   SLINK_RX_UNF			(1 << 18)
#define   SLINK_TX_OVF			(1 << 19)
#define   SLINK_TX_FULL			(1 << 20)
#define   SLINK_TX_EMPTY		(1 << 21)
#define   SLINK_RX_FULL			(1 << 22)
#define   SLINK_RX_EMPTY		(1 << 23)
#define   SLINK_TX_UNF			(1 << 24)
#define   SLINK_RX_OVF			(1 << 25)
#define   SLINK_TX_FLUSH		(1 << 26)
#define   SLINK_RX_FLUSH		(1 << 27)
#define   SLINK_SCLK			(1 << 28)
#define   SLINK_ERR			(1 << 29)
#define   SLINK_RDY			(1 << 30)
#define   SLINK_BSY			(1 << 31)

#define SLINK_MAS_DATA		0x010
#define SLINK_SLAVE_DATA	0x014

#define SLINK_DMA_CTL		0x018
#define   SLINK_DMA_BLOCK_SIZE(x)	(((x) & 0xffff) << 0)
#define   SLINK_TX_TRIG_1		(0 << 16)
#define   SLINK_TX_TRIG_4		(1 << 16)
#define   SLINK_TX_TRIG_8		(2 << 16)
#define   SLINK_TX_TRIG_16		(3 << 16)
#define   SLINK_TX_TRIG_MASK		(3 << 16)
#define   SLINK_RX_TRIG_1		(0 << 18)
#define   SLINK_RX_TRIG_4		(1 << 18)
#define   SLINK_RX_TRIG_8		(2 << 18)
#define   SLINK_RX_TRIG_16		(3 << 18)
#define   SLINK_RX_TRIG_MASK		(3 << 18)
#define   SLINK_PACKED			(1 << 20)
#define   SLINK_PACK_SIZE_4		(0 << 21)
#define   SLINK_PACK_SIZE_8		(1 << 21)
#define   SLINK_PACK_SIZE_16		(2 << 21)
#define   SLINK_PACK_SIZE_32		(3 << 21)
#define   SLINK_PACK_SIZE_MASK		(3 << 21)
#define   SLINK_IE_TXC			(1 << 26)
#define   SLINK_IE_RXC			(1 << 27)
#define   SLINK_DMA_EN			(1 << 31)

#define SLINK_STATUS2		0x01c
#define   SLINK_TX_FIFO_EMPTY_COUNT(val)	(((val) & 0x3f) >> 0)
#define   SLINK_RX_FIFO_FULL_COUNT(val)		(((val) & 0x3f) >> 16)

#define SLINK_TX_FIFO		0x100
#define SLINK_RX_FIFO		0x180

static const unsigned long spi_tegra_req_sels[] = {
	TEGRA_DMA_REQ_SEL_SL2B1,
	TEGRA_DMA_REQ_SEL_SL2B2,
	TEGRA_DMA_REQ_SEL_SL2B3,
	TEGRA_DMA_REQ_SEL_SL2B4,
};

#define BB_LEN			32

struct spi_tegra_data {
	struct spi_master	*master;
	struct platform_device	*pdev;
	spinlock_t		lock;

	struct clk		*clk;
	void __iomem		*base;
	unsigned long		phys;

	u32			cur_speed;

	struct list_head	queue;
	struct spi_transfer	*cur;
	unsigned		cur_pos;
	unsigned		cur_len;
	unsigned		cur_bytes_per_word;

	/* The tegra spi controller has a bug which causes the first word
	 * in PIO transactions to be garbage.  Since packed DMA transactions
	 * require transfers to be 4 byte aligned we need a bounce buffer
	 * for the generic case.
	 */
	struct tegra_dma_req	rx_dma_req;
	struct tegra_dma_channel *rx_dma;
	u32			*rx_bb;
	dma_addr_t		rx_bb_phys;
};


static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
					    unsigned long reg)
{
	return readl(tspi->base + reg);
}

static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
				    unsigned long val,
				    unsigned long reg)
{
	writel(val, tspi->base + reg);
}

static void spi_tegra_go(struct spi_tegra_data *tspi)
{
	unsigned long val;

	wmb();

	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
	val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
	val |= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1);
	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);

	tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);

	val |= SLINK_DMA_EN;
	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
}

static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
				  struct spi_transfer *t)
{
	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
			   tspi->cur_bytes_per_word);
	u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_pos;
	int i, j;
	unsigned long val;

	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	val &= ~SLINK_WORD_SIZE(~0);
	val |= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
	spi_tegra_writel(tspi, val, SLINK_COMMAND);

	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
		val = 0;
		for (j = 0; j < tspi->cur_bytes_per_word; j++)
			val |= tx_buf[i + j] << j * 8;

		spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
	}

	tspi->rx_dma_req.size = len / tspi->cur_bytes_per_word * 4;

	return len;
}

static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
				  struct spi_transfer *t)
{
	unsigned len = tspi->cur_len;
	u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_pos;
	int i, j;
	unsigned long val;

	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
		val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
		for (j = 0; j < tspi->cur_bytes_per_word; j++)
			rx_buf[i + j] = (val >> (j * 8)) & 0xff;
	}

	return len;
}

static void spi_tegra_start_transfer(struct spi_device *spi,
				    struct spi_transfer *t)
{
	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	u32 speed;
	u8 bits_per_word;
	unsigned long val;

	speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
	bits_per_word = t->bits_per_word ? t->bits_per_word  :
		spi->bits_per_word;

	tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;

	if (speed != tspi->cur_speed)
		clk_set_rate(tspi->clk, speed);

	if (tspi->cur_speed == 0)
		clk_enable(tspi->clk);

	tspi->cur_speed = speed;

	val = spi_tegra_readl(tspi, SLINK_COMMAND2);
	val &= ~SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN;
	if (t->rx_buf)
		val |= SLINK_RXEN;
	if (t->tx_buf)
		val |= SLINK_TXEN;
	val |= SLINK_SS_EN_CS(spi->chip_select);
	val |= SLINK_SPIE;
	spi_tegra_writel(tspi, val, SLINK_COMMAND2);

	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	val &= ~SLINK_BIT_LENGTH(~0);
	val |= SLINK_BIT_LENGTH(bits_per_word - 1);

	/* FIXME: should probably control CS manually so that we can be sure
	 * it does not go low between transfer and to support delay_usecs
	 * correctly.
	 */
	val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;

	if (spi->mode & SPI_CPHA)
		val |= SLINK_CK_SDA;

	if (spi->mode & SPI_CPOL)
		val |= SLINK_IDLE_SCLK_DRIVE_HIGH;
	else
		val |= SLINK_IDLE_SCLK_DRIVE_LOW;

	val |= SLINK_M_S;

	spi_tegra_writel(tspi, val, SLINK_COMMAND);

	spi_tegra_writel(tspi, SLINK_RX_FLUSH | SLINK_TX_FLUSH, SLINK_STATUS);

	tspi->cur = t;
	tspi->cur_pos = 0;
	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);

	spi_tegra_go(tspi);
}

static void spi_tegra_start_message(struct spi_device *spi,
				    struct spi_message *m)
{
	struct spi_transfer *t;

	m->actual_length = 0;
	m->status = 0;

	t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
	spi_tegra_start_transfer(spi, t);
}

static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
{
	struct spi_tegra_data *tspi = req->dev;
	unsigned long flags;
	struct spi_message *m;
	struct spi_device *spi;
	int timeout = 0;
	unsigned long val;

	/* the SPI controller may come back with both the BSY and RDY bits
	 * set.  In this case we need to wait for the BSY bit to clear so
	 * that we are sure the DMA is finished.  1000 reads was empirically
	 * determined to be long enough.
	 */
	while (timeout++ < 1000) {
		if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))
			break;
	}

	spin_lock_irqsave(&tspi->lock, flags);

	val = spi_tegra_readl(tspi, SLINK_STATUS);
	val |= SLINK_RDY;
	spi_tegra_writel(tspi, val, SLINK_STATUS);

	m = list_first_entry(&tspi->queue, struct spi_message, queue);

	if (timeout >= 1000)
		m->status = -EIO;

	spi = m->state;

	tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
	m->actual_length += tspi->cur_pos;

	if (tspi->cur_pos < tspi->cur->len) {
		tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);
		spi_tegra_go(tspi);
	} else if (!list_is_last(&tspi->cur->transfer_list,
				 &m->transfers)) {
		tspi->cur =  list_first_entry(&tspi->cur->transfer_list,
					      struct spi_transfer,
					      transfer_list);
		spi_tegra_start_transfer(spi, tspi->cur);
	} else {
		list_del(&m->queue);

		m->complete(m->context);

		if (!list_empty(&tspi->queue)) {
			m = list_first_entry(&tspi->queue, struct spi_message,
					     queue);
			spi = m->state;
			spi_tegra_start_message(spi, m);
		} else {
			clk_disable(tspi->clk);
			tspi->cur_speed = 0;
		}
	}

	spin_unlock_irqrestore(&tspi->lock, flags);
}

static int spi_tegra_setup(struct spi_device *spi)
{
	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	unsigned long cs_bit;
	unsigned long val;
	unsigned long flags;

	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
		spi->bits_per_word,
		spi->mode & SPI_CPOL ? "" : "~",
		spi->mode & SPI_CPHA ? "" : "~",
		spi->max_speed_hz);


	switch (spi->chip_select) {
	case 0:
		cs_bit = SLINK_CS_POLARITY;
		break;

	case 1:
		cs_bit = SLINK_CS_POLARITY1;
		break;

	case 2:
		cs_bit = SLINK_CS_POLARITY2;
		break;

	case 4:
		cs_bit = SLINK_CS_POLARITY3;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&tspi->lock, flags);

	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	if (spi->mode & SPI_CS_HIGH)
		val |= cs_bit;
	else
		val &= ~cs_bit;
	spi_tegra_writel(tspi, val, SLINK_COMMAND);

	spin_unlock_irqrestore(&tspi->lock, flags);

	return 0;
}

static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m)
{
	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	struct spi_transfer *t;
	unsigned long flags;
	int was_empty;

	if (list_empty(&m->transfers) || !m->complete)
		return -EINVAL;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->bits_per_word < 0 || t->bits_per_word > 32)
			return -EINVAL;

		if (t->len == 0)
			return -EINVAL;

		if (!t->rx_buf && !t->tx_buf)
			return -EINVAL;
	}

	m->state = spi;

	spin_lock_irqsave(&tspi->lock, flags);
	was_empty = list_empty(&tspi->queue);
	list_add_tail(&m->queue, &tspi->queue);

	if (was_empty)
		spi_tegra_start_message(spi, m);

	spin_unlock_irqrestore(&tspi->lock, flags);

	return 0;
}

static int __devinit spi_tegra_probe(struct platform_device *pdev)
{
	struct spi_master	*master;
	struct spi_tegra_data	*tspi;
	struct resource		*r;
	int ret;

	master = spi_alloc_master(&pdev->dev, sizeof *tspi);
	if (master == NULL) {
		dev_err(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;

	master->bus_num = pdev->id;

	master->setup = spi_tegra_setup;
	master->transfer = spi_tegra_transfer;
	master->num_chipselect = 4;

	dev_set_drvdata(&pdev->dev, master);
	tspi = spi_master_get_devdata(master);
	tspi->master = master;
	tspi->pdev = pdev;
	spin_lock_init(&tspi->lock);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENODEV;
		goto err0;
	}

	if (!request_mem_region(r->start, resource_size(r),
				dev_name(&pdev->dev))) {
		ret = -EBUSY;
		goto err0;
	}

	tspi->phys = r->start;
	tspi->base = ioremap(r->start, resource_size(r));
	if (!tspi->base) {
		dev_err(&pdev->dev, "can't ioremap iomem\n");
		ret = -ENOMEM;
		goto err1;
	}

	tspi->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(tspi->clk)) {
		dev_err(&pdev->dev, "can not get clock\n");
		ret = PTR_ERR(tspi->clk);
		goto err2;
	}

	INIT_LIST_HEAD(&tspi->queue);

	tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
	if (!tspi->rx_dma) {
		dev_err(&pdev->dev, "can not allocate rx dma channel\n");
		ret = -ENODEV;
		goto err3;
	}

	tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
					 &tspi->rx_bb_phys, GFP_KERNEL);
	if (!tspi->rx_bb) {
		dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
		ret = -ENOMEM;
		goto err4;
	}

	tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
	tspi->rx_dma_req.to_memory = 1;
	tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
	tspi->rx_dma_req.dest_bus_width = 32;
	tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
	tspi->rx_dma_req.source_bus_width = 32;
	tspi->rx_dma_req.source_wrap = 4;
	tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
	tspi->rx_dma_req.dev = tspi;

	master->dev.of_node = pdev->dev.of_node;
	ret = spi_register_master(master);

	if (ret < 0)
		goto err5;

	return ret;

err5:
	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
			  tspi->rx_bb, tspi->rx_bb_phys);
err4:
	tegra_dma_free_channel(tspi->rx_dma);
err3:
	clk_put(tspi->clk);
err2:
	iounmap(tspi->base);
err1:
	release_mem_region(r->start, resource_size(r));
err0:
	spi_master_put(master);
	return ret;
}

static int __devexit spi_tegra_remove(struct platform_device *pdev)
{
	struct spi_master	*master;
	struct spi_tegra_data	*tspi;
	struct resource		*r;

	master = dev_get_drvdata(&pdev->dev);
	tspi = spi_master_get_devdata(master);

	spi_unregister_master(master);
	tegra_dma_free_channel(tspi->rx_dma);

	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
			  tspi->rx_bb, tspi->rx_bb_phys);

	clk_put(tspi->clk);
	iounmap(tspi->base);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(r->start, resource_size(r));

	return 0;
}

MODULE_ALIAS("platform:spi_tegra");

#ifdef CONFIG_OF
static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {
	{ .compatible = "nvidia,tegra20-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);
#else /* CONFIG_OF */
#define spi_tegra_of_match_table NULL
#endif /* CONFIG_OF */

static struct platform_driver spi_tegra_driver = {
	.driver = {
		.name =		"spi_tegra",
		.owner =	THIS_MODULE,
		.of_match_table = spi_tegra_of_match_table,
	},
	.probe =	spi_tegra_probe,
	.remove =	__devexit_p(spi_tegra_remove),
};
module_platform_driver(spi_tegra_driver);

MODULE_LICENSE("GPL");
Commit	Line	Data
0c03a1dd EG	1	/*
	2	* Driver for Nvidia TEGRA spi controller.
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@android.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
5b7bea9f	21	#include <linux/module.h>
0c03a1dd EG	22	#include <linux/init.h>
	23	#include <linux/err.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/io.h>
	26	#include <linux/dma-mapping.h>
	27	#include <linux/dmapool.h>
	28	#include <linux/clk.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/delay.h>
	31
	32	#include <linux/spi/spi.h>
	33
	34	#include <mach/dma.h>
	35
	36	#define SLINK_COMMAND 0x000
	37	#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
	38	#define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
	39	#define SLINK_BOTH_EN (1 << 10)
	40	#define SLINK_CS_SW (1 << 11)
	41	#define SLINK_CS_VALUE (1 << 12)
	42	#define SLINK_CS_POLARITY (1 << 13)
	43	#define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
	44	#define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
	45	#define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
	46	#define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
	47	#define SLINK_IDLE_SDA_MASK (3 << 16)
	48	#define SLINK_CS_POLARITY1 (1 << 20)
	49	#define SLINK_CK_SDA (1 << 21)
	50	#define SLINK_CS_POLARITY2 (1 << 22)
	51	#define SLINK_CS_POLARITY3 (1 << 23)
	52	#define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
	53	#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
	54	#define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
	55	#define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
	56	#define SLINK_IDLE_SCLK_MASK (3 << 24)
	57	#define SLINK_M_S (1 << 28)
	58	#define SLINK_WAIT (1 << 29)
	59	#define SLINK_GO (1 << 30)
	60	#define SLINK_ENB (1 << 31)
	61
	62	#define SLINK_COMMAND2 0x004
	63	#define SLINK_LSBFE (1 << 0)
	64	#define SLINK_SSOE (1 << 1)
	65	#define SLINK_SPIE (1 << 4)
	66	#define SLINK_BIDIROE (1 << 6)
	67	#define SLINK_MODFEN (1 << 7)
	68	#define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
	69	#define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
	70	#define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
	71	#define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
	72	#define SLINK_FIFO_REFILLS_0 (0 << 22)
	73	#define SLINK_FIFO_REFILLS_1 (1 << 22)
	74	#define SLINK_FIFO_REFILLS_2 (2 << 22)
	75	#define SLINK_FIFO_REFILLS_3 (3 << 22)
	76	#define SLINK_FIFO_REFILLS_MASK (3 << 22)
	77	#define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
	78	#define SLINK_SPC0 (1 << 29)
	79	#define SLINK_TXEN (1 << 30)
	80	#define SLINK_RXEN (1 << 31)
	81
	82	#define SLINK_STATUS 0x008
	83	#define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
	84	#define SLINK_WORD(val) (((val) >> 5) & 0x1f)
	85	#define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
86	#define SLINK_MODF (1 << 16)
87	#define SLINK_RX_UNF (1 << 18)
88	#define SLINK_TX_OVF (1 << 19)
89	#define SLINK_TX_FULL (1 << 20)
90	#define SLINK_TX_EMPTY (1 << 21)
91	#define SLINK_RX_FULL (1 << 22)
92	#define SLINK_RX_EMPTY (1 << 23)
93	#define SLINK_TX_UNF (1 << 24)
94	#define SLINK_RX_OVF (1 << 25)
95	#define SLINK_TX_FLUSH (1 << 26)
96	#define SLINK_RX_FLUSH (1 << 27)
97	#define SLINK_SCLK (1 << 28)
98	#define SLINK_ERR (1 << 29)
99	#define SLINK_RDY (1 << 30)
100	#define SLINK_BSY (1 << 31)
101
102	#define SLINK_MAS_DATA 0x010
103	#define SLINK_SLAVE_DATA 0x014
104
105	#define SLINK_DMA_CTL 0x018
106	#define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
107	#define SLINK_TX_TRIG_1 (0 << 16)
108	#define SLINK_TX_TRIG_4 (1 << 16)
109	#define SLINK_TX_TRIG_8 (2 << 16)
110	#define SLINK_TX_TRIG_16 (3 << 16)
111	#define SLINK_TX_TRIG_MASK (3 << 16)
112	#define SLINK_RX_TRIG_1 (0 << 18)
113	#define SLINK_RX_TRIG_4 (1 << 18)
114	#define SLINK_RX_TRIG_8 (2 << 18)
115	#define SLINK_RX_TRIG_16 (3 << 18)
116	#define SLINK_RX_TRIG_MASK (3 << 18)
117	#define SLINK_PACKED (1 << 20)
118	#define SLINK_PACK_SIZE_4 (0 << 21)
119	#define SLINK_PACK_SIZE_8 (1 << 21)
120	#define SLINK_PACK_SIZE_16 (2 << 21)
121	#define SLINK_PACK_SIZE_32 (3 << 21)
122	#define SLINK_PACK_SIZE_MASK (3 << 21)
123	#define SLINK_IE_TXC (1 << 26)
124	#define SLINK_IE_RXC (1 << 27)
125	#define SLINK_DMA_EN (1 << 31)
126
127	#define SLINK_STATUS2 0x01c
128	#define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
129	#define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f) >> 16)
130
131	#define SLINK_TX_FIFO 0x100
132	#define SLINK_RX_FIFO 0x180
133
134	static const unsigned long spi_tegra_req_sels[] = {
135	TEGRA_DMA_REQ_SEL_SL2B1,
136	TEGRA_DMA_REQ_SEL_SL2B2,
137	TEGRA_DMA_REQ_SEL_SL2B3,
138	TEGRA_DMA_REQ_SEL_SL2B4,
139	};
140
141	#define BB_LEN 32
142
143	struct spi_tegra_data {
144	struct spi_master *master;
145	struct platform_device *pdev;
146	spinlock_t lock;
147
148	struct clk *clk;
149	void __iomem *base;
150	unsigned long phys;
151
152	u32 cur_speed;
153
154	struct list_head queue;
155	struct spi_transfer *cur;
156	unsigned cur_pos;
157	unsigned cur_len;
158	unsigned cur_bytes_per_word;
159
160	/* The tegra spi controller has a bug which causes the first word
161	* in PIO transactions to be garbage. Since packed DMA transactions
162	* require transfers to be 4 byte aligned we need a bounce buffer
163	* for the generic case.
164	*/
165	struct tegra_dma_req rx_dma_req;
166	struct tegra_dma_channel *rx_dma;
167	u32 *rx_bb;
168	dma_addr_t rx_bb_phys;
169	};
170
171
172	static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
173	unsigned long reg)
174	{
175	return readl(tspi->base + reg);
176	}
177
178	static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
179	unsigned long val,
180	unsigned long reg)
181	{
182	writel(val, tspi->base + reg);
183	}
184
185	static void spi_tegra_go(struct spi_tegra_data *tspi)
186	{
187	unsigned long val;
188
189	wmb();
190
191	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
192	val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
193	val \|= SLINK_DMA_BLOCK_SIZE(tspi->rx_dma_req.size / 4 - 1);
194	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
195
196	tegra_dma_enqueue_req(tspi->rx_dma, &tspi->rx_dma_req);
197
198	val \|= SLINK_DMA_EN;
199	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
200	}
201
202	static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
203	struct spi_transfer *t)
204	{
205	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
206	tspi->cur_bytes_per_word);
207	u8 tx_buf = (u8 )t->tx_buf + tspi->cur_pos;
208	int i, j;
209	unsigned long val;
210
211	val = spi_tegra_readl(tspi, SLINK_COMMAND);
212	val &= ~SLINK_WORD_SIZE(~0);
213	val \|= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
214	spi_tegra_writel(tspi, val, SLINK_COMMAND);
215
216	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
217	val = 0;
218	for (j = 0; j < tspi->cur_bytes_per_word; j++)
219	val \|= tx_buf[i + j] << j * 8;
220
221	spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
222	}
223
224	tspi->rx_dma_req.size = len / tspi->cur_bytes_per_word * 4;
225
226	return len;
227	}
228
229	static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
230	struct spi_transfer *t)
231	{
232	unsigned len = tspi->cur_len;
233	u8 rx_buf = (u8 )t->rx_buf + tspi->cur_pos;
234	int i, j;
235	unsigned long val;
236
237	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
238	val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
239	for (j = 0; j < tspi->cur_bytes_per_word; j++)
240	rx_buf[i + j] = (val >> (j * 8)) & 0xff;
241	}
242
243	return len;
244	}
245
246	static void spi_tegra_start_transfer(struct spi_device *spi,
247	struct spi_transfer *t)
248	{
249	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
250	u32 speed;
251	u8 bits_per_word;
252	unsigned long val;
253
254	speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
255	bits_per_word = t->bits_per_word ? t->bits_per_word :
256	spi->bits_per_word;
257
258	tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;
259
260	if (speed != tspi->cur_speed)
261	clk_set_rate(tspi->clk, speed);
262
263	if (tspi->cur_speed == 0)
264	clk_enable(tspi->clk);
265
266	tspi->cur_speed = speed;
267
268	val = spi_tegra_readl(tspi, SLINK_COMMAND2);
269	val &= ~SLINK_SS_EN_CS(~0) \| SLINK_RXEN \| SLINK_TXEN;
270	if (t->rx_buf)
271	val \|= SLINK_RXEN;
272	if (t->tx_buf)
273	val \|= SLINK_TXEN;
274	val \|= SLINK_SS_EN_CS(spi->chip_select);
275	val \|= SLINK_SPIE;
276	spi_tegra_writel(tspi, val, SLINK_COMMAND2);
277
278	val = spi_tegra_readl(tspi, SLINK_COMMAND);
279	val &= ~SLINK_BIT_LENGTH(~0);
280	val \|= SLINK_BIT_LENGTH(bits_per_word - 1);
281
282	/* FIXME: should probably control CS manually so that we can be sure
283	* it does not go low between transfer and to support delay_usecs
284	* correctly.
285	*/
286	val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;
287
288	if (spi->mode & SPI_CPHA)
289	val \|= SLINK_CK_SDA;
290
291	if (spi->mode & SPI_CPOL)
292	val \|= SLINK_IDLE_SCLK_DRIVE_HIGH;
293	else
294	val \|= SLINK_IDLE_SCLK_DRIVE_LOW;
295
296	val \|= SLINK_M_S;
297
298	spi_tegra_writel(tspi, val, SLINK_COMMAND);
299
300	spi_tegra_writel(tspi, SLINK_RX_FLUSH \| SLINK_TX_FLUSH, SLINK_STATUS);
301
302	tspi->cur = t;
303	tspi->cur_pos = 0;
304	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);
305
306	spi_tegra_go(tspi);
307	}
308
309	static void spi_tegra_start_message(struct spi_device *spi,
310	struct spi_message *m)
311	{
312	struct spi_transfer *t;
313
314	m->actual_length = 0;
315	m->status = 0;
316
317	t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
318	spi_tegra_start_transfer(spi, t);
319	}
320
321	static void tegra_spi_rx_dma_complete(struct tegra_dma_req *req)
322	{
323	struct spi_tegra_data *tspi = req->dev;
324	unsigned long flags;
325	struct spi_message *m;
326	struct spi_device *spi;
327	int timeout = 0;
328	unsigned long val;
329
330	/* the SPI controller may come back with both the BSY and RDY bits
331	* set. In this case we need to wait for the BSY bit to clear so
332	* that we are sure the DMA is finished. 1000 reads was empirically
333	* determined to be long enough.
334	*/
335	while (timeout++ < 1000) {
336	if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))
337	break;
338	}
339
340	spin_lock_irqsave(&tspi->lock, flags);
341
0c03a1dd EG	342	val = spi_tegra_readl(tspi, SLINK_STATUS);
	343	val \|= SLINK_RDY;
	344	spi_tegra_writel(tspi, val, SLINK_STATUS);
	345
0c03a1dd	346	m = list_first_entry(&tspi->queue, struct spi_message, queue);
f41649e0 EG	347
	348	if (timeout >= 1000)
	349	m->status = -EIO;
	350
0c03a1dd EG	351	spi = m->state;
	352
	353	tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
	354	m->actual_length += tspi->cur_pos;
	355
	356	if (tspi->cur_pos < tspi->cur->len) {
	357	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);
	358	spi_tegra_go(tspi);
	359	} else if (!list_is_last(&tspi->cur->transfer_list,
	360	&m->transfers)) {
	361	tspi->cur = list_first_entry(&tspi->cur->transfer_list,
	362	struct spi_transfer,
	363	transfer_list);
	364	spi_tegra_start_transfer(spi, tspi->cur);
	365	} else {
	366	list_del(&m->queue);
	367
	368	m->complete(m->context);
	369
	370	if (!list_empty(&tspi->queue)) {
	371	m = list_first_entry(&tspi->queue, struct spi_message,
	372	queue);
	373	spi = m->state;
	374	spi_tegra_start_message(spi, m);
	375	} else {
	376	clk_disable(tspi->clk);
	377	tspi->cur_speed = 0;
	378	}
	379	}
	380
	381	spin_unlock_irqrestore(&tspi->lock, flags);
	382	}
	383
	384	static int spi_tegra_setup(struct spi_device *spi)
	385	{
	386	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	387	unsigned long cs_bit;
	388	unsigned long val;
	389	unsigned long flags;
	390
	391	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
	392	spi->bits_per_word,
	393	spi->mode & SPI_CPOL ? "" : "~",
	394	spi->mode & SPI_CPHA ? "" : "~",
	395	spi->max_speed_hz);
	396
	397
	398	switch (spi->chip_select) {
	399	case 0:
	400	cs_bit = SLINK_CS_POLARITY;
	401	break;
	402
	403	case 1:
	404	cs_bit = SLINK_CS_POLARITY1;
	405	break;
	406
	407	case 2:
	408	cs_bit = SLINK_CS_POLARITY2;
	409	break;
	410
	411	case 4:
	412	cs_bit = SLINK_CS_POLARITY3;
	413	break;
	414
415	default:
416	return -EINVAL;
417	}
418
419	spin_lock_irqsave(&tspi->lock, flags);
420
421	val = spi_tegra_readl(tspi, SLINK_COMMAND);
422	if (spi->mode & SPI_CS_HIGH)
423	val \|= cs_bit;
424	else
425	val &= ~cs_bit;
426	spi_tegra_writel(tspi, val, SLINK_COMMAND);
427
428	spin_unlock_irqrestore(&tspi->lock, flags);
429
430	return 0;
431	}
432
433	static int spi_tegra_transfer(struct spi_device spi, struct spi_message m)
434	{
435	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
436	struct spi_transfer *t;
437	unsigned long flags;
438	int was_empty;
439
440	if (list_empty(&m->transfers) \|\| !m->complete)
441	return -EINVAL;
442
443	list_for_each_entry(t, &m->transfers, transfer_list) {
444	if (t->bits_per_word < 0 \|\| t->bits_per_word > 32)
445	return -EINVAL;
446
447	if (t->len == 0)
448	return -EINVAL;
449
450	if (!t->rx_buf && !t->tx_buf)
451	return -EINVAL;
452	}
453
454	m->state = spi;
455
456	spin_lock_irqsave(&tspi->lock, flags);
457	was_empty = list_empty(&tspi->queue);
458	list_add_tail(&m->queue, &tspi->queue);
459
460	if (was_empty)
461	spi_tegra_start_message(spi, m);
462
463	spin_unlock_irqrestore(&tspi->lock, flags);
464
465	return 0;
466	}
467
940ab889	468	static int __devinit spi_tegra_probe(struct platform_device *pdev)
0c03a1dd EG	469	{
	470	struct spi_master *master;
	471	struct spi_tegra_data *tspi;
	472	struct resource *r;
	473	int ret;
	474
	475	master = spi_alloc_master(&pdev->dev, sizeof *tspi);
	476	if (master == NULL) {
	477	dev_err(&pdev->dev, "master allocation failed\n");
	478	return -ENOMEM;
	479	}
	480
	481	/* the spi->mode bits understood by this driver: */
	482	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
	483
	484	master->bus_num = pdev->id;
	485
	486	master->setup = spi_tegra_setup;
	487	master->transfer = spi_tegra_transfer;
	488	master->num_chipselect = 4;
	489
	490	dev_set_drvdata(&pdev->dev, master);
	491	tspi = spi_master_get_devdata(master);
	492	tspi->master = master;
	493	tspi->pdev = pdev;
	494	spin_lock_init(&tspi->lock);
	495
	496	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	497	if (r == NULL) {
	498	ret = -ENODEV;
	499	goto err0;
	500	}
	501
8e2943c0	502	if (!request_mem_region(r->start, resource_size(r),
0c03a1dd EG	503	dev_name(&pdev->dev))) {
	504	ret = -EBUSY;
	505	goto err0;
	506	}
	507
	508	tspi->phys = r->start;
8e2943c0	509	tspi->base = ioremap(r->start, resource_size(r));
0c03a1dd EG	510	if (!tspi->base) {
	511	dev_err(&pdev->dev, "can't ioremap iomem\n");
	512	ret = -ENOMEM;
	513	goto err1;
	514	}
	515
	516	tspi->clk = clk_get(&pdev->dev, NULL);
76d9cc45	517	if (IS_ERR(tspi->clk)) {
0c03a1dd EG	518	dev_err(&pdev->dev, "can not get clock\n");
	519	ret = PTR_ERR(tspi->clk);
	520	goto err2;
	521	}
	522
	523	INIT_LIST_HEAD(&tspi->queue);
	524
	525	tspi->rx_dma = tegra_dma_allocate_channel(TEGRA_DMA_MODE_ONESHOT);
	526	if (!tspi->rx_dma) {
	527	dev_err(&pdev->dev, "can not allocate rx dma channel\n");
	528	ret = -ENODEV;
	529	goto err3;
	530	}
	531
	532	tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
	533	&tspi->rx_bb_phys, GFP_KERNEL);
	534	if (!tspi->rx_bb) {
	535	dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
	536	ret = -ENOMEM;
	537	goto err4;
	538	}
	539
	540	tspi->rx_dma_req.complete = tegra_spi_rx_dma_complete;
	541	tspi->rx_dma_req.to_memory = 1;
	542	tspi->rx_dma_req.dest_addr = tspi->rx_bb_phys;
	543	tspi->rx_dma_req.dest_bus_width = 32;
	544	tspi->rx_dma_req.source_addr = tspi->phys + SLINK_RX_FIFO;
	545	tspi->rx_dma_req.source_bus_width = 32;
	546	tspi->rx_dma_req.source_wrap = 4;
	547	tspi->rx_dma_req.req_sel = spi_tegra_req_sels[pdev->id];
	548	tspi->rx_dma_req.dev = tspi;
	549
e892bac1	550	master->dev.of_node = pdev->dev.of_node;
0c03a1dd EG	551	ret = spi_register_master(master);
	552
	553	if (ret < 0)
	554	goto err5;
	555
	556	return ret;
	557
	558	err5:
	559	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
	560	tspi->rx_bb, tspi->rx_bb_phys);
	561	err4:
	562	tegra_dma_free_channel(tspi->rx_dma);
	563	err3:
	564	clk_put(tspi->clk);
	565	err2:
	566	iounmap(tspi->base);
	567	err1:
8e2943c0	568	release_mem_region(r->start, resource_size(r));
0c03a1dd EG	569	err0:
	570	spi_master_put(master);
	571	return ret;
	572	}
	573
	574	static int __devexit spi_tegra_remove(struct platform_device *pdev)
	575	{
	576	struct spi_master *master;
	577	struct spi_tegra_data *tspi;
	578	struct resource *r;
	579
	580	master = dev_get_drvdata(&pdev->dev);
	581	tspi = spi_master_get_devdata(master);
	582
8901e1b9	583	spi_unregister_master(master);
0c03a1dd EG	584	tegra_dma_free_channel(tspi->rx_dma);
	585
	586	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
	587	tspi->rx_bb, tspi->rx_bb_phys);
	588
	589	clk_put(tspi->clk);
	590	iounmap(tspi->base);
	591
0c03a1dd	592	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8e2943c0	593	release_mem_region(r->start, resource_size(r));
0c03a1dd EG	594
	595	return 0;
	596	}
	597
	598	MODULE_ALIAS("platform:spi_tegra");
	599
e892bac1 GL	600	#ifdef CONFIG_OF
e892bac1 GL	601	static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {
22032c77	602	{ .compatible = "nvidia,tegra20-spi", },
e892bac1 GL	603	{}
	604	};
	605	MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);
	606	#else /* CONFIG_OF */
	607	#define spi_tegra_of_match_table NULL
	608	#endif /* CONFIG_OF */
	609
0c03a1dd EG	610	static struct platform_driver spi_tegra_driver = {
	611	.driver = {
	612	.name = "spi_tegra",
	613	.owner = THIS_MODULE,
e892bac1	614	.of_match_table = spi_tegra_of_match_table,
0c03a1dd	615	},
940ab889	616	.probe = spi_tegra_probe,
0c03a1dd EG	617	.remove = __devexit_p(spi_tegra_remove),
0c03a1dd EG	618	};
940ab889	619	module_platform_driver(spi_tegra_driver);
0c03a1dd EG	620
0c03a1dd EG	621	MODULE_LICENSE("GPL");