[deliverable/linux.git] / drivers / spi / spi-tegra.c

/*
 * Driver for Nvidia TEGRA spi controller.
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *     Erik Gilling <konkers@android.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/err.h>
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/dmapool.h>
#include <linux/clk.h>
#include <linux/interrupt.h>
#include <linux/delay.h>

#include <linux/spi/spi.h>
#include <linux/dmaengine.h>

#include <mach/dma.h>

#define SLINK_COMMAND		0x000
#define   SLINK_BIT_LENGTH(x)		(((x) & 0x1f) << 0)
#define   SLINK_WORD_SIZE(x)		(((x) & 0x1f) << 5)
#define   SLINK_BOTH_EN			(1 << 10)
#define   SLINK_CS_SW			(1 << 11)
#define   SLINK_CS_VALUE		(1 << 12)
#define   SLINK_CS_POLARITY		(1 << 13)
#define   SLINK_IDLE_SDA_DRIVE_LOW	(0 << 16)
#define   SLINK_IDLE_SDA_DRIVE_HIGH	(1 << 16)
#define   SLINK_IDLE_SDA_PULL_LOW	(2 << 16)
#define   SLINK_IDLE_SDA_PULL_HIGH	(3 << 16)
#define   SLINK_IDLE_SDA_MASK		(3 << 16)
#define   SLINK_CS_POLARITY1		(1 << 20)
#define   SLINK_CK_SDA			(1 << 21)
#define   SLINK_CS_POLARITY2		(1 << 22)
#define   SLINK_CS_POLARITY3		(1 << 23)
#define   SLINK_IDLE_SCLK_DRIVE_LOW	(0 << 24)
#define   SLINK_IDLE_SCLK_DRIVE_HIGH	(1 << 24)
#define   SLINK_IDLE_SCLK_PULL_LOW	(2 << 24)
#define   SLINK_IDLE_SCLK_PULL_HIGH	(3 << 24)
#define   SLINK_IDLE_SCLK_MASK		(3 << 24)
#define   SLINK_M_S			(1 << 28)
#define   SLINK_WAIT			(1 << 29)
#define   SLINK_GO			(1 << 30)
#define   SLINK_ENB			(1 << 31)

#define SLINK_COMMAND2		0x004
#define   SLINK_LSBFE			(1 << 0)
#define   SLINK_SSOE			(1 << 1)
#define   SLINK_SPIE			(1 << 4)
#define   SLINK_BIDIROE			(1 << 6)
#define   SLINK_MODFEN			(1 << 7)
#define   SLINK_INT_SIZE(x)		(((x) & 0x1f) << 8)
#define   SLINK_CS_ACTIVE_BETWEEN	(1 << 17)
#define   SLINK_SS_EN_CS(x)		(((x) & 0x3) << 18)
#define   SLINK_SS_SETUP(x)		(((x) & 0x3) << 20)
#define   SLINK_FIFO_REFILLS_0		(0 << 22)
#define   SLINK_FIFO_REFILLS_1		(1 << 22)
#define   SLINK_FIFO_REFILLS_2		(2 << 22)
#define   SLINK_FIFO_REFILLS_3		(3 << 22)
#define   SLINK_FIFO_REFILLS_MASK	(3 << 22)
#define   SLINK_WAIT_PACK_INT(x)	(((x) & 0x7) << 26)
#define   SLINK_SPC0			(1 << 29)
#define   SLINK_TXEN			(1 << 30)
#define   SLINK_RXEN			(1 << 31)

#define SLINK_STATUS		0x008
#define   SLINK_COUNT(val)		(((val) >> 0) & 0x1f)
#define   SLINK_WORD(val)		(((val) >> 5) & 0x1f)
#define   SLINK_BLK_CNT(val)		(((val) >> 0) & 0xffff)
#define   SLINK_MODF			(1 << 16)
#define   SLINK_RX_UNF			(1 << 18)
#define   SLINK_TX_OVF			(1 << 19)
#define   SLINK_TX_FULL			(1 << 20)
#define   SLINK_TX_EMPTY		(1 << 21)
#define   SLINK_RX_FULL			(1 << 22)
#define   SLINK_RX_EMPTY		(1 << 23)
#define   SLINK_TX_UNF			(1 << 24)
#define   SLINK_RX_OVF			(1 << 25)
#define   SLINK_TX_FLUSH		(1 << 26)
#define   SLINK_RX_FLUSH		(1 << 27)
#define   SLINK_SCLK			(1 << 28)
#define   SLINK_ERR			(1 << 29)
#define   SLINK_RDY			(1 << 30)
#define   SLINK_BSY			(1 << 31)

#define SLINK_MAS_DATA		0x010
#define SLINK_SLAVE_DATA	0x014

#define SLINK_DMA_CTL		0x018
#define   SLINK_DMA_BLOCK_SIZE(x)	(((x) & 0xffff) << 0)
#define   SLINK_TX_TRIG_1		(0 << 16)
#define   SLINK_TX_TRIG_4		(1 << 16)
#define   SLINK_TX_TRIG_8		(2 << 16)
#define   SLINK_TX_TRIG_16		(3 << 16)
#define   SLINK_TX_TRIG_MASK		(3 << 16)
#define   SLINK_RX_TRIG_1		(0 << 18)
#define   SLINK_RX_TRIG_4		(1 << 18)
#define   SLINK_RX_TRIG_8		(2 << 18)
#define   SLINK_RX_TRIG_16		(3 << 18)
#define   SLINK_RX_TRIG_MASK		(3 << 18)
#define   SLINK_PACKED			(1 << 20)
#define   SLINK_PACK_SIZE_4		(0 << 21)
#define   SLINK_PACK_SIZE_8		(1 << 21)
#define   SLINK_PACK_SIZE_16		(2 << 21)
#define   SLINK_PACK_SIZE_32		(3 << 21)
#define   SLINK_PACK_SIZE_MASK		(3 << 21)
#define   SLINK_IE_TXC			(1 << 26)
#define   SLINK_IE_RXC			(1 << 27)
#define   SLINK_DMA_EN			(1 << 31)

#define SLINK_STATUS2		0x01c
#define   SLINK_TX_FIFO_EMPTY_COUNT(val)	(((val) & 0x3f) >> 0)
#define   SLINK_RX_FIFO_FULL_COUNT(val)		(((val) & 0x3f) >> 16)

#define SLINK_TX_FIFO		0x100
#define SLINK_RX_FIFO		0x180

static const unsigned long spi_tegra_req_sels[] = {
	TEGRA_DMA_REQ_SEL_SL2B1,
	TEGRA_DMA_REQ_SEL_SL2B2,
	TEGRA_DMA_REQ_SEL_SL2B3,
	TEGRA_DMA_REQ_SEL_SL2B4,
};

#define BB_LEN			32

struct spi_tegra_data {
	struct spi_master	*master;
	struct platform_device	*pdev;
	spinlock_t		lock;

	struct clk		*clk;
	void __iomem		*base;
	unsigned long		phys;

	u32			cur_speed;

	struct list_head	queue;
	struct spi_transfer	*cur;
	unsigned		cur_pos;
	unsigned		cur_len;
	unsigned		cur_bytes_per_word;

	/* The tegra spi controller has a bug which causes the first word
	 * in PIO transactions to be garbage.  Since packed DMA transactions
	 * require transfers to be 4 byte aligned we need a bounce buffer
	 * for the generic case.
	 */
	int			dma_req_len;
	struct dma_chan		*rx_dma;
	struct dma_slave_config	sconfig;
	struct dma_async_tx_descriptor	*rx_dma_desc;
	dma_cookie_t		rx_cookie;
	u32			*rx_bb;
	dma_addr_t		rx_bb_phys;
};

static void tegra_spi_rx_dma_complete(void *args);
static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
					    unsigned long reg)
{
	return readl(tspi->base + reg);
}

static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
				    unsigned long val,
				    unsigned long reg)
{
	writel(val, tspi->base + reg);
}

static void spi_tegra_go(struct spi_tegra_data *tspi)
{
	unsigned long val;

	wmb();

	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
	val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
	val |= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
	tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
				tspi->rx_bb_phys, tspi->dma_req_len,
				DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
	if (!tspi->rx_dma_desc) {
		dev_err(&tspi->pdev->dev, "dmaengine slave prep failed\n");
		return;
	}
	tspi->rx_dma_desc->callback = tegra_spi_rx_dma_complete;
	tspi->rx_dma_desc->callback_param = tspi;
	tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
	dma_async_issue_pending(tspi->rx_dma);

	val |= SLINK_DMA_EN;
	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
}

static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
				  struct spi_transfer *t)
{
	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
			   tspi->cur_bytes_per_word);
	u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_pos;
	int i, j;
	unsigned long val;

	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	val &= ~SLINK_WORD_SIZE(~0);
	val |= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
	spi_tegra_writel(tspi, val, SLINK_COMMAND);

	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
		val = 0;
		for (j = 0; j < tspi->cur_bytes_per_word; j++)
			val |= tx_buf[i + j] << j * 8;

		spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
	}

	tspi->dma_req_len = len / tspi->cur_bytes_per_word * 4;

	return len;
}

static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
				  struct spi_transfer *t)
{
	unsigned len = tspi->cur_len;
	u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_pos;
	int i, j;
	unsigned long val;

	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
		val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
		for (j = 0; j < tspi->cur_bytes_per_word; j++)
			rx_buf[i + j] = (val >> (j * 8)) & 0xff;
	}

	return len;
}

static void spi_tegra_start_transfer(struct spi_device *spi,
				    struct spi_transfer *t)
{
	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	u32 speed;
	u8 bits_per_word;
	unsigned long val;

	speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
	bits_per_word = t->bits_per_word ? t->bits_per_word  :
		spi->bits_per_word;

	tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;

	if (speed != tspi->cur_speed)
		clk_set_rate(tspi->clk, speed);

	if (tspi->cur_speed == 0)
		clk_prepare_enable(tspi->clk);

	tspi->cur_speed = speed;

	val = spi_tegra_readl(tspi, SLINK_COMMAND2);
	val &= ~SLINK_SS_EN_CS(~0) | SLINK_RXEN | SLINK_TXEN;
	if (t->rx_buf)
		val |= SLINK_RXEN;
	if (t->tx_buf)
		val |= SLINK_TXEN;
	val |= SLINK_SS_EN_CS(spi->chip_select);
	val |= SLINK_SPIE;
	spi_tegra_writel(tspi, val, SLINK_COMMAND2);

	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	val &= ~SLINK_BIT_LENGTH(~0);
	val |= SLINK_BIT_LENGTH(bits_per_word - 1);

	/* FIXME: should probably control CS manually so that we can be sure
	 * it does not go low between transfer and to support delay_usecs
	 * correctly.
	 */
	val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;

	if (spi->mode & SPI_CPHA)
		val |= SLINK_CK_SDA;

	if (spi->mode & SPI_CPOL)
		val |= SLINK_IDLE_SCLK_DRIVE_HIGH;
	else
		val |= SLINK_IDLE_SCLK_DRIVE_LOW;

	val |= SLINK_M_S;

	spi_tegra_writel(tspi, val, SLINK_COMMAND);

	spi_tegra_writel(tspi, SLINK_RX_FLUSH | SLINK_TX_FLUSH, SLINK_STATUS);

	tspi->cur = t;
	tspi->cur_pos = 0;
	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);

	spi_tegra_go(tspi);
}

static void spi_tegra_start_message(struct spi_device *spi,
				    struct spi_message *m)
{
	struct spi_transfer *t;

	m->actual_length = 0;
	m->status = 0;

	t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
	spi_tegra_start_transfer(spi, t);
}

static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
{
	unsigned long flags;
	struct spi_message *m;
	struct spi_device *spi;
	int timeout = 0;
	unsigned long val;

	/* the SPI controller may come back with both the BSY and RDY bits
	 * set.  In this case we need to wait for the BSY bit to clear so
	 * that we are sure the DMA is finished.  1000 reads was empirically
	 * determined to be long enough.
	 */
	while (timeout++ < 1000) {
		if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))
			break;
	}

	spin_lock_irqsave(&tspi->lock, flags);

	val = spi_tegra_readl(tspi, SLINK_STATUS);
	val |= SLINK_RDY;
	spi_tegra_writel(tspi, val, SLINK_STATUS);

	m = list_first_entry(&tspi->queue, struct spi_message, queue);

	if (timeout >= 1000)
		m->status = -EIO;

	spi = m->state;

	tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
	m->actual_length += tspi->cur_pos;

	if (tspi->cur_pos < tspi->cur->len) {
		tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);
		spi_tegra_go(tspi);
	} else if (!list_is_last(&tspi->cur->transfer_list,
				 &m->transfers)) {
		tspi->cur =  list_first_entry(&tspi->cur->transfer_list,
					      struct spi_transfer,
					      transfer_list);
		spi_tegra_start_transfer(spi, tspi->cur);
	} else {
		list_del(&m->queue);

		m->complete(m->context);

		if (!list_empty(&tspi->queue)) {
			m = list_first_entry(&tspi->queue, struct spi_message,
					     queue);
			spi = m->state;
			spi_tegra_start_message(spi, m);
		} else {
			clk_disable_unprepare(tspi->clk);
			tspi->cur_speed = 0;
		}
	}

	spin_unlock_irqrestore(&tspi->lock, flags);
}

static void tegra_spi_rx_dma_complete(void *args)
{
	struct spi_tegra_data *tspi = args;
	handle_spi_rx_dma_complete(tspi);
}

static int spi_tegra_setup(struct spi_device *spi)
{
	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	unsigned long cs_bit;
	unsigned long val;
	unsigned long flags;

	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
		spi->bits_per_word,
		spi->mode & SPI_CPOL ? "" : "~",
		spi->mode & SPI_CPHA ? "" : "~",
		spi->max_speed_hz);


	switch (spi->chip_select) {
	case 0:
		cs_bit = SLINK_CS_POLARITY;
		break;

	case 1:
		cs_bit = SLINK_CS_POLARITY1;
		break;

	case 2:
		cs_bit = SLINK_CS_POLARITY2;
		break;

	case 4:
		cs_bit = SLINK_CS_POLARITY3;
		break;

	default:
		return -EINVAL;
	}

	spin_lock_irqsave(&tspi->lock, flags);

	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	if (spi->mode & SPI_CS_HIGH)
		val |= cs_bit;
	else
		val &= ~cs_bit;
	spi_tegra_writel(tspi, val, SLINK_COMMAND);

	spin_unlock_irqrestore(&tspi->lock, flags);

	return 0;
}

static int spi_tegra_transfer(struct spi_device *spi, struct spi_message *m)
{
	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	struct spi_transfer *t;
	unsigned long flags;
	int was_empty;

	if (list_empty(&m->transfers) || !m->complete)
		return -EINVAL;

	list_for_each_entry(t, &m->transfers, transfer_list) {
		if (t->bits_per_word < 0 || t->bits_per_word > 32)
			return -EINVAL;

		if (t->len == 0)
			return -EINVAL;

		if (!t->rx_buf && !t->tx_buf)
			return -EINVAL;
	}

	m->state = spi;

	spin_lock_irqsave(&tspi->lock, flags);
	was_empty = list_empty(&tspi->queue);
	list_add_tail(&m->queue, &tspi->queue);

	if (was_empty)
		spi_tegra_start_message(spi, m);

	spin_unlock_irqrestore(&tspi->lock, flags);

	return 0;
}

static int __devinit spi_tegra_probe(struct platform_device *pdev)
{
	struct spi_master	*master;
	struct spi_tegra_data	*tspi;
	struct resource		*r;
	int ret;
	dma_cap_mask_t mask;

	master = spi_alloc_master(&pdev->dev, sizeof *tspi);
	if (master == NULL) {
		dev_err(&pdev->dev, "master allocation failed\n");
		return -ENOMEM;
	}

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;

	master->bus_num = pdev->id;

	master->setup = spi_tegra_setup;
	master->transfer = spi_tegra_transfer;
	master->num_chipselect = 4;

	dev_set_drvdata(&pdev->dev, master);
	tspi = spi_master_get_devdata(master);
	tspi->master = master;
	tspi->pdev = pdev;
	spin_lock_init(&tspi->lock);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (r == NULL) {
		ret = -ENODEV;
		goto err0;
	}

	if (!request_mem_region(r->start, resource_size(r),
				dev_name(&pdev->dev))) {
		ret = -EBUSY;
		goto err0;
	}

	tspi->phys = r->start;
	tspi->base = ioremap(r->start, resource_size(r));
	if (!tspi->base) {
		dev_err(&pdev->dev, "can't ioremap iomem\n");
		ret = -ENOMEM;
		goto err1;
	}

	tspi->clk = clk_get(&pdev->dev, NULL);
	if (IS_ERR(tspi->clk)) {
		dev_err(&pdev->dev, "can not get clock\n");
		ret = PTR_ERR(tspi->clk);
		goto err2;
	}

	INIT_LIST_HEAD(&tspi->queue);

	dma_cap_zero(mask);
	dma_cap_set(DMA_SLAVE, mask);
	tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
	if (!tspi->rx_dma) {
		dev_err(&pdev->dev, "can not allocate rx dma channel\n");
		ret = -ENODEV;
		goto err3;
	}

	tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
					 &tspi->rx_bb_phys, GFP_KERNEL);
	if (!tspi->rx_bb) {
		dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
		ret = -ENOMEM;
		goto err4;
	}

	/* Dmaengine Dma slave config */
	tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
	tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
	tspi->sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	tspi->sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	tspi->sconfig.slave_id = spi_tegra_req_sels[pdev->id];
	tspi->sconfig.src_maxburst = 1;
	tspi->sconfig.dst_maxburst = 1;
	ret = dmaengine_device_control(tspi->rx_dma,
			DMA_SLAVE_CONFIG, (unsigned long) &tspi->sconfig);
	if (ret < 0) {
		dev_err(&pdev->dev, "can not do slave configure for dma %d\n",
			ret);
		goto err4;
	}

	master->dev.of_node = pdev->dev.of_node;
	ret = spi_register_master(master);

	if (ret < 0)
		goto err5;

	return ret;

err5:
	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
			  tspi->rx_bb, tspi->rx_bb_phys);
err4:
	dma_release_channel(tspi->rx_dma);
err3:
	clk_put(tspi->clk);
err2:
	iounmap(tspi->base);
err1:
	release_mem_region(r->start, resource_size(r));
err0:
	spi_master_put(master);
	return ret;
}

static int __devexit spi_tegra_remove(struct platform_device *pdev)
{
	struct spi_master	*master;
	struct spi_tegra_data	*tspi;
	struct resource		*r;

	master = dev_get_drvdata(&pdev->dev);
	tspi = spi_master_get_devdata(master);

	spi_unregister_master(master);
	dma_release_channel(tspi->rx_dma);
	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
			  tspi->rx_bb, tspi->rx_bb_phys);

	clk_put(tspi->clk);
	iounmap(tspi->base);

	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	release_mem_region(r->start, resource_size(r));

	return 0;
}

MODULE_ALIAS("platform:spi_tegra");

#ifdef CONFIG_OF
static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {
	{ .compatible = "nvidia,tegra20-spi", },
	{}
};
MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);
#else /* CONFIG_OF */
#define spi_tegra_of_match_table NULL
#endif /* CONFIG_OF */

static struct platform_driver spi_tegra_driver = {
	.driver = {
		.name =		"spi_tegra",
		.owner =	THIS_MODULE,
		.of_match_table = spi_tegra_of_match_table,
	},
	.probe =	spi_tegra_probe,
	.remove =	__devexit_p(spi_tegra_remove),
};
module_platform_driver(spi_tegra_driver);

MODULE_LICENSE("GPL");
Commit	Line	Data
0c03a1dd EG	1	/*
	2	* Driver for Nvidia TEGRA spi controller.
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Erik Gilling <konkers@android.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/kernel.h>
5b7bea9f	21	#include <linux/module.h>
0c03a1dd EG	22	#include <linux/init.h>
	23	#include <linux/err.h>
	24	#include <linux/platform_device.h>
	25	#include <linux/io.h>
	26	#include <linux/dma-mapping.h>
	27	#include <linux/dmapool.h>
	28	#include <linux/clk.h>
	29	#include <linux/interrupt.h>
	30	#include <linux/delay.h>
	31
	32	#include <linux/spi/spi.h>
619ac8d3	33	#include <linux/dmaengine.h>
0c03a1dd EG	34
	35	#include <mach/dma.h>
	36
	37	#define SLINK_COMMAND 0x000
	38	#define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0)
	39	#define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5)
	40	#define SLINK_BOTH_EN (1 << 10)
	41	#define SLINK_CS_SW (1 << 11)
	42	#define SLINK_CS_VALUE (1 << 12)
	43	#define SLINK_CS_POLARITY (1 << 13)
	44	#define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16)
	45	#define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16)
	46	#define SLINK_IDLE_SDA_PULL_LOW (2 << 16)
	47	#define SLINK_IDLE_SDA_PULL_HIGH (3 << 16)
	48	#define SLINK_IDLE_SDA_MASK (3 << 16)
	49	#define SLINK_CS_POLARITY1 (1 << 20)
	50	#define SLINK_CK_SDA (1 << 21)
	51	#define SLINK_CS_POLARITY2 (1 << 22)
	52	#define SLINK_CS_POLARITY3 (1 << 23)
	53	#define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24)
	54	#define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24)
	55	#define SLINK_IDLE_SCLK_PULL_LOW (2 << 24)
	56	#define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24)
	57	#define SLINK_IDLE_SCLK_MASK (3 << 24)
	58	#define SLINK_M_S (1 << 28)
	59	#define SLINK_WAIT (1 << 29)
	60	#define SLINK_GO (1 << 30)
	61	#define SLINK_ENB (1 << 31)
	62
	63	#define SLINK_COMMAND2 0x004
	64	#define SLINK_LSBFE (1 << 0)
	65	#define SLINK_SSOE (1 << 1)
	66	#define SLINK_SPIE (1 << 4)
	67	#define SLINK_BIDIROE (1 << 6)
	68	#define SLINK_MODFEN (1 << 7)
	69	#define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8)
	70	#define SLINK_CS_ACTIVE_BETWEEN (1 << 17)
	71	#define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18)
	72	#define SLINK_SS_SETUP(x) (((x) & 0x3) << 20)
	73	#define SLINK_FIFO_REFILLS_0 (0 << 22)
	74	#define SLINK_FIFO_REFILLS_1 (1 << 22)
	75	#define SLINK_FIFO_REFILLS_2 (2 << 22)
	76	#define SLINK_FIFO_REFILLS_3 (3 << 22)
	77	#define SLINK_FIFO_REFILLS_MASK (3 << 22)
	78	#define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26)
	79	#define SLINK_SPC0 (1 << 29)
	80	#define SLINK_TXEN (1 << 30)
	81	#define SLINK_RXEN (1 << 31)
	82
	83	#define SLINK_STATUS 0x008
	84	#define SLINK_COUNT(val) (((val) >> 0) & 0x1f)
	85	#define SLINK_WORD(val) (((val) >> 5) & 0x1f)
	86	#define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff)
	87	#define SLINK_MODF (1 << 16)
	88	#define SLINK_RX_UNF (1 << 18)
	89	#define SLINK_TX_OVF (1 << 19)
	90	#define SLINK_TX_FULL (1 << 20)
	91	#define SLINK_TX_EMPTY (1 << 21)
	92	#define SLINK_RX_FULL (1 << 22)
	93	#define SLINK_RX_EMPTY (1 << 23)
	94	#define SLINK_TX_UNF (1 << 24)
	95	#define SLINK_RX_OVF (1 << 25)
	96	#define SLINK_TX_FLUSH (1 << 26)
	97	#define SLINK_RX_FLUSH (1 << 27)
98	#define SLINK_SCLK (1 << 28)
99	#define SLINK_ERR (1 << 29)
100	#define SLINK_RDY (1 << 30)
101	#define SLINK_BSY (1 << 31)
102
103	#define SLINK_MAS_DATA 0x010
104	#define SLINK_SLAVE_DATA 0x014
105
106	#define SLINK_DMA_CTL 0x018
107	#define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0)
108	#define SLINK_TX_TRIG_1 (0 << 16)
109	#define SLINK_TX_TRIG_4 (1 << 16)
110	#define SLINK_TX_TRIG_8 (2 << 16)
111	#define SLINK_TX_TRIG_16 (3 << 16)
112	#define SLINK_TX_TRIG_MASK (3 << 16)
113	#define SLINK_RX_TRIG_1 (0 << 18)
114	#define SLINK_RX_TRIG_4 (1 << 18)
115	#define SLINK_RX_TRIG_8 (2 << 18)
116	#define SLINK_RX_TRIG_16 (3 << 18)
117	#define SLINK_RX_TRIG_MASK (3 << 18)
118	#define SLINK_PACKED (1 << 20)
119	#define SLINK_PACK_SIZE_4 (0 << 21)
120	#define SLINK_PACK_SIZE_8 (1 << 21)
121	#define SLINK_PACK_SIZE_16 (2 << 21)
122	#define SLINK_PACK_SIZE_32 (3 << 21)
123	#define SLINK_PACK_SIZE_MASK (3 << 21)
124	#define SLINK_IE_TXC (1 << 26)
125	#define SLINK_IE_RXC (1 << 27)
126	#define SLINK_DMA_EN (1 << 31)
127
128	#define SLINK_STATUS2 0x01c
129	#define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0)
130	#define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f) >> 16)
131
132	#define SLINK_TX_FIFO 0x100
133	#define SLINK_RX_FIFO 0x180
134
135	static const unsigned long spi_tegra_req_sels[] = {
136	TEGRA_DMA_REQ_SEL_SL2B1,
137	TEGRA_DMA_REQ_SEL_SL2B2,
138	TEGRA_DMA_REQ_SEL_SL2B3,
139	TEGRA_DMA_REQ_SEL_SL2B4,
140	};
141
142	#define BB_LEN 32
143
144	struct spi_tegra_data {
145	struct spi_master *master;
146	struct platform_device *pdev;
147	spinlock_t lock;
148
149	struct clk *clk;
150	void __iomem *base;
151	unsigned long phys;
152
153	u32 cur_speed;
154
155	struct list_head queue;
156	struct spi_transfer *cur;
157	unsigned cur_pos;
158	unsigned cur_len;
159	unsigned cur_bytes_per_word;
160
161	/* The tegra spi controller has a bug which causes the first word
162	* in PIO transactions to be garbage. Since packed DMA transactions
163	* require transfers to be 4 byte aligned we need a bounce buffer
164	* for the generic case.
165	*/
619ac8d3	166	int dma_req_len;
619ac8d3 LD	167	struct dma_chan *rx_dma;
	168	struct dma_slave_config sconfig;
	169	struct dma_async_tx_descriptor *rx_dma_desc;
	170	dma_cookie_t rx_cookie;
0c03a1dd EG	171	u32 *rx_bb;
	172	dma_addr_t rx_bb_phys;
	173	};
	174
619ac8d3	175	static void tegra_spi_rx_dma_complete(void *args);
0c03a1dd EG	176	static inline unsigned long spi_tegra_readl(struct spi_tegra_data *tspi,
	177	unsigned long reg)
	178	{
	179	return readl(tspi->base + reg);
	180	}
	181
	182	static inline void spi_tegra_writel(struct spi_tegra_data *tspi,
	183	unsigned long val,
	184	unsigned long reg)
	185	{
	186	writel(val, tspi->base + reg);
	187	}
	188
	189	static void spi_tegra_go(struct spi_tegra_data *tspi)
	190	{
	191	unsigned long val;
	192
	193	wmb();
	194
	195	val = spi_tegra_readl(tspi, SLINK_DMA_CTL);
	196	val &= ~SLINK_DMA_BLOCK_SIZE(~0) & ~SLINK_DMA_EN;
619ac8d3	197	val \|= SLINK_DMA_BLOCK_SIZE(tspi->dma_req_len / 4 - 1);
0c03a1dd	198	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
619ac8d3 LD	199	tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma,
	200	tspi->rx_bb_phys, tspi->dma_req_len,
	201	DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
	202	if (!tspi->rx_dma_desc) {
	203	dev_err(&tspi->pdev->dev, "dmaengine slave prep failed\n");
	204	return;
	205	}
	206	tspi->rx_dma_desc->callback = tegra_spi_rx_dma_complete;
	207	tspi->rx_dma_desc->callback_param = tspi;
	208	tspi->rx_cookie = dmaengine_submit(tspi->rx_dma_desc);
	209	dma_async_issue_pending(tspi->rx_dma);
0c03a1dd EG	210
	211	val \|= SLINK_DMA_EN;
	212	spi_tegra_writel(tspi, val, SLINK_DMA_CTL);
	213	}
	214
	215	static unsigned spi_tegra_fill_tx_fifo(struct spi_tegra_data *tspi,
	216	struct spi_transfer *t)
	217	{
	218	unsigned len = min(t->len - tspi->cur_pos, BB_LEN *
	219	tspi->cur_bytes_per_word);
	220	u8 tx_buf = (u8 )t->tx_buf + tspi->cur_pos;
	221	int i, j;
	222	unsigned long val;
	223
	224	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	225	val &= ~SLINK_WORD_SIZE(~0);
	226	val \|= SLINK_WORD_SIZE(len / tspi->cur_bytes_per_word - 1);
	227	spi_tegra_writel(tspi, val, SLINK_COMMAND);
	228
	229	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
	230	val = 0;
	231	for (j = 0; j < tspi->cur_bytes_per_word; j++)
	232	val \|= tx_buf[i + j] << j * 8;
	233
	234	spi_tegra_writel(tspi, val, SLINK_TX_FIFO);
	235	}
	236
619ac8d3	237	tspi->dma_req_len = len / tspi->cur_bytes_per_word * 4;
0c03a1dd EG	238
	239	return len;
	240	}
	241
	242	static unsigned spi_tegra_drain_rx_fifo(struct spi_tegra_data *tspi,
	243	struct spi_transfer *t)
	244	{
	245	unsigned len = tspi->cur_len;
	246	u8 rx_buf = (u8 )t->rx_buf + tspi->cur_pos;
	247	int i, j;
	248	unsigned long val;
	249
	250	for (i = 0; i < len; i += tspi->cur_bytes_per_word) {
	251	val = tspi->rx_bb[i / tspi->cur_bytes_per_word];
	252	for (j = 0; j < tspi->cur_bytes_per_word; j++)
	253	rx_buf[i + j] = (val >> (j * 8)) & 0xff;
	254	}
	255
	256	return len;
	257	}
	258
	259	static void spi_tegra_start_transfer(struct spi_device *spi,
	260	struct spi_transfer *t)
	261	{
	262	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	263	u32 speed;
	264	u8 bits_per_word;
	265	unsigned long val;
	266
	267	speed = t->speed_hz ? t->speed_hz : spi->max_speed_hz;
	268	bits_per_word = t->bits_per_word ? t->bits_per_word :
	269	spi->bits_per_word;
	270
	271	tspi->cur_bytes_per_word = (bits_per_word - 1) / 8 + 1;
	272
	273	if (speed != tspi->cur_speed)
	274	clk_set_rate(tspi->clk, speed);
	275
	276	if (tspi->cur_speed == 0)
cb53417e	277	clk_prepare_enable(tspi->clk);
0c03a1dd EG	278
	279	tspi->cur_speed = speed;
	280
	281	val = spi_tegra_readl(tspi, SLINK_COMMAND2);
	282	val &= ~SLINK_SS_EN_CS(~0) \| SLINK_RXEN \| SLINK_TXEN;
	283	if (t->rx_buf)
	284	val \|= SLINK_RXEN;
	285	if (t->tx_buf)
	286	val \|= SLINK_TXEN;
	287	val \|= SLINK_SS_EN_CS(spi->chip_select);
	288	val \|= SLINK_SPIE;
	289	spi_tegra_writel(tspi, val, SLINK_COMMAND2);
	290
	291	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	292	val &= ~SLINK_BIT_LENGTH(~0);
	293	val \|= SLINK_BIT_LENGTH(bits_per_word - 1);
	294
	295	/* FIXME: should probably control CS manually so that we can be sure
	296	* it does not go low between transfer and to support delay_usecs
	297	* correctly.
	298	*/
	299	val &= ~SLINK_IDLE_SCLK_MASK & ~SLINK_CK_SDA & ~SLINK_CS_SW;
	300
	301	if (spi->mode & SPI_CPHA)
	302	val \|= SLINK_CK_SDA;
	303
	304	if (spi->mode & SPI_CPOL)
	305	val \|= SLINK_IDLE_SCLK_DRIVE_HIGH;
	306	else
	307	val \|= SLINK_IDLE_SCLK_DRIVE_LOW;
	308
	309	val \|= SLINK_M_S;
	310
	311	spi_tegra_writel(tspi, val, SLINK_COMMAND);
	312
	313	spi_tegra_writel(tspi, SLINK_RX_FLUSH \| SLINK_TX_FLUSH, SLINK_STATUS);
	314
	315	tspi->cur = t;
	316	tspi->cur_pos = 0;
	317	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, t);
	318
	319	spi_tegra_go(tspi);
	320	}
	321
	322	static void spi_tegra_start_message(struct spi_device *spi,
	323	struct spi_message *m)
	324	{
	325	struct spi_transfer *t;
	326
	327	m->actual_length = 0;
	328	m->status = 0;
	329
	330	t = list_first_entry(&m->transfers, struct spi_transfer, transfer_list);
	331	spi_tegra_start_transfer(spi, t);
	332	}
	333
619ac8d3	334	static void handle_spi_rx_dma_complete(struct spi_tegra_data *tspi)
0c03a1dd	335	{
0c03a1dd EG	336	unsigned long flags;
	337	struct spi_message *m;
	338	struct spi_device *spi;
	339	int timeout = 0;
	340	unsigned long val;
	341
	342	/* the SPI controller may come back with both the BSY and RDY bits
	343	* set. In this case we need to wait for the BSY bit to clear so
	344	* that we are sure the DMA is finished. 1000 reads was empirically
	345	* determined to be long enough.
	346	*/
	347	while (timeout++ < 1000) {
	348	if (!(spi_tegra_readl(tspi, SLINK_STATUS) & SLINK_BSY))
	349	break;
	350	}
	351
	352	spin_lock_irqsave(&tspi->lock, flags);
	353
0c03a1dd EG	354	val = spi_tegra_readl(tspi, SLINK_STATUS);
	355	val \|= SLINK_RDY;
	356	spi_tegra_writel(tspi, val, SLINK_STATUS);
	357
0c03a1dd	358	m = list_first_entry(&tspi->queue, struct spi_message, queue);
f41649e0 EG	359
	360	if (timeout >= 1000)
	361	m->status = -EIO;
	362
0c03a1dd EG	363	spi = m->state;
	364
	365	tspi->cur_pos += spi_tegra_drain_rx_fifo(tspi, tspi->cur);
	366	m->actual_length += tspi->cur_pos;
	367
	368	if (tspi->cur_pos < tspi->cur->len) {
	369	tspi->cur_len = spi_tegra_fill_tx_fifo(tspi, tspi->cur);
	370	spi_tegra_go(tspi);
	371	} else if (!list_is_last(&tspi->cur->transfer_list,
	372	&m->transfers)) {
	373	tspi->cur = list_first_entry(&tspi->cur->transfer_list,
	374	struct spi_transfer,
	375	transfer_list);
	376	spi_tegra_start_transfer(spi, tspi->cur);
	377	} else {
	378	list_del(&m->queue);
	379
	380	m->complete(m->context);
	381
	382	if (!list_empty(&tspi->queue)) {
	383	m = list_first_entry(&tspi->queue, struct spi_message,
	384	queue);
	385	spi = m->state;
	386	spi_tegra_start_message(spi, m);
	387	} else {
cb53417e	388	clk_disable_unprepare(tspi->clk);
0c03a1dd EG	389	tspi->cur_speed = 0;
	390	}
	391	}
	392
	393	spin_unlock_irqrestore(&tspi->lock, flags);
	394	}
5bd27611	395
619ac8d3 LD	396	static void tegra_spi_rx_dma_complete(void *args)
	397	{
	398	struct spi_tegra_data *tspi = args;
	399	handle_spi_rx_dma_complete(tspi);
	400	}
0c03a1dd EG	401
	402	static int spi_tegra_setup(struct spi_device *spi)
	403	{
	404	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	405	unsigned long cs_bit;
	406	unsigned long val;
	407	unsigned long flags;
	408
	409	dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
	410	spi->bits_per_word,
	411	spi->mode & SPI_CPOL ? "" : "~",
	412	spi->mode & SPI_CPHA ? "" : "~",
	413	spi->max_speed_hz);
	414
	415
	416	switch (spi->chip_select) {
	417	case 0:
	418	cs_bit = SLINK_CS_POLARITY;
	419	break;
	420
	421	case 1:
	422	cs_bit = SLINK_CS_POLARITY1;
	423	break;
	424
	425	case 2:
	426	cs_bit = SLINK_CS_POLARITY2;
	427	break;
	428
	429	case 4:
	430	cs_bit = SLINK_CS_POLARITY3;
	431	break;
	432
	433	default:
	434	return -EINVAL;
	435	}
	436
	437	spin_lock_irqsave(&tspi->lock, flags);
	438
	439	val = spi_tegra_readl(tspi, SLINK_COMMAND);
	440	if (spi->mode & SPI_CS_HIGH)
	441	val \|= cs_bit;
	442	else
	443	val &= ~cs_bit;
	444	spi_tegra_writel(tspi, val, SLINK_COMMAND);
	445
	446	spin_unlock_irqrestore(&tspi->lock, flags);
	447
	448	return 0;
	449	}
	450
	451	static int spi_tegra_transfer(struct spi_device spi, struct spi_message m)
	452	{
	453	struct spi_tegra_data *tspi = spi_master_get_devdata(spi->master);
	454	struct spi_transfer *t;
	455	unsigned long flags;
	456	int was_empty;
	457
	458	if (list_empty(&m->transfers) \|\| !m->complete)
	459	return -EINVAL;
	460
	461	list_for_each_entry(t, &m->transfers, transfer_list) {
	462	if (t->bits_per_word < 0 \|\| t->bits_per_word > 32)
	463	return -EINVAL;
	464
465	if (t->len == 0)
466	return -EINVAL;
467
468	if (!t->rx_buf && !t->tx_buf)
469	return -EINVAL;
470	}
471
472	m->state = spi;
473
474	spin_lock_irqsave(&tspi->lock, flags);
475	was_empty = list_empty(&tspi->queue);
476	list_add_tail(&m->queue, &tspi->queue);
477
478	if (was_empty)
479	spi_tegra_start_message(spi, m);
480
481	spin_unlock_irqrestore(&tspi->lock, flags);
482
483	return 0;
484	}
485
940ab889	486	static int __devinit spi_tegra_probe(struct platform_device *pdev)
0c03a1dd EG	487	{
	488	struct spi_master *master;
	489	struct spi_tegra_data *tspi;
	490	struct resource *r;
	491	int ret;
619ac8d3	492	dma_cap_mask_t mask;
0c03a1dd EG	493
	494	master = spi_alloc_master(&pdev->dev, sizeof *tspi);
	495	if (master == NULL) {
	496	dev_err(&pdev->dev, "master allocation failed\n");
	497	return -ENOMEM;
	498	}
	499
	500	/* the spi->mode bits understood by this driver: */
	501	master->mode_bits = SPI_CPOL \| SPI_CPHA \| SPI_CS_HIGH;
	502
	503	master->bus_num = pdev->id;
	504
	505	master->setup = spi_tegra_setup;
	506	master->transfer = spi_tegra_transfer;
	507	master->num_chipselect = 4;
	508
	509	dev_set_drvdata(&pdev->dev, master);
	510	tspi = spi_master_get_devdata(master);
	511	tspi->master = master;
	512	tspi->pdev = pdev;
	513	spin_lock_init(&tspi->lock);
	514
	515	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	516	if (r == NULL) {
	517	ret = -ENODEV;
	518	goto err0;
	519	}
	520
8e2943c0	521	if (!request_mem_region(r->start, resource_size(r),
0c03a1dd EG	522	dev_name(&pdev->dev))) {
	523	ret = -EBUSY;
	524	goto err0;
	525	}
	526
	527	tspi->phys = r->start;
8e2943c0	528	tspi->base = ioremap(r->start, resource_size(r));
0c03a1dd EG	529	if (!tspi->base) {
	530	dev_err(&pdev->dev, "can't ioremap iomem\n");
	531	ret = -ENOMEM;
	532	goto err1;
	533	}
	534
	535	tspi->clk = clk_get(&pdev->dev, NULL);
76d9cc45	536	if (IS_ERR(tspi->clk)) {
0c03a1dd EG	537	dev_err(&pdev->dev, "can not get clock\n");
	538	ret = PTR_ERR(tspi->clk);
	539	goto err2;
	540	}
	541
	542	INIT_LIST_HEAD(&tspi->queue);
	543
619ac8d3 LD	544	dma_cap_zero(mask);
	545	dma_cap_set(DMA_SLAVE, mask);
	546	tspi->rx_dma = dma_request_channel(mask, NULL, NULL);
	547	if (!tspi->rx_dma) {
	548	dev_err(&pdev->dev, "can not allocate rx dma channel\n");
	549	ret = -ENODEV;
	550	goto err3;
	551	}
	552
0c03a1dd EG	553	tspi->rx_bb = dma_alloc_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
	554	&tspi->rx_bb_phys, GFP_KERNEL);
	555	if (!tspi->rx_bb) {
	556	dev_err(&pdev->dev, "can not allocate rx bounce buffer\n");
	557	ret = -ENOMEM;
	558	goto err4;
	559	}
	560
619ac8d3 LD	561	/* Dmaengine Dma slave config */
	562	tspi->sconfig.src_addr = tspi->phys + SLINK_RX_FIFO;
	563	tspi->sconfig.dst_addr = tspi->phys + SLINK_RX_FIFO;
	564	tspi->sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	565	tspi->sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
	566	tspi->sconfig.slave_id = spi_tegra_req_sels[pdev->id];
	567	tspi->sconfig.src_maxburst = 1;
	568	tspi->sconfig.dst_maxburst = 1;
	569	ret = dmaengine_device_control(tspi->rx_dma,
	570	DMA_SLAVE_CONFIG, (unsigned long) &tspi->sconfig);
	571	if (ret < 0) {
	572	dev_err(&pdev->dev, "can not do slave configure for dma %d\n",
	573	ret);
	574	goto err4;
	575	}
0c03a1dd	576
e892bac1	577	master->dev.of_node = pdev->dev.of_node;
0c03a1dd EG	578	ret = spi_register_master(master);
	579
	580	if (ret < 0)
	581	goto err5;
	582
	583	return ret;
	584
	585	err5:
	586	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
	587	tspi->rx_bb, tspi->rx_bb_phys);
	588	err4:
619ac8d3	589	dma_release_channel(tspi->rx_dma);
0c03a1dd EG	590	err3:
	591	clk_put(tspi->clk);
	592	err2:
	593	iounmap(tspi->base);
	594	err1:
8e2943c0	595	release_mem_region(r->start, resource_size(r));
0c03a1dd EG	596	err0:
	597	spi_master_put(master);
	598	return ret;
	599	}
	600
	601	static int __devexit spi_tegra_remove(struct platform_device *pdev)
	602	{
	603	struct spi_master *master;
	604	struct spi_tegra_data *tspi;
	605	struct resource *r;
	606
	607	master = dev_get_drvdata(&pdev->dev);
	608	tspi = spi_master_get_devdata(master);
	609
8901e1b9	610	spi_unregister_master(master);
619ac8d3	611	dma_release_channel(tspi->rx_dma);
0c03a1dd EG	612	dma_free_coherent(&pdev->dev, sizeof(u32) * BB_LEN,
	613	tspi->rx_bb, tspi->rx_bb_phys);
	614
	615	clk_put(tspi->clk);
	616	iounmap(tspi->base);
	617
0c03a1dd	618	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8e2943c0	619	release_mem_region(r->start, resource_size(r));
0c03a1dd EG	620
	621	return 0;
	622	}
	623
	624	MODULE_ALIAS("platform:spi_tegra");
	625
e892bac1 GL	626	#ifdef CONFIG_OF
e892bac1 GL	627	static struct of_device_id spi_tegra_of_match_table[] __devinitdata = {
22032c77	628	{ .compatible = "nvidia,tegra20-spi", },
e892bac1 GL	629	{}
	630	};
	631	MODULE_DEVICE_TABLE(of, spi_tegra_of_match_table);
	632	#else /* CONFIG_OF */
	633	#define spi_tegra_of_match_table NULL
	634	#endif /* CONFIG_OF */
	635
0c03a1dd EG	636	static struct platform_driver spi_tegra_driver = {
	637	.driver = {
	638	.name = "spi_tegra",
	639	.owner = THIS_MODULE,
e892bac1	640	.of_match_table = spi_tegra_of_match_table,
0c03a1dd	641	},
940ab889	642	.probe = spi_tegra_probe,
0c03a1dd EG	643	.remove = __devexit_p(spi_tegra_remove),
0c03a1dd EG	644	};
940ab889	645	module_platform_driver(spi_tegra_driver);
0c03a1dd EG	646
0c03a1dd EG	647	MODULE_LICENSE("GPL");