Commit | Line | Data |
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e8b17b5b MO |
1 | /* |
2 | * SPI bus driver for the Topcliff PCH used by Intel SoCs | |
65308c46 | 3 | * |
e8b17b5b MO |
4 | * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; version 2 of the License. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. | |
18 | */ | |
19 | ||
65308c46 | 20 | #include <linux/delay.h> |
e8b17b5b MO |
21 | #include <linux/pci.h> |
22 | #include <linux/wait.h> | |
23 | #include <linux/spi/spi.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/sched.h> | |
26 | #include <linux/spi/spidev.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/device.h> | |
f016aeb6 | 29 | #include <linux/platform_device.h> |
e8b17b5b | 30 | |
c37f3c27 TM |
31 | #include <linux/dmaengine.h> |
32 | #include <linux/pch_dma.h> | |
33 | ||
e8b17b5b MO |
34 | /* Register offsets */ |
35 | #define PCH_SPCR 0x00 /* SPI control register */ | |
36 | #define PCH_SPBRR 0x04 /* SPI baud rate register */ | |
37 | #define PCH_SPSR 0x08 /* SPI status register */ | |
38 | #define PCH_SPDWR 0x0C /* SPI write data register */ | |
39 | #define PCH_SPDRR 0x10 /* SPI read data register */ | |
40 | #define PCH_SSNXCR 0x18 /* SSN Expand Control Register */ | |
41 | #define PCH_SRST 0x1C /* SPI reset register */ | |
c37f3c27 | 42 | #define PCH_ADDRESS_SIZE 0x20 |
e8b17b5b MO |
43 | |
44 | #define PCH_SPSR_TFD 0x000007C0 | |
45 | #define PCH_SPSR_RFD 0x0000F800 | |
46 | ||
47 | #define PCH_READABLE(x) (((x) & PCH_SPSR_RFD)>>11) | |
48 | #define PCH_WRITABLE(x) (((x) & PCH_SPSR_TFD)>>6) | |
49 | ||
50 | #define PCH_RX_THOLD 7 | |
51 | #define PCH_RX_THOLD_MAX 15 | |
e8b17b5b | 52 | |
e8b17b5b MO |
53 | #define PCH_MAX_BAUDRATE 5000000 |
54 | #define PCH_MAX_FIFO_DEPTH 16 | |
55 | ||
56 | #define STATUS_RUNNING 1 | |
57 | #define STATUS_EXITING 2 | |
58 | #define PCH_SLEEP_TIME 10 | |
59 | ||
e8b17b5b | 60 | #define SSN_LOW 0x02U |
8b7aa961 | 61 | #define SSN_HIGH 0x03U |
e8b17b5b MO |
62 | #define SSN_NO_CONTROL 0x00U |
63 | #define PCH_MAX_CS 0xFF | |
64 | #define PCI_DEVICE_ID_GE_SPI 0x8816 | |
65 | ||
66 | #define SPCR_SPE_BIT (1 << 0) | |
67 | #define SPCR_MSTR_BIT (1 << 1) | |
68 | #define SPCR_LSBF_BIT (1 << 4) | |
69 | #define SPCR_CPHA_BIT (1 << 5) | |
70 | #define SPCR_CPOL_BIT (1 << 6) | |
71 | #define SPCR_TFIE_BIT (1 << 8) | |
72 | #define SPCR_RFIE_BIT (1 << 9) | |
73 | #define SPCR_FIE_BIT (1 << 10) | |
74 | #define SPCR_ORIE_BIT (1 << 11) | |
75 | #define SPCR_MDFIE_BIT (1 << 12) | |
76 | #define SPCR_FICLR_BIT (1 << 24) | |
77 | #define SPSR_TFI_BIT (1 << 0) | |
78 | #define SPSR_RFI_BIT (1 << 1) | |
79 | #define SPSR_FI_BIT (1 << 2) | |
c37f3c27 | 80 | #define SPSR_ORF_BIT (1 << 3) |
e8b17b5b MO |
81 | #define SPBRR_SIZE_BIT (1 << 10) |
82 | ||
f016aeb6 TM |
83 | #define PCH_ALL (SPCR_TFIE_BIT|SPCR_RFIE_BIT|SPCR_FIE_BIT|\ |
84 | SPCR_ORIE_BIT|SPCR_MDFIE_BIT) | |
65308c46 | 85 | |
e8b17b5b MO |
86 | #define SPCR_RFIC_FIELD 20 |
87 | #define SPCR_TFIC_FIELD 16 | |
88 | ||
c37f3c27 TM |
89 | #define MASK_SPBRR_SPBR_BITS ((1 << 10) - 1) |
90 | #define MASK_RFIC_SPCR_BITS (0xf << SPCR_RFIC_FIELD) | |
91 | #define MASK_TFIC_SPCR_BITS (0xf << SPCR_TFIC_FIELD) | |
e8b17b5b MO |
92 | |
93 | #define PCH_CLOCK_HZ 50000000 | |
94 | #define PCH_MAX_SPBR 1023 | |
95 | ||
f016aeb6 TM |
96 | /* Definition for ML7213 by OKI SEMICONDUCTOR */ |
97 | #define PCI_VENDOR_ID_ROHM 0x10DB | |
98 | #define PCI_DEVICE_ID_ML7213_SPI 0x802c | |
2e2de2e3 | 99 | #define PCI_DEVICE_ID_ML7223_SPI 0x800F |
f016aeb6 TM |
100 | |
101 | /* | |
102 | * Set the number of SPI instance max | |
103 | * Intel EG20T PCH : 1ch | |
104 | * OKI SEMICONDUCTOR ML7213 IOH : 2ch | |
2e2de2e3 | 105 | * OKI SEMICONDUCTOR ML7223 IOH : 1ch |
f016aeb6 TM |
106 | */ |
107 | #define PCH_SPI_MAX_DEV 2 | |
e8b17b5b | 108 | |
c37f3c27 TM |
109 | #define PCH_BUF_SIZE 4096 |
110 | #define PCH_DMA_TRANS_SIZE 12 | |
111 | ||
112 | static int use_dma = 1; | |
113 | ||
114 | struct pch_spi_dma_ctrl { | |
115 | struct dma_async_tx_descriptor *desc_tx; | |
116 | struct dma_async_tx_descriptor *desc_rx; | |
117 | struct pch_dma_slave param_tx; | |
118 | struct pch_dma_slave param_rx; | |
119 | struct dma_chan *chan_tx; | |
120 | struct dma_chan *chan_rx; | |
121 | struct scatterlist *sg_tx_p; | |
122 | struct scatterlist *sg_rx_p; | |
123 | struct scatterlist sg_tx; | |
124 | struct scatterlist sg_rx; | |
125 | int nent; | |
126 | void *tx_buf_virt; | |
127 | void *rx_buf_virt; | |
128 | dma_addr_t tx_buf_dma; | |
129 | dma_addr_t rx_buf_dma; | |
130 | }; | |
e8b17b5b MO |
131 | /** |
132 | * struct pch_spi_data - Holds the SPI channel specific details | |
133 | * @io_remap_addr: The remapped PCI base address | |
134 | * @master: Pointer to the SPI master structure | |
135 | * @work: Reference to work queue handler | |
136 | * @wk: Workqueue for carrying out execution of the | |
137 | * requests | |
138 | * @wait: Wait queue for waking up upon receiving an | |
139 | * interrupt. | |
140 | * @transfer_complete: Status of SPI Transfer | |
141 | * @bcurrent_msg_processing: Status flag for message processing | |
142 | * @lock: Lock for protecting this structure | |
143 | * @queue: SPI Message queue | |
144 | * @status: Status of the SPI driver | |
145 | * @bpw_len: Length of data to be transferred in bits per | |
146 | * word | |
147 | * @transfer_active: Flag showing active transfer | |
148 | * @tx_index: Transmit data count; for bookkeeping during | |
149 | * transfer | |
150 | * @rx_index: Receive data count; for bookkeeping during | |
151 | * transfer | |
152 | * @tx_buff: Buffer for data to be transmitted | |
153 | * @rx_index: Buffer for Received data | |
154 | * @n_curnt_chip: The chip number that this SPI driver currently | |
155 | * operates on | |
156 | * @current_chip: Reference to the current chip that this SPI | |
157 | * driver currently operates on | |
158 | * @current_msg: The current message that this SPI driver is | |
159 | * handling | |
160 | * @cur_trans: The current transfer that this SPI driver is | |
161 | * handling | |
162 | * @board_dat: Reference to the SPI device data structure | |
f016aeb6 TM |
163 | * @plat_dev: platform_device structure |
164 | * @ch: SPI channel number | |
165 | * @irq_reg_sts: Status of IRQ registration | |
e8b17b5b MO |
166 | */ |
167 | struct pch_spi_data { | |
168 | void __iomem *io_remap_addr; | |
c37f3c27 | 169 | unsigned long io_base_addr; |
e8b17b5b MO |
170 | struct spi_master *master; |
171 | struct work_struct work; | |
172 | struct workqueue_struct *wk; | |
173 | wait_queue_head_t wait; | |
174 | u8 transfer_complete; | |
175 | u8 bcurrent_msg_processing; | |
176 | spinlock_t lock; | |
177 | struct list_head queue; | |
178 | u8 status; | |
179 | u32 bpw_len; | |
180 | u8 transfer_active; | |
181 | u32 tx_index; | |
182 | u32 rx_index; | |
183 | u16 *pkt_tx_buff; | |
184 | u16 *pkt_rx_buff; | |
185 | u8 n_curnt_chip; | |
186 | struct spi_device *current_chip; | |
187 | struct spi_message *current_msg; | |
188 | struct spi_transfer *cur_trans; | |
189 | struct pch_spi_board_data *board_dat; | |
f016aeb6 TM |
190 | struct platform_device *plat_dev; |
191 | int ch; | |
c37f3c27 TM |
192 | struct pch_spi_dma_ctrl dma; |
193 | int use_dma; | |
f016aeb6 | 194 | u8 irq_reg_sts; |
e8b17b5b MO |
195 | }; |
196 | ||
197 | /** | |
198 | * struct pch_spi_board_data - Holds the SPI device specific details | |
199 | * @pdev: Pointer to the PCI device | |
e8b17b5b | 200 | * @suspend_sts: Status of suspend |
f016aeb6 | 201 | * @num: The number of SPI device instance |
e8b17b5b MO |
202 | */ |
203 | struct pch_spi_board_data { | |
204 | struct pci_dev *pdev; | |
e8b17b5b | 205 | u8 suspend_sts; |
f016aeb6 TM |
206 | int num; |
207 | }; | |
208 | ||
209 | struct pch_pd_dev_save { | |
210 | int num; | |
211 | struct platform_device *pd_save[PCH_SPI_MAX_DEV]; | |
212 | struct pch_spi_board_data *board_dat; | |
e8b17b5b MO |
213 | }; |
214 | ||
215 | static struct pci_device_id pch_spi_pcidev_id[] = { | |
f016aeb6 TM |
216 | { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_GE_SPI), 1, }, |
217 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_SPI), 2, }, | |
2e2de2e3 | 218 | { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_SPI), 1, }, |
f016aeb6 | 219 | { } |
e8b17b5b MO |
220 | }; |
221 | ||
e8b17b5b MO |
222 | /** |
223 | * pch_spi_writereg() - Performs register writes | |
224 | * @master: Pointer to struct spi_master. | |
225 | * @idx: Register offset. | |
226 | * @val: Value to be written to register. | |
227 | */ | |
228 | static inline void pch_spi_writereg(struct spi_master *master, int idx, u32 val) | |
229 | { | |
e8b17b5b | 230 | struct pch_spi_data *data = spi_master_get_devdata(master); |
e8b17b5b MO |
231 | iowrite32(val, (data->io_remap_addr + idx)); |
232 | } | |
233 | ||
234 | /** | |
235 | * pch_spi_readreg() - Performs register reads | |
236 | * @master: Pointer to struct spi_master. | |
237 | * @idx: Register offset. | |
238 | */ | |
239 | static inline u32 pch_spi_readreg(struct spi_master *master, int idx) | |
240 | { | |
241 | struct pch_spi_data *data = spi_master_get_devdata(master); | |
e8b17b5b MO |
242 | return ioread32(data->io_remap_addr + idx); |
243 | } | |
244 | ||
e8b17b5b MO |
245 | static inline void pch_spi_setclr_reg(struct spi_master *master, int idx, |
246 | u32 set, u32 clr) | |
247 | { | |
248 | u32 tmp = pch_spi_readreg(master, idx); | |
249 | tmp = (tmp & ~clr) | set; | |
250 | pch_spi_writereg(master, idx, tmp); | |
251 | } | |
252 | ||
e8b17b5b MO |
253 | static void pch_spi_set_master_mode(struct spi_master *master) |
254 | { | |
255 | pch_spi_setclr_reg(master, PCH_SPCR, SPCR_MSTR_BIT, 0); | |
256 | } | |
257 | ||
258 | /** | |
259 | * pch_spi_clear_fifo() - Clears the Transmit and Receive FIFOs | |
260 | * @master: Pointer to struct spi_master. | |
261 | */ | |
262 | static void pch_spi_clear_fifo(struct spi_master *master) | |
263 | { | |
264 | pch_spi_setclr_reg(master, PCH_SPCR, SPCR_FICLR_BIT, 0); | |
265 | pch_spi_setclr_reg(master, PCH_SPCR, 0, SPCR_FICLR_BIT); | |
266 | } | |
267 | ||
e8b17b5b MO |
268 | static void pch_spi_handler_sub(struct pch_spi_data *data, u32 reg_spsr_val, |
269 | void __iomem *io_remap_addr) | |
270 | { | |
271 | u32 n_read, tx_index, rx_index, bpw_len; | |
272 | u16 *pkt_rx_buffer, *pkt_tx_buff; | |
273 | int read_cnt; | |
274 | u32 reg_spcr_val; | |
275 | void __iomem *spsr; | |
276 | void __iomem *spdrr; | |
277 | void __iomem *spdwr; | |
278 | ||
279 | spsr = io_remap_addr + PCH_SPSR; | |
280 | iowrite32(reg_spsr_val, spsr); | |
281 | ||
282 | if (data->transfer_active) { | |
283 | rx_index = data->rx_index; | |
284 | tx_index = data->tx_index; | |
285 | bpw_len = data->bpw_len; | |
286 | pkt_rx_buffer = data->pkt_rx_buff; | |
287 | pkt_tx_buff = data->pkt_tx_buff; | |
288 | ||
289 | spdrr = io_remap_addr + PCH_SPDRR; | |
290 | spdwr = io_remap_addr + PCH_SPDWR; | |
291 | ||
292 | n_read = PCH_READABLE(reg_spsr_val); | |
293 | ||
294 | for (read_cnt = 0; (read_cnt < n_read); read_cnt++) { | |
295 | pkt_rx_buffer[rx_index++] = ioread32(spdrr); | |
296 | if (tx_index < bpw_len) | |
297 | iowrite32(pkt_tx_buff[tx_index++], spdwr); | |
298 | } | |
299 | ||
300 | /* disable RFI if not needed */ | |
301 | if ((bpw_len - rx_index) <= PCH_MAX_FIFO_DEPTH) { | |
302 | reg_spcr_val = ioread32(io_remap_addr + PCH_SPCR); | |
65308c46 | 303 | reg_spcr_val &= ~SPCR_RFIE_BIT; /* disable RFI */ |
e8b17b5b MO |
304 | |
305 | /* reset rx threshold */ | |
c37f3c27 | 306 | reg_spcr_val &= ~MASK_RFIC_SPCR_BITS; |
e8b17b5b | 307 | reg_spcr_val |= (PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD); |
c37f3c27 TM |
308 | |
309 | iowrite32(reg_spcr_val, (io_remap_addr + PCH_SPCR)); | |
e8b17b5b MO |
310 | } |
311 | ||
312 | /* update counts */ | |
313 | data->tx_index = tx_index; | |
314 | data->rx_index = rx_index; | |
315 | ||
316 | } | |
317 | ||
318 | /* if transfer complete interrupt */ | |
319 | if (reg_spsr_val & SPSR_FI_BIT) { | |
373b0eb6 TM |
320 | if ((tx_index == bpw_len) && (rx_index == tx_index)) { |
321 | /* disable interrupts */ | |
322 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); | |
323 | ||
324 | /* transfer is completed; | |
325 | inform pch_spi_process_messages */ | |
326 | data->transfer_complete = true; | |
327 | data->transfer_active = false; | |
328 | wake_up(&data->wait); | |
329 | } else { | |
c37f3c27 TM |
330 | dev_err(&data->master->dev, |
331 | "%s : Transfer is not completed", __func__); | |
373b0eb6 | 332 | } |
e8b17b5b MO |
333 | } |
334 | } | |
335 | ||
e8b17b5b MO |
336 | /** |
337 | * pch_spi_handler() - Interrupt handler | |
338 | * @irq: The interrupt number. | |
339 | * @dev_id: Pointer to struct pch_spi_board_data. | |
340 | */ | |
341 | static irqreturn_t pch_spi_handler(int irq, void *dev_id) | |
342 | { | |
343 | u32 reg_spsr_val; | |
e8b17b5b MO |
344 | void __iomem *spsr; |
345 | void __iomem *io_remap_addr; | |
346 | irqreturn_t ret = IRQ_NONE; | |
f016aeb6 TM |
347 | struct pch_spi_data *data = dev_id; |
348 | struct pch_spi_board_data *board_dat = data->board_dat; | |
e8b17b5b MO |
349 | |
350 | if (board_dat->suspend_sts) { | |
351 | dev_dbg(&board_dat->pdev->dev, | |
352 | "%s returning due to suspend\n", __func__); | |
353 | return IRQ_NONE; | |
354 | } | |
c37f3c27 TM |
355 | if (data->use_dma) |
356 | return IRQ_NONE; | |
e8b17b5b | 357 | |
e8b17b5b MO |
358 | io_remap_addr = data->io_remap_addr; |
359 | spsr = io_remap_addr + PCH_SPSR; | |
360 | ||
361 | reg_spsr_val = ioread32(spsr); | |
362 | ||
c37f3c27 TM |
363 | if (reg_spsr_val & SPSR_ORF_BIT) |
364 | dev_err(&board_dat->pdev->dev, "%s Over run error", __func__); | |
365 | ||
e8b17b5b | 366 | /* Check if the interrupt is for SPI device */ |
e8b17b5b MO |
367 | if (reg_spsr_val & (SPSR_FI_BIT | SPSR_RFI_BIT)) { |
368 | pch_spi_handler_sub(data, reg_spsr_val, io_remap_addr); | |
369 | ret = IRQ_HANDLED; | |
370 | } | |
371 | ||
372 | dev_dbg(&board_dat->pdev->dev, "%s EXIT return value=%d\n", | |
373 | __func__, ret); | |
374 | ||
375 | return ret; | |
376 | } | |
377 | ||
378 | /** | |
379 | * pch_spi_set_baud_rate() - Sets SPBR field in SPBRR | |
380 | * @master: Pointer to struct spi_master. | |
381 | * @speed_hz: Baud rate. | |
382 | */ | |
383 | static void pch_spi_set_baud_rate(struct spi_master *master, u32 speed_hz) | |
384 | { | |
65308c46 | 385 | u32 n_spbr = PCH_CLOCK_HZ / (speed_hz * 2); |
e8b17b5b MO |
386 | |
387 | /* if baud rate is less than we can support limit it */ | |
e8b17b5b MO |
388 | if (n_spbr > PCH_MAX_SPBR) |
389 | n_spbr = PCH_MAX_SPBR; | |
390 | ||
c37f3c27 | 391 | pch_spi_setclr_reg(master, PCH_SPBRR, n_spbr, MASK_SPBRR_SPBR_BITS); |
e8b17b5b MO |
392 | } |
393 | ||
394 | /** | |
395 | * pch_spi_set_bits_per_word() - Sets SIZE field in SPBRR | |
396 | * @master: Pointer to struct spi_master. | |
397 | * @bits_per_word: Bits per word for SPI transfer. | |
398 | */ | |
399 | static void pch_spi_set_bits_per_word(struct spi_master *master, | |
400 | u8 bits_per_word) | |
401 | { | |
402 | if (bits_per_word == 8) | |
403 | pch_spi_setclr_reg(master, PCH_SPBRR, 0, SPBRR_SIZE_BIT); | |
404 | else | |
405 | pch_spi_setclr_reg(master, PCH_SPBRR, SPBRR_SIZE_BIT, 0); | |
406 | } | |
407 | ||
408 | /** | |
409 | * pch_spi_setup_transfer() - Configures the PCH SPI hardware for transfer | |
410 | * @spi: Pointer to struct spi_device. | |
411 | */ | |
412 | static void pch_spi_setup_transfer(struct spi_device *spi) | |
413 | { | |
65308c46 | 414 | u32 flags = 0; |
e8b17b5b MO |
415 | |
416 | dev_dbg(&spi->dev, "%s SPBRR content =%x setting baud rate=%d\n", | |
417 | __func__, pch_spi_readreg(spi->master, PCH_SPBRR), | |
418 | spi->max_speed_hz); | |
e8b17b5b MO |
419 | pch_spi_set_baud_rate(spi->master, spi->max_speed_hz); |
420 | ||
421 | /* set bits per word */ | |
422 | pch_spi_set_bits_per_word(spi->master, spi->bits_per_word); | |
423 | ||
65308c46 GL |
424 | if (!(spi->mode & SPI_LSB_FIRST)) |
425 | flags |= SPCR_LSBF_BIT; | |
e8b17b5b | 426 | if (spi->mode & SPI_CPOL) |
65308c46 | 427 | flags |= SPCR_CPOL_BIT; |
e8b17b5b | 428 | if (spi->mode & SPI_CPHA) |
65308c46 GL |
429 | flags |= SPCR_CPHA_BIT; |
430 | pch_spi_setclr_reg(spi->master, PCH_SPCR, flags, | |
431 | (SPCR_LSBF_BIT | SPCR_CPOL_BIT | SPCR_CPHA_BIT)); | |
e8b17b5b MO |
432 | |
433 | /* Clear the FIFO by toggling FICLR to 1 and back to 0 */ | |
434 | pch_spi_clear_fifo(spi->master); | |
435 | } | |
436 | ||
e8b17b5b MO |
437 | /** |
438 | * pch_spi_reset() - Clears SPI registers | |
439 | * @master: Pointer to struct spi_master. | |
440 | */ | |
441 | static void pch_spi_reset(struct spi_master *master) | |
442 | { | |
443 | /* write 1 to reset SPI */ | |
444 | pch_spi_writereg(master, PCH_SRST, 0x1); | |
445 | ||
446 | /* clear reset */ | |
447 | pch_spi_writereg(master, PCH_SRST, 0x0); | |
448 | } | |
449 | ||
450 | static int pch_spi_setup(struct spi_device *pspi) | |
451 | { | |
452 | /* check bits per word */ | |
65308c46 | 453 | if (pspi->bits_per_word == 0) { |
e8b17b5b MO |
454 | pspi->bits_per_word = 8; |
455 | dev_dbg(&pspi->dev, "%s 8 bits per word\n", __func__); | |
456 | } | |
457 | ||
65308c46 | 458 | if ((pspi->bits_per_word != 8) && (pspi->bits_per_word != 16)) { |
e8b17b5b MO |
459 | dev_err(&pspi->dev, "%s Invalid bits per word\n", __func__); |
460 | return -EINVAL; | |
461 | } | |
462 | ||
463 | /* Check baud rate setting */ | |
464 | /* if baud rate of chip is greater than | |
465 | max we can support,return error */ | |
466 | if ((pspi->max_speed_hz) > PCH_MAX_BAUDRATE) | |
467 | pspi->max_speed_hz = PCH_MAX_BAUDRATE; | |
468 | ||
469 | dev_dbg(&pspi->dev, "%s MODE = %x\n", __func__, | |
65308c46 | 470 | (pspi->mode) & (SPI_CPOL | SPI_CPHA)); |
e8b17b5b MO |
471 | |
472 | return 0; | |
473 | } | |
474 | ||
475 | static int pch_spi_transfer(struct spi_device *pspi, struct spi_message *pmsg) | |
476 | { | |
477 | ||
478 | struct spi_transfer *transfer; | |
479 | struct pch_spi_data *data = spi_master_get_devdata(pspi->master); | |
480 | int retval; | |
481 | unsigned long flags; | |
482 | ||
483 | /* validate spi message and baud rate */ | |
65308c46 GL |
484 | if (unlikely(list_empty(&pmsg->transfers) == 1)) { |
485 | dev_err(&pspi->dev, "%s list empty\n", __func__); | |
486 | retval = -EINVAL; | |
487 | goto err_out; | |
488 | } | |
e8b17b5b | 489 | |
65308c46 GL |
490 | if (unlikely(pspi->max_speed_hz == 0)) { |
491 | dev_err(&pspi->dev, "%s pch_spi_tranfer maxspeed=%d\n", | |
492 | __func__, pspi->max_speed_hz); | |
e8b17b5b MO |
493 | retval = -EINVAL; |
494 | goto err_out; | |
495 | } | |
496 | ||
497 | dev_dbg(&pspi->dev, "%s Transfer List not empty. " | |
498 | "Transfer Speed is set.\n", __func__); | |
499 | ||
c37f3c27 | 500 | spin_lock_irqsave(&data->lock, flags); |
e8b17b5b MO |
501 | /* validate Tx/Rx buffers and Transfer length */ |
502 | list_for_each_entry(transfer, &pmsg->transfers, transfer_list) { | |
65308c46 | 503 | if (!transfer->tx_buf && !transfer->rx_buf) { |
e8b17b5b MO |
504 | dev_err(&pspi->dev, |
505 | "%s Tx and Rx buffer NULL\n", __func__); | |
506 | retval = -EINVAL; | |
c37f3c27 | 507 | goto err_return_spinlock; |
e8b17b5b MO |
508 | } |
509 | ||
65308c46 | 510 | if (!transfer->len) { |
e8b17b5b MO |
511 | dev_err(&pspi->dev, "%s Transfer length invalid\n", |
512 | __func__); | |
513 | retval = -EINVAL; | |
c37f3c27 | 514 | goto err_return_spinlock; |
e8b17b5b MO |
515 | } |
516 | ||
517 | dev_dbg(&pspi->dev, "%s Tx/Rx buffer valid. Transfer length" | |
518 | " valid\n", __func__); | |
519 | ||
c37f3c27 | 520 | /* if baud rate has been specified validate the same */ |
65308c46 GL |
521 | if (transfer->speed_hz > PCH_MAX_BAUDRATE) |
522 | transfer->speed_hz = PCH_MAX_BAUDRATE; | |
e8b17b5b MO |
523 | |
524 | /* if bits per word has been specified validate the same */ | |
525 | if (transfer->bits_per_word) { | |
526 | if ((transfer->bits_per_word != 8) | |
527 | && (transfer->bits_per_word != 16)) { | |
528 | retval = -EINVAL; | |
529 | dev_err(&pspi->dev, | |
530 | "%s Invalid bits per word\n", __func__); | |
c37f3c27 | 531 | goto err_return_spinlock; |
e8b17b5b MO |
532 | } |
533 | } | |
534 | } | |
c37f3c27 | 535 | spin_unlock_irqrestore(&data->lock, flags); |
e8b17b5b | 536 | |
65308c46 GL |
537 | /* We won't process any messages if we have been asked to terminate */ |
538 | if (data->status == STATUS_EXITING) { | |
e8b17b5b MO |
539 | dev_err(&pspi->dev, "%s status = STATUS_EXITING.\n", __func__); |
540 | retval = -ESHUTDOWN; | |
c37f3c27 | 541 | goto err_out; |
e8b17b5b MO |
542 | } |
543 | ||
544 | /* If suspended ,return -EINVAL */ | |
545 | if (data->board_dat->suspend_sts) { | |
65308c46 | 546 | dev_err(&pspi->dev, "%s suspend; returning EINVAL\n", __func__); |
e8b17b5b | 547 | retval = -EINVAL; |
c37f3c27 | 548 | goto err_out; |
e8b17b5b MO |
549 | } |
550 | ||
551 | /* set status of message */ | |
552 | pmsg->actual_length = 0; | |
e8b17b5b MO |
553 | dev_dbg(&pspi->dev, "%s - pmsg->status =%d\n", __func__, pmsg->status); |
554 | ||
555 | pmsg->status = -EINPROGRESS; | |
c37f3c27 | 556 | spin_lock_irqsave(&data->lock, flags); |
e8b17b5b MO |
557 | /* add message to queue */ |
558 | list_add_tail(&pmsg->queue, &data->queue); | |
c37f3c27 TM |
559 | spin_unlock_irqrestore(&data->lock, flags); |
560 | ||
e8b17b5b MO |
561 | dev_dbg(&pspi->dev, "%s - Invoked list_add_tail\n", __func__); |
562 | ||
563 | /* schedule work queue to run */ | |
564 | queue_work(data->wk, &data->work); | |
e8b17b5b MO |
565 | dev_dbg(&pspi->dev, "%s - Invoked queue work\n", __func__); |
566 | ||
567 | retval = 0; | |
568 | ||
e8b17b5b MO |
569 | err_out: |
570 | dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); | |
571 | return retval; | |
c37f3c27 TM |
572 | err_return_spinlock: |
573 | dev_dbg(&pspi->dev, "%s RETURN=%d\n", __func__, retval); | |
574 | spin_unlock_irqrestore(&data->lock, flags); | |
575 | return retval; | |
e8b17b5b MO |
576 | } |
577 | ||
578 | static inline void pch_spi_select_chip(struct pch_spi_data *data, | |
579 | struct spi_device *pspi) | |
580 | { | |
65308c46 GL |
581 | if (data->current_chip != NULL) { |
582 | if (pspi->chip_select != data->n_curnt_chip) { | |
583 | dev_dbg(&pspi->dev, "%s : different slave\n", __func__); | |
e8b17b5b MO |
584 | data->current_chip = NULL; |
585 | } | |
586 | } | |
587 | ||
588 | data->current_chip = pspi; | |
589 | ||
590 | data->n_curnt_chip = data->current_chip->chip_select; | |
591 | ||
592 | dev_dbg(&pspi->dev, "%s :Invoking pch_spi_setup_transfer\n", __func__); | |
593 | pch_spi_setup_transfer(pspi); | |
594 | } | |
595 | ||
c37f3c27 | 596 | static void pch_spi_set_tx(struct pch_spi_data *data, int *bpw) |
e8b17b5b | 597 | { |
e8b17b5b MO |
598 | int size; |
599 | u32 n_writes; | |
600 | int j; | |
601 | struct spi_message *pmsg; | |
602 | const u8 *tx_buf; | |
603 | const u16 *tx_sbuf; | |
604 | ||
e8b17b5b MO |
605 | /* set baud rate if needed */ |
606 | if (data->cur_trans->speed_hz) { | |
65308c46 GL |
607 | dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); |
608 | pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); | |
e8b17b5b MO |
609 | } |
610 | ||
611 | /* set bits per word if needed */ | |
65308c46 GL |
612 | if (data->cur_trans->bits_per_word && |
613 | (data->current_msg->spi->bits_per_word != data->cur_trans->bits_per_word)) { | |
614 | dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); | |
e8b17b5b | 615 | pch_spi_set_bits_per_word(data->master, |
65308c46 | 616 | data->cur_trans->bits_per_word); |
e8b17b5b MO |
617 | *bpw = data->cur_trans->bits_per_word; |
618 | } else { | |
619 | *bpw = data->current_msg->spi->bits_per_word; | |
620 | } | |
621 | ||
622 | /* reset Tx/Rx index */ | |
623 | data->tx_index = 0; | |
624 | data->rx_index = 0; | |
625 | ||
626 | data->bpw_len = data->cur_trans->len / (*bpw / 8); | |
e8b17b5b MO |
627 | |
628 | /* find alloc size */ | |
65308c46 GL |
629 | size = data->cur_trans->len * sizeof(*data->pkt_tx_buff); |
630 | ||
e8b17b5b MO |
631 | /* allocate memory for pkt_tx_buff & pkt_rx_buffer */ |
632 | data->pkt_tx_buff = kzalloc(size, GFP_KERNEL); | |
e8b17b5b MO |
633 | if (data->pkt_tx_buff != NULL) { |
634 | data->pkt_rx_buff = kzalloc(size, GFP_KERNEL); | |
65308c46 | 635 | if (!data->pkt_rx_buff) |
e8b17b5b | 636 | kfree(data->pkt_tx_buff); |
e8b17b5b MO |
637 | } |
638 | ||
65308c46 | 639 | if (!data->pkt_rx_buff) { |
e8b17b5b | 640 | /* flush queue and set status of all transfers to -ENOMEM */ |
65308c46 | 641 | dev_err(&data->master->dev, "%s :kzalloc failed\n", __func__); |
e8b17b5b MO |
642 | list_for_each_entry(pmsg, data->queue.next, queue) { |
643 | pmsg->status = -ENOMEM; | |
644 | ||
645 | if (pmsg->complete != 0) | |
646 | pmsg->complete(pmsg->context); | |
647 | ||
648 | /* delete from queue */ | |
649 | list_del_init(&pmsg->queue); | |
650 | } | |
e8b17b5b MO |
651 | return; |
652 | } | |
653 | ||
654 | /* copy Tx Data */ | |
65308c46 | 655 | if (data->cur_trans->tx_buf != NULL) { |
e8b17b5b | 656 | if (*bpw == 8) { |
65308c46 GL |
657 | tx_buf = data->cur_trans->tx_buf; |
658 | for (j = 0; j < data->bpw_len; j++) | |
659 | data->pkt_tx_buff[j] = *tx_buf++; | |
e8b17b5b | 660 | } else { |
65308c46 GL |
661 | tx_sbuf = data->cur_trans->tx_buf; |
662 | for (j = 0; j < data->bpw_len; j++) | |
663 | data->pkt_tx_buff[j] = *tx_sbuf++; | |
e8b17b5b MO |
664 | } |
665 | } | |
666 | ||
667 | /* if len greater than PCH_MAX_FIFO_DEPTH, write 16,else len bytes */ | |
65308c46 GL |
668 | n_writes = data->bpw_len; |
669 | if (n_writes > PCH_MAX_FIFO_DEPTH) | |
e8b17b5b | 670 | n_writes = PCH_MAX_FIFO_DEPTH; |
e8b17b5b | 671 | |
65308c46 | 672 | dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " |
e8b17b5b MO |
673 | "0x2 to SSNXCR\n", __func__); |
674 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); | |
675 | ||
65308c46 GL |
676 | for (j = 0; j < n_writes; j++) |
677 | pch_spi_writereg(data->master, PCH_SPDWR, data->pkt_tx_buff[j]); | |
e8b17b5b MO |
678 | |
679 | /* update tx_index */ | |
680 | data->tx_index = j; | |
681 | ||
682 | /* reset transfer complete flag */ | |
683 | data->transfer_complete = false; | |
684 | data->transfer_active = true; | |
685 | } | |
686 | ||
c37f3c27 | 687 | static void pch_spi_nomore_transfer(struct pch_spi_data *data) |
e8b17b5b | 688 | { |
c37f3c27 | 689 | struct spi_message *pmsg; |
65308c46 | 690 | dev_dbg(&data->master->dev, "%s called\n", __func__); |
e8b17b5b | 691 | /* Invoke complete callback |
65308c46 | 692 | * [To the spi core..indicating end of transfer] */ |
e8b17b5b MO |
693 | data->current_msg->status = 0; |
694 | ||
65308c46 | 695 | if (data->current_msg->complete != 0) { |
e8b17b5b MO |
696 | dev_dbg(&data->master->dev, |
697 | "%s:Invoking callback of SPI core\n", __func__); | |
698 | data->current_msg->complete(data->current_msg->context); | |
699 | } | |
700 | ||
701 | /* update status in global variable */ | |
702 | data->bcurrent_msg_processing = false; | |
703 | ||
704 | dev_dbg(&data->master->dev, | |
705 | "%s:data->bcurrent_msg_processing = false\n", __func__); | |
706 | ||
707 | data->current_msg = NULL; | |
708 | data->cur_trans = NULL; | |
709 | ||
65308c46 GL |
710 | /* check if we have items in list and not suspending |
711 | * return 1 if list empty */ | |
e8b17b5b | 712 | if ((list_empty(&data->queue) == 0) && |
65308c46 GL |
713 | (!data->board_dat->suspend_sts) && |
714 | (data->status != STATUS_EXITING)) { | |
e8b17b5b | 715 | /* We have some more work to do (either there is more tranint |
65308c46 GL |
716 | * bpw;sfer requests in the current message or there are |
717 | *more messages) | |
718 | */ | |
719 | dev_dbg(&data->master->dev, "%s:Invoke queue_work\n", __func__); | |
e8b17b5b | 720 | queue_work(data->wk, &data->work); |
65308c46 GL |
721 | } else if (data->board_dat->suspend_sts || |
722 | data->status == STATUS_EXITING) { | |
e8b17b5b MO |
723 | dev_dbg(&data->master->dev, |
724 | "%s suspend/remove initiated, flushing queue\n", | |
725 | __func__); | |
726 | list_for_each_entry(pmsg, data->queue.next, queue) { | |
727 | pmsg->status = -EIO; | |
728 | ||
65308c46 | 729 | if (pmsg->complete) |
e8b17b5b MO |
730 | pmsg->complete(pmsg->context); |
731 | ||
732 | /* delete from queue */ | |
733 | list_del_init(&pmsg->queue); | |
734 | } | |
735 | } | |
736 | } | |
737 | ||
738 | static void pch_spi_set_ir(struct pch_spi_data *data) | |
739 | { | |
c37f3c27 TM |
740 | /* enable interrupts, set threshold, enable SPI */ |
741 | if ((data->bpw_len) > PCH_MAX_FIFO_DEPTH) | |
77e58efd | 742 | /* set receive threshold to PCH_RX_THOLD */ |
65308c46 | 743 | pch_spi_setclr_reg(data->master, PCH_SPCR, |
c37f3c27 TM |
744 | PCH_RX_THOLD << SPCR_RFIC_FIELD | |
745 | SPCR_FIE_BIT | SPCR_RFIE_BIT | | |
746 | SPCR_ORIE_BIT | SPCR_SPE_BIT, | |
747 | MASK_RFIC_SPCR_BITS | PCH_ALL); | |
748 | else | |
77e58efd | 749 | /* set receive threshold to maximum */ |
65308c46 | 750 | pch_spi_setclr_reg(data->master, PCH_SPCR, |
c37f3c27 TM |
751 | PCH_RX_THOLD_MAX << SPCR_RFIC_FIELD | |
752 | SPCR_FIE_BIT | SPCR_ORIE_BIT | | |
753 | SPCR_SPE_BIT, | |
754 | MASK_RFIC_SPCR_BITS | PCH_ALL); | |
e8b17b5b MO |
755 | |
756 | /* Wait until the transfer completes; go to sleep after | |
757 | initiating the transfer. */ | |
758 | dev_dbg(&data->master->dev, | |
759 | "%s:waiting for transfer to get over\n", __func__); | |
760 | ||
761 | wait_event_interruptible(data->wait, data->transfer_complete); | |
762 | ||
e8b17b5b MO |
763 | /* clear all interrupts */ |
764 | pch_spi_writereg(data->master, PCH_SPSR, | |
65308c46 | 765 | pch_spi_readreg(data->master, PCH_SPSR)); |
c37f3c27 TM |
766 | /* Disable interrupts and SPI transfer */ |
767 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL | SPCR_SPE_BIT); | |
768 | /* clear FIFO */ | |
769 | pch_spi_clear_fifo(data->master); | |
e8b17b5b MO |
770 | } |
771 | ||
772 | static void pch_spi_copy_rx_data(struct pch_spi_data *data, int bpw) | |
773 | { | |
774 | int j; | |
775 | u8 *rx_buf; | |
776 | u16 *rx_sbuf; | |
777 | ||
778 | /* copy Rx Data */ | |
65308c46 | 779 | if (!data->cur_trans->rx_buf) |
e8b17b5b MO |
780 | return; |
781 | ||
782 | if (bpw == 8) { | |
65308c46 GL |
783 | rx_buf = data->cur_trans->rx_buf; |
784 | for (j = 0; j < data->bpw_len; j++) | |
785 | *rx_buf++ = data->pkt_rx_buff[j] & 0xFF; | |
e8b17b5b | 786 | } else { |
65308c46 GL |
787 | rx_sbuf = data->cur_trans->rx_buf; |
788 | for (j = 0; j < data->bpw_len; j++) | |
789 | *rx_sbuf++ = data->pkt_rx_buff[j]; | |
e8b17b5b MO |
790 | } |
791 | } | |
792 | ||
c37f3c27 TM |
793 | static void pch_spi_copy_rx_data_for_dma(struct pch_spi_data *data, int bpw) |
794 | { | |
795 | int j; | |
796 | u8 *rx_buf; | |
797 | u16 *rx_sbuf; | |
798 | const u8 *rx_dma_buf; | |
799 | const u16 *rx_dma_sbuf; | |
800 | ||
801 | /* copy Rx Data */ | |
802 | if (!data->cur_trans->rx_buf) | |
803 | return; | |
804 | ||
805 | if (bpw == 8) { | |
806 | rx_buf = data->cur_trans->rx_buf; | |
807 | rx_dma_buf = data->dma.rx_buf_virt; | |
808 | for (j = 0; j < data->bpw_len; j++) | |
809 | *rx_buf++ = *rx_dma_buf++ & 0xFF; | |
810 | } else { | |
811 | rx_sbuf = data->cur_trans->rx_buf; | |
812 | rx_dma_sbuf = data->dma.rx_buf_virt; | |
813 | for (j = 0; j < data->bpw_len; j++) | |
814 | *rx_sbuf++ = *rx_dma_sbuf++; | |
815 | } | |
816 | } | |
817 | ||
818 | static void pch_spi_start_transfer(struct pch_spi_data *data) | |
819 | { | |
820 | struct pch_spi_dma_ctrl *dma; | |
821 | unsigned long flags; | |
822 | ||
823 | dma = &data->dma; | |
824 | ||
825 | spin_lock_irqsave(&data->lock, flags); | |
826 | ||
827 | /* disable interrupts, SPI set enable */ | |
828 | pch_spi_setclr_reg(data->master, PCH_SPCR, SPCR_SPE_BIT, PCH_ALL); | |
829 | ||
830 | spin_unlock_irqrestore(&data->lock, flags); | |
831 | ||
832 | /* Wait until the transfer completes; go to sleep after | |
833 | initiating the transfer. */ | |
834 | dev_dbg(&data->master->dev, | |
835 | "%s:waiting for transfer to get over\n", __func__); | |
836 | wait_event_interruptible(data->wait, data->transfer_complete); | |
837 | ||
838 | dma_sync_sg_for_cpu(&data->master->dev, dma->sg_rx_p, dma->nent, | |
839 | DMA_FROM_DEVICE); | |
27504be5 TM |
840 | |
841 | dma_sync_sg_for_cpu(&data->master->dev, dma->sg_tx_p, dma->nent, | |
842 | DMA_FROM_DEVICE); | |
843 | memset(data->dma.tx_buf_virt, 0, PAGE_SIZE); | |
844 | ||
c37f3c27 TM |
845 | async_tx_ack(dma->desc_rx); |
846 | async_tx_ack(dma->desc_tx); | |
847 | kfree(dma->sg_tx_p); | |
848 | kfree(dma->sg_rx_p); | |
849 | ||
850 | spin_lock_irqsave(&data->lock, flags); | |
c37f3c27 TM |
851 | |
852 | /* clear fifo threshold, disable interrupts, disable SPI transfer */ | |
853 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, | |
854 | MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS | PCH_ALL | | |
855 | SPCR_SPE_BIT); | |
856 | /* clear all interrupts */ | |
857 | pch_spi_writereg(data->master, PCH_SPSR, | |
858 | pch_spi_readreg(data->master, PCH_SPSR)); | |
859 | /* clear FIFO */ | |
860 | pch_spi_clear_fifo(data->master); | |
861 | ||
862 | spin_unlock_irqrestore(&data->lock, flags); | |
863 | } | |
864 | ||
865 | static void pch_dma_rx_complete(void *arg) | |
866 | { | |
867 | struct pch_spi_data *data = arg; | |
868 | ||
869 | /* transfer is completed;inform pch_spi_process_messages_dma */ | |
870 | data->transfer_complete = true; | |
871 | wake_up_interruptible(&data->wait); | |
872 | } | |
873 | ||
874 | static bool pch_spi_filter(struct dma_chan *chan, void *slave) | |
875 | { | |
876 | struct pch_dma_slave *param = slave; | |
877 | ||
878 | if ((chan->chan_id == param->chan_id) && | |
879 | (param->dma_dev == chan->device->dev)) { | |
880 | chan->private = param; | |
881 | return true; | |
882 | } else { | |
883 | return false; | |
884 | } | |
885 | } | |
886 | ||
887 | static void pch_spi_request_dma(struct pch_spi_data *data, int bpw) | |
888 | { | |
889 | dma_cap_mask_t mask; | |
890 | struct dma_chan *chan; | |
891 | struct pci_dev *dma_dev; | |
892 | struct pch_dma_slave *param; | |
893 | struct pch_spi_dma_ctrl *dma; | |
894 | unsigned int width; | |
895 | ||
896 | if (bpw == 8) | |
897 | width = PCH_DMA_WIDTH_1_BYTE; | |
898 | else | |
899 | width = PCH_DMA_WIDTH_2_BYTES; | |
900 | ||
901 | dma = &data->dma; | |
902 | dma_cap_zero(mask); | |
903 | dma_cap_set(DMA_SLAVE, mask); | |
904 | ||
905 | /* Get DMA's dev information */ | |
906 | dma_dev = pci_get_bus_and_slot(2, PCI_DEVFN(12, 0)); | |
907 | ||
908 | /* Set Tx DMA */ | |
909 | param = &dma->param_tx; | |
910 | param->dma_dev = &dma_dev->dev; | |
911 | param->chan_id = data->master->bus_num * 2; /* Tx = 0, 2 */ | |
912 | param->tx_reg = data->io_base_addr + PCH_SPDWR; | |
913 | param->width = width; | |
914 | chan = dma_request_channel(mask, pch_spi_filter, param); | |
915 | if (!chan) { | |
916 | dev_err(&data->master->dev, | |
917 | "ERROR: dma_request_channel FAILS(Tx)\n"); | |
918 | data->use_dma = 0; | |
919 | return; | |
920 | } | |
921 | dma->chan_tx = chan; | |
922 | ||
923 | /* Set Rx DMA */ | |
924 | param = &dma->param_rx; | |
925 | param->dma_dev = &dma_dev->dev; | |
926 | param->chan_id = data->master->bus_num * 2 + 1; /* Rx = Tx + 1 */ | |
927 | param->rx_reg = data->io_base_addr + PCH_SPDRR; | |
928 | param->width = width; | |
929 | chan = dma_request_channel(mask, pch_spi_filter, param); | |
930 | if (!chan) { | |
931 | dev_err(&data->master->dev, | |
932 | "ERROR: dma_request_channel FAILS(Rx)\n"); | |
933 | dma_release_channel(dma->chan_tx); | |
934 | dma->chan_tx = NULL; | |
935 | data->use_dma = 0; | |
936 | return; | |
937 | } | |
938 | dma->chan_rx = chan; | |
939 | } | |
940 | ||
941 | static void pch_spi_release_dma(struct pch_spi_data *data) | |
942 | { | |
943 | struct pch_spi_dma_ctrl *dma; | |
944 | ||
945 | dma = &data->dma; | |
946 | if (dma->chan_tx) { | |
947 | dma_release_channel(dma->chan_tx); | |
948 | dma->chan_tx = NULL; | |
949 | } | |
950 | if (dma->chan_rx) { | |
951 | dma_release_channel(dma->chan_rx); | |
952 | dma->chan_rx = NULL; | |
953 | } | |
954 | return; | |
955 | } | |
956 | ||
957 | static void pch_spi_handle_dma(struct pch_spi_data *data, int *bpw) | |
958 | { | |
959 | const u8 *tx_buf; | |
960 | const u16 *tx_sbuf; | |
961 | u8 *tx_dma_buf; | |
962 | u16 *tx_dma_sbuf; | |
963 | struct scatterlist *sg; | |
964 | struct dma_async_tx_descriptor *desc_tx; | |
965 | struct dma_async_tx_descriptor *desc_rx; | |
966 | int num; | |
967 | int i; | |
968 | int size; | |
969 | int rem; | |
970 | unsigned long flags; | |
971 | struct pch_spi_dma_ctrl *dma; | |
972 | ||
973 | dma = &data->dma; | |
974 | ||
975 | /* set baud rate if needed */ | |
976 | if (data->cur_trans->speed_hz) { | |
977 | dev_dbg(&data->master->dev, "%s:setting baud rate\n", __func__); | |
978 | spin_lock_irqsave(&data->lock, flags); | |
979 | pch_spi_set_baud_rate(data->master, data->cur_trans->speed_hz); | |
980 | spin_unlock_irqrestore(&data->lock, flags); | |
981 | } | |
982 | ||
983 | /* set bits per word if needed */ | |
984 | if (data->cur_trans->bits_per_word && | |
985 | (data->current_msg->spi->bits_per_word != | |
986 | data->cur_trans->bits_per_word)) { | |
987 | dev_dbg(&data->master->dev, "%s:set bits per word\n", __func__); | |
988 | spin_lock_irqsave(&data->lock, flags); | |
989 | pch_spi_set_bits_per_word(data->master, | |
990 | data->cur_trans->bits_per_word); | |
991 | spin_unlock_irqrestore(&data->lock, flags); | |
992 | *bpw = data->cur_trans->bits_per_word; | |
993 | } else { | |
994 | *bpw = data->current_msg->spi->bits_per_word; | |
995 | } | |
996 | data->bpw_len = data->cur_trans->len / (*bpw / 8); | |
997 | ||
998 | /* copy Tx Data */ | |
999 | if (data->cur_trans->tx_buf != NULL) { | |
1000 | if (*bpw == 8) { | |
1001 | tx_buf = data->cur_trans->tx_buf; | |
1002 | tx_dma_buf = dma->tx_buf_virt; | |
1003 | for (i = 0; i < data->bpw_len; i++) | |
1004 | *tx_dma_buf++ = *tx_buf++; | |
1005 | } else { | |
1006 | tx_sbuf = data->cur_trans->tx_buf; | |
1007 | tx_dma_sbuf = dma->tx_buf_virt; | |
1008 | for (i = 0; i < data->bpw_len; i++) | |
1009 | *tx_dma_sbuf++ = *tx_sbuf++; | |
1010 | } | |
1011 | } | |
1012 | if (data->bpw_len > PCH_DMA_TRANS_SIZE) { | |
1013 | num = data->bpw_len / PCH_DMA_TRANS_SIZE + 1; | |
1014 | size = PCH_DMA_TRANS_SIZE; | |
1015 | rem = data->bpw_len % PCH_DMA_TRANS_SIZE; | |
1016 | } else { | |
1017 | num = 1; | |
1018 | size = data->bpw_len; | |
1019 | rem = data->bpw_len; | |
1020 | } | |
1021 | dev_dbg(&data->master->dev, "%s num=%d size=%d rem=%d\n", | |
1022 | __func__, num, size, rem); | |
1023 | spin_lock_irqsave(&data->lock, flags); | |
1024 | ||
1025 | /* set receive fifo threshold and transmit fifo threshold */ | |
1026 | pch_spi_setclr_reg(data->master, PCH_SPCR, | |
1027 | ((size - 1) << SPCR_RFIC_FIELD) | | |
1028 | ((PCH_MAX_FIFO_DEPTH - PCH_DMA_TRANS_SIZE) << | |
1029 | SPCR_TFIC_FIELD), | |
1030 | MASK_RFIC_SPCR_BITS | MASK_TFIC_SPCR_BITS); | |
1031 | ||
1032 | spin_unlock_irqrestore(&data->lock, flags); | |
1033 | ||
1034 | /* RX */ | |
1035 | dma->sg_rx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); | |
1036 | sg_init_table(dma->sg_rx_p, num); /* Initialize SG table */ | |
1037 | /* offset, length setting */ | |
1038 | sg = dma->sg_rx_p; | |
1039 | for (i = 0; i < num; i++, sg++) { | |
1040 | if (i == 0) { | |
1041 | sg->offset = 0; | |
1042 | sg_set_page(sg, virt_to_page(dma->rx_buf_virt), rem, | |
1043 | sg->offset); | |
1044 | sg_dma_len(sg) = rem; | |
1045 | } else { | |
1046 | sg->offset = rem + size * (i - 1); | |
1047 | sg->offset = sg->offset * (*bpw / 8); | |
1048 | sg_set_page(sg, virt_to_page(dma->rx_buf_virt), size, | |
1049 | sg->offset); | |
1050 | sg_dma_len(sg) = size; | |
1051 | } | |
1052 | sg_dma_address(sg) = dma->rx_buf_dma + sg->offset; | |
1053 | } | |
1054 | sg = dma->sg_rx_p; | |
1055 | desc_rx = dma->chan_rx->device->device_prep_slave_sg(dma->chan_rx, sg, | |
1056 | num, DMA_FROM_DEVICE, | |
1057 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1058 | if (!desc_rx) { | |
1059 | dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", | |
1060 | __func__); | |
1061 | return; | |
1062 | } | |
1063 | dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_FROM_DEVICE); | |
1064 | desc_rx->callback = pch_dma_rx_complete; | |
1065 | desc_rx->callback_param = data; | |
1066 | dma->nent = num; | |
1067 | dma->desc_rx = desc_rx; | |
1068 | ||
1069 | /* TX */ | |
1070 | dma->sg_tx_p = kzalloc(sizeof(struct scatterlist)*num, GFP_ATOMIC); | |
1071 | sg_init_table(dma->sg_tx_p, num); /* Initialize SG table */ | |
1072 | /* offset, length setting */ | |
1073 | sg = dma->sg_tx_p; | |
1074 | for (i = 0; i < num; i++, sg++) { | |
1075 | if (i == 0) { | |
1076 | sg->offset = 0; | |
1077 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), rem, | |
1078 | sg->offset); | |
1079 | sg_dma_len(sg) = rem; | |
1080 | } else { | |
1081 | sg->offset = rem + size * (i - 1); | |
1082 | sg->offset = sg->offset * (*bpw / 8); | |
1083 | sg_set_page(sg, virt_to_page(dma->tx_buf_virt), size, | |
1084 | sg->offset); | |
1085 | sg_dma_len(sg) = size; | |
1086 | } | |
1087 | sg_dma_address(sg) = dma->tx_buf_dma + sg->offset; | |
1088 | } | |
1089 | sg = dma->sg_tx_p; | |
1090 | desc_tx = dma->chan_tx->device->device_prep_slave_sg(dma->chan_tx, | |
1091 | sg, num, DMA_TO_DEVICE, | |
1092 | DMA_PREP_INTERRUPT | DMA_CTRL_ACK); | |
1093 | if (!desc_tx) { | |
1094 | dev_err(&data->master->dev, "%s:device_prep_slave_sg Failed\n", | |
1095 | __func__); | |
1096 | return; | |
1097 | } | |
1098 | dma_sync_sg_for_device(&data->master->dev, sg, num, DMA_TO_DEVICE); | |
1099 | desc_tx->callback = NULL; | |
1100 | desc_tx->callback_param = data; | |
1101 | dma->nent = num; | |
1102 | dma->desc_tx = desc_tx; | |
1103 | ||
1104 | dev_dbg(&data->master->dev, "\n%s:Pulling down SSN low - writing " | |
1105 | "0x2 to SSNXCR\n", __func__); | |
1106 | ||
1107 | spin_lock_irqsave(&data->lock, flags); | |
1108 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_LOW); | |
1109 | desc_rx->tx_submit(desc_rx); | |
1110 | desc_tx->tx_submit(desc_tx); | |
1111 | spin_unlock_irqrestore(&data->lock, flags); | |
1112 | ||
1113 | /* reset transfer complete flag */ | |
1114 | data->transfer_complete = false; | |
1115 | } | |
e8b17b5b MO |
1116 | |
1117 | static void pch_spi_process_messages(struct work_struct *pwork) | |
1118 | { | |
1119 | struct spi_message *pmsg; | |
65308c46 | 1120 | struct pch_spi_data *data; |
e8b17b5b MO |
1121 | int bpw; |
1122 | ||
65308c46 | 1123 | data = container_of(pwork, struct pch_spi_data, work); |
8e41b527 | 1124 | dev_dbg(&data->master->dev, "%s data initialized\n", __func__); |
e8b17b5b MO |
1125 | |
1126 | spin_lock(&data->lock); | |
e8b17b5b | 1127 | /* check if suspend has been initiated;if yes flush queue */ |
65308c46 | 1128 | if (data->board_dat->suspend_sts || (data->status == STATUS_EXITING)) { |
c37f3c27 TM |
1129 | dev_dbg(&data->master->dev, "%s suspend/remove initiated," |
1130 | "flushing queue\n", __func__); | |
e8b17b5b MO |
1131 | list_for_each_entry(pmsg, data->queue.next, queue) { |
1132 | pmsg->status = -EIO; | |
1133 | ||
1134 | if (pmsg->complete != 0) { | |
1135 | spin_unlock(&data->lock); | |
1136 | pmsg->complete(pmsg->context); | |
1137 | spin_lock(&data->lock); | |
1138 | } | |
1139 | ||
1140 | /* delete from queue */ | |
1141 | list_del_init(&pmsg->queue); | |
1142 | } | |
1143 | ||
1144 | spin_unlock(&data->lock); | |
1145 | return; | |
1146 | } | |
1147 | ||
1148 | data->bcurrent_msg_processing = true; | |
1149 | dev_dbg(&data->master->dev, | |
1150 | "%s Set data->bcurrent_msg_processing= true\n", __func__); | |
1151 | ||
1152 | /* Get the message from the queue and delete it from there. */ | |
65308c46 GL |
1153 | data->current_msg = list_entry(data->queue.next, struct spi_message, |
1154 | queue); | |
e8b17b5b MO |
1155 | |
1156 | list_del_init(&data->current_msg->queue); | |
1157 | ||
1158 | data->current_msg->status = 0; | |
1159 | ||
1160 | pch_spi_select_chip(data, data->current_msg->spi); | |
1161 | ||
1162 | spin_unlock(&data->lock); | |
1163 | ||
c37f3c27 TM |
1164 | if (data->use_dma) |
1165 | pch_spi_request_dma(data, | |
1166 | data->current_msg->spi->bits_per_word); | |
8b7aa961 | 1167 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_NO_CONTROL); |
e8b17b5b MO |
1168 | do { |
1169 | /* If we are already processing a message get the next | |
1170 | transfer structure from the message otherwise retrieve | |
1171 | the 1st transfer request from the message. */ | |
1172 | spin_lock(&data->lock); | |
e8b17b5b MO |
1173 | if (data->cur_trans == NULL) { |
1174 | data->cur_trans = | |
c37f3c27 TM |
1175 | list_entry(data->current_msg->transfers.next, |
1176 | struct spi_transfer, transfer_list); | |
1177 | dev_dbg(&data->master->dev, "%s " | |
1178 | ":Getting 1st transfer message\n", __func__); | |
e8b17b5b MO |
1179 | } else { |
1180 | data->cur_trans = | |
c37f3c27 TM |
1181 | list_entry(data->cur_trans->transfer_list.next, |
1182 | struct spi_transfer, transfer_list); | |
1183 | dev_dbg(&data->master->dev, "%s " | |
1184 | ":Getting next transfer message\n", __func__); | |
e8b17b5b | 1185 | } |
e8b17b5b MO |
1186 | spin_unlock(&data->lock); |
1187 | ||
c37f3c27 TM |
1188 | if (data->use_dma) { |
1189 | pch_spi_handle_dma(data, &bpw); | |
1190 | pch_spi_start_transfer(data); | |
1191 | pch_spi_copy_rx_data_for_dma(data, bpw); | |
1192 | } else { | |
1193 | pch_spi_set_tx(data, &bpw); | |
1194 | pch_spi_set_ir(data); | |
1195 | pch_spi_copy_rx_data(data, bpw); | |
1196 | kfree(data->pkt_rx_buff); | |
1197 | data->pkt_rx_buff = NULL; | |
1198 | kfree(data->pkt_tx_buff); | |
1199 | data->pkt_tx_buff = NULL; | |
1200 | } | |
e8b17b5b MO |
1201 | /* increment message count */ |
1202 | data->current_msg->actual_length += data->cur_trans->len; | |
1203 | ||
1204 | dev_dbg(&data->master->dev, | |
1205 | "%s:data->current_msg->actual_length=%d\n", | |
1206 | __func__, data->current_msg->actual_length); | |
1207 | ||
1208 | /* check for delay */ | |
1209 | if (data->cur_trans->delay_usecs) { | |
1210 | dev_dbg(&data->master->dev, "%s:" | |
1211 | "delay in usec=%d\n", __func__, | |
1212 | data->cur_trans->delay_usecs); | |
1213 | udelay(data->cur_trans->delay_usecs); | |
1214 | } | |
1215 | ||
1216 | spin_lock(&data->lock); | |
1217 | ||
1218 | /* No more transfer in this message. */ | |
1219 | if ((data->cur_trans->transfer_list.next) == | |
1220 | &(data->current_msg->transfers)) { | |
c37f3c27 | 1221 | pch_spi_nomore_transfer(data); |
e8b17b5b MO |
1222 | } |
1223 | ||
1224 | spin_unlock(&data->lock); | |
1225 | ||
65308c46 | 1226 | } while (data->cur_trans != NULL); |
c37f3c27 | 1227 | |
8b7aa961 | 1228 | pch_spi_writereg(data->master, PCH_SSNXCR, SSN_HIGH); |
c37f3c27 TM |
1229 | if (data->use_dma) |
1230 | pch_spi_release_dma(data); | |
e8b17b5b MO |
1231 | } |
1232 | ||
f016aeb6 TM |
1233 | static void pch_spi_free_resources(struct pch_spi_board_data *board_dat, |
1234 | struct pch_spi_data *data) | |
e8b17b5b MO |
1235 | { |
1236 | dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); | |
1237 | ||
1238 | /* free workqueue */ | |
f016aeb6 TM |
1239 | if (data->wk != NULL) { |
1240 | destroy_workqueue(data->wk); | |
1241 | data->wk = NULL; | |
e8b17b5b MO |
1242 | dev_dbg(&board_dat->pdev->dev, |
1243 | "%s destroy_workqueue invoked successfully\n", | |
1244 | __func__); | |
1245 | } | |
e8b17b5b MO |
1246 | } |
1247 | ||
f016aeb6 TM |
1248 | static int pch_spi_get_resources(struct pch_spi_board_data *board_dat, |
1249 | struct pch_spi_data *data) | |
e8b17b5b | 1250 | { |
f016aeb6 TM |
1251 | int retval = 0; |
1252 | ||
e8b17b5b MO |
1253 | dev_dbg(&board_dat->pdev->dev, "%s ENTRY\n", __func__); |
1254 | ||
e8b17b5b | 1255 | /* create workqueue */ |
f016aeb6 TM |
1256 | data->wk = create_singlethread_workqueue(KBUILD_MODNAME); |
1257 | if (!data->wk) { | |
e8b17b5b MO |
1258 | dev_err(&board_dat->pdev->dev, |
1259 | "%s create_singlet hread_workqueue failed\n", __func__); | |
1260 | retval = -EBUSY; | |
1261 | goto err_return; | |
1262 | } | |
1263 | ||
e8b17b5b | 1264 | /* reset PCH SPI h/w */ |
f016aeb6 | 1265 | pch_spi_reset(data->master); |
e8b17b5b MO |
1266 | dev_dbg(&board_dat->pdev->dev, |
1267 | "%s pch_spi_reset invoked successfully\n", __func__); | |
1268 | ||
65308c46 | 1269 | dev_dbg(&board_dat->pdev->dev, "%s data->irq_reg_sts=true\n", __func__); |
e8b17b5b MO |
1270 | |
1271 | err_return: | |
1272 | if (retval != 0) { | |
1273 | dev_err(&board_dat->pdev->dev, | |
1274 | "%s FAIL:invoking pch_spi_free_resources\n", __func__); | |
f016aeb6 | 1275 | pch_spi_free_resources(board_dat, data); |
e8b17b5b MO |
1276 | } |
1277 | ||
1278 | dev_dbg(&board_dat->pdev->dev, "%s Return=%d\n", __func__, retval); | |
1279 | ||
1280 | return retval; | |
1281 | } | |
1282 | ||
c37f3c27 TM |
1283 | static void pch_free_dma_buf(struct pch_spi_board_data *board_dat, |
1284 | struct pch_spi_data *data) | |
1285 | { | |
1286 | struct pch_spi_dma_ctrl *dma; | |
1287 | ||
1288 | dma = &data->dma; | |
1289 | if (dma->tx_buf_dma) | |
1290 | dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, | |
1291 | dma->tx_buf_virt, dma->tx_buf_dma); | |
1292 | if (dma->rx_buf_dma) | |
1293 | dma_free_coherent(&board_dat->pdev->dev, PCH_BUF_SIZE, | |
1294 | dma->rx_buf_virt, dma->rx_buf_dma); | |
1295 | return; | |
1296 | } | |
1297 | ||
1298 | static void pch_alloc_dma_buf(struct pch_spi_board_data *board_dat, | |
1299 | struct pch_spi_data *data) | |
1300 | { | |
1301 | struct pch_spi_dma_ctrl *dma; | |
1302 | ||
1303 | dma = &data->dma; | |
1304 | /* Get Consistent memory for Tx DMA */ | |
1305 | dma->tx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, | |
1306 | PCH_BUF_SIZE, &dma->tx_buf_dma, GFP_KERNEL); | |
1307 | /* Get Consistent memory for Rx DMA */ | |
1308 | dma->rx_buf_virt = dma_alloc_coherent(&board_dat->pdev->dev, | |
1309 | PCH_BUF_SIZE, &dma->rx_buf_dma, GFP_KERNEL); | |
1310 | } | |
1311 | ||
f016aeb6 | 1312 | static int __devinit pch_spi_pd_probe(struct platform_device *plat_dev) |
e8b17b5b | 1313 | { |
f016aeb6 | 1314 | int ret; |
e8b17b5b | 1315 | struct spi_master *master; |
f016aeb6 TM |
1316 | struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); |
1317 | struct pch_spi_data *data; | |
e8b17b5b | 1318 | |
c37f3c27 TM |
1319 | dev_dbg(&plat_dev->dev, "%s:debug\n", __func__); |
1320 | ||
f016aeb6 TM |
1321 | master = spi_alloc_master(&board_dat->pdev->dev, |
1322 | sizeof(struct pch_spi_data)); | |
1323 | if (!master) { | |
1324 | dev_err(&plat_dev->dev, "spi_alloc_master[%d] failed.\n", | |
1325 | plat_dev->id); | |
1326 | return -ENOMEM; | |
e8b17b5b MO |
1327 | } |
1328 | ||
f016aeb6 TM |
1329 | data = spi_master_get_devdata(master); |
1330 | data->master = master; | |
e8b17b5b | 1331 | |
f016aeb6 | 1332 | platform_set_drvdata(plat_dev, data); |
e8b17b5b | 1333 | |
c37f3c27 TM |
1334 | /* baseaddress + address offset) */ |
1335 | data->io_base_addr = pci_resource_start(board_dat->pdev, 1) + | |
1336 | PCH_ADDRESS_SIZE * plat_dev->id; | |
f016aeb6 | 1337 | data->io_remap_addr = pci_iomap(board_dat->pdev, 1, 0) + |
c37f3c27 | 1338 | PCH_ADDRESS_SIZE * plat_dev->id; |
f016aeb6 TM |
1339 | if (!data->io_remap_addr) { |
1340 | dev_err(&plat_dev->dev, "%s pci_iomap failed\n", __func__); | |
1341 | ret = -ENOMEM; | |
1342 | goto err_pci_iomap; | |
e8b17b5b MO |
1343 | } |
1344 | ||
f016aeb6 TM |
1345 | dev_dbg(&plat_dev->dev, "[ch%d] remap_addr=%p\n", |
1346 | plat_dev->id, data->io_remap_addr); | |
e8b17b5b MO |
1347 | |
1348 | /* initialize members of SPI master */ | |
1349 | master->bus_num = -1; | |
1350 | master->num_chipselect = PCH_MAX_CS; | |
1351 | master->setup = pch_spi_setup; | |
1352 | master->transfer = pch_spi_transfer; | |
e8b17b5b | 1353 | |
f016aeb6 TM |
1354 | data->board_dat = board_dat; |
1355 | data->plat_dev = plat_dev; | |
1356 | data->n_curnt_chip = 255; | |
1357 | data->status = STATUS_RUNNING; | |
1358 | data->ch = plat_dev->id; | |
c37f3c27 | 1359 | data->use_dma = use_dma; |
e8b17b5b | 1360 | |
f016aeb6 TM |
1361 | INIT_LIST_HEAD(&data->queue); |
1362 | spin_lock_init(&data->lock); | |
1363 | INIT_WORK(&data->work, pch_spi_process_messages); | |
1364 | init_waitqueue_head(&data->wait); | |
65308c46 | 1365 | |
f016aeb6 TM |
1366 | ret = pch_spi_get_resources(board_dat, data); |
1367 | if (ret) { | |
1368 | dev_err(&plat_dev->dev, "%s fail(retval=%d)\n", __func__, ret); | |
e8b17b5b MO |
1369 | goto err_spi_get_resources; |
1370 | } | |
1371 | ||
f016aeb6 TM |
1372 | ret = request_irq(board_dat->pdev->irq, pch_spi_handler, |
1373 | IRQF_SHARED, KBUILD_MODNAME, data); | |
1374 | if (ret) { | |
1375 | dev_err(&plat_dev->dev, | |
1376 | "%s request_irq failed\n", __func__); | |
1377 | goto err_request_irq; | |
1378 | } | |
1379 | data->irq_reg_sts = true; | |
e8b17b5b | 1380 | |
e8b17b5b | 1381 | pch_spi_set_master_mode(master); |
e8b17b5b | 1382 | |
f016aeb6 TM |
1383 | ret = spi_register_master(master); |
1384 | if (ret != 0) { | |
1385 | dev_err(&plat_dev->dev, | |
e8b17b5b | 1386 | "%s spi_register_master FAILED\n", __func__); |
f016aeb6 | 1387 | goto err_spi_register_master; |
e8b17b5b MO |
1388 | } |
1389 | ||
c37f3c27 TM |
1390 | if (use_dma) { |
1391 | dev_info(&plat_dev->dev, "Use DMA for data transfers\n"); | |
1392 | pch_alloc_dma_buf(board_dat, data); | |
1393 | } | |
1394 | ||
e8b17b5b MO |
1395 | return 0; |
1396 | ||
f016aeb6 TM |
1397 | err_spi_register_master: |
1398 | free_irq(board_dat->pdev->irq, board_dat); | |
1399 | err_request_irq: | |
1400 | pch_spi_free_resources(board_dat, data); | |
e8b17b5b | 1401 | err_spi_get_resources: |
f016aeb6 TM |
1402 | pci_iounmap(board_dat->pdev, data->io_remap_addr); |
1403 | err_pci_iomap: | |
e8b17b5b | 1404 | spi_master_put(master); |
f016aeb6 TM |
1405 | |
1406 | return ret; | |
e8b17b5b MO |
1407 | } |
1408 | ||
f016aeb6 | 1409 | static int __devexit pch_spi_pd_remove(struct platform_device *plat_dev) |
e8b17b5b | 1410 | { |
f016aeb6 TM |
1411 | struct pch_spi_board_data *board_dat = dev_get_platdata(&plat_dev->dev); |
1412 | struct pch_spi_data *data = platform_get_drvdata(plat_dev); | |
65308c46 | 1413 | int count; |
c37f3c27 | 1414 | unsigned long flags; |
e8b17b5b | 1415 | |
f016aeb6 TM |
1416 | dev_dbg(&plat_dev->dev, "%s:[ch%d] irq=%d\n", |
1417 | __func__, plat_dev->id, board_dat->pdev->irq); | |
c37f3c27 TM |
1418 | |
1419 | if (use_dma) | |
1420 | pch_free_dma_buf(board_dat, data); | |
1421 | ||
65308c46 GL |
1422 | /* check for any pending messages; no action is taken if the queue |
1423 | * is still full; but at least we tried. Unload anyway */ | |
1424 | count = 500; | |
c37f3c27 | 1425 | spin_lock_irqsave(&data->lock, flags); |
f016aeb6 TM |
1426 | data->status = STATUS_EXITING; |
1427 | while ((list_empty(&data->queue) == 0) && --count) { | |
65308c46 GL |
1428 | dev_dbg(&board_dat->pdev->dev, "%s :queue not empty\n", |
1429 | __func__); | |
c37f3c27 | 1430 | spin_unlock_irqrestore(&data->lock, flags); |
65308c46 | 1431 | msleep(PCH_SLEEP_TIME); |
c37f3c27 | 1432 | spin_lock_irqsave(&data->lock, flags); |
e8b17b5b | 1433 | } |
c37f3c27 | 1434 | spin_unlock_irqrestore(&data->lock, flags); |
e8b17b5b | 1435 | |
f016aeb6 TM |
1436 | pch_spi_free_resources(board_dat, data); |
1437 | /* disable interrupts & free IRQ */ | |
1438 | if (data->irq_reg_sts) { | |
1439 | /* disable interrupts */ | |
1440 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); | |
1441 | data->irq_reg_sts = false; | |
1442 | free_irq(board_dat->pdev->irq, data); | |
1443 | } | |
e8b17b5b | 1444 | |
f016aeb6 TM |
1445 | pci_iounmap(board_dat->pdev, data->io_remap_addr); |
1446 | spi_unregister_master(data->master); | |
1447 | spi_master_put(data->master); | |
1448 | platform_set_drvdata(plat_dev, NULL); | |
e8b17b5b | 1449 | |
f016aeb6 | 1450 | return 0; |
e8b17b5b | 1451 | } |
e8b17b5b | 1452 | #ifdef CONFIG_PM |
f016aeb6 TM |
1453 | static int pch_spi_pd_suspend(struct platform_device *pd_dev, |
1454 | pm_message_t state) | |
e8b17b5b MO |
1455 | { |
1456 | u8 count; | |
f016aeb6 TM |
1457 | struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); |
1458 | struct pch_spi_data *data = platform_get_drvdata(pd_dev); | |
e8b17b5b | 1459 | |
f016aeb6 | 1460 | dev_dbg(&pd_dev->dev, "%s ENTRY\n", __func__); |
e8b17b5b MO |
1461 | |
1462 | if (!board_dat) { | |
f016aeb6 | 1463 | dev_err(&pd_dev->dev, |
e8b17b5b MO |
1464 | "%s pci_get_drvdata returned NULL\n", __func__); |
1465 | return -EFAULT; | |
1466 | } | |
1467 | ||
e8b17b5b MO |
1468 | /* check if the current message is processed: |
1469 | Only after thats done the transfer will be suspended */ | |
1470 | count = 255; | |
c37f3c27 TM |
1471 | while ((--count) > 0) { |
1472 | if (!(data->bcurrent_msg_processing)) | |
e8b17b5b | 1473 | break; |
e8b17b5b MO |
1474 | msleep(PCH_SLEEP_TIME); |
1475 | } | |
1476 | ||
1477 | /* Free IRQ */ | |
f016aeb6 | 1478 | if (data->irq_reg_sts) { |
e8b17b5b | 1479 | /* disable all interrupts */ |
f016aeb6 TM |
1480 | pch_spi_setclr_reg(data->master, PCH_SPCR, 0, PCH_ALL); |
1481 | pch_spi_reset(data->master); | |
1482 | free_irq(board_dat->pdev->irq, data); | |
e8b17b5b | 1483 | |
f016aeb6 TM |
1484 | data->irq_reg_sts = false; |
1485 | dev_dbg(&pd_dev->dev, | |
e8b17b5b MO |
1486 | "%s free_irq invoked successfully.\n", __func__); |
1487 | } | |
1488 | ||
f016aeb6 TM |
1489 | return 0; |
1490 | } | |
1491 | ||
1492 | static int pch_spi_pd_resume(struct platform_device *pd_dev) | |
1493 | { | |
1494 | struct pch_spi_board_data *board_dat = dev_get_platdata(&pd_dev->dev); | |
1495 | struct pch_spi_data *data = platform_get_drvdata(pd_dev); | |
1496 | int retval; | |
1497 | ||
1498 | if (!board_dat) { | |
1499 | dev_err(&pd_dev->dev, | |
1500 | "%s pci_get_drvdata returned NULL\n", __func__); | |
1501 | return -EFAULT; | |
1502 | } | |
1503 | ||
1504 | if (!data->irq_reg_sts) { | |
1505 | /* register IRQ */ | |
1506 | retval = request_irq(board_dat->pdev->irq, pch_spi_handler, | |
1507 | IRQF_SHARED, KBUILD_MODNAME, data); | |
1508 | if (retval < 0) { | |
1509 | dev_err(&pd_dev->dev, | |
1510 | "%s request_irq failed\n", __func__); | |
1511 | return retval; | |
1512 | } | |
1513 | ||
1514 | /* reset PCH SPI h/w */ | |
1515 | pch_spi_reset(data->master); | |
1516 | pch_spi_set_master_mode(data->master); | |
1517 | data->irq_reg_sts = true; | |
1518 | } | |
1519 | return 0; | |
1520 | } | |
1521 | #else | |
1522 | #define pch_spi_pd_suspend NULL | |
1523 | #define pch_spi_pd_resume NULL | |
1524 | #endif | |
1525 | ||
1526 | static struct platform_driver pch_spi_pd_driver = { | |
1527 | .driver = { | |
1528 | .name = "pch-spi", | |
1529 | .owner = THIS_MODULE, | |
1530 | }, | |
1531 | .probe = pch_spi_pd_probe, | |
1532 | .remove = __devexit_p(pch_spi_pd_remove), | |
1533 | .suspend = pch_spi_pd_suspend, | |
1534 | .resume = pch_spi_pd_resume | |
1535 | }; | |
1536 | ||
1537 | static int __devinit pch_spi_probe(struct pci_dev *pdev, | |
1538 | const struct pci_device_id *id) | |
1539 | { | |
1540 | struct pch_spi_board_data *board_dat; | |
1541 | struct platform_device *pd_dev = NULL; | |
1542 | int retval; | |
1543 | int i; | |
1544 | struct pch_pd_dev_save *pd_dev_save; | |
1545 | ||
1546 | pd_dev_save = kzalloc(sizeof(struct pch_pd_dev_save), GFP_KERNEL); | |
1547 | if (!pd_dev_save) { | |
1548 | dev_err(&pdev->dev, "%s Can't allocate pd_dev_sav\n", __func__); | |
1549 | return -ENOMEM; | |
1550 | } | |
1551 | ||
1552 | board_dat = kzalloc(sizeof(struct pch_spi_board_data), GFP_KERNEL); | |
1553 | if (!board_dat) { | |
1554 | dev_err(&pdev->dev, "%s Can't allocate board_dat\n", __func__); | |
1555 | retval = -ENOMEM; | |
1556 | goto err_no_mem; | |
1557 | } | |
1558 | ||
1559 | retval = pci_request_regions(pdev, KBUILD_MODNAME); | |
1560 | if (retval) { | |
1561 | dev_err(&pdev->dev, "%s request_region failed\n", __func__); | |
1562 | goto pci_request_regions; | |
1563 | } | |
1564 | ||
1565 | board_dat->pdev = pdev; | |
1566 | board_dat->num = id->driver_data; | |
1567 | pd_dev_save->num = id->driver_data; | |
1568 | pd_dev_save->board_dat = board_dat; | |
1569 | ||
1570 | retval = pci_enable_device(pdev); | |
1571 | if (retval) { | |
1572 | dev_err(&pdev->dev, "%s pci_enable_device failed\n", __func__); | |
1573 | goto pci_enable_device; | |
1574 | } | |
1575 | ||
1576 | for (i = 0; i < board_dat->num; i++) { | |
1577 | pd_dev = platform_device_alloc("pch-spi", i); | |
1578 | if (!pd_dev) { | |
1579 | dev_err(&pdev->dev, "platform_device_alloc failed\n"); | |
1580 | goto err_platform_device; | |
1581 | } | |
1582 | pd_dev_save->pd_save[i] = pd_dev; | |
1583 | pd_dev->dev.parent = &pdev->dev; | |
1584 | ||
1585 | retval = platform_device_add_data(pd_dev, board_dat, | |
1586 | sizeof(*board_dat)); | |
1587 | if (retval) { | |
1588 | dev_err(&pdev->dev, | |
1589 | "platform_device_add_data failed\n"); | |
1590 | platform_device_put(pd_dev); | |
1591 | goto err_platform_device; | |
1592 | } | |
1593 | ||
1594 | retval = platform_device_add(pd_dev); | |
1595 | if (retval) { | |
1596 | dev_err(&pdev->dev, "platform_device_add failed\n"); | |
1597 | platform_device_put(pd_dev); | |
1598 | goto err_platform_device; | |
1599 | } | |
1600 | } | |
1601 | ||
1602 | pci_set_drvdata(pdev, pd_dev_save); | |
1603 | ||
1604 | return 0; | |
1605 | ||
1606 | err_platform_device: | |
1607 | pci_disable_device(pdev); | |
1608 | pci_enable_device: | |
1609 | pci_release_regions(pdev); | |
1610 | pci_request_regions: | |
1611 | kfree(board_dat); | |
1612 | err_no_mem: | |
1613 | kfree(pd_dev_save); | |
1614 | ||
1615 | return retval; | |
1616 | } | |
1617 | ||
1618 | static void __devexit pch_spi_remove(struct pci_dev *pdev) | |
1619 | { | |
1620 | int i; | |
1621 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); | |
1622 | ||
1623 | dev_dbg(&pdev->dev, "%s ENTRY:pdev=%p\n", __func__, pdev); | |
1624 | ||
1625 | for (i = 0; i < pd_dev_save->num; i++) | |
1626 | platform_device_unregister(pd_dev_save->pd_save[i]); | |
1627 | ||
1628 | pci_disable_device(pdev); | |
1629 | pci_release_regions(pdev); | |
1630 | kfree(pd_dev_save->board_dat); | |
1631 | kfree(pd_dev_save); | |
1632 | } | |
1633 | ||
1634 | #ifdef CONFIG_PM | |
1635 | static int pch_spi_suspend(struct pci_dev *pdev, pm_message_t state) | |
1636 | { | |
1637 | int retval; | |
1638 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); | |
1639 | ||
1640 | dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); | |
1641 | ||
1642 | pd_dev_save->board_dat->suspend_sts = true; | |
1643 | ||
e8b17b5b MO |
1644 | /* save config space */ |
1645 | retval = pci_save_state(pdev); | |
e8b17b5b | 1646 | if (retval == 0) { |
e8b17b5b | 1647 | pci_enable_wake(pdev, PCI_D3hot, 0); |
e8b17b5b | 1648 | pci_disable_device(pdev); |
e8b17b5b | 1649 | pci_set_power_state(pdev, PCI_D3hot); |
e8b17b5b MO |
1650 | } else { |
1651 | dev_err(&pdev->dev, "%s pci_save_state failed\n", __func__); | |
1652 | } | |
1653 | ||
e8b17b5b MO |
1654 | return retval; |
1655 | } | |
1656 | ||
1657 | static int pch_spi_resume(struct pci_dev *pdev) | |
1658 | { | |
1659 | int retval; | |
f016aeb6 | 1660 | struct pch_pd_dev_save *pd_dev_save = pci_get_drvdata(pdev); |
e8b17b5b MO |
1661 | dev_dbg(&pdev->dev, "%s ENTRY\n", __func__); |
1662 | ||
e8b17b5b | 1663 | pci_set_power_state(pdev, PCI_D0); |
e8b17b5b MO |
1664 | pci_restore_state(pdev); |
1665 | ||
1666 | retval = pci_enable_device(pdev); | |
1667 | if (retval < 0) { | |
1668 | dev_err(&pdev->dev, | |
1669 | "%s pci_enable_device failed\n", __func__); | |
1670 | } else { | |
e8b17b5b MO |
1671 | pci_enable_wake(pdev, PCI_D3hot, 0); |
1672 | ||
f016aeb6 TM |
1673 | /* set suspend status to false */ |
1674 | pd_dev_save->board_dat->suspend_sts = false; | |
e8b17b5b MO |
1675 | } |
1676 | ||
e8b17b5b MO |
1677 | return retval; |
1678 | } | |
1679 | #else | |
1680 | #define pch_spi_suspend NULL | |
1681 | #define pch_spi_resume NULL | |
1682 | ||
1683 | #endif | |
1684 | ||
1685 | static struct pci_driver pch_spi_pcidev = { | |
1686 | .name = "pch_spi", | |
1687 | .id_table = pch_spi_pcidev_id, | |
1688 | .probe = pch_spi_probe, | |
1689 | .remove = pch_spi_remove, | |
1690 | .suspend = pch_spi_suspend, | |
1691 | .resume = pch_spi_resume, | |
1692 | }; | |
1693 | ||
1694 | static int __init pch_spi_init(void) | |
1695 | { | |
f016aeb6 TM |
1696 | int ret; |
1697 | ret = platform_driver_register(&pch_spi_pd_driver); | |
1698 | if (ret) | |
1699 | return ret; | |
1700 | ||
1701 | ret = pci_register_driver(&pch_spi_pcidev); | |
1702 | if (ret) | |
1703 | return ret; | |
1704 | ||
1705 | return 0; | |
e8b17b5b MO |
1706 | } |
1707 | module_init(pch_spi_init); | |
1708 | ||
e8b17b5b MO |
1709 | static void __exit pch_spi_exit(void) |
1710 | { | |
1711 | pci_unregister_driver(&pch_spi_pcidev); | |
f016aeb6 | 1712 | platform_driver_unregister(&pch_spi_pd_driver); |
e8b17b5b MO |
1713 | } |
1714 | module_exit(pch_spi_exit); | |
1715 | ||
c37f3c27 TM |
1716 | module_param(use_dma, int, 0644); |
1717 | MODULE_PARM_DESC(use_dma, | |
1718 | "to use DMA for data transfers pass 1 else 0; default 1"); | |
1719 | ||
e8b17b5b | 1720 | MODULE_LICENSE("GPL"); |
2e2de2e3 | 1721 | MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR ML7xxx IOH SPI Driver"); |