Commit | Line | Data |
---|---|---|
ae918c02 | 1 | /* |
ae918c02 AK |
2 | * Xilinx SPI controller driver (master mode only) |
3 | * | |
4 | * Author: MontaVista Software, Inc. | |
5 | * source@mvista.com | |
6 | * | |
8fd8821b GL |
7 | * Copyright (c) 2010 Secret Lab Technologies, Ltd. |
8 | * Copyright (c) 2009 Intel Corporation | |
9 | * 2002-2007 (c) MontaVista Software, Inc. | |
10 | ||
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
ae918c02 AK |
14 | */ |
15 | ||
16 | #include <linux/module.h> | |
ae918c02 | 17 | #include <linux/interrupt.h> |
eae6cb31 | 18 | #include <linux/of.h> |
8fd8821b | 19 | #include <linux/platform_device.h> |
ae918c02 AK |
20 | #include <linux/spi/spi.h> |
21 | #include <linux/spi/spi_bitbang.h> | |
d5af91a1 | 22 | #include <linux/spi/xilinx_spi.h> |
eae6cb31 | 23 | #include <linux/io.h> |
d5af91a1 | 24 | |
eb25f16c RR |
25 | #define XILINX_SPI_MAX_CS 32 |
26 | ||
fc3ba952 | 27 | #define XILINX_SPI_NAME "xilinx_spi" |
ae918c02 AK |
28 | |
29 | /* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e) | |
30 | * Product Specification", DS464 | |
31 | */ | |
c9da2e12 | 32 | #define XSPI_CR_OFFSET 0x60 /* Control Register */ |
ae918c02 | 33 | |
082339bc | 34 | #define XSPI_CR_LOOP 0x01 |
ae918c02 AK |
35 | #define XSPI_CR_ENABLE 0x02 |
36 | #define XSPI_CR_MASTER_MODE 0x04 | |
37 | #define XSPI_CR_CPOL 0x08 | |
38 | #define XSPI_CR_CPHA 0x10 | |
bca690db | 39 | #define XSPI_CR_MODE_MASK (XSPI_CR_CPHA | XSPI_CR_CPOL | \ |
0240f945 | 40 | XSPI_CR_LSB_FIRST | XSPI_CR_LOOP) |
ae918c02 AK |
41 | #define XSPI_CR_TXFIFO_RESET 0x20 |
42 | #define XSPI_CR_RXFIFO_RESET 0x40 | |
43 | #define XSPI_CR_MANUAL_SSELECT 0x80 | |
44 | #define XSPI_CR_TRANS_INHIBIT 0x100 | |
c9da2e12 | 45 | #define XSPI_CR_LSB_FIRST 0x200 |
ae918c02 | 46 | |
c9da2e12 | 47 | #define XSPI_SR_OFFSET 0x64 /* Status Register */ |
ae918c02 AK |
48 | |
49 | #define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */ | |
50 | #define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */ | |
51 | #define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */ | |
52 | #define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */ | |
53 | #define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */ | |
54 | ||
c9da2e12 RR |
55 | #define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */ |
56 | #define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */ | |
ae918c02 AK |
57 | |
58 | #define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */ | |
59 | ||
60 | /* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414 | |
61 | * IPIF registers are 32 bit | |
62 | */ | |
63 | #define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */ | |
64 | #define XIPIF_V123B_GINTR_ENABLE 0x80000000 | |
65 | ||
66 | #define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */ | |
67 | #define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */ | |
68 | ||
69 | #define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */ | |
70 | #define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while | |
71 | * disabled */ | |
72 | #define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */ | |
73 | #define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */ | |
74 | #define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */ | |
75 | #define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */ | |
c9da2e12 | 76 | #define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */ |
ae918c02 AK |
77 | |
78 | #define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */ | |
79 | #define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */ | |
80 | ||
81 | struct xilinx_spi { | |
82 | /* bitbang has to be first */ | |
83 | struct spi_bitbang bitbang; | |
84 | struct completion done; | |
ae918c02 AK |
85 | void __iomem *regs; /* virt. address of the control registers */ |
86 | ||
9ca1273b | 87 | int irq; |
ae918c02 | 88 | |
ae918c02 AK |
89 | u8 *rx_ptr; /* pointer in the Tx buffer */ |
90 | const u8 *tx_ptr; /* pointer in the Rx buffer */ | |
17aaaa80 | 91 | u8 bytes_per_word; |
4c9a7614 | 92 | int buffer_size; /* buffer size in words */ |
f9c6ef6c | 93 | u32 cs_inactive; /* Level of the CS pins when inactive*/ |
6ff8672a JH |
94 | unsigned int (*read_fn)(void __iomem *); |
95 | void (*write_fn)(u32, void __iomem *); | |
ae918c02 AK |
96 | }; |
97 | ||
0635287a MB |
98 | static void xspi_write32(u32 val, void __iomem *addr) |
99 | { | |
100 | iowrite32(val, addr); | |
101 | } | |
102 | ||
103 | static unsigned int xspi_read32(void __iomem *addr) | |
104 | { | |
105 | return ioread32(addr); | |
106 | } | |
107 | ||
108 | static void xspi_write32_be(u32 val, void __iomem *addr) | |
109 | { | |
110 | iowrite32be(val, addr); | |
111 | } | |
112 | ||
113 | static unsigned int xspi_read32_be(void __iomem *addr) | |
114 | { | |
115 | return ioread32be(addr); | |
116 | } | |
117 | ||
24ba5e59 | 118 | static void xilinx_spi_tx(struct xilinx_spi *xspi) |
c9da2e12 | 119 | { |
34093cb9 RRD |
120 | u32 data = 0; |
121 | ||
c3092941 RRD |
122 | if (!xspi->tx_ptr) { |
123 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
124 | return; | |
125 | } | |
34093cb9 RRD |
126 | |
127 | switch (xspi->bytes_per_word) { | |
128 | case 1: | |
129 | data = *(u8 *)(xspi->tx_ptr); | |
130 | break; | |
131 | case 2: | |
132 | data = *(u16 *)(xspi->tx_ptr); | |
133 | break; | |
134 | case 4: | |
135 | data = *(u32 *)(xspi->tx_ptr); | |
136 | break; | |
137 | } | |
138 | ||
139 | xspi->write_fn(data, xspi->regs + XSPI_TXD_OFFSET); | |
17aaaa80 | 140 | xspi->tx_ptr += xspi->bytes_per_word; |
c9da2e12 RR |
141 | } |
142 | ||
24ba5e59 | 143 | static void xilinx_spi_rx(struct xilinx_spi *xspi) |
c9da2e12 RR |
144 | { |
145 | u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET); | |
c9da2e12 | 146 | |
24ba5e59 RRD |
147 | if (!xspi->rx_ptr) |
148 | return; | |
c9da2e12 | 149 | |
17aaaa80 RRD |
150 | switch (xspi->bytes_per_word) { |
151 | case 1: | |
24ba5e59 RRD |
152 | *(u8 *)(xspi->rx_ptr) = data; |
153 | break; | |
17aaaa80 | 154 | case 2: |
24ba5e59 RRD |
155 | *(u16 *)(xspi->rx_ptr) = data; |
156 | break; | |
17aaaa80 | 157 | case 4: |
c9da2e12 | 158 | *(u32 *)(xspi->rx_ptr) = data; |
24ba5e59 | 159 | break; |
c9da2e12 | 160 | } |
24ba5e59 | 161 | |
17aaaa80 | 162 | xspi->rx_ptr += xspi->bytes_per_word; |
c9da2e12 RR |
163 | } |
164 | ||
86fc5935 | 165 | static void xspi_init_hw(struct xilinx_spi *xspi) |
ae918c02 | 166 | { |
86fc5935 RR |
167 | void __iomem *regs_base = xspi->regs; |
168 | ||
ae918c02 | 169 | /* Reset the SPI device */ |
86fc5935 RR |
170 | xspi->write_fn(XIPIF_V123B_RESET_MASK, |
171 | regs_base + XIPIF_V123B_RESETR_OFFSET); | |
899929ba RRD |
172 | /* Enable the transmit empty interrupt, which we use to determine |
173 | * progress on the transmission. | |
174 | */ | |
175 | xspi->write_fn(XSPI_INTR_TX_EMPTY, | |
176 | regs_base + XIPIF_V123B_IIER_OFFSET); | |
22417352 RRD |
177 | /* Disable the global IPIF interrupt */ |
178 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ae918c02 | 179 | /* Deselect the slave on the SPI bus */ |
86fc5935 | 180 | xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET); |
ae918c02 AK |
181 | /* Disable the transmitter, enable Manual Slave Select Assertion, |
182 | * put SPI controller into master mode, and enable it */ | |
22417352 RRD |
183 | xspi->write_fn(XSPI_CR_MANUAL_SSELECT | XSPI_CR_MASTER_MODE | |
184 | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET | XSPI_CR_RXFIFO_RESET, | |
185 | regs_base + XSPI_CR_OFFSET); | |
ae918c02 AK |
186 | } |
187 | ||
188 | static void xilinx_spi_chipselect(struct spi_device *spi, int is_on) | |
189 | { | |
190 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
f9c6ef6c RRD |
191 | u16 cr; |
192 | u32 cs; | |
ae918c02 AK |
193 | |
194 | if (is_on == BITBANG_CS_INACTIVE) { | |
195 | /* Deselect the slave on the SPI bus */ | |
f9c6ef6c RRD |
196 | xspi->write_fn(xspi->cs_inactive, xspi->regs + XSPI_SSR_OFFSET); |
197 | return; | |
ae918c02 | 198 | } |
f9c6ef6c RRD |
199 | |
200 | /* Set the SPI clock phase and polarity */ | |
201 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) & ~XSPI_CR_MODE_MASK; | |
202 | if (spi->mode & SPI_CPHA) | |
203 | cr |= XSPI_CR_CPHA; | |
204 | if (spi->mode & SPI_CPOL) | |
205 | cr |= XSPI_CR_CPOL; | |
206 | if (spi->mode & SPI_LSB_FIRST) | |
207 | cr |= XSPI_CR_LSB_FIRST; | |
208 | if (spi->mode & SPI_LOOP) | |
209 | cr |= XSPI_CR_LOOP; | |
210 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); | |
211 | ||
212 | /* We do not check spi->max_speed_hz here as the SPI clock | |
213 | * frequency is not software programmable (the IP block design | |
214 | * parameter) | |
215 | */ | |
216 | ||
217 | cs = xspi->cs_inactive; | |
218 | cs ^= BIT(spi->chip_select); | |
219 | ||
220 | /* Activate the chip select */ | |
221 | xspi->write_fn(cs, xspi->regs + XSPI_SSR_OFFSET); | |
ae918c02 AK |
222 | } |
223 | ||
224 | /* spi_bitbang requires custom setup_transfer() to be defined if there is a | |
9bf46f6d | 225 | * custom txrx_bufs(). |
ae918c02 AK |
226 | */ |
227 | static int xilinx_spi_setup_transfer(struct spi_device *spi, | |
228 | struct spi_transfer *t) | |
229 | { | |
f9c6ef6c RRD |
230 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); |
231 | ||
232 | if (spi->mode & SPI_CS_HIGH) | |
233 | xspi->cs_inactive &= ~BIT(spi->chip_select); | |
234 | else | |
235 | xspi->cs_inactive |= BIT(spi->chip_select); | |
236 | ||
ae918c02 AK |
237 | return 0; |
238 | } | |
239 | ||
ae918c02 AK |
240 | static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) |
241 | { | |
242 | struct xilinx_spi *xspi = spi_master_get_devdata(spi->master); | |
b563bfb8 | 243 | int remaining_words; /* the number of words left to transfer */ |
22417352 RRD |
244 | bool use_irq = false; |
245 | u16 cr = 0; | |
ae918c02 AK |
246 | |
247 | /* We get here with transmitter inhibited */ | |
248 | ||
249 | xspi->tx_ptr = t->tx_buf; | |
250 | xspi->rx_ptr = t->rx_buf; | |
b563bfb8 | 251 | remaining_words = t->len / xspi->bytes_per_word; |
ae918c02 | 252 | |
22417352 | 253 | if (xspi->irq >= 0 && remaining_words > xspi->buffer_size) { |
74346841 | 254 | u32 isr; |
22417352 | 255 | use_irq = true; |
22417352 RRD |
256 | /* Inhibit irq to avoid spurious irqs on tx_empty*/ |
257 | cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
258 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, | |
259 | xspi->regs + XSPI_CR_OFFSET); | |
74346841 RRD |
260 | /* ACK old irqs (if any) */ |
261 | isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
262 | if (isr) | |
263 | xspi->write_fn(isr, | |
264 | xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
265 | /* Enable the global IPIF interrupt */ | |
266 | xspi->write_fn(XIPIF_V123B_GINTR_ENABLE, | |
267 | xspi->regs + XIPIF_V123B_DGIER_OFFSET); | |
268 | reinit_completion(&xspi->done); | |
22417352 RRD |
269 | } |
270 | ||
b563bfb8 | 271 | while (remaining_words) { |
b563bfb8 | 272 | int n_words, tx_words, rx_words; |
eca37c7c | 273 | u32 sr; |
68c315bb | 274 | |
b563bfb8 | 275 | n_words = min(remaining_words, xspi->buffer_size); |
4c9a7614 | 276 | |
b563bfb8 RRD |
277 | tx_words = n_words; |
278 | while (tx_words--) | |
279 | xilinx_spi_tx(xspi); | |
68c315bb PC |
280 | |
281 | /* Start the transfer by not inhibiting the transmitter any | |
282 | * longer | |
283 | */ | |
68c315bb | 284 | |
22417352 | 285 | if (use_irq) { |
d9f58812 | 286 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
5fe11cc0 | 287 | wait_for_completion(&xspi->done); |
eca37c7c RRD |
288 | /* A transmit has just completed. Process received data |
289 | * and check for more data to transmit. Always inhibit | |
290 | * the transmitter while the Isr refills the transmit | |
291 | * register/FIFO, or make sure it is stopped if we're | |
292 | * done. | |
293 | */ | |
d9f58812 | 294 | xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT, |
eca37c7c RRD |
295 | xspi->regs + XSPI_CR_OFFSET); |
296 | sr = XSPI_SR_TX_EMPTY_MASK; | |
297 | } else | |
298 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
68c315bb PC |
299 | |
300 | /* Read out all the data from the Rx FIFO */ | |
b563bfb8 | 301 | rx_words = n_words; |
eca37c7c RRD |
302 | while (rx_words) { |
303 | if ((sr & XSPI_SR_TX_EMPTY_MASK) && (rx_words > 1)) { | |
304 | xilinx_spi_rx(xspi); | |
305 | rx_words--; | |
306 | continue; | |
307 | } | |
308 | ||
309 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
310 | if (!(sr & XSPI_SR_RX_EMPTY_MASK)) { | |
311 | xilinx_spi_rx(xspi); | |
312 | rx_words--; | |
313 | } | |
314 | } | |
b563bfb8 RRD |
315 | |
316 | remaining_words -= n_words; | |
68c315bb | 317 | } |
ae918c02 | 318 | |
16ea9b8a | 319 | if (use_irq) { |
22417352 | 320 | xspi->write_fn(0, xspi->regs + XIPIF_V123B_DGIER_OFFSET); |
16ea9b8a RRD |
321 | xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET); |
322 | } | |
22417352 | 323 | |
d79b2d07 | 324 | return t->len; |
ae918c02 AK |
325 | } |
326 | ||
327 | ||
328 | /* This driver supports single master mode only. Hence Tx FIFO Empty | |
329 | * is the only interrupt we care about. | |
330 | * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode | |
331 | * Fault are not to happen. | |
332 | */ | |
333 | static irqreturn_t xilinx_spi_irq(int irq, void *dev_id) | |
334 | { | |
335 | struct xilinx_spi *xspi = dev_id; | |
336 | u32 ipif_isr; | |
337 | ||
338 | /* Get the IPIF interrupts, and clear them immediately */ | |
86fc5935 RR |
339 | ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET); |
340 | xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET); | |
ae918c02 AK |
341 | |
342 | if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */ | |
68c315bb | 343 | complete(&xspi->done); |
ae918c02 AK |
344 | } |
345 | ||
346 | return IRQ_HANDLED; | |
347 | } | |
348 | ||
4c9a7614 RRD |
349 | static int xilinx_spi_find_buffer_size(struct xilinx_spi *xspi) |
350 | { | |
351 | u8 sr; | |
352 | int n_words = 0; | |
353 | ||
354 | /* | |
355 | * Before the buffer_size detection we reset the core | |
356 | * to make sure we start with a clean state. | |
357 | */ | |
358 | xspi->write_fn(XIPIF_V123B_RESET_MASK, | |
359 | xspi->regs + XIPIF_V123B_RESETR_OFFSET); | |
360 | ||
361 | /* Fill the Tx FIFO with as many words as possible */ | |
362 | do { | |
363 | xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET); | |
364 | sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET); | |
365 | n_words++; | |
366 | } while (!(sr & XSPI_SR_TX_FULL_MASK)); | |
367 | ||
368 | return n_words; | |
369 | } | |
370 | ||
eae6cb31 GL |
371 | static const struct of_device_id xilinx_spi_of_match[] = { |
372 | { .compatible = "xlnx,xps-spi-2.00.a", }, | |
373 | { .compatible = "xlnx,xps-spi-2.00.b", }, | |
374 | {} | |
375 | }; | |
376 | MODULE_DEVICE_TABLE(of, xilinx_spi_of_match); | |
eae6cb31 | 377 | |
7cb2abd0 | 378 | static int xilinx_spi_probe(struct platform_device *pdev) |
ae918c02 | 379 | { |
ae918c02 | 380 | struct xilinx_spi *xspi; |
d81c0bbb | 381 | struct xspi_platform_data *pdata; |
ad3fdbca | 382 | struct resource *res; |
7b3b7432 | 383 | int ret, num_cs = 0, bits_per_word = 8; |
d81c0bbb | 384 | struct spi_master *master; |
082339bc | 385 | u32 tmp; |
d81c0bbb MB |
386 | u8 i; |
387 | ||
8074cf06 | 388 | pdata = dev_get_platdata(&pdev->dev); |
d81c0bbb MB |
389 | if (pdata) { |
390 | num_cs = pdata->num_chipselect; | |
391 | bits_per_word = pdata->bits_per_word; | |
be3acdff MS |
392 | } else { |
393 | of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits", | |
394 | &num_cs); | |
d81c0bbb | 395 | } |
ae918c02 | 396 | |
d81c0bbb | 397 | if (!num_cs) { |
7cb2abd0 MB |
398 | dev_err(&pdev->dev, |
399 | "Missing slave select configuration data\n"); | |
d81c0bbb MB |
400 | return -EINVAL; |
401 | } | |
402 | ||
eb25f16c RR |
403 | if (num_cs > XILINX_SPI_MAX_CS) { |
404 | dev_err(&pdev->dev, "Invalid number of spi slaves\n"); | |
405 | return -EINVAL; | |
406 | } | |
407 | ||
7cb2abd0 | 408 | master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi)); |
d5af91a1 | 409 | if (!master) |
d81c0bbb | 410 | return -ENODEV; |
ae918c02 | 411 | |
e7db06b5 | 412 | /* the spi->mode bits understood by this driver: */ |
f9c6ef6c RRD |
413 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST | SPI_LOOP | |
414 | SPI_CS_HIGH; | |
e7db06b5 | 415 | |
ae918c02 | 416 | xspi = spi_master_get_devdata(master); |
f9c6ef6c | 417 | xspi->cs_inactive = 0xffffffff; |
94c69f76 | 418 | xspi->bitbang.master = master; |
ae918c02 AK |
419 | xspi->bitbang.chipselect = xilinx_spi_chipselect; |
420 | xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; | |
421 | xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; | |
ae918c02 AK |
422 | init_completion(&xspi->done); |
423 | ||
ad3fdbca MS |
424 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
425 | xspi->regs = devm_ioremap_resource(&pdev->dev, res); | |
c40537d0 MB |
426 | if (IS_ERR(xspi->regs)) { |
427 | ret = PTR_ERR(xspi->regs); | |
ae918c02 | 428 | goto put_master; |
ae918c02 AK |
429 | } |
430 | ||
4b153a21 | 431 | master->bus_num = pdev->id; |
91565c40 | 432 | master->num_chipselect = num_cs; |
7cb2abd0 | 433 | master->dev.of_node = pdev->dev.of_node; |
082339bc MS |
434 | |
435 | /* | |
436 | * Detect endianess on the IP via loop bit in CR. Detection | |
437 | * must be done before reset is sent because incorrect reset | |
438 | * value generates error interrupt. | |
439 | * Setup little endian helper functions first and try to use them | |
440 | * and check if bit was correctly setup or not. | |
441 | */ | |
0635287a MB |
442 | xspi->read_fn = xspi_read32; |
443 | xspi->write_fn = xspi_write32; | |
082339bc MS |
444 | |
445 | xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET); | |
446 | tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET); | |
447 | tmp &= XSPI_CR_LOOP; | |
448 | if (tmp != XSPI_CR_LOOP) { | |
0635287a MB |
449 | xspi->read_fn = xspi_read32_be; |
450 | xspi->write_fn = xspi_write32_be; | |
86fc5935 | 451 | } |
082339bc | 452 | |
9bf46f6d | 453 | master->bits_per_word_mask = SPI_BPW_MASK(bits_per_word); |
17aaaa80 | 454 | xspi->bytes_per_word = bits_per_word / 8; |
4c9a7614 RRD |
455 | xspi->buffer_size = xilinx_spi_find_buffer_size(xspi); |
456 | ||
7b3b7432 | 457 | xspi->irq = platform_get_irq(pdev, 0); |
5fe11cc0 RRD |
458 | if (xspi->irq >= 0) { |
459 | /* Register for SPI Interrupt */ | |
460 | ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0, | |
461 | dev_name(&pdev->dev), xspi); | |
462 | if (ret) | |
463 | goto put_master; | |
7b3b7432 MS |
464 | } |
465 | ||
5fe11cc0 RRD |
466 | /* SPI controller initializations */ |
467 | xspi_init_hw(xspi); | |
ae918c02 | 468 | |
d5af91a1 RR |
469 | ret = spi_bitbang_start(&xspi->bitbang); |
470 | if (ret) { | |
7cb2abd0 | 471 | dev_err(&pdev->dev, "spi_bitbang_start FAILED\n"); |
7b3b7432 | 472 | goto put_master; |
eae6cb31 GL |
473 | } |
474 | ||
7cb2abd0 | 475 | dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n", |
ad3fdbca | 476 | (unsigned long long)res->start, xspi->regs, xspi->irq); |
8fd8821b | 477 | |
eae6cb31 GL |
478 | if (pdata) { |
479 | for (i = 0; i < pdata->num_devices; i++) | |
480 | spi_new_device(master, pdata->devices + i); | |
481 | } | |
8fd8821b | 482 | |
7cb2abd0 | 483 | platform_set_drvdata(pdev, master); |
8fd8821b | 484 | return 0; |
ae918c02 | 485 | |
ae918c02 AK |
486 | put_master: |
487 | spi_master_put(master); | |
d81c0bbb MB |
488 | |
489 | return ret; | |
8fd8821b GL |
490 | } |
491 | ||
7cb2abd0 | 492 | static int xilinx_spi_remove(struct platform_device *pdev) |
8fd8821b | 493 | { |
7cb2abd0 | 494 | struct spi_master *master = platform_get_drvdata(pdev); |
d81c0bbb | 495 | struct xilinx_spi *xspi = spi_master_get_devdata(master); |
7b3b7432 | 496 | void __iomem *regs_base = xspi->regs; |
ae918c02 AK |
497 | |
498 | spi_bitbang_stop(&xspi->bitbang); | |
7b3b7432 MS |
499 | |
500 | /* Disable all the interrupts just in case */ | |
501 | xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET); | |
502 | /* Disable the global IPIF interrupt */ | |
503 | xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET); | |
ff82c587 | 504 | |
d5af91a1 | 505 | spi_master_put(xspi->bitbang.master); |
8fd8821b GL |
506 | |
507 | return 0; | |
508 | } | |
509 | ||
510 | /* work with hotplug and coldplug */ | |
511 | MODULE_ALIAS("platform:" XILINX_SPI_NAME); | |
512 | ||
513 | static struct platform_driver xilinx_spi_driver = { | |
514 | .probe = xilinx_spi_probe, | |
fd4a319b | 515 | .remove = xilinx_spi_remove, |
8fd8821b GL |
516 | .driver = { |
517 | .name = XILINX_SPI_NAME, | |
eae6cb31 | 518 | .of_match_table = xilinx_spi_of_match, |
8fd8821b GL |
519 | }, |
520 | }; | |
940ab889 | 521 | module_platform_driver(xilinx_spi_driver); |
8fd8821b | 522 | |
ae918c02 AK |
523 | MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>"); |
524 | MODULE_DESCRIPTION("Xilinx SPI driver"); | |
525 | MODULE_LICENSE("GPL"); |