[deliverable/linux.git] / drivers / spi / spi-xilinx.c

/*
 * Xilinx SPI controller driver (master mode only)
 *
 * Author: MontaVista Software, Inc.
 *	source@mvista.com
 *
 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
 * Copyright (c) 2009 Intel Corporation
 * 2002-2007 (c) MontaVista Software, Inc.

 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/spi/xilinx_spi.h>
#include <linux/io.h>

#define XILINX_SPI_NAME "xilinx_spi"

/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
 * Product Specification", DS464
 */
#define XSPI_CR_OFFSET		0x60	/* Control Register */

#define XSPI_CR_ENABLE		0x02
#define XSPI_CR_MASTER_MODE	0x04
#define XSPI_CR_CPOL		0x08
#define XSPI_CR_CPHA		0x10
#define XSPI_CR_MODE_MASK	(XSPI_CR_CPHA | XSPI_CR_CPOL)
#define XSPI_CR_TXFIFO_RESET	0x20
#define XSPI_CR_RXFIFO_RESET	0x40
#define XSPI_CR_MANUAL_SSELECT	0x80
#define XSPI_CR_TRANS_INHIBIT	0x100
#define XSPI_CR_LSB_FIRST	0x200

#define XSPI_SR_OFFSET		0x64	/* Status Register */

#define XSPI_SR_RX_EMPTY_MASK	0x01	/* Receive FIFO is empty */
#define XSPI_SR_RX_FULL_MASK	0x02	/* Receive FIFO is full */
#define XSPI_SR_TX_EMPTY_MASK	0x04	/* Transmit FIFO is empty */
#define XSPI_SR_TX_FULL_MASK	0x08	/* Transmit FIFO is full */
#define XSPI_SR_MODE_FAULT_MASK	0x10	/* Mode fault error */

#define XSPI_TXD_OFFSET		0x68	/* Data Transmit Register */
#define XSPI_RXD_OFFSET		0x6c	/* Data Receive Register */

#define XSPI_SSR_OFFSET		0x70	/* 32-bit Slave Select Register */

/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
 * IPIF registers are 32 bit
 */
#define XIPIF_V123B_DGIER_OFFSET	0x1c	/* IPIF global int enable reg */
#define XIPIF_V123B_GINTR_ENABLE	0x80000000

#define XIPIF_V123B_IISR_OFFSET		0x20	/* IPIF interrupt status reg */
#define XIPIF_V123B_IIER_OFFSET		0x28	/* IPIF interrupt enable reg */

#define XSPI_INTR_MODE_FAULT		0x01	/* Mode fault error */
#define XSPI_INTR_SLAVE_MODE_FAULT	0x02	/* Selected as slave while
						 * disabled */
#define XSPI_INTR_TX_EMPTY		0x04	/* TxFIFO is empty */
#define XSPI_INTR_TX_UNDERRUN		0x08	/* TxFIFO was underrun */
#define XSPI_INTR_RX_FULL		0x10	/* RxFIFO is full */
#define XSPI_INTR_RX_OVERRUN		0x20	/* RxFIFO was overrun */
#define XSPI_INTR_TX_HALF_EMPTY		0x40	/* TxFIFO is half empty */

#define XIPIF_V123B_RESETR_OFFSET	0x40	/* IPIF reset register */
#define XIPIF_V123B_RESET_MASK		0x0a	/* the value to write */

struct xilinx_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;
	struct completion done;
	struct resource mem; /* phys mem */
	void __iomem	*regs;	/* virt. address of the control registers */

	u32		irq;

	u8 *rx_ptr;		/* pointer in the Tx buffer */
	const u8 *tx_ptr;	/* pointer in the Rx buffer */
	int remaining_bytes;	/* the number of bytes left to transfer */
	u8 bits_per_word;
	unsigned int (*read_fn) (void __iomem *);
	void (*write_fn) (u32, void __iomem *);
	void (*tx_fn) (struct xilinx_spi *);
	void (*rx_fn) (struct xilinx_spi *);
};

static void xspi_write32(u32 val, void __iomem *addr)
{
	iowrite32(val, addr);
}

static unsigned int xspi_read32(void __iomem *addr)
{
	return ioread32(addr);
}

static void xspi_write32_be(u32 val, void __iomem *addr)
{
	iowrite32be(val, addr);
}

static unsigned int xspi_read32_be(void __iomem *addr)
{
	return ioread32be(addr);
}

static void xspi_tx8(struct xilinx_spi *xspi)
{
	xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr++;
}

static void xspi_tx16(struct xilinx_spi *xspi)
{
	xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr += 2;
}

static void xspi_tx32(struct xilinx_spi *xspi)
{
	xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr += 4;
}

static void xspi_rx8(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*xspi->rx_ptr = data & 0xff;
		xspi->rx_ptr++;
	}
}

static void xspi_rx16(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*(u16 *)(xspi->rx_ptr) = data & 0xffff;
		xspi->rx_ptr += 2;
	}
}

static void xspi_rx32(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*(u32 *)(xspi->rx_ptr) = data;
		xspi->rx_ptr += 4;
	}
}

static void xspi_init_hw(struct xilinx_spi *xspi)
{
	void __iomem *regs_base = xspi->regs;

	/* Reset the SPI device */
	xspi->write_fn(XIPIF_V123B_RESET_MASK,
		regs_base + XIPIF_V123B_RESETR_OFFSET);
	/* Disable all the interrupts just in case */
	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	/* Enable the global IPIF interrupt */
	xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
		regs_base + XIPIF_V123B_DGIER_OFFSET);
	/* Deselect the slave on the SPI bus */
	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
	/* Disable the transmitter, enable Manual Slave Select Assertion,
	 * put SPI controller into master mode, and enable it */
	xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
		XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
		XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
}

static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);

	if (is_on == BITBANG_CS_INACTIVE) {
		/* Deselect the slave on the SPI bus */
		xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
	} else if (is_on == BITBANG_CS_ACTIVE) {
		/* Set the SPI clock phase and polarity */
		u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
			 & ~XSPI_CR_MODE_MASK;
		if (spi->mode & SPI_CPHA)
			cr |= XSPI_CR_CPHA;
		if (spi->mode & SPI_CPOL)
			cr |= XSPI_CR_CPOL;
		xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);

		/* We do not check spi->max_speed_hz here as the SPI clock
		 * frequency is not software programmable (the IP block design
		 * parameter)
		 */

		/* Activate the chip select */
		xspi->write_fn(~(0x0001 << spi->chip_select),
			xspi->regs + XSPI_SSR_OFFSET);
	}
}

/* spi_bitbang requires custom setup_transfer() to be defined if there is a
 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
 * supports 8 or 16 bits per word which cannot be changed in software.
 * SPI clock can't be changed in software either.
 * Check for correct bits per word. Chip select delay calculations could be
 * added here as soon as bitbang_work() can be made aware of the delay value.
 */
static int xilinx_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	u8 bits_per_word;

	bits_per_word = (t && t->bits_per_word)
			 ? t->bits_per_word : spi->bits_per_word;
	if (bits_per_word != xspi->bits_per_word) {
		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
			__func__, bits_per_word);
		return -EINVAL;
	}

	return 0;
}

static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
{
	u8 sr;

	/* Fill the Tx FIFO with as many bytes as possible */
	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
		if (xspi->tx_ptr)
			xspi->tx_fn(xspi);
		else
			xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
		xspi->remaining_bytes -= xspi->bits_per_word / 8;
		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	}
}

static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	u32 ipif_ier;
	u16 cr;

	/* We get here with transmitter inhibited */

	xspi->tx_ptr = t->tx_buf;
	xspi->rx_ptr = t->rx_buf;
	xspi->remaining_bytes = t->len;
	INIT_COMPLETION(xspi->done);

	xilinx_spi_fill_tx_fifo(xspi);

	/* Enable the transmit empty interrupt, which we use to determine
	 * progress on the transmission.
	 */
	ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
	xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
		xspi->regs + XIPIF_V123B_IIER_OFFSET);

	/* Start the transfer by not inhibiting the transmitter any longer */
	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
		~XSPI_CR_TRANS_INHIBIT;
	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);

	wait_for_completion(&xspi->done);

	/* Disable the transmit empty interrupt */
	xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);

	return t->len - xspi->remaining_bytes;
}


/* This driver supports single master mode only. Hence Tx FIFO Empty
 * is the only interrupt we care about.
 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
 * Fault are not to happen.
 */
static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
{
	struct xilinx_spi *xspi = dev_id;
	u32 ipif_isr;

	/* Get the IPIF interrupts, and clear them immediately */
	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);

	if (ipif_isr & XSPI_INTR_TX_EMPTY) {	/* Transmission completed */
		u16 cr;
		u8 sr;

		/* A transmit has just completed. Process received data and
		 * check for more data to transmit. Always inhibit the
		 * transmitter while the Isr refills the transmit register/FIFO,
		 * or make sure it is stopped if we're done.
		 */
		cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
		xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
			xspi->regs + XSPI_CR_OFFSET);

		/* Read out all the data from the Rx FIFO */
		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
		while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
			xspi->rx_fn(xspi);
			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
		}

		/* See if there is more data to send */
		if (xspi->remaining_bytes > 0) {
			xilinx_spi_fill_tx_fifo(xspi);
			/* Start the transfer by not inhibiting the
			 * transmitter any longer
			 */
			xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
		} else {
			/* No more data to send.
			 * Indicate the transfer is completed.
			 */
			complete(&xspi->done);
		}
	}

	return IRQ_HANDLED;
}

static const struct of_device_id xilinx_spi_of_match[] = {
	{ .compatible = "xlnx,xps-spi-2.00.a", },
	{ .compatible = "xlnx,xps-spi-2.00.b", },
	{}
};
MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);

struct spi_master *xilinx_spi_init(struct device *dev, struct resource *mem,
	u32 irq, s16 bus_num, int num_cs, int little_endian, int bits_per_word)
{
	struct spi_master *master;
	struct xilinx_spi *xspi;
	int ret;

	master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
	if (!master)
		return NULL;

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA;

	xspi = spi_master_get_devdata(master);
	xspi->bitbang.master = spi_master_get(master);
	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
	init_completion(&xspi->done);

	if (!request_mem_region(mem->start, resource_size(mem),
		XILINX_SPI_NAME))
		goto put_master;

	xspi->regs = ioremap(mem->start, resource_size(mem));
	if (xspi->regs == NULL) {
		dev_warn(dev, "ioremap failure\n");
		goto map_failed;
	}

	master->bus_num = bus_num;
	master->num_chipselect = num_cs;
	master->dev.of_node = dev->of_node;

	xspi->mem = *mem;
	xspi->irq = irq;
	if (little_endian) {
		xspi->read_fn = xspi_read32;
		xspi->write_fn = xspi_write32;
	} else {
		xspi->read_fn = xspi_read32_be;
		xspi->write_fn = xspi_write32_be;
	}
	xspi->bits_per_word = bits_per_word;
	if (xspi->bits_per_word == 8) {
		xspi->tx_fn = xspi_tx8;
		xspi->rx_fn = xspi_rx8;
	} else if (xspi->bits_per_word == 16) {
		xspi->tx_fn = xspi_tx16;
		xspi->rx_fn = xspi_rx16;
	} else if (xspi->bits_per_word == 32) {
		xspi->tx_fn = xspi_tx32;
		xspi->rx_fn = xspi_rx32;
	} else
		goto unmap_io;


	/* SPI controller initializations */
	xspi_init_hw(xspi);

	/* Register for SPI Interrupt */
	ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
	if (ret)
		goto unmap_io;

	ret = spi_bitbang_start(&xspi->bitbang);
	if (ret) {
		dev_err(dev, "spi_bitbang_start FAILED\n");
		goto free_irq;
	}

	dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
		(unsigned long long)mem->start, xspi->regs, xspi->irq);
	return master;

free_irq:
	free_irq(xspi->irq, xspi);
unmap_io:
	iounmap(xspi->regs);
map_failed:
	release_mem_region(mem->start, resource_size(mem));
put_master:
	spi_master_put(master);
	return NULL;
}
EXPORT_SYMBOL(xilinx_spi_init);

void xilinx_spi_deinit(struct spi_master *master)
{
	struct xilinx_spi *xspi;

	xspi = spi_master_get_devdata(master);

	spi_bitbang_stop(&xspi->bitbang);
	free_irq(xspi->irq, xspi);
	iounmap(xspi->regs);

	release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
	spi_master_put(xspi->bitbang.master);
}
EXPORT_SYMBOL(xilinx_spi_deinit);

static int xilinx_spi_probe(struct platform_device *dev)
{
	struct xspi_platform_data *pdata;
	struct resource *r;
	int irq, num_cs = 0, little_endian = 0, bits_per_word = 8;
	struct spi_master *master;
	u8 i;

	pdata = dev->dev.platform_data;
	if (pdata) {
		num_cs = pdata->num_chipselect;
		little_endian = pdata->little_endian;
		bits_per_word = pdata->bits_per_word;
	}

#ifdef CONFIG_OF
	if (dev->dev.of_node) {
		const __be32 *prop;
		int len;

		/* number of slave select bits is required */
		prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits",
				       &len);
		if (prop && len >= sizeof(*prop))
			num_cs = __be32_to_cpup(prop);
	}
#endif

	if (!num_cs) {
		dev_err(&dev->dev, "Missing slave select configuration data\n");
		return -EINVAL;
	}


	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	if (!r)
		return -ENODEV;

	irq = platform_get_irq(dev, 0);
	if (irq < 0)
		return -ENXIO;

	master = xilinx_spi_init(&dev->dev, r, irq, dev->id, num_cs,
				 little_endian, bits_per_word);
	if (!master)
		return -ENODEV;

	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			spi_new_device(master, pdata->devices + i);
	}

	platform_set_drvdata(dev, master);
	return 0;
}

static int xilinx_spi_remove(struct platform_device *dev)
{
	xilinx_spi_deinit(platform_get_drvdata(dev));
	platform_set_drvdata(dev, 0);

	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:" XILINX_SPI_NAME);

static struct platform_driver xilinx_spi_driver = {
	.probe = xilinx_spi_probe,
	.remove = xilinx_spi_remove,
	.driver = {
		.name = XILINX_SPI_NAME,
		.owner = THIS_MODULE,
		.of_match_table = xilinx_spi_of_match,
	},
};
module_platform_driver(xilinx_spi_driver);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("Xilinx SPI driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ae918c02	1	/*
ae918c02 AK	2	* Xilinx SPI controller driver (master mode only)
	3	*
	4	* Author: MontaVista Software, Inc.
	5	* source@mvista.com
	6	*
8fd8821b GL	7	* Copyright (c) 2010 Secret Lab Technologies, Ltd.
	8	* Copyright (c) 2009 Intel Corporation
	9	* 2002-2007 (c) MontaVista Software, Inc.
	10
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
ae918c02 AK	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/init.h>
	18	#include <linux/interrupt.h>
eae6cb31	19	#include <linux/of.h>
8fd8821b	20	#include <linux/platform_device.h>
ae918c02 AK	21	#include <linux/spi/spi.h>
ae918c02 AK	22	#include <linux/spi/spi_bitbang.h>
d5af91a1	23	#include <linux/spi/xilinx_spi.h>
eae6cb31	24	#include <linux/io.h>
d5af91a1	25
fc3ba952	26	#define XILINX_SPI_NAME "xilinx_spi"
ae918c02 AK	27
	28	/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
	29	* Product Specification", DS464
	30	*/
c9da2e12	31	#define XSPI_CR_OFFSET 0x60 /* Control Register */
ae918c02 AK	32
	33	#define XSPI_CR_ENABLE 0x02
	34	#define XSPI_CR_MASTER_MODE 0x04
	35	#define XSPI_CR_CPOL 0x08
	36	#define XSPI_CR_CPHA 0x10
	37	#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA \| XSPI_CR_CPOL)
	38	#define XSPI_CR_TXFIFO_RESET 0x20
	39	#define XSPI_CR_RXFIFO_RESET 0x40
	40	#define XSPI_CR_MANUAL_SSELECT 0x80
	41	#define XSPI_CR_TRANS_INHIBIT 0x100
c9da2e12	42	#define XSPI_CR_LSB_FIRST 0x200
ae918c02	43
c9da2e12	44	#define XSPI_SR_OFFSET 0x64 /* Status Register */
ae918c02 AK	45
	46	#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
	47	#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
	48	#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
	49	#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
	50	#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
	51
c9da2e12 RR	52	#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
c9da2e12 RR	53	#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
ae918c02 AK	54
	55	#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
	56
	57	/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
	58	* IPIF registers are 32 bit
	59	*/
	60	#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
	61	#define XIPIF_V123B_GINTR_ENABLE 0x80000000
	62
	63	#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
	64	#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
	65
	66	#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
	67	#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
	68	* disabled */
	69	#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
	70	#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
	71	#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
	72	#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
c9da2e12	73	#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
ae918c02 AK	74
	75	#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
	76	#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
	77
	78	struct xilinx_spi {
	79	/* bitbang has to be first */
	80	struct spi_bitbang bitbang;
	81	struct completion done;
d5af91a1	82	struct resource mem; /* phys mem */
ae918c02 AK	83	void __iomem regs; / virt. address of the control registers */
	84
	85	u32 irq;
	86
ae918c02 AK	87	u8 rx_ptr; / pointer in the Tx buffer */
	88	const u8 tx_ptr; / pointer in the Rx buffer */
	89	int remaining_bytes; /* the number of bytes left to transfer */
c9da2e12	90	u8 bits_per_word;
86fc5935 RR	91	unsigned int (read_fn) (void __iomem );
86fc5935 RR	92	void (write_fn) (u32, void __iomem );
c9da2e12 RR	93	void (tx_fn) (struct xilinx_spi );
c9da2e12 RR	94	void (rx_fn) (struct xilinx_spi );
ae918c02 AK	95	};
ae918c02 AK	96
97782149 PM	97	static void xspi_write32(u32 val, void __iomem *addr)
	98	{
	99	iowrite32(val, addr);
	100	}
	101
	102	static unsigned int xspi_read32(void __iomem *addr)
	103	{
	104	return ioread32(addr);
	105	}
	106
	107	static void xspi_write32_be(u32 val, void __iomem *addr)
	108	{
	109	iowrite32be(val, addr);
	110	}
	111
	112	static unsigned int xspi_read32_be(void __iomem *addr)
	113	{
	114	return ioread32be(addr);
	115	}
	116
c9da2e12 RR	117	static void xspi_tx8(struct xilinx_spi *xspi)
	118	{
	119	xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
	120	xspi->tx_ptr++;
	121	}
	122
	123	static void xspi_tx16(struct xilinx_spi *xspi)
	124	{
	125	xspi->write_fn((u16 )(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	126	xspi->tx_ptr += 2;
	127	}
	128
	129	static void xspi_tx32(struct xilinx_spi *xspi)
	130	{
	131	xspi->write_fn((u32 )(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	132	xspi->tx_ptr += 4;
	133	}
	134
	135	static void xspi_rx8(struct xilinx_spi *xspi)
	136	{
	137	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	138	if (xspi->rx_ptr) {
	139	*xspi->rx_ptr = data & 0xff;
	140	xspi->rx_ptr++;
	141	}
	142	}
	143
	144	static void xspi_rx16(struct xilinx_spi *xspi)
	145	{
	146	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	147	if (xspi->rx_ptr) {
	148	(u16 )(xspi->rx_ptr) = data & 0xffff;
	149	xspi->rx_ptr += 2;
	150	}
	151	}
	152
	153	static void xspi_rx32(struct xilinx_spi *xspi)
	154	{
	155	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	156	if (xspi->rx_ptr) {
	157	(u32 )(xspi->rx_ptr) = data;
	158	xspi->rx_ptr += 4;
	159	}
	160	}
	161
86fc5935	162	static void xspi_init_hw(struct xilinx_spi *xspi)
ae918c02	163	{
86fc5935 RR	164	void __iomem *regs_base = xspi->regs;
86fc5935 RR	165
ae918c02	166	/* Reset the SPI device */
86fc5935 RR	167	xspi->write_fn(XIPIF_V123B_RESET_MASK,
86fc5935 RR	168	regs_base + XIPIF_V123B_RESETR_OFFSET);
ae918c02	169	/* Disable all the interrupts just in case */
86fc5935	170	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
ae918c02	171	/* Enable the global IPIF interrupt */
86fc5935 RR	172	xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
86fc5935 RR	173	regs_base + XIPIF_V123B_DGIER_OFFSET);
ae918c02	174	/* Deselect the slave on the SPI bus */
86fc5935	175	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
ae918c02 AK	176	/* Disable the transmitter, enable Manual Slave Select Assertion,
ae918c02 AK	177	* put SPI controller into master mode, and enable it */
86fc5935	178	xspi->write_fn(XSPI_CR_TRANS_INHIBIT \| XSPI_CR_MANUAL_SSELECT \|
c9da2e12 RR	179	XSPI_CR_MASTER_MODE \| XSPI_CR_ENABLE \| XSPI_CR_TXFIFO_RESET \|
c9da2e12 RR	180	XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
ae918c02 AK	181	}
	182
	183	static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
	184	{
	185	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	186
	187	if (is_on == BITBANG_CS_INACTIVE) {
	188	/* Deselect the slave on the SPI bus */
86fc5935	189	xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
ae918c02 AK	190	} else if (is_on == BITBANG_CS_ACTIVE) {
ae918c02 AK	191	/* Set the SPI clock phase and polarity */
86fc5935	192	u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
ae918c02 AK	193	& ~XSPI_CR_MODE_MASK;
	194	if (spi->mode & SPI_CPHA)
	195	cr \|= XSPI_CR_CPHA;
	196	if (spi->mode & SPI_CPOL)
	197	cr \|= XSPI_CR_CPOL;
86fc5935	198	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	199
	200	/* We do not check spi->max_speed_hz here as the SPI clock
	201	* frequency is not software programmable (the IP block design
	202	* parameter)
	203	*/
	204
	205	/* Activate the chip select */
86fc5935 RR	206	xspi->write_fn(~(0x0001 << spi->chip_select),
86fc5935 RR	207	xspi->regs + XSPI_SSR_OFFSET);
ae918c02 AK	208	}
	209	}
	210
	211	/* spi_bitbang requires custom setup_transfer() to be defined if there is a
	212	* custom txrx_bufs(). We have nothing to setup here as the SPI IP block
c9da2e12 RR	213	* supports 8 or 16 bits per word which cannot be changed in software.
	214	* SPI clock can't be changed in software either.
	215	* Check for correct bits per word. Chip select delay calculations could be
ae918c02 AK	216	* added here as soon as bitbang_work() can be made aware of the delay value.
	217	*/
	218	static int xilinx_spi_setup_transfer(struct spi_device *spi,
	219	struct spi_transfer *t)
	220	{
c9da2e12	221	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
ae918c02	222	u8 bits_per_word;
ae918c02	223
1a8d3b77 JL	224	bits_per_word = (t && t->bits_per_word)
1a8d3b77 JL	225	? t->bits_per_word : spi->bits_per_word;
c9da2e12	226	if (bits_per_word != xspi->bits_per_word) {
ae918c02	227	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
b687d2a8	228	__func__, bits_per_word);
ae918c02 AK	229	return -EINVAL;
	230	}
	231
ae918c02 AK	232	return 0;
	233	}
	234
ae918c02 AK	235	static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
	236	{
	237	u8 sr;
	238
	239	/* Fill the Tx FIFO with as many bytes as possible */
86fc5935	240	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02	241	while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
86fc5935	242	if (xspi->tx_ptr)
c9da2e12	243	xspi->tx_fn(xspi);
86fc5935 RR	244	else
86fc5935 RR	245	xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
c9da2e12	246	xspi->remaining_bytes -= xspi->bits_per_word / 8;
86fc5935	247	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02 AK	248	}
	249	}
	250
	251	static int xilinx_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
	252	{
	253	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	254	u32 ipif_ier;
	255	u16 cr;
	256
	257	/* We get here with transmitter inhibited */
	258
	259	xspi->tx_ptr = t->tx_buf;
	260	xspi->rx_ptr = t->rx_buf;
	261	xspi->remaining_bytes = t->len;
	262	INIT_COMPLETION(xspi->done);
	263
	264	xilinx_spi_fill_tx_fifo(xspi);
	265
	266	/* Enable the transmit empty interrupt, which we use to determine
	267	* progress on the transmission.
	268	*/
86fc5935 RR	269	ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
	270	xspi->write_fn(ipif_ier \| XSPI_INTR_TX_EMPTY,
	271	xspi->regs + XIPIF_V123B_IIER_OFFSET);
ae918c02 AK	272
ae918c02 AK	273	/* Start the transfer by not inhibiting the transmitter any longer */
86fc5935 RR	274	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
	275	~XSPI_CR_TRANS_INHIBIT;
	276	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	277
	278	wait_for_completion(&xspi->done);
	279
	280	/* Disable the transmit empty interrupt */
86fc5935	281	xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
ae918c02 AK	282
	283	return t->len - xspi->remaining_bytes;
	284	}
	285
	286
	287	/* This driver supports single master mode only. Hence Tx FIFO Empty
	288	* is the only interrupt we care about.
	289	* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
	290	* Fault are not to happen.
	291	*/
	292	static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
	293	{
	294	struct xilinx_spi *xspi = dev_id;
	295	u32 ipif_isr;
	296
	297	/* Get the IPIF interrupts, and clear them immediately */
86fc5935 RR	298	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
86fc5935 RR	299	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
ae918c02 AK	300
	301	if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
	302	u16 cr;
	303	u8 sr;
	304
	305	/* A transmit has just completed. Process received data and
	306	* check for more data to transmit. Always inhibit the
	307	* transmitter while the Isr refills the transmit register/FIFO,
	308	* or make sure it is stopped if we're done.
	309	*/
86fc5935 RR	310	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	311	xspi->write_fn(cr \| XSPI_CR_TRANS_INHIBIT,
	312	xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	313
ae918c02 AK	314	/* Read out all the data from the Rx FIFO */
86fc5935	315	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02	316	while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
c9da2e12	317	xspi->rx_fn(xspi);
86fc5935	318	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02 AK	319	}
	320
	321	/* See if there is more data to send */
	322	if (xspi->remaining_bytes > 0) {
	323	xilinx_spi_fill_tx_fifo(xspi);
	324	/* Start the transfer by not inhibiting the
	325	* transmitter any longer
	326	*/
86fc5935	327	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	328	} else {
	329	/* No more data to send.
	330	* Indicate the transfer is completed.
	331	*/
	332	complete(&xspi->done);
	333	}
	334	}
	335
	336	return IRQ_HANDLED;
	337	}
	338
eae6cb31 GL	339	static const struct of_device_id xilinx_spi_of_match[] = {
	340	{ .compatible = "xlnx,xps-spi-2.00.a", },
	341	{ .compatible = "xlnx,xps-spi-2.00.b", },
	342	{}
	343	};
	344	MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
eae6cb31	345
d5af91a1	346	struct spi_master xilinx_spi_init(struct device dev, struct resource *mem,
91565c40	347	u32 irq, s16 bus_num, int num_cs, int little_endian, int bits_per_word)
ae918c02	348	{
ae918c02 AK	349	struct spi_master *master;
ae918c02 AK	350	struct xilinx_spi *xspi;
d5af91a1	351	int ret;
ae918c02	352
d5af91a1 RR	353	master = spi_alloc_master(dev, sizeof(struct xilinx_spi));
	354	if (!master)
	355	return NULL;
ae918c02	356
e7db06b5 DB	357	/* the spi->mode bits understood by this driver: */
	358	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	359
ae918c02 AK	360	xspi = spi_master_get_devdata(master);
	361	xspi->bitbang.master = spi_master_get(master);
	362	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	363	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	364	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
ae918c02 AK	365	init_completion(&xspi->done);
ae918c02 AK	366
d5af91a1 RR	367	if (!request_mem_region(mem->start, resource_size(mem),
d5af91a1 RR	368	XILINX_SPI_NAME))
ae918c02	369	goto put_master;
ae918c02	370
d5af91a1	371	xspi->regs = ioremap(mem->start, resource_size(mem));
ae918c02	372	if (xspi->regs == NULL) {
d5af91a1 RR	373	dev_warn(dev, "ioremap failure\n");
d5af91a1 RR	374	goto map_failed;
ae918c02 AK	375	}
ae918c02 AK	376
d5af91a1	377	master->bus_num = bus_num;
91565c40	378	master->num_chipselect = num_cs;
12b15e83	379	master->dev.of_node = dev->of_node;
ae918c02	380
d5af91a1 RR	381	xspi->mem = *mem;
d5af91a1 RR	382	xspi->irq = irq;
91565c40	383	if (little_endian) {
97782149 PM	384	xspi->read_fn = xspi_read32;
97782149 PM	385	xspi->write_fn = xspi_write32;
86fc5935	386	} else {
97782149 PM	387	xspi->read_fn = xspi_read32_be;
97782149 PM	388	xspi->write_fn = xspi_write32_be;
86fc5935	389	}
91565c40	390	xspi->bits_per_word = bits_per_word;
c9da2e12 RR	391	if (xspi->bits_per_word == 8) {
	392	xspi->tx_fn = xspi_tx8;
	393	xspi->rx_fn = xspi_rx8;
	394	} else if (xspi->bits_per_word == 16) {
	395	xspi->tx_fn = xspi_tx16;
	396	xspi->rx_fn = xspi_rx16;
	397	} else if (xspi->bits_per_word == 32) {
	398	xspi->tx_fn = xspi_tx32;
	399	xspi->rx_fn = xspi_rx32;
	400	} else
	401	goto unmap_io;
	402
ae918c02 AK	403
ae918c02 AK	404	/* SPI controller initializations */
86fc5935	405	xspi_init_hw(xspi);
ae918c02 AK	406
ae918c02 AK	407	/* Register for SPI Interrupt */
d5af91a1 RR	408	ret = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi);
d5af91a1 RR	409	if (ret)
ae918c02 AK	410	goto unmap_io;
ae918c02 AK	411
d5af91a1 RR	412	ret = spi_bitbang_start(&xspi->bitbang);
	413	if (ret) {
	414	dev_err(dev, "spi_bitbang_start FAILED\n");
ae918c02 AK	415	goto free_irq;
	416	}
	417
920712af GL	418	dev_info(dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
920712af GL	419	(unsigned long long)mem->start, xspi->regs, xspi->irq);
d5af91a1	420	return master;
ae918c02 AK	421
	422	free_irq:
	423	free_irq(xspi->irq, xspi);
	424	unmap_io:
	425	iounmap(xspi->regs);
d5af91a1 RR	426	map_failed:
d5af91a1 RR	427	release_mem_region(mem->start, resource_size(mem));
ae918c02 AK	428	put_master:
ae918c02 AK	429	spi_master_put(master);
d5af91a1	430	return NULL;
ae918c02	431	}
d5af91a1	432	EXPORT_SYMBOL(xilinx_spi_init);
ae918c02	433
d5af91a1	434	void xilinx_spi_deinit(struct spi_master *master)
ae918c02 AK	435	{
ae918c02 AK	436	struct xilinx_spi *xspi;
ae918c02	437
ae918c02 AK	438	xspi = spi_master_get_devdata(master);
	439
	440	spi_bitbang_stop(&xspi->bitbang);
	441	free_irq(xspi->irq, xspi);
	442	iounmap(xspi->regs);
ff82c587	443
d5af91a1 RR	444	release_mem_region(xspi->mem.start, resource_size(&xspi->mem));
d5af91a1 RR	445	spi_master_put(xspi->bitbang.master);
ae918c02	446	}
d5af91a1	447	EXPORT_SYMBOL(xilinx_spi_deinit);
ae918c02	448
fd4a319b	449	static int xilinx_spi_probe(struct platform_device *dev)
8fd8821b GL	450	{
	451	struct xspi_platform_data *pdata;
	452	struct resource *r;
eae6cb31	453	int irq, num_cs = 0, little_endian = 0, bits_per_word = 8;
8fd8821b GL	454	struct spi_master *master;
	455	u8 i;
	456
3271d382	457	pdata = dev->dev.platform_data;
eae6cb31 GL	458	if (pdata) {
	459	num_cs = pdata->num_chipselect;
	460	little_endian = pdata->little_endian;
	461	bits_per_word = pdata->bits_per_word;
	462	}
	463
	464	#ifdef CONFIG_OF
	465	if (dev->dev.of_node) {
	466	const __be32 *prop;
	467	int len;
	468
	469	/* number of slave select bits is required */
	470	prop = of_get_property(dev->dev.of_node, "xlnx,num-ss-bits",
	471	&len);
	472	if (prop && len >= sizeof(*prop))
	473	num_cs = __be32_to_cpup(prop);
	474	}
	475	#endif
	476
	477	if (!num_cs) {
	478	dev_err(&dev->dev, "Missing slave select configuration data\n");
	479	return -EINVAL;
	480	}
	481
8fd8821b GL	482
	483	r = platform_get_resource(dev, IORESOURCE_MEM, 0);
	484	if (!r)
	485	return -ENODEV;
	486
	487	irq = platform_get_irq(dev, 0);
	488	if (irq < 0)
	489	return -ENXIO;
	490
eae6cb31 GL	491	master = xilinx_spi_init(&dev->dev, r, irq, dev->id, num_cs,
eae6cb31 GL	492	little_endian, bits_per_word);
8fd8821b GL	493	if (!master)
	494	return -ENODEV;
	495
eae6cb31 GL	496	if (pdata) {
	497	for (i = 0; i < pdata->num_devices; i++)
	498	spi_new_device(master, pdata->devices + i);
	499	}
8fd8821b GL	500
	501	platform_set_drvdata(dev, master);
	502	return 0;
	503	}
	504
fd4a319b	505	static int xilinx_spi_remove(struct platform_device *dev)
8fd8821b GL	506	{
	507	xilinx_spi_deinit(platform_get_drvdata(dev));
	508	platform_set_drvdata(dev, 0);
	509
	510	return 0;
	511	}
	512
	513	/* work with hotplug and coldplug */
	514	MODULE_ALIAS("platform:" XILINX_SPI_NAME);
	515
	516	static struct platform_driver xilinx_spi_driver = {
	517	.probe = xilinx_spi_probe,
fd4a319b	518	.remove = xilinx_spi_remove,
8fd8821b GL	519	.driver = {
	520	.name = XILINX_SPI_NAME,
	521	.owner = THIS_MODULE,
eae6cb31	522	.of_match_table = xilinx_spi_of_match,
8fd8821b GL	523	},
8fd8821b GL	524	};
940ab889	525	module_platform_driver(xilinx_spi_driver);
8fd8821b	526
ae918c02 AK	527	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	528	MODULE_DESCRIPTION("Xilinx SPI driver");
	529	MODULE_LICENSE("GPL");