[deliverable/linux.git] / drivers / spi / spi-xilinx.c

/*
 * Xilinx SPI controller driver (master mode only)
 *
 * Author: MontaVista Software, Inc.
 *	source@mvista.com
 *
 * Copyright (c) 2010 Secret Lab Technologies, Ltd.
 * Copyright (c) 2009 Intel Corporation
 * 2002-2007 (c) MontaVista Software, Inc.

 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/module.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/spi/spi_bitbang.h>
#include <linux/spi/xilinx_spi.h>
#include <linux/io.h>

#define XILINX_SPI_NAME "xilinx_spi"

/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
 * Product Specification", DS464
 */
#define XSPI_CR_OFFSET		0x60	/* Control Register */

#define XSPI_CR_LOOP		0x01
#define XSPI_CR_ENABLE		0x02
#define XSPI_CR_MASTER_MODE	0x04
#define XSPI_CR_CPOL		0x08
#define XSPI_CR_CPHA		0x10
#define XSPI_CR_MODE_MASK	(XSPI_CR_CPHA | XSPI_CR_CPOL)
#define XSPI_CR_TXFIFO_RESET	0x20
#define XSPI_CR_RXFIFO_RESET	0x40
#define XSPI_CR_MANUAL_SSELECT	0x80
#define XSPI_CR_TRANS_INHIBIT	0x100
#define XSPI_CR_LSB_FIRST	0x200

#define XSPI_SR_OFFSET		0x64	/* Status Register */

#define XSPI_SR_RX_EMPTY_MASK	0x01	/* Receive FIFO is empty */
#define XSPI_SR_RX_FULL_MASK	0x02	/* Receive FIFO is full */
#define XSPI_SR_TX_EMPTY_MASK	0x04	/* Transmit FIFO is empty */
#define XSPI_SR_TX_FULL_MASK	0x08	/* Transmit FIFO is full */
#define XSPI_SR_MODE_FAULT_MASK	0x10	/* Mode fault error */

#define XSPI_TXD_OFFSET		0x68	/* Data Transmit Register */
#define XSPI_RXD_OFFSET		0x6c	/* Data Receive Register */

#define XSPI_SSR_OFFSET		0x70	/* 32-bit Slave Select Register */

/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
 * IPIF registers are 32 bit
 */
#define XIPIF_V123B_DGIER_OFFSET	0x1c	/* IPIF global int enable reg */
#define XIPIF_V123B_GINTR_ENABLE	0x80000000

#define XIPIF_V123B_IISR_OFFSET		0x20	/* IPIF interrupt status reg */
#define XIPIF_V123B_IIER_OFFSET		0x28	/* IPIF interrupt enable reg */

#define XSPI_INTR_MODE_FAULT		0x01	/* Mode fault error */
#define XSPI_INTR_SLAVE_MODE_FAULT	0x02	/* Selected as slave while
						 * disabled */
#define XSPI_INTR_TX_EMPTY		0x04	/* TxFIFO is empty */
#define XSPI_INTR_TX_UNDERRUN		0x08	/* TxFIFO was underrun */
#define XSPI_INTR_RX_FULL		0x10	/* RxFIFO is full */
#define XSPI_INTR_RX_OVERRUN		0x20	/* RxFIFO was overrun */
#define XSPI_INTR_TX_HALF_EMPTY		0x40	/* TxFIFO is half empty */

#define XIPIF_V123B_RESETR_OFFSET	0x40	/* IPIF reset register */
#define XIPIF_V123B_RESET_MASK		0x0a	/* the value to write */

struct xilinx_spi {
	/* bitbang has to be first */
	struct spi_bitbang bitbang;
	struct completion done;
	void __iomem	*regs;	/* virt. address of the control registers */

	int		irq;

	u8 *rx_ptr;		/* pointer in the Tx buffer */
	const u8 *tx_ptr;	/* pointer in the Rx buffer */
	int remaining_bytes;	/* the number of bytes left to transfer */
	u8 bits_per_word;
	unsigned int (*read_fn) (void __iomem *);
	void (*write_fn) (u32, void __iomem *);
	void (*tx_fn) (struct xilinx_spi *);
	void (*rx_fn) (struct xilinx_spi *);
};

static void xspi_write32(u32 val, void __iomem *addr)
{
	iowrite32(val, addr);
}

static unsigned int xspi_read32(void __iomem *addr)
{
	return ioread32(addr);
}

static void xspi_write32_be(u32 val, void __iomem *addr)
{
	iowrite32be(val, addr);
}

static unsigned int xspi_read32_be(void __iomem *addr)
{
	return ioread32be(addr);
}

static void xspi_tx8(struct xilinx_spi *xspi)
{
	xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr++;
}

static void xspi_tx16(struct xilinx_spi *xspi)
{
	xspi->write_fn(*(u16 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr += 2;
}

static void xspi_tx32(struct xilinx_spi *xspi)
{
	xspi->write_fn(*(u32 *)(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	xspi->tx_ptr += 4;
}

static void xspi_rx8(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*xspi->rx_ptr = data & 0xff;
		xspi->rx_ptr++;
	}
}

static void xspi_rx16(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*(u16 *)(xspi->rx_ptr) = data & 0xffff;
		xspi->rx_ptr += 2;
	}
}

static void xspi_rx32(struct xilinx_spi *xspi)
{
	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	if (xspi->rx_ptr) {
		*(u32 *)(xspi->rx_ptr) = data;
		xspi->rx_ptr += 4;
	}
}

static void xspi_init_hw(struct xilinx_spi *xspi)
{
	void __iomem *regs_base = xspi->regs;

	/* Reset the SPI device */
	xspi->write_fn(XIPIF_V123B_RESET_MASK,
		regs_base + XIPIF_V123B_RESETR_OFFSET);
	/* Disable all the interrupts just in case */
	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	/* Enable the global IPIF interrupt */
	xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
		regs_base + XIPIF_V123B_DGIER_OFFSET);
	/* Deselect the slave on the SPI bus */
	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
	/* Disable the transmitter, enable Manual Slave Select Assertion,
	 * put SPI controller into master mode, and enable it */
	xspi->write_fn(XSPI_CR_TRANS_INHIBIT | XSPI_CR_MANUAL_SSELECT |
		XSPI_CR_MASTER_MODE | XSPI_CR_ENABLE | XSPI_CR_TXFIFO_RESET |
		XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
}

static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);

	if (is_on == BITBANG_CS_INACTIVE) {
		/* Deselect the slave on the SPI bus */
		xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
	} else if (is_on == BITBANG_CS_ACTIVE) {
		/* Set the SPI clock phase and polarity */
		u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
			 & ~XSPI_CR_MODE_MASK;
		if (spi->mode & SPI_CPHA)
			cr |= XSPI_CR_CPHA;
		if (spi->mode & SPI_CPOL)
			cr |= XSPI_CR_CPOL;
		xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);

		/* We do not check spi->max_speed_hz here as the SPI clock
		 * frequency is not software programmable (the IP block design
		 * parameter)
		 */

		/* Activate the chip select */
		xspi->write_fn(~(0x0001 << spi->chip_select),
			xspi->regs + XSPI_SSR_OFFSET);
	}
}

/* spi_bitbang requires custom setup_transfer() to be defined if there is a
 * custom txrx_bufs(). We have nothing to setup here as the SPI IP block
 * supports 8 or 16 bits per word which cannot be changed in software.
 * SPI clock can't be changed in software either.
 * Check for correct bits per word. Chip select delay calculations could be
 * added here as soon as bitbang_work() can be made aware of the delay value.
 */
static int xilinx_spi_setup_transfer(struct spi_device *spi,
		struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	u8 bits_per_word;

	bits_per_word = (t && t->bits_per_word)
			 ? t->bits_per_word : spi->bits_per_word;
	if (bits_per_word != xspi->bits_per_word) {
		dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
			__func__, bits_per_word);
		return -EINVAL;
	}

	return 0;
}

static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
{
	u8 sr;

	/* Fill the Tx FIFO with as many bytes as possible */
	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
		if (xspi->tx_ptr)
			xspi->tx_fn(xspi);
		else
			xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
		xspi->remaining_bytes -= xspi->bits_per_word / 8;
		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	}
}

static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
{
	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	u32 ipif_ier;

	/* We get here with transmitter inhibited */

	xspi->tx_ptr = t->tx_buf;
	xspi->rx_ptr = t->rx_buf;
	xspi->remaining_bytes = t->len;
	INIT_COMPLETION(xspi->done);


	/* Enable the transmit empty interrupt, which we use to determine
	 * progress on the transmission.
	 */
	ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
	xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
		xspi->regs + XIPIF_V123B_IIER_OFFSET);

	for (;;) {
		u16 cr;
		u8 sr;

		xilinx_spi_fill_tx_fifo(xspi);

		/* Start the transfer by not inhibiting the transmitter any
		 * longer
		 */
		cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
							~XSPI_CR_TRANS_INHIBIT;
		xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);

		wait_for_completion(&xspi->done);

		/* A transmit has just completed. Process received data and
		 * check for more data to transmit. Always inhibit the
		 * transmitter while the Isr refills the transmit register/FIFO,
		 * or make sure it is stopped if we're done.
		 */
		cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
		xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
			       xspi->regs + XSPI_CR_OFFSET);

		/* Read out all the data from the Rx FIFO */
		sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
		while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
			xspi->rx_fn(xspi);
			sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
		}

		/* See if there is more data to send */
		if (xspi->remaining_bytes <= 0)
			break;
	}

	/* Disable the transmit empty interrupt */
	xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);

	return t->len - xspi->remaining_bytes;
}


/* This driver supports single master mode only. Hence Tx FIFO Empty
 * is the only interrupt we care about.
 * Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
 * Fault are not to happen.
 */
static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
{
	struct xilinx_spi *xspi = dev_id;
	u32 ipif_isr;

	/* Get the IPIF interrupts, and clear them immediately */
	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);

	if (ipif_isr & XSPI_INTR_TX_EMPTY) {	/* Transmission completed */
		complete(&xspi->done);
	}

	return IRQ_HANDLED;
}

static const struct of_device_id xilinx_spi_of_match[] = {
	{ .compatible = "xlnx,xps-spi-2.00.a", },
	{ .compatible = "xlnx,xps-spi-2.00.b", },
	{}
};
MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);

static int xilinx_spi_probe(struct platform_device *pdev)
{
	struct xilinx_spi *xspi;
	struct xspi_platform_data *pdata;
	struct resource *res;
	int ret, num_cs = 0, bits_per_word = 8;
	struct spi_master *master;
	u32 tmp;
	u8 i;

	pdata = dev_get_platdata(&pdev->dev);
	if (pdata) {
		num_cs = pdata->num_chipselect;
		bits_per_word = pdata->bits_per_word;
	} else {
		of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
					  &num_cs);
	}

	if (!num_cs) {
		dev_err(&pdev->dev,
			"Missing slave select configuration data\n");
		return -EINVAL;
	}

	master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
	if (!master)
		return -ENODEV;

	/* the spi->mode bits understood by this driver: */
	master->mode_bits = SPI_CPOL | SPI_CPHA;

	xspi = spi_master_get_devdata(master);
	xspi->bitbang.master = spi_master_get(master);
	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
	init_completion(&xspi->done);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	xspi->regs = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(xspi->regs)) {
		ret = PTR_ERR(xspi->regs);
		goto put_master;
	}

	master->bus_num = pdev->dev.id;
	master->num_chipselect = num_cs;
	master->dev.of_node = pdev->dev.of_node;

	/*
	 * Detect endianess on the IP via loop bit in CR. Detection
	 * must be done before reset is sent because incorrect reset
	 * value generates error interrupt.
	 * Setup little endian helper functions first and try to use them
	 * and check if bit was correctly setup or not.
	 */
	xspi->read_fn = xspi_read32;
	xspi->write_fn = xspi_write32;

	xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
	tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	tmp &= XSPI_CR_LOOP;
	if (tmp != XSPI_CR_LOOP) {
		xspi->read_fn = xspi_read32_be;
		xspi->write_fn = xspi_write32_be;
	}

	xspi->bits_per_word = bits_per_word;
	if (xspi->bits_per_word == 8) {
		xspi->tx_fn = xspi_tx8;
		xspi->rx_fn = xspi_rx8;
	} else if (xspi->bits_per_word == 16) {
		xspi->tx_fn = xspi_tx16;
		xspi->rx_fn = xspi_rx16;
	} else if (xspi->bits_per_word == 32) {
		xspi->tx_fn = xspi_tx32;
		xspi->rx_fn = xspi_rx32;
	} else {
		ret = -EINVAL;
		goto put_master;
	}

	/* SPI controller initializations */
	xspi_init_hw(xspi);

	xspi->irq = platform_get_irq(pdev, 0);
	if (xspi->irq < 0) {
		ret = xspi->irq;
		goto put_master;
	}

	/* Register for SPI Interrupt */
	ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
			       dev_name(&pdev->dev), xspi);
	if (ret)
		goto put_master;

	ret = spi_bitbang_start(&xspi->bitbang);
	if (ret) {
		dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
		goto put_master;
	}

	dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
		(unsigned long long)res->start, xspi->regs, xspi->irq);

	if (pdata) {
		for (i = 0; i < pdata->num_devices; i++)
			spi_new_device(master, pdata->devices + i);
	}

	platform_set_drvdata(pdev, master);
	return 0;

put_master:
	spi_master_put(master);

	return ret;
}

static int xilinx_spi_remove(struct platform_device *pdev)
{
	struct spi_master *master = platform_get_drvdata(pdev);
	struct xilinx_spi *xspi = spi_master_get_devdata(master);
	void __iomem *regs_base = xspi->regs;

	spi_bitbang_stop(&xspi->bitbang);

	/* Disable all the interrupts just in case */
	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	/* Disable the global IPIF interrupt */
	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);

	spi_master_put(xspi->bitbang.master);

	return 0;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:" XILINX_SPI_NAME);

static struct platform_driver xilinx_spi_driver = {
	.probe = xilinx_spi_probe,
	.remove = xilinx_spi_remove,
	.driver = {
		.name = XILINX_SPI_NAME,
		.owner = THIS_MODULE,
		.of_match_table = xilinx_spi_of_match,
	},
};
module_platform_driver(xilinx_spi_driver);

MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
MODULE_DESCRIPTION("Xilinx SPI driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
ae918c02	1	/*
ae918c02 AK	2	* Xilinx SPI controller driver (master mode only)
	3	*
	4	* Author: MontaVista Software, Inc.
	5	* source@mvista.com
	6	*
8fd8821b GL	7	* Copyright (c) 2010 Secret Lab Technologies, Ltd.
	8	* Copyright (c) 2009 Intel Corporation
	9	* 2002-2007 (c) MontaVista Software, Inc.
	10
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License version 2 as
	13	* published by the Free Software Foundation.
ae918c02 AK	14	*/
	15
	16	#include <linux/module.h>
	17	#include <linux/init.h>
	18	#include <linux/interrupt.h>
eae6cb31	19	#include <linux/of.h>
8fd8821b	20	#include <linux/platform_device.h>
ae918c02 AK	21	#include <linux/spi/spi.h>
ae918c02 AK	22	#include <linux/spi/spi_bitbang.h>
d5af91a1	23	#include <linux/spi/xilinx_spi.h>
eae6cb31	24	#include <linux/io.h>
d5af91a1	25
fc3ba952	26	#define XILINX_SPI_NAME "xilinx_spi"
ae918c02 AK	27
	28	/* Register definitions as per "OPB Serial Peripheral Interface (SPI) (v1.00e)
	29	* Product Specification", DS464
	30	*/
c9da2e12	31	#define XSPI_CR_OFFSET 0x60 /* Control Register */
ae918c02	32
082339bc	33	#define XSPI_CR_LOOP 0x01
ae918c02 AK	34	#define XSPI_CR_ENABLE 0x02
	35	#define XSPI_CR_MASTER_MODE 0x04
	36	#define XSPI_CR_CPOL 0x08
	37	#define XSPI_CR_CPHA 0x10
	38	#define XSPI_CR_MODE_MASK (XSPI_CR_CPHA \| XSPI_CR_CPOL)
	39	#define XSPI_CR_TXFIFO_RESET 0x20
	40	#define XSPI_CR_RXFIFO_RESET 0x40
	41	#define XSPI_CR_MANUAL_SSELECT 0x80
	42	#define XSPI_CR_TRANS_INHIBIT 0x100
c9da2e12	43	#define XSPI_CR_LSB_FIRST 0x200
ae918c02	44
c9da2e12	45	#define XSPI_SR_OFFSET 0x64 /* Status Register */
ae918c02 AK	46
	47	#define XSPI_SR_RX_EMPTY_MASK 0x01 /* Receive FIFO is empty */
	48	#define XSPI_SR_RX_FULL_MASK 0x02 /* Receive FIFO is full */
	49	#define XSPI_SR_TX_EMPTY_MASK 0x04 /* Transmit FIFO is empty */
	50	#define XSPI_SR_TX_FULL_MASK 0x08 /* Transmit FIFO is full */
	51	#define XSPI_SR_MODE_FAULT_MASK 0x10 /* Mode fault error */
	52
c9da2e12 RR	53	#define XSPI_TXD_OFFSET 0x68 /* Data Transmit Register */
c9da2e12 RR	54	#define XSPI_RXD_OFFSET 0x6c /* Data Receive Register */
ae918c02 AK	55
	56	#define XSPI_SSR_OFFSET 0x70 /* 32-bit Slave Select Register */
	57
	58	/* Register definitions as per "OPB IPIF (v3.01c) Product Specification", DS414
	59	* IPIF registers are 32 bit
	60	*/
	61	#define XIPIF_V123B_DGIER_OFFSET 0x1c /* IPIF global int enable reg */
	62	#define XIPIF_V123B_GINTR_ENABLE 0x80000000
	63
	64	#define XIPIF_V123B_IISR_OFFSET 0x20 /* IPIF interrupt status reg */
	65	#define XIPIF_V123B_IIER_OFFSET 0x28 /* IPIF interrupt enable reg */
	66
	67	#define XSPI_INTR_MODE_FAULT 0x01 /* Mode fault error */
	68	#define XSPI_INTR_SLAVE_MODE_FAULT 0x02 /* Selected as slave while
	69	* disabled */
	70	#define XSPI_INTR_TX_EMPTY 0x04 /* TxFIFO is empty */
	71	#define XSPI_INTR_TX_UNDERRUN 0x08 /* TxFIFO was underrun */
	72	#define XSPI_INTR_RX_FULL 0x10 /* RxFIFO is full */
	73	#define XSPI_INTR_RX_OVERRUN 0x20 /* RxFIFO was overrun */
c9da2e12	74	#define XSPI_INTR_TX_HALF_EMPTY 0x40 /* TxFIFO is half empty */
ae918c02 AK	75
	76	#define XIPIF_V123B_RESETR_OFFSET 0x40 /* IPIF reset register */
	77	#define XIPIF_V123B_RESET_MASK 0x0a /* the value to write */
	78
	79	struct xilinx_spi {
	80	/* bitbang has to be first */
	81	struct spi_bitbang bitbang;
	82	struct completion done;
ae918c02 AK	83	void __iomem regs; / virt. address of the control registers */
ae918c02 AK	84
9ca1273b	85	int irq;
ae918c02	86
ae918c02 AK	87	u8 rx_ptr; / pointer in the Tx buffer */
	88	const u8 tx_ptr; / pointer in the Rx buffer */
	89	int remaining_bytes; /* the number of bytes left to transfer */
c9da2e12	90	u8 bits_per_word;
86fc5935 RR	91	unsigned int (read_fn) (void __iomem );
86fc5935 RR	92	void (write_fn) (u32, void __iomem );
c9da2e12 RR	93	void (tx_fn) (struct xilinx_spi );
c9da2e12 RR	94	void (rx_fn) (struct xilinx_spi );
ae918c02 AK	95	};
ae918c02 AK	96
97782149 PM	97	static void xspi_write32(u32 val, void __iomem *addr)
	98	{
	99	iowrite32(val, addr);
	100	}
	101
	102	static unsigned int xspi_read32(void __iomem *addr)
	103	{
	104	return ioread32(addr);
	105	}
	106
	107	static void xspi_write32_be(u32 val, void __iomem *addr)
	108	{
	109	iowrite32be(val, addr);
	110	}
	111
	112	static unsigned int xspi_read32_be(void __iomem *addr)
	113	{
	114	return ioread32be(addr);
	115	}
	116
c9da2e12 RR	117	static void xspi_tx8(struct xilinx_spi *xspi)
	118	{
	119	xspi->write_fn(*xspi->tx_ptr, xspi->regs + XSPI_TXD_OFFSET);
	120	xspi->tx_ptr++;
	121	}
	122
	123	static void xspi_tx16(struct xilinx_spi *xspi)
	124	{
	125	xspi->write_fn((u16 )(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	126	xspi->tx_ptr += 2;
	127	}
	128
	129	static void xspi_tx32(struct xilinx_spi *xspi)
	130	{
	131	xspi->write_fn((u32 )(xspi->tx_ptr), xspi->regs + XSPI_TXD_OFFSET);
	132	xspi->tx_ptr += 4;
	133	}
	134
	135	static void xspi_rx8(struct xilinx_spi *xspi)
	136	{
	137	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	138	if (xspi->rx_ptr) {
	139	*xspi->rx_ptr = data & 0xff;
	140	xspi->rx_ptr++;
	141	}
	142	}
	143
	144	static void xspi_rx16(struct xilinx_spi *xspi)
	145	{
	146	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	147	if (xspi->rx_ptr) {
	148	(u16 )(xspi->rx_ptr) = data & 0xffff;
	149	xspi->rx_ptr += 2;
	150	}
	151	}
	152
	153	static void xspi_rx32(struct xilinx_spi *xspi)
	154	{
	155	u32 data = xspi->read_fn(xspi->regs + XSPI_RXD_OFFSET);
	156	if (xspi->rx_ptr) {
	157	(u32 )(xspi->rx_ptr) = data;
	158	xspi->rx_ptr += 4;
	159	}
	160	}
	161
86fc5935	162	static void xspi_init_hw(struct xilinx_spi *xspi)
ae918c02	163	{
86fc5935 RR	164	void __iomem *regs_base = xspi->regs;
86fc5935 RR	165
ae918c02	166	/* Reset the SPI device */
86fc5935 RR	167	xspi->write_fn(XIPIF_V123B_RESET_MASK,
86fc5935 RR	168	regs_base + XIPIF_V123B_RESETR_OFFSET);
ae918c02	169	/* Disable all the interrupts just in case */
86fc5935	170	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
ae918c02	171	/* Enable the global IPIF interrupt */
86fc5935 RR	172	xspi->write_fn(XIPIF_V123B_GINTR_ENABLE,
86fc5935 RR	173	regs_base + XIPIF_V123B_DGIER_OFFSET);
ae918c02	174	/* Deselect the slave on the SPI bus */
86fc5935	175	xspi->write_fn(0xffff, regs_base + XSPI_SSR_OFFSET);
ae918c02 AK	176	/* Disable the transmitter, enable Manual Slave Select Assertion,
ae918c02 AK	177	* put SPI controller into master mode, and enable it */
86fc5935	178	xspi->write_fn(XSPI_CR_TRANS_INHIBIT \| XSPI_CR_MANUAL_SSELECT \|
c9da2e12 RR	179	XSPI_CR_MASTER_MODE \| XSPI_CR_ENABLE \| XSPI_CR_TXFIFO_RESET \|
c9da2e12 RR	180	XSPI_CR_RXFIFO_RESET, regs_base + XSPI_CR_OFFSET);
ae918c02 AK	181	}
	182
	183	static void xilinx_spi_chipselect(struct spi_device *spi, int is_on)
	184	{
	185	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	186
	187	if (is_on == BITBANG_CS_INACTIVE) {
	188	/* Deselect the slave on the SPI bus */
86fc5935	189	xspi->write_fn(0xffff, xspi->regs + XSPI_SSR_OFFSET);
ae918c02 AK	190	} else if (is_on == BITBANG_CS_ACTIVE) {
ae918c02 AK	191	/* Set the SPI clock phase and polarity */
86fc5935	192	u16 cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET)
ae918c02 AK	193	& ~XSPI_CR_MODE_MASK;
	194	if (spi->mode & SPI_CPHA)
	195	cr \|= XSPI_CR_CPHA;
	196	if (spi->mode & SPI_CPOL)
	197	cr \|= XSPI_CR_CPOL;
86fc5935	198	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
ae918c02 AK	199
	200	/* We do not check spi->max_speed_hz here as the SPI clock
	201	* frequency is not software programmable (the IP block design
	202	* parameter)
	203	*/
	204
	205	/* Activate the chip select */
86fc5935 RR	206	xspi->write_fn(~(0x0001 << spi->chip_select),
86fc5935 RR	207	xspi->regs + XSPI_SSR_OFFSET);
ae918c02 AK	208	}
	209	}
	210
	211	/* spi_bitbang requires custom setup_transfer() to be defined if there is a
	212	* custom txrx_bufs(). We have nothing to setup here as the SPI IP block
c9da2e12 RR	213	* supports 8 or 16 bits per word which cannot be changed in software.
	214	* SPI clock can't be changed in software either.
	215	* Check for correct bits per word. Chip select delay calculations could be
ae918c02 AK	216	* added here as soon as bitbang_work() can be made aware of the delay value.
	217	*/
	218	static int xilinx_spi_setup_transfer(struct spi_device *spi,
	219	struct spi_transfer *t)
	220	{
c9da2e12	221	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
ae918c02	222	u8 bits_per_word;
ae918c02	223
1a8d3b77 JL	224	bits_per_word = (t && t->bits_per_word)
1a8d3b77 JL	225	? t->bits_per_word : spi->bits_per_word;
c9da2e12	226	if (bits_per_word != xspi->bits_per_word) {
ae918c02	227	dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
b687d2a8	228	__func__, bits_per_word);
ae918c02 AK	229	return -EINVAL;
	230	}
	231
ae918c02 AK	232	return 0;
	233	}
	234
ae918c02 AK	235	static void xilinx_spi_fill_tx_fifo(struct xilinx_spi *xspi)
	236	{
	237	u8 sr;
	238
	239	/* Fill the Tx FIFO with as many bytes as possible */
86fc5935	240	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02	241	while ((sr & XSPI_SR_TX_FULL_MASK) == 0 && xspi->remaining_bytes > 0) {
86fc5935	242	if (xspi->tx_ptr)
c9da2e12	243	xspi->tx_fn(xspi);
86fc5935 RR	244	else
86fc5935 RR	245	xspi->write_fn(0, xspi->regs + XSPI_TXD_OFFSET);
c9da2e12	246	xspi->remaining_bytes -= xspi->bits_per_word / 8;
86fc5935	247	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
ae918c02 AK	248	}
	249	}
	250
	251	static int xilinx_spi_txrx_bufs(struct spi_device spi, struct spi_transfer t)
	252	{
	253	struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
	254	u32 ipif_ier;
ae918c02 AK	255
	256	/* We get here with transmitter inhibited */
	257
	258	xspi->tx_ptr = t->tx_buf;
	259	xspi->rx_ptr = t->rx_buf;
	260	xspi->remaining_bytes = t->len;
	261	INIT_COMPLETION(xspi->done);
	262
ae918c02 AK	263
	264	/* Enable the transmit empty interrupt, which we use to determine
	265	* progress on the transmission.
	266	*/
86fc5935 RR	267	ipif_ier = xspi->read_fn(xspi->regs + XIPIF_V123B_IIER_OFFSET);
	268	xspi->write_fn(ipif_ier \| XSPI_INTR_TX_EMPTY,
	269	xspi->regs + XIPIF_V123B_IIER_OFFSET);
ae918c02	270
68c315bb PC	271	for (;;) {
	272	u16 cr;
	273	u8 sr;
	274
	275	xilinx_spi_fill_tx_fifo(xspi);
	276
	277	/* Start the transfer by not inhibiting the transmitter any
	278	* longer
	279	*/
	280	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
	281	~XSPI_CR_TRANS_INHIBIT;
	282	xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
	283
	284	wait_for_completion(&xspi->done);
	285
	286	/* A transmit has just completed. Process received data and
	287	* check for more data to transmit. Always inhibit the
	288	* transmitter while the Isr refills the transmit register/FIFO,
	289	* or make sure it is stopped if we're done.
	290	*/
	291	cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	292	xspi->write_fn(cr \| XSPI_CR_TRANS_INHIBIT,
	293	xspi->regs + XSPI_CR_OFFSET);
	294
	295	/* Read out all the data from the Rx FIFO */
	296	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	297	while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
	298	xspi->rx_fn(xspi);
	299	sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
	300	}
ae918c02	301
68c315bb	302	/* See if there is more data to send */
e33d085d	303	if (xspi->remaining_bytes <= 0)
68c315bb PC	304	break;
68c315bb PC	305	}
ae918c02 AK	306
ae918c02 AK	307	/* Disable the transmit empty interrupt */
86fc5935	308	xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
ae918c02 AK	309
	310	return t->len - xspi->remaining_bytes;
	311	}
	312
	313
	314	/* This driver supports single master mode only. Hence Tx FIFO Empty
	315	* is the only interrupt we care about.
	316	* Receive FIFO Overrun, Transmit FIFO Underrun, Mode Fault, and Slave Mode
	317	* Fault are not to happen.
	318	*/
	319	static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
	320	{
	321	struct xilinx_spi *xspi = dev_id;
	322	u32 ipif_isr;
	323
	324	/* Get the IPIF interrupts, and clear them immediately */
86fc5935 RR	325	ipif_isr = xspi->read_fn(xspi->regs + XIPIF_V123B_IISR_OFFSET);
86fc5935 RR	326	xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
ae918c02 AK	327
ae918c02 AK	328	if (ipif_isr & XSPI_INTR_TX_EMPTY) { /* Transmission completed */
68c315bb	329	complete(&xspi->done);
ae918c02 AK	330	}
	331
	332	return IRQ_HANDLED;
	333	}
	334
eae6cb31 GL	335	static const struct of_device_id xilinx_spi_of_match[] = {
	336	{ .compatible = "xlnx,xps-spi-2.00.a", },
	337	{ .compatible = "xlnx,xps-spi-2.00.b", },
	338	{}
	339	};
	340	MODULE_DEVICE_TABLE(of, xilinx_spi_of_match);
eae6cb31	341
7cb2abd0	342	static int xilinx_spi_probe(struct platform_device *pdev)
ae918c02	343	{
ae918c02	344	struct xilinx_spi *xspi;
d81c0bbb	345	struct xspi_platform_data *pdata;
ad3fdbca	346	struct resource *res;
7b3b7432	347	int ret, num_cs = 0, bits_per_word = 8;
d81c0bbb	348	struct spi_master *master;
082339bc	349	u32 tmp;
d81c0bbb MB	350	u8 i;
d81c0bbb MB	351
8074cf06	352	pdata = dev_get_platdata(&pdev->dev);
d81c0bbb MB	353	if (pdata) {
	354	num_cs = pdata->num_chipselect;
	355	bits_per_word = pdata->bits_per_word;
be3acdff MS	356	} else {
	357	of_property_read_u32(pdev->dev.of_node, "xlnx,num-ss-bits",
	358	&num_cs);
d81c0bbb	359	}
ae918c02	360
d81c0bbb	361	if (!num_cs) {
7cb2abd0 MB	362	dev_err(&pdev->dev,
7cb2abd0 MB	363	"Missing slave select configuration data\n");
d81c0bbb MB	364	return -EINVAL;
	365	}
	366
7cb2abd0	367	master = spi_alloc_master(&pdev->dev, sizeof(struct xilinx_spi));
d5af91a1	368	if (!master)
d81c0bbb	369	return -ENODEV;
ae918c02	370
e7db06b5 DB	371	/* the spi->mode bits understood by this driver: */
	372	master->mode_bits = SPI_CPOL \| SPI_CPHA;
	373
ae918c02 AK	374	xspi = spi_master_get_devdata(master);
	375	xspi->bitbang.master = spi_master_get(master);
	376	xspi->bitbang.chipselect = xilinx_spi_chipselect;
	377	xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer;
	378	xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs;
ae918c02 AK	379	init_completion(&xspi->done);
ae918c02 AK	380
ad3fdbca MS	381	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ad3fdbca MS	382	xspi->regs = devm_ioremap_resource(&pdev->dev, res);
c40537d0 MB	383	if (IS_ERR(xspi->regs)) {
c40537d0 MB	384	ret = PTR_ERR(xspi->regs);
ae918c02	385	goto put_master;
ae918c02 AK	386	}
ae918c02 AK	387
7cb2abd0	388	master->bus_num = pdev->dev.id;
91565c40	389	master->num_chipselect = num_cs;
7cb2abd0	390	master->dev.of_node = pdev->dev.of_node;
ae918c02	391
082339bc MS	392	/*
	393	* Detect endianess on the IP via loop bit in CR. Detection
	394	* must be done before reset is sent because incorrect reset
	395	* value generates error interrupt.
	396	* Setup little endian helper functions first and try to use them
	397	* and check if bit was correctly setup or not.
	398	*/
	399	xspi->read_fn = xspi_read32;
	400	xspi->write_fn = xspi_write32;
	401
	402	xspi->write_fn(XSPI_CR_LOOP, xspi->regs + XSPI_CR_OFFSET);
	403	tmp = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
	404	tmp &= XSPI_CR_LOOP;
	405	if (tmp != XSPI_CR_LOOP) {
97782149 PM	406	xspi->read_fn = xspi_read32_be;
97782149 PM	407	xspi->write_fn = xspi_write32_be;
86fc5935	408	}
082339bc	409
91565c40	410	xspi->bits_per_word = bits_per_word;
c9da2e12 RR	411	if (xspi->bits_per_word == 8) {
	412	xspi->tx_fn = xspi_tx8;
	413	xspi->rx_fn = xspi_rx8;
	414	} else if (xspi->bits_per_word == 16) {
	415	xspi->tx_fn = xspi_tx16;
	416	xspi->rx_fn = xspi_rx16;
	417	} else if (xspi->bits_per_word == 32) {
	418	xspi->tx_fn = xspi_tx32;
	419	xspi->rx_fn = xspi_rx32;
d81c0bbb MB	420	} else {
d81c0bbb MB	421	ret = -EINVAL;
c40537d0	422	goto put_master;
d81c0bbb	423	}
c9da2e12	424
ae918c02	425	/* SPI controller initializations */
86fc5935	426	xspi_init_hw(xspi);
ae918c02	427
7b3b7432 MS	428	xspi->irq = platform_get_irq(pdev, 0);
	429	if (xspi->irq < 0) {
	430	ret = xspi->irq;
	431	goto put_master;
	432	}
	433
ae918c02	434	/* Register for SPI Interrupt */
7b3b7432 MS	435	ret = devm_request_irq(&pdev->dev, xspi->irq, xilinx_spi_irq, 0,
7b3b7432 MS	436	dev_name(&pdev->dev), xspi);
d5af91a1	437	if (ret)
c40537d0	438	goto put_master;
ae918c02	439
d5af91a1 RR	440	ret = spi_bitbang_start(&xspi->bitbang);
d5af91a1 RR	441	if (ret) {
7cb2abd0	442	dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
7b3b7432	443	goto put_master;
ae918c02 AK	444	}
ae918c02 AK	445
7cb2abd0	446	dev_info(&pdev->dev, "at 0x%08llX mapped to 0x%p, irq=%d\n",
ad3fdbca	447	(unsigned long long)res->start, xspi->regs, xspi->irq);
d81c0bbb MB	448
	449	if (pdata) {
	450	for (i = 0; i < pdata->num_devices; i++)
	451	spi_new_device(master, pdata->devices + i);
	452	}
	453
7cb2abd0	454	platform_set_drvdata(pdev, master);
d81c0bbb	455	return 0;
ae918c02	456
ae918c02 AK	457	put_master:
ae918c02 AK	458	spi_master_put(master);
d81c0bbb MB	459
d81c0bbb MB	460	return ret;
ae918c02 AK	461	}
ae918c02 AK	462
7cb2abd0	463	static int xilinx_spi_remove(struct platform_device *pdev)
ae918c02	464	{
7cb2abd0	465	struct spi_master *master = platform_get_drvdata(pdev);
d81c0bbb	466	struct xilinx_spi *xspi = spi_master_get_devdata(master);
7b3b7432	467	void __iomem *regs_base = xspi->regs;
ae918c02 AK	468
ae918c02 AK	469	spi_bitbang_stop(&xspi->bitbang);
7b3b7432 MS	470
	471	/* Disable all the interrupts just in case */
	472	xspi->write_fn(0, regs_base + XIPIF_V123B_IIER_OFFSET);
	473	/* Disable the global IPIF interrupt */
	474	xspi->write_fn(0, regs_base + XIPIF_V123B_DGIER_OFFSET);
ff82c587	475
d5af91a1	476	spi_master_put(xspi->bitbang.master);
8fd8821b GL	477
	478	return 0;
	479	}
	480
	481	/* work with hotplug and coldplug */
	482	MODULE_ALIAS("platform:" XILINX_SPI_NAME);
	483
	484	static struct platform_driver xilinx_spi_driver = {
	485	.probe = xilinx_spi_probe,
fd4a319b	486	.remove = xilinx_spi_remove,
8fd8821b GL	487	.driver = {
	488	.name = XILINX_SPI_NAME,
	489	.owner = THIS_MODULE,
eae6cb31	490	.of_match_table = xilinx_spi_of_match,
8fd8821b GL	491	},
8fd8821b GL	492	};
940ab889	493	module_platform_driver(xilinx_spi_driver);
8fd8821b	494
ae918c02 AK	495	MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
	496	MODULE_DESCRIPTION("Xilinx SPI driver");
	497	MODULE_LICENSE("GPL");