Commit | Line | Data |
---|---|---|
a5f6abd4 | 1 | /* |
26fdc1f0 | 2 | * Blackfin On-Chip SPI Driver |
a5f6abd4 | 3 | * |
131b17d4 | 4 | * Copyright 2004-2007 Analog Devices Inc. |
a5f6abd4 | 5 | * |
26fdc1f0 | 6 | * Enter bugs at http://blackfin.uclinux.org/ |
a5f6abd4 | 7 | * |
26fdc1f0 | 8 | * Licensed under the GPL-2 or later. |
a5f6abd4 WB |
9 | */ |
10 | ||
11 | #include <linux/init.h> | |
12 | #include <linux/module.h> | |
131b17d4 | 13 | #include <linux/delay.h> |
a5f6abd4 | 14 | #include <linux/device.h> |
131b17d4 | 15 | #include <linux/io.h> |
a5f6abd4 | 16 | #include <linux/ioport.h> |
131b17d4 | 17 | #include <linux/irq.h> |
a5f6abd4 WB |
18 | #include <linux/errno.h> |
19 | #include <linux/interrupt.h> | |
20 | #include <linux/platform_device.h> | |
21 | #include <linux/dma-mapping.h> | |
22 | #include <linux/spi/spi.h> | |
23 | #include <linux/workqueue.h> | |
a5f6abd4 | 24 | |
a5f6abd4 | 25 | #include <asm/dma.h> |
131b17d4 | 26 | #include <asm/portmux.h> |
a5f6abd4 | 27 | #include <asm/bfin5xx_spi.h> |
8cf5858c VM |
28 | #include <asm/cacheflush.h> |
29 | ||
a32c691d BW |
30 | #define DRV_NAME "bfin-spi" |
31 | #define DRV_AUTHOR "Bryan Wu, Luke Yang" | |
138f97cd | 32 | #define DRV_DESC "Blackfin on-chip SPI Controller Driver" |
a32c691d BW |
33 | #define DRV_VERSION "1.0" |
34 | ||
35 | MODULE_AUTHOR(DRV_AUTHOR); | |
36 | MODULE_DESCRIPTION(DRV_DESC); | |
a5f6abd4 WB |
37 | MODULE_LICENSE("GPL"); |
38 | ||
bb90eb00 BW |
39 | #define START_STATE ((void *)0) |
40 | #define RUNNING_STATE ((void *)1) | |
41 | #define DONE_STATE ((void *)2) | |
42 | #define ERROR_STATE ((void *)-1) | |
43 | #define QUEUE_RUNNING 0 | |
44 | #define QUEUE_STOPPED 1 | |
a5f6abd4 | 45 | |
93b61bdd WM |
46 | /* Value to send if no TX value is supplied */ |
47 | #define SPI_IDLE_TXVAL 0x0000 | |
48 | ||
a5f6abd4 WB |
49 | struct driver_data { |
50 | /* Driver model hookup */ | |
51 | struct platform_device *pdev; | |
52 | ||
53 | /* SPI framework hookup */ | |
54 | struct spi_master *master; | |
55 | ||
bb90eb00 | 56 | /* Regs base of SPI controller */ |
f452126c | 57 | void __iomem *regs_base; |
bb90eb00 | 58 | |
003d9226 BW |
59 | /* Pin request list */ |
60 | u16 *pin_req; | |
61 | ||
a5f6abd4 WB |
62 | /* BFIN hookup */ |
63 | struct bfin5xx_spi_master *master_info; | |
64 | ||
65 | /* Driver message queue */ | |
66 | struct workqueue_struct *workqueue; | |
67 | struct work_struct pump_messages; | |
68 | spinlock_t lock; | |
69 | struct list_head queue; | |
70 | int busy; | |
71 | int run; | |
72 | ||
73 | /* Message Transfer pump */ | |
74 | struct tasklet_struct pump_transfers; | |
75 | ||
76 | /* Current message transfer state info */ | |
77 | struct spi_message *cur_msg; | |
78 | struct spi_transfer *cur_transfer; | |
79 | struct chip_data *cur_chip; | |
80 | size_t len_in_bytes; | |
81 | size_t len; | |
82 | void *tx; | |
83 | void *tx_end; | |
84 | void *rx; | |
85 | void *rx_end; | |
bb90eb00 BW |
86 | |
87 | /* DMA stuffs */ | |
88 | int dma_channel; | |
a5f6abd4 | 89 | int dma_mapped; |
bb90eb00 | 90 | int dma_requested; |
a5f6abd4 WB |
91 | dma_addr_t rx_dma; |
92 | dma_addr_t tx_dma; | |
bb90eb00 | 93 | |
a5f6abd4 WB |
94 | size_t rx_map_len; |
95 | size_t tx_map_len; | |
96 | u8 n_bytes; | |
fad91c89 | 97 | int cs_change; |
a5f6abd4 WB |
98 | void (*write) (struct driver_data *); |
99 | void (*read) (struct driver_data *); | |
100 | void (*duplex) (struct driver_data *); | |
101 | }; | |
102 | ||
103 | struct chip_data { | |
104 | u16 ctl_reg; | |
105 | u16 baud; | |
106 | u16 flag; | |
107 | ||
108 | u8 chip_select_num; | |
109 | u8 n_bytes; | |
88b40369 | 110 | u8 width; /* 0 or 1 */ |
a5f6abd4 WB |
111 | u8 enable_dma; |
112 | u8 bits_per_word; /* 8 or 16 */ | |
113 | u8 cs_change_per_word; | |
62310e51 | 114 | u16 cs_chg_udelay; /* Some devices require > 255usec delay */ |
42c78b2b | 115 | u32 cs_gpio; |
93b61bdd | 116 | u16 idle_tx_val; |
a5f6abd4 WB |
117 | void (*write) (struct driver_data *); |
118 | void (*read) (struct driver_data *); | |
119 | void (*duplex) (struct driver_data *); | |
120 | }; | |
121 | ||
bb90eb00 BW |
122 | #define DEFINE_SPI_REG(reg, off) \ |
123 | static inline u16 read_##reg(struct driver_data *drv_data) \ | |
124 | { return bfin_read16(drv_data->regs_base + off); } \ | |
125 | static inline void write_##reg(struct driver_data *drv_data, u16 v) \ | |
126 | { bfin_write16(drv_data->regs_base + off, v); } | |
127 | ||
128 | DEFINE_SPI_REG(CTRL, 0x00) | |
129 | DEFINE_SPI_REG(FLAG, 0x04) | |
130 | DEFINE_SPI_REG(STAT, 0x08) | |
131 | DEFINE_SPI_REG(TDBR, 0x0C) | |
132 | DEFINE_SPI_REG(RDBR, 0x10) | |
133 | DEFINE_SPI_REG(BAUD, 0x14) | |
134 | DEFINE_SPI_REG(SHAW, 0x18) | |
135 | ||
88b40369 | 136 | static void bfin_spi_enable(struct driver_data *drv_data) |
a5f6abd4 WB |
137 | { |
138 | u16 cr; | |
139 | ||
bb90eb00 BW |
140 | cr = read_CTRL(drv_data); |
141 | write_CTRL(drv_data, (cr | BIT_CTL_ENABLE)); | |
a5f6abd4 WB |
142 | } |
143 | ||
88b40369 | 144 | static void bfin_spi_disable(struct driver_data *drv_data) |
a5f6abd4 WB |
145 | { |
146 | u16 cr; | |
147 | ||
bb90eb00 BW |
148 | cr = read_CTRL(drv_data); |
149 | write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE))); | |
a5f6abd4 WB |
150 | } |
151 | ||
152 | /* Caculate the SPI_BAUD register value based on input HZ */ | |
153 | static u16 hz_to_spi_baud(u32 speed_hz) | |
154 | { | |
155 | u_long sclk = get_sclk(); | |
156 | u16 spi_baud = (sclk / (2 * speed_hz)); | |
157 | ||
158 | if ((sclk % (2 * speed_hz)) > 0) | |
159 | spi_baud++; | |
160 | ||
7513e006 MH |
161 | if (spi_baud < MIN_SPI_BAUD_VAL) |
162 | spi_baud = MIN_SPI_BAUD_VAL; | |
163 | ||
a5f6abd4 WB |
164 | return spi_baud; |
165 | } | |
166 | ||
138f97cd | 167 | static int bfin_spi_flush(struct driver_data *drv_data) |
a5f6abd4 WB |
168 | { |
169 | unsigned long limit = loops_per_jiffy << 1; | |
170 | ||
171 | /* wait for stop and clear stat */ | |
b4bd2aba | 172 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && --limit) |
d8c05008 | 173 | cpu_relax(); |
a5f6abd4 | 174 | |
bb90eb00 | 175 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 WB |
176 | |
177 | return limit; | |
178 | } | |
179 | ||
fad91c89 | 180 | /* Chip select operation functions for cs_change flag */ |
138f97cd | 181 | static void bfin_spi_cs_active(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 182 | { |
42c78b2b MH |
183 | if (likely(chip->chip_select_num)) { |
184 | u16 flag = read_FLAG(drv_data); | |
fad91c89 | 185 | |
42c78b2b MH |
186 | flag |= chip->flag; |
187 | flag &= ~(chip->flag << 8); | |
fad91c89 | 188 | |
42c78b2b MH |
189 | write_FLAG(drv_data, flag); |
190 | } else { | |
191 | gpio_set_value(chip->cs_gpio, 0); | |
192 | } | |
fad91c89 BW |
193 | } |
194 | ||
138f97cd | 195 | static void bfin_spi_cs_deactive(struct driver_data *drv_data, struct chip_data *chip) |
fad91c89 | 196 | { |
42c78b2b MH |
197 | if (likely(chip->chip_select_num)) { |
198 | u16 flag = read_FLAG(drv_data); | |
fad91c89 | 199 | |
42c78b2b MH |
200 | flag &= ~chip->flag; |
201 | flag |= (chip->flag << 8); | |
fad91c89 | 202 | |
42c78b2b MH |
203 | write_FLAG(drv_data, flag); |
204 | } else { | |
205 | gpio_set_value(chip->cs_gpio, 1); | |
206 | } | |
62310e51 BW |
207 | |
208 | /* Move delay here for consistency */ | |
209 | if (chip->cs_chg_udelay) | |
210 | udelay(chip->cs_chg_udelay); | |
fad91c89 BW |
211 | } |
212 | ||
a5f6abd4 | 213 | /* stop controller and re-config current chip*/ |
138f97cd | 214 | static void bfin_spi_restore_state(struct driver_data *drv_data) |
a5f6abd4 WB |
215 | { |
216 | struct chip_data *chip = drv_data->cur_chip; | |
12e17c42 | 217 | |
a5f6abd4 | 218 | /* Clear status and disable clock */ |
bb90eb00 | 219 | write_STAT(drv_data, BIT_STAT_CLR); |
a5f6abd4 | 220 | bfin_spi_disable(drv_data); |
88b40369 | 221 | dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n"); |
a5f6abd4 | 222 | |
5fec5b5a | 223 | /* Load the registers */ |
bb90eb00 | 224 | write_CTRL(drv_data, chip->ctl_reg); |
092e1fda | 225 | write_BAUD(drv_data, chip->baud); |
cc487e73 SZ |
226 | |
227 | bfin_spi_enable(drv_data); | |
138f97cd | 228 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 WB |
229 | } |
230 | ||
93b61bdd WM |
231 | /* used to kick off transfer in rx mode and read unwanted RX data */ |
232 | static inline void bfin_spi_dummy_read(struct driver_data *drv_data) | |
a5f6abd4 | 233 | { |
93b61bdd | 234 | (void) read_RDBR(drv_data); |
a5f6abd4 WB |
235 | } |
236 | ||
138f97cd | 237 | static void bfin_spi_null_writer(struct driver_data *drv_data) |
a5f6abd4 WB |
238 | { |
239 | u8 n_bytes = drv_data->n_bytes; | |
93b61bdd WM |
240 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
241 | ||
242 | /* clear RXS (we check for RXS inside the loop) */ | |
243 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 WB |
244 | |
245 | while (drv_data->tx < drv_data->tx_end) { | |
93b61bdd | 246 | write_TDBR(drv_data, tx_val); |
a5f6abd4 | 247 | drv_data->tx += n_bytes; |
93b61bdd WM |
248 | /* wait until transfer finished. |
249 | checking SPIF or TXS may not guarantee transfer completion */ | |
250 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
251 | cpu_relax(); | |
252 | /* discard RX data and clear RXS */ | |
253 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 WB |
254 | } |
255 | } | |
256 | ||
138f97cd | 257 | static void bfin_spi_null_reader(struct driver_data *drv_data) |
a5f6abd4 WB |
258 | { |
259 | u8 n_bytes = drv_data->n_bytes; | |
93b61bdd WM |
260 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
261 | ||
262 | /* discard old RX data and clear RXS */ | |
138f97cd | 263 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 WB |
264 | |
265 | while (drv_data->rx < drv_data->rx_end) { | |
93b61bdd WM |
266 | write_TDBR(drv_data, tx_val); |
267 | drv_data->rx += n_bytes; | |
bb90eb00 | 268 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 269 | cpu_relax(); |
138f97cd | 270 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 WB |
271 | } |
272 | } | |
273 | ||
138f97cd | 274 | static void bfin_spi_u8_writer(struct driver_data *drv_data) |
a5f6abd4 | 275 | { |
93b61bdd WM |
276 | /* clear RXS (we check for RXS inside the loop) */ |
277 | bfin_spi_dummy_read(drv_data); | |
cc487e73 | 278 | |
a5f6abd4 | 279 | while (drv_data->tx < drv_data->tx_end) { |
93b61bdd WM |
280 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
281 | /* wait until transfer finished. | |
282 | checking SPIF or TXS may not guarantee transfer completion */ | |
283 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
d8c05008 | 284 | cpu_relax(); |
93b61bdd WM |
285 | /* discard RX data and clear RXS */ |
286 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 287 | } |
a5f6abd4 WB |
288 | } |
289 | ||
138f97cd | 290 | static void bfin_spi_u8_cs_chg_writer(struct driver_data *drv_data) |
a5f6abd4 WB |
291 | { |
292 | struct chip_data *chip = drv_data->cur_chip; | |
293 | ||
93b61bdd WM |
294 | /* clear RXS (we check for RXS inside the loop) */ |
295 | bfin_spi_dummy_read(drv_data); | |
296 | ||
a5f6abd4 | 297 | while (drv_data->tx < drv_data->tx_end) { |
138f97cd | 298 | bfin_spi_cs_active(drv_data, chip); |
93b61bdd WM |
299 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
300 | /* make sure transfer finished before deactiving CS */ | |
301 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
e26aa015 | 302 | cpu_relax(); |
93b61bdd | 303 | bfin_spi_dummy_read(drv_data); |
138f97cd | 304 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 305 | } |
a5f6abd4 WB |
306 | } |
307 | ||
138f97cd | 308 | static void bfin_spi_u8_reader(struct driver_data *drv_data) |
a5f6abd4 | 309 | { |
93b61bdd | 310 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
a5f6abd4 | 311 | |
93b61bdd | 312 | /* discard old RX data and clear RXS */ |
138f97cd | 313 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 314 | |
93b61bdd WM |
315 | while (drv_data->rx < drv_data->rx_end) { |
316 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 317 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 318 | cpu_relax(); |
93b61bdd | 319 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 | 320 | } |
a5f6abd4 WB |
321 | } |
322 | ||
138f97cd | 323 | static void bfin_spi_u8_cs_chg_reader(struct driver_data *drv_data) |
a5f6abd4 WB |
324 | { |
325 | struct chip_data *chip = drv_data->cur_chip; | |
93b61bdd WM |
326 | u16 tx_val = chip->idle_tx_val; |
327 | ||
328 | /* discard old RX data and clear RXS */ | |
329 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 330 | |
e26aa015 | 331 | while (drv_data->rx < drv_data->rx_end) { |
138f97cd | 332 | bfin_spi_cs_active(drv_data, chip); |
93b61bdd | 333 | write_TDBR(drv_data, tx_val); |
e26aa015 BW |
334 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
335 | cpu_relax(); | |
93b61bdd | 336 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
138f97cd | 337 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 338 | } |
a5f6abd4 WB |
339 | } |
340 | ||
138f97cd | 341 | static void bfin_spi_u8_duplex(struct driver_data *drv_data) |
a5f6abd4 | 342 | { |
93b61bdd WM |
343 | /* discard old RX data and clear RXS */ |
344 | bfin_spi_dummy_read(drv_data); | |
345 | ||
a5f6abd4 | 346 | while (drv_data->rx < drv_data->rx_end) { |
93b61bdd | 347 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 348 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 349 | cpu_relax(); |
93b61bdd | 350 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
a5f6abd4 WB |
351 | } |
352 | } | |
353 | ||
138f97cd | 354 | static void bfin_spi_u8_cs_chg_duplex(struct driver_data *drv_data) |
a5f6abd4 WB |
355 | { |
356 | struct chip_data *chip = drv_data->cur_chip; | |
357 | ||
93b61bdd WM |
358 | /* discard old RX data and clear RXS */ |
359 | bfin_spi_dummy_read(drv_data); | |
360 | ||
a5f6abd4 | 361 | while (drv_data->rx < drv_data->rx_end) { |
138f97cd | 362 | bfin_spi_cs_active(drv_data, chip); |
93b61bdd | 363 | write_TDBR(drv_data, (*(u8 *) (drv_data->tx++))); |
bb90eb00 | 364 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 365 | cpu_relax(); |
93b61bdd | 366 | *(u8 *) (drv_data->rx++) = read_RDBR(drv_data); |
138f97cd | 367 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 368 | } |
a5f6abd4 WB |
369 | } |
370 | ||
138f97cd | 371 | static void bfin_spi_u16_writer(struct driver_data *drv_data) |
a5f6abd4 | 372 | { |
93b61bdd WM |
373 | /* clear RXS (we check for RXS inside the loop) */ |
374 | bfin_spi_dummy_read(drv_data); | |
88b40369 | 375 | |
a5f6abd4 | 376 | while (drv_data->tx < drv_data->tx_end) { |
bb90eb00 | 377 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
a5f6abd4 | 378 | drv_data->tx += 2; |
93b61bdd WM |
379 | /* wait until transfer finished. |
380 | checking SPIF or TXS may not guarantee transfer completion */ | |
381 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
382 | cpu_relax(); | |
383 | /* discard RX data and clear RXS */ | |
384 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 385 | } |
a5f6abd4 WB |
386 | } |
387 | ||
138f97cd | 388 | static void bfin_spi_u16_cs_chg_writer(struct driver_data *drv_data) |
a5f6abd4 WB |
389 | { |
390 | struct chip_data *chip = drv_data->cur_chip; | |
391 | ||
93b61bdd WM |
392 | /* clear RXS (we check for RXS inside the loop) */ |
393 | bfin_spi_dummy_read(drv_data); | |
394 | ||
a5f6abd4 | 395 | while (drv_data->tx < drv_data->tx_end) { |
138f97cd | 396 | bfin_spi_cs_active(drv_data, chip); |
bb90eb00 | 397 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd WM |
398 | drv_data->tx += 2; |
399 | /* make sure transfer finished before deactiving CS */ | |
400 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) | |
13f3e642 | 401 | cpu_relax(); |
93b61bdd | 402 | bfin_spi_dummy_read(drv_data); |
138f97cd | 403 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 404 | } |
a5f6abd4 WB |
405 | } |
406 | ||
138f97cd | 407 | static void bfin_spi_u16_reader(struct driver_data *drv_data) |
a5f6abd4 | 408 | { |
93b61bdd | 409 | u16 tx_val = drv_data->cur_chip->idle_tx_val; |
cc487e73 | 410 | |
93b61bdd | 411 | /* discard old RX data and clear RXS */ |
138f97cd | 412 | bfin_spi_dummy_read(drv_data); |
a5f6abd4 | 413 | |
93b61bdd WM |
414 | while (drv_data->rx < drv_data->rx_end) { |
415 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 416 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 417 | cpu_relax(); |
bb90eb00 | 418 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 WB |
419 | drv_data->rx += 2; |
420 | } | |
a5f6abd4 WB |
421 | } |
422 | ||
138f97cd | 423 | static void bfin_spi_u16_cs_chg_reader(struct driver_data *drv_data) |
a5f6abd4 WB |
424 | { |
425 | struct chip_data *chip = drv_data->cur_chip; | |
93b61bdd | 426 | u16 tx_val = chip->idle_tx_val; |
a5f6abd4 | 427 | |
93b61bdd | 428 | /* discard old RX data and clear RXS */ |
138f97cd | 429 | bfin_spi_dummy_read(drv_data); |
cc487e73 | 430 | |
93b61bdd WM |
431 | while (drv_data->rx < drv_data->rx_end) { |
432 | bfin_spi_cs_active(drv_data, chip); | |
433 | write_TDBR(drv_data, tx_val); | |
bb90eb00 | 434 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 435 | cpu_relax(); |
bb90eb00 | 436 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 437 | drv_data->rx += 2; |
93b61bdd | 438 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 439 | } |
a5f6abd4 WB |
440 | } |
441 | ||
138f97cd | 442 | static void bfin_spi_u16_duplex(struct driver_data *drv_data) |
a5f6abd4 | 443 | { |
93b61bdd WM |
444 | /* discard old RX data and clear RXS */ |
445 | bfin_spi_dummy_read(drv_data); | |
446 | ||
447 | while (drv_data->rx < drv_data->rx_end) { | |
bb90eb00 | 448 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 449 | drv_data->tx += 2; |
bb90eb00 | 450 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 451 | cpu_relax(); |
bb90eb00 | 452 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 453 | drv_data->rx += 2; |
a5f6abd4 WB |
454 | } |
455 | } | |
456 | ||
138f97cd | 457 | static void bfin_spi_u16_cs_chg_duplex(struct driver_data *drv_data) |
a5f6abd4 WB |
458 | { |
459 | struct chip_data *chip = drv_data->cur_chip; | |
460 | ||
93b61bdd WM |
461 | /* discard old RX data and clear RXS */ |
462 | bfin_spi_dummy_read(drv_data); | |
a5f6abd4 | 463 | |
93b61bdd WM |
464 | while (drv_data->rx < drv_data->rx_end) { |
465 | bfin_spi_cs_active(drv_data, chip); | |
bb90eb00 | 466 | write_TDBR(drv_data, (*(u16 *) (drv_data->tx))); |
93b61bdd | 467 | drv_data->tx += 2; |
bb90eb00 | 468 | while (!(read_STAT(drv_data) & BIT_STAT_RXS)) |
d8c05008 | 469 | cpu_relax(); |
bb90eb00 | 470 | *(u16 *) (drv_data->rx) = read_RDBR(drv_data); |
a5f6abd4 | 471 | drv_data->rx += 2; |
93b61bdd | 472 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 473 | } |
a5f6abd4 WB |
474 | } |
475 | ||
476 | /* test if ther is more transfer to be done */ | |
138f97cd | 477 | static void *bfin_spi_next_transfer(struct driver_data *drv_data) |
a5f6abd4 WB |
478 | { |
479 | struct spi_message *msg = drv_data->cur_msg; | |
480 | struct spi_transfer *trans = drv_data->cur_transfer; | |
481 | ||
482 | /* Move to next transfer */ | |
483 | if (trans->transfer_list.next != &msg->transfers) { | |
484 | drv_data->cur_transfer = | |
485 | list_entry(trans->transfer_list.next, | |
486 | struct spi_transfer, transfer_list); | |
487 | return RUNNING_STATE; | |
488 | } else | |
489 | return DONE_STATE; | |
490 | } | |
491 | ||
492 | /* | |
493 | * caller already set message->status; | |
494 | * dma and pio irqs are blocked give finished message back | |
495 | */ | |
138f97cd | 496 | static void bfin_spi_giveback(struct driver_data *drv_data) |
a5f6abd4 | 497 | { |
fad91c89 | 498 | struct chip_data *chip = drv_data->cur_chip; |
a5f6abd4 WB |
499 | struct spi_transfer *last_transfer; |
500 | unsigned long flags; | |
501 | struct spi_message *msg; | |
502 | ||
503 | spin_lock_irqsave(&drv_data->lock, flags); | |
504 | msg = drv_data->cur_msg; | |
505 | drv_data->cur_msg = NULL; | |
506 | drv_data->cur_transfer = NULL; | |
507 | drv_data->cur_chip = NULL; | |
508 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
509 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
510 | ||
511 | last_transfer = list_entry(msg->transfers.prev, | |
512 | struct spi_transfer, transfer_list); | |
513 | ||
514 | msg->state = NULL; | |
515 | ||
fad91c89 | 516 | if (!drv_data->cs_change) |
138f97cd | 517 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 518 | |
b9b2a76a YL |
519 | /* Not stop spi in autobuffer mode */ |
520 | if (drv_data->tx_dma != 0xFFFF) | |
521 | bfin_spi_disable(drv_data); | |
522 | ||
a5f6abd4 WB |
523 | if (msg->complete) |
524 | msg->complete(msg->context); | |
525 | } | |
526 | ||
138f97cd | 527 | static irqreturn_t bfin_spi_dma_irq_handler(int irq, void *dev_id) |
a5f6abd4 | 528 | { |
15aafa2f | 529 | struct driver_data *drv_data = dev_id; |
fad91c89 | 530 | struct chip_data *chip = drv_data->cur_chip; |
bb90eb00 | 531 | struct spi_message *msg = drv_data->cur_msg; |
aaaf939c | 532 | unsigned long timeout; |
d24bd1d0 | 533 | unsigned short dmastat = get_dma_curr_irqstat(drv_data->dma_channel); |
04b95d2f | 534 | u16 spistat = read_STAT(drv_data); |
a5f6abd4 | 535 | |
d24bd1d0 MF |
536 | dev_dbg(&drv_data->pdev->dev, |
537 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
538 | dmastat, spistat); | |
539 | ||
bb90eb00 | 540 | clear_dma_irqstat(drv_data->dma_channel); |
a5f6abd4 | 541 | |
d6fe89b0 | 542 | /* Wait for DMA to complete */ |
bb90eb00 | 543 | while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN) |
d8c05008 | 544 | cpu_relax(); |
d6fe89b0 | 545 | |
a5f6abd4 | 546 | /* |
d6fe89b0 BW |
547 | * wait for the last transaction shifted out. HRM states: |
548 | * at this point there may still be data in the SPI DMA FIFO waiting | |
549 | * to be transmitted ... software needs to poll TXS in the SPI_STAT | |
550 | * register until it goes low for 2 successive reads | |
a5f6abd4 WB |
551 | */ |
552 | if (drv_data->tx != NULL) { | |
bb90eb00 BW |
553 | while ((read_STAT(drv_data) & TXS) || |
554 | (read_STAT(drv_data) & TXS)) | |
d8c05008 | 555 | cpu_relax(); |
a5f6abd4 WB |
556 | } |
557 | ||
aaaf939c MF |
558 | dev_dbg(&drv_data->pdev->dev, |
559 | "in dma_irq_handler dmastat:0x%x spistat:0x%x\n", | |
560 | dmastat, read_STAT(drv_data)); | |
561 | ||
562 | timeout = jiffies + HZ; | |
bb90eb00 | 563 | while (!(read_STAT(drv_data) & SPIF)) |
aaaf939c MF |
564 | if (!time_before(jiffies, timeout)) { |
565 | dev_warn(&drv_data->pdev->dev, "timeout waiting for SPIF"); | |
566 | break; | |
567 | } else | |
568 | cpu_relax(); | |
a5f6abd4 | 569 | |
40a2945b | 570 | if ((dmastat & DMA_ERR) && (spistat & RBSY)) { |
04b95d2f MF |
571 | msg->state = ERROR_STATE; |
572 | dev_err(&drv_data->pdev->dev, "dma receive: fifo/buffer overflow\n"); | |
573 | } else { | |
574 | msg->actual_length += drv_data->len_in_bytes; | |
a5f6abd4 | 575 | |
04b95d2f | 576 | if (drv_data->cs_change) |
138f97cd | 577 | bfin_spi_cs_deactive(drv_data, chip); |
fad91c89 | 578 | |
04b95d2f | 579 | /* Move to next transfer */ |
138f97cd | 580 | msg->state = bfin_spi_next_transfer(drv_data); |
04b95d2f | 581 | } |
a5f6abd4 WB |
582 | |
583 | /* Schedule transfer tasklet */ | |
584 | tasklet_schedule(&drv_data->pump_transfers); | |
585 | ||
586 | /* free the irq handler before next transfer */ | |
88b40369 BW |
587 | dev_dbg(&drv_data->pdev->dev, |
588 | "disable dma channel irq%d\n", | |
bb90eb00 BW |
589 | drv_data->dma_channel); |
590 | dma_disable_irq(drv_data->dma_channel); | |
a5f6abd4 WB |
591 | |
592 | return IRQ_HANDLED; | |
593 | } | |
594 | ||
138f97cd | 595 | static void bfin_spi_pump_transfers(unsigned long data) |
a5f6abd4 WB |
596 | { |
597 | struct driver_data *drv_data = (struct driver_data *)data; | |
598 | struct spi_message *message = NULL; | |
599 | struct spi_transfer *transfer = NULL; | |
600 | struct spi_transfer *previous = NULL; | |
601 | struct chip_data *chip = NULL; | |
88b40369 BW |
602 | u8 width; |
603 | u16 cr, dma_width, dma_config; | |
a5f6abd4 | 604 | u32 tranf_success = 1; |
8eeb12e5 | 605 | u8 full_duplex = 0; |
a5f6abd4 WB |
606 | |
607 | /* Get current state information */ | |
608 | message = drv_data->cur_msg; | |
609 | transfer = drv_data->cur_transfer; | |
610 | chip = drv_data->cur_chip; | |
092e1fda | 611 | |
a5f6abd4 WB |
612 | /* |
613 | * if msg is error or done, report it back using complete() callback | |
614 | */ | |
615 | ||
616 | /* Handle for abort */ | |
617 | if (message->state == ERROR_STATE) { | |
d24bd1d0 | 618 | dev_dbg(&drv_data->pdev->dev, "transfer: we've hit an error\n"); |
a5f6abd4 | 619 | message->status = -EIO; |
138f97cd | 620 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
621 | return; |
622 | } | |
623 | ||
624 | /* Handle end of message */ | |
625 | if (message->state == DONE_STATE) { | |
d24bd1d0 | 626 | dev_dbg(&drv_data->pdev->dev, "transfer: all done!\n"); |
a5f6abd4 | 627 | message->status = 0; |
138f97cd | 628 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
629 | return; |
630 | } | |
631 | ||
632 | /* Delay if requested at end of transfer */ | |
633 | if (message->state == RUNNING_STATE) { | |
d24bd1d0 | 634 | dev_dbg(&drv_data->pdev->dev, "transfer: still running ...\n"); |
a5f6abd4 WB |
635 | previous = list_entry(transfer->transfer_list.prev, |
636 | struct spi_transfer, transfer_list); | |
637 | if (previous->delay_usecs) | |
638 | udelay(previous->delay_usecs); | |
639 | } | |
640 | ||
641 | /* Setup the transfer state based on the type of transfer */ | |
138f97cd | 642 | if (bfin_spi_flush(drv_data) == 0) { |
a5f6abd4 WB |
643 | dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n"); |
644 | message->status = -EIO; | |
138f97cd | 645 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
646 | return; |
647 | } | |
648 | ||
93b61bdd WM |
649 | if (transfer->len == 0) { |
650 | /* Move to next transfer of this msg */ | |
651 | message->state = bfin_spi_next_transfer(drv_data); | |
652 | /* Schedule next transfer tasklet */ | |
653 | tasklet_schedule(&drv_data->pump_transfers); | |
654 | } | |
655 | ||
a5f6abd4 WB |
656 | if (transfer->tx_buf != NULL) { |
657 | drv_data->tx = (void *)transfer->tx_buf; | |
658 | drv_data->tx_end = drv_data->tx + transfer->len; | |
88b40369 BW |
659 | dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n", |
660 | transfer->tx_buf, drv_data->tx_end); | |
a5f6abd4 WB |
661 | } else { |
662 | drv_data->tx = NULL; | |
663 | } | |
664 | ||
665 | if (transfer->rx_buf != NULL) { | |
8eeb12e5 | 666 | full_duplex = transfer->tx_buf != NULL; |
a5f6abd4 WB |
667 | drv_data->rx = transfer->rx_buf; |
668 | drv_data->rx_end = drv_data->rx + transfer->len; | |
88b40369 BW |
669 | dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n", |
670 | transfer->rx_buf, drv_data->rx_end); | |
a5f6abd4 WB |
671 | } else { |
672 | drv_data->rx = NULL; | |
673 | } | |
674 | ||
675 | drv_data->rx_dma = transfer->rx_dma; | |
676 | drv_data->tx_dma = transfer->tx_dma; | |
677 | drv_data->len_in_bytes = transfer->len; | |
fad91c89 | 678 | drv_data->cs_change = transfer->cs_change; |
a5f6abd4 | 679 | |
092e1fda BW |
680 | /* Bits per word setup */ |
681 | switch (transfer->bits_per_word) { | |
682 | case 8: | |
683 | drv_data->n_bytes = 1; | |
684 | width = CFG_SPI_WORDSIZE8; | |
685 | drv_data->read = chip->cs_change_per_word ? | |
138f97cd | 686 | bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader; |
092e1fda | 687 | drv_data->write = chip->cs_change_per_word ? |
138f97cd | 688 | bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer; |
092e1fda | 689 | drv_data->duplex = chip->cs_change_per_word ? |
138f97cd | 690 | bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex; |
092e1fda BW |
691 | break; |
692 | ||
693 | case 16: | |
694 | drv_data->n_bytes = 2; | |
695 | width = CFG_SPI_WORDSIZE16; | |
696 | drv_data->read = chip->cs_change_per_word ? | |
138f97cd | 697 | bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader; |
092e1fda | 698 | drv_data->write = chip->cs_change_per_word ? |
138f97cd | 699 | bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer; |
092e1fda | 700 | drv_data->duplex = chip->cs_change_per_word ? |
138f97cd | 701 | bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex; |
092e1fda BW |
702 | break; |
703 | ||
704 | default: | |
705 | /* No change, the same as default setting */ | |
706 | drv_data->n_bytes = chip->n_bytes; | |
707 | width = chip->width; | |
138f97cd MF |
708 | drv_data->write = drv_data->tx ? chip->write : bfin_spi_null_writer; |
709 | drv_data->read = drv_data->rx ? chip->read : bfin_spi_null_reader; | |
710 | drv_data->duplex = chip->duplex ? chip->duplex : bfin_spi_null_writer; | |
092e1fda BW |
711 | break; |
712 | } | |
713 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
714 | cr |= (width << 8); | |
715 | write_CTRL(drv_data, cr); | |
716 | ||
a5f6abd4 WB |
717 | if (width == CFG_SPI_WORDSIZE16) { |
718 | drv_data->len = (transfer->len) >> 1; | |
719 | } else { | |
720 | drv_data->len = transfer->len; | |
721 | } | |
4fb98efa MF |
722 | dev_dbg(&drv_data->pdev->dev, |
723 | "transfer: drv_data->write is %p, chip->write is %p, null_wr is %p\n", | |
138f97cd | 724 | drv_data->write, chip->write, bfin_spi_null_writer); |
a5f6abd4 WB |
725 | |
726 | /* speed and width has been set on per message */ | |
727 | message->state = RUNNING_STATE; | |
728 | dma_config = 0; | |
729 | ||
092e1fda BW |
730 | /* Speed setup (surely valid because already checked) */ |
731 | if (transfer->speed_hz) | |
732 | write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz)); | |
733 | else | |
734 | write_BAUD(drv_data, chip->baud); | |
735 | ||
bb90eb00 BW |
736 | write_STAT(drv_data, BIT_STAT_CLR); |
737 | cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD)); | |
b9b2a76a | 738 | if (drv_data->cs_change) |
138f97cd | 739 | bfin_spi_cs_active(drv_data, chip); |
a5f6abd4 | 740 | |
88b40369 BW |
741 | dev_dbg(&drv_data->pdev->dev, |
742 | "now pumping a transfer: width is %d, len is %d\n", | |
743 | width, transfer->len); | |
a5f6abd4 WB |
744 | |
745 | /* | |
8cf5858c VM |
746 | * Try to map dma buffer and do a dma transfer. If successful use, |
747 | * different way to r/w according to the enable_dma settings and if | |
748 | * we are not doing a full duplex transfer (since the hardware does | |
749 | * not support full duplex DMA transfers). | |
a5f6abd4 | 750 | */ |
8eeb12e5 VM |
751 | if (!full_duplex && drv_data->cur_chip->enable_dma |
752 | && drv_data->len > 6) { | |
a5f6abd4 | 753 | |
11d6f599 | 754 | unsigned long dma_start_addr, flags; |
7aec3566 | 755 | |
bb90eb00 BW |
756 | disable_dma(drv_data->dma_channel); |
757 | clear_dma_irqstat(drv_data->dma_channel); | |
a5f6abd4 WB |
758 | |
759 | /* config dma channel */ | |
88b40369 | 760 | dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n"); |
7aec3566 | 761 | set_dma_x_count(drv_data->dma_channel, drv_data->len); |
a5f6abd4 | 762 | if (width == CFG_SPI_WORDSIZE16) { |
bb90eb00 | 763 | set_dma_x_modify(drv_data->dma_channel, 2); |
a5f6abd4 WB |
764 | dma_width = WDSIZE_16; |
765 | } else { | |
bb90eb00 | 766 | set_dma_x_modify(drv_data->dma_channel, 1); |
a5f6abd4 WB |
767 | dma_width = WDSIZE_8; |
768 | } | |
769 | ||
3f479a65 | 770 | /* poll for SPI completion before start */ |
bb90eb00 | 771 | while (!(read_STAT(drv_data) & BIT_STAT_SPIF)) |
d8c05008 | 772 | cpu_relax(); |
3f479a65 | 773 | |
a5f6abd4 WB |
774 | /* dirty hack for autobuffer DMA mode */ |
775 | if (drv_data->tx_dma == 0xFFFF) { | |
88b40369 BW |
776 | dev_dbg(&drv_data->pdev->dev, |
777 | "doing autobuffer DMA out.\n"); | |
a5f6abd4 WB |
778 | |
779 | /* no irq in autobuffer mode */ | |
780 | dma_config = | |
781 | (DMAFLOW_AUTO | RESTART | dma_width | DI_EN); | |
bb90eb00 BW |
782 | set_dma_config(drv_data->dma_channel, dma_config); |
783 | set_dma_start_addr(drv_data->dma_channel, | |
a32c691d | 784 | (unsigned long)drv_data->tx); |
bb90eb00 | 785 | enable_dma(drv_data->dma_channel); |
a5f6abd4 | 786 | |
07612e5f | 787 | /* start SPI transfer */ |
11d6f599 | 788 | write_CTRL(drv_data, cr | BIT_CTL_TIMOD_DMA_TX); |
07612e5f SZ |
789 | |
790 | /* just return here, there can only be one transfer | |
791 | * in this mode | |
792 | */ | |
a5f6abd4 | 793 | message->status = 0; |
138f97cd | 794 | bfin_spi_giveback(drv_data); |
a5f6abd4 WB |
795 | return; |
796 | } | |
797 | ||
798 | /* In dma mode, rx or tx must be NULL in one transfer */ | |
7aec3566 | 799 | dma_config = (RESTART | dma_width | DI_EN); |
a5f6abd4 WB |
800 | if (drv_data->rx != NULL) { |
801 | /* set transfer mode, and enable SPI */ | |
d24bd1d0 MF |
802 | dev_dbg(&drv_data->pdev->dev, "doing DMA in to %p (size %zx)\n", |
803 | drv_data->rx, drv_data->len_in_bytes); | |
a5f6abd4 | 804 | |
8cf5858c | 805 | /* invalidate caches, if needed */ |
67834fa9 | 806 | if (bfin_addr_dcacheable((unsigned long) drv_data->rx)) |
8cf5858c VM |
807 | invalidate_dcache_range((unsigned long) drv_data->rx, |
808 | (unsigned long) (drv_data->rx + | |
ace32865 | 809 | drv_data->len_in_bytes)); |
8cf5858c | 810 | |
7aec3566 MF |
811 | dma_config |= WNR; |
812 | dma_start_addr = (unsigned long)drv_data->rx; | |
b31e27a6 | 813 | cr |= BIT_CTL_TIMOD_DMA_RX | BIT_CTL_SENDOPT; |
07612e5f | 814 | |
a5f6abd4 | 815 | } else if (drv_data->tx != NULL) { |
88b40369 | 816 | dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n"); |
a5f6abd4 | 817 | |
8cf5858c | 818 | /* flush caches, if needed */ |
67834fa9 | 819 | if (bfin_addr_dcacheable((unsigned long) drv_data->tx)) |
8cf5858c VM |
820 | flush_dcache_range((unsigned long) drv_data->tx, |
821 | (unsigned long) (drv_data->tx + | |
ace32865 | 822 | drv_data->len_in_bytes)); |
8cf5858c | 823 | |
7aec3566 | 824 | dma_start_addr = (unsigned long)drv_data->tx; |
b31e27a6 | 825 | cr |= BIT_CTL_TIMOD_DMA_TX; |
7aec3566 MF |
826 | |
827 | } else | |
828 | BUG(); | |
829 | ||
11d6f599 MF |
830 | /* oh man, here there be monsters ... and i dont mean the |
831 | * fluffy cute ones from pixar, i mean the kind that'll eat | |
832 | * your data, kick your dog, and love it all. do *not* try | |
833 | * and change these lines unless you (1) heavily test DMA | |
834 | * with SPI flashes on a loaded system (e.g. ping floods), | |
835 | * (2) know just how broken the DMA engine interaction with | |
836 | * the SPI peripheral is, and (3) have someone else to blame | |
837 | * when you screw it all up anyways. | |
838 | */ | |
7aec3566 | 839 | set_dma_start_addr(drv_data->dma_channel, dma_start_addr); |
11d6f599 MF |
840 | set_dma_config(drv_data->dma_channel, dma_config); |
841 | local_irq_save(flags); | |
a963ea83 | 842 | SSYNC(); |
11d6f599 | 843 | write_CTRL(drv_data, cr); |
a963ea83 | 844 | enable_dma(drv_data->dma_channel); |
11d6f599 MF |
845 | dma_enable_irq(drv_data->dma_channel); |
846 | local_irq_restore(flags); | |
07612e5f | 847 | |
a5f6abd4 WB |
848 | } else { |
849 | /* IO mode write then read */ | |
88b40369 | 850 | dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n"); |
a5f6abd4 | 851 | |
93b61bdd WM |
852 | /* we always use SPI_WRITE mode. SPI_READ mode |
853 | seems to have problems with setting up the | |
854 | output value in TDBR prior to the transfer. */ | |
855 | write_CTRL(drv_data, (cr | CFG_SPI_WRITE)); | |
856 | ||
8eeb12e5 | 857 | if (full_duplex) { |
a5f6abd4 WB |
858 | /* full duplex mode */ |
859 | BUG_ON((drv_data->tx_end - drv_data->tx) != | |
860 | (drv_data->rx_end - drv_data->rx)); | |
88b40369 BW |
861 | dev_dbg(&drv_data->pdev->dev, |
862 | "IO duplex: cr is 0x%x\n", cr); | |
a5f6abd4 | 863 | |
a5f6abd4 WB |
864 | drv_data->duplex(drv_data); |
865 | ||
866 | if (drv_data->tx != drv_data->tx_end) | |
867 | tranf_success = 0; | |
868 | } else if (drv_data->tx != NULL) { | |
869 | /* write only half duplex */ | |
131b17d4 | 870 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 871 | "IO write: cr is 0x%x\n", cr); |
a5f6abd4 | 872 | |
a5f6abd4 WB |
873 | drv_data->write(drv_data); |
874 | ||
875 | if (drv_data->tx != drv_data->tx_end) | |
876 | tranf_success = 0; | |
877 | } else if (drv_data->rx != NULL) { | |
878 | /* read only half duplex */ | |
131b17d4 | 879 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 880 | "IO read: cr is 0x%x\n", cr); |
a5f6abd4 | 881 | |
a5f6abd4 WB |
882 | drv_data->read(drv_data); |
883 | if (drv_data->rx != drv_data->rx_end) | |
884 | tranf_success = 0; | |
885 | } | |
886 | ||
887 | if (!tranf_success) { | |
131b17d4 | 888 | dev_dbg(&drv_data->pdev->dev, |
88b40369 | 889 | "IO write error!\n"); |
a5f6abd4 WB |
890 | message->state = ERROR_STATE; |
891 | } else { | |
892 | /* Update total byte transfered */ | |
ace32865 | 893 | message->actual_length += drv_data->len_in_bytes; |
a5f6abd4 | 894 | /* Move to next transfer of this msg */ |
138f97cd | 895 | message->state = bfin_spi_next_transfer(drv_data); |
b9b2a76a | 896 | if (drv_data->cs_change) |
138f97cd | 897 | bfin_spi_cs_deactive(drv_data, chip); |
a5f6abd4 | 898 | } |
a5f6abd4 WB |
899 | /* Schedule next transfer tasklet */ |
900 | tasklet_schedule(&drv_data->pump_transfers); | |
a5f6abd4 WB |
901 | } |
902 | } | |
903 | ||
904 | /* pop a msg from queue and kick off real transfer */ | |
138f97cd | 905 | static void bfin_spi_pump_messages(struct work_struct *work) |
a5f6abd4 | 906 | { |
131b17d4 | 907 | struct driver_data *drv_data; |
a5f6abd4 WB |
908 | unsigned long flags; |
909 | ||
131b17d4 BW |
910 | drv_data = container_of(work, struct driver_data, pump_messages); |
911 | ||
a5f6abd4 WB |
912 | /* Lock queue and check for queue work */ |
913 | spin_lock_irqsave(&drv_data->lock, flags); | |
914 | if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) { | |
915 | /* pumper kicked off but no work to do */ | |
916 | drv_data->busy = 0; | |
917 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
918 | return; | |
919 | } | |
920 | ||
921 | /* Make sure we are not already running a message */ | |
922 | if (drv_data->cur_msg) { | |
923 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
924 | return; | |
925 | } | |
926 | ||
927 | /* Extract head of queue */ | |
928 | drv_data->cur_msg = list_entry(drv_data->queue.next, | |
929 | struct spi_message, queue); | |
5fec5b5a BW |
930 | |
931 | /* Setup the SSP using the per chip configuration */ | |
932 | drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi); | |
138f97cd | 933 | bfin_spi_restore_state(drv_data); |
5fec5b5a | 934 | |
a5f6abd4 WB |
935 | list_del_init(&drv_data->cur_msg->queue); |
936 | ||
937 | /* Initial message state */ | |
938 | drv_data->cur_msg->state = START_STATE; | |
939 | drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next, | |
940 | struct spi_transfer, transfer_list); | |
941 | ||
5fec5b5a BW |
942 | dev_dbg(&drv_data->pdev->dev, "got a message to pump, " |
943 | "state is set to: baud %d, flag 0x%x, ctl 0x%x\n", | |
944 | drv_data->cur_chip->baud, drv_data->cur_chip->flag, | |
945 | drv_data->cur_chip->ctl_reg); | |
131b17d4 BW |
946 | |
947 | dev_dbg(&drv_data->pdev->dev, | |
88b40369 BW |
948 | "the first transfer len is %d\n", |
949 | drv_data->cur_transfer->len); | |
a5f6abd4 WB |
950 | |
951 | /* Mark as busy and launch transfers */ | |
952 | tasklet_schedule(&drv_data->pump_transfers); | |
953 | ||
954 | drv_data->busy = 1; | |
955 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
956 | } | |
957 | ||
958 | /* | |
959 | * got a msg to transfer, queue it in drv_data->queue. | |
960 | * And kick off message pumper | |
961 | */ | |
138f97cd | 962 | static int bfin_spi_transfer(struct spi_device *spi, struct spi_message *msg) |
a5f6abd4 WB |
963 | { |
964 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
965 | unsigned long flags; | |
966 | ||
967 | spin_lock_irqsave(&drv_data->lock, flags); | |
968 | ||
969 | if (drv_data->run == QUEUE_STOPPED) { | |
970 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
971 | return -ESHUTDOWN; | |
972 | } | |
973 | ||
974 | msg->actual_length = 0; | |
975 | msg->status = -EINPROGRESS; | |
976 | msg->state = START_STATE; | |
977 | ||
88b40369 | 978 | dev_dbg(&spi->dev, "adding an msg in transfer() \n"); |
a5f6abd4 WB |
979 | list_add_tail(&msg->queue, &drv_data->queue); |
980 | ||
981 | if (drv_data->run == QUEUE_RUNNING && !drv_data->busy) | |
982 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
983 | ||
984 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
985 | ||
986 | return 0; | |
987 | } | |
988 | ||
12e17c42 SZ |
989 | #define MAX_SPI_SSEL 7 |
990 | ||
4160bde2 | 991 | static u16 ssel[][MAX_SPI_SSEL] = { |
12e17c42 SZ |
992 | {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3, |
993 | P_SPI0_SSEL4, P_SPI0_SSEL5, | |
994 | P_SPI0_SSEL6, P_SPI0_SSEL7}, | |
995 | ||
996 | {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3, | |
997 | P_SPI1_SSEL4, P_SPI1_SSEL5, | |
998 | P_SPI1_SSEL6, P_SPI1_SSEL7}, | |
999 | ||
1000 | {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3, | |
1001 | P_SPI2_SSEL4, P_SPI2_SSEL5, | |
1002 | P_SPI2_SSEL6, P_SPI2_SSEL7}, | |
1003 | }; | |
1004 | ||
a5f6abd4 | 1005 | /* first setup for new devices */ |
138f97cd | 1006 | static int bfin_spi_setup(struct spi_device *spi) |
a5f6abd4 WB |
1007 | { |
1008 | struct bfin5xx_spi_chip *chip_info = NULL; | |
1009 | struct chip_data *chip; | |
1010 | struct driver_data *drv_data = spi_master_get_devdata(spi->master); | |
42c78b2b | 1011 | int ret; |
a5f6abd4 | 1012 | |
a5f6abd4 WB |
1013 | if (spi->bits_per_word != 8 && spi->bits_per_word != 16) |
1014 | return -EINVAL; | |
1015 | ||
1016 | /* Only alloc (or use chip_info) on first setup */ | |
1017 | chip = spi_get_ctldata(spi); | |
1018 | if (chip == NULL) { | |
1019 | chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); | |
1020 | if (!chip) | |
1021 | return -ENOMEM; | |
1022 | ||
1023 | chip->enable_dma = 0; | |
1024 | chip_info = spi->controller_data; | |
1025 | } | |
1026 | ||
1027 | /* chip_info isn't always needed */ | |
1028 | if (chip_info) { | |
2ed35516 MF |
1029 | /* Make sure people stop trying to set fields via ctl_reg |
1030 | * when they should actually be using common SPI framework. | |
1031 | * Currently we let through: WOM EMISO PSSE GM SZ TIMOD. | |
1032 | * Not sure if a user actually needs/uses any of these, | |
1033 | * but let's assume (for now) they do. | |
1034 | */ | |
1035 | if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) { | |
1036 | dev_err(&spi->dev, "do not set bits in ctl_reg " | |
1037 | "that the SPI framework manages\n"); | |
1038 | return -EINVAL; | |
1039 | } | |
1040 | ||
a5f6abd4 WB |
1041 | chip->enable_dma = chip_info->enable_dma != 0 |
1042 | && drv_data->master_info->enable_dma; | |
1043 | chip->ctl_reg = chip_info->ctl_reg; | |
1044 | chip->bits_per_word = chip_info->bits_per_word; | |
1045 | chip->cs_change_per_word = chip_info->cs_change_per_word; | |
1046 | chip->cs_chg_udelay = chip_info->cs_chg_udelay; | |
42c78b2b | 1047 | chip->cs_gpio = chip_info->cs_gpio; |
93b61bdd | 1048 | chip->idle_tx_val = chip_info->idle_tx_val; |
a5f6abd4 WB |
1049 | } |
1050 | ||
1051 | /* translate common spi framework into our register */ | |
1052 | if (spi->mode & SPI_CPOL) | |
1053 | chip->ctl_reg |= CPOL; | |
1054 | if (spi->mode & SPI_CPHA) | |
1055 | chip->ctl_reg |= CPHA; | |
1056 | if (spi->mode & SPI_LSB_FIRST) | |
1057 | chip->ctl_reg |= LSBF; | |
1058 | /* we dont support running in slave mode (yet?) */ | |
1059 | chip->ctl_reg |= MSTR; | |
1060 | ||
1061 | /* | |
1062 | * if any one SPI chip is registered and wants DMA, request the | |
1063 | * DMA channel for it | |
1064 | */ | |
bb90eb00 | 1065 | if (chip->enable_dma && !drv_data->dma_requested) { |
a5f6abd4 | 1066 | /* register dma irq handler */ |
59bfcc66 | 1067 | if (request_dma(drv_data->dma_channel, "BFIN_SPI_DMA") < 0) { |
88b40369 BW |
1068 | dev_dbg(&spi->dev, |
1069 | "Unable to request BlackFin SPI DMA channel\n"); | |
a5f6abd4 WB |
1070 | return -ENODEV; |
1071 | } | |
bb90eb00 | 1072 | if (set_dma_callback(drv_data->dma_channel, |
138f97cd | 1073 | bfin_spi_dma_irq_handler, drv_data) < 0) { |
88b40369 | 1074 | dev_dbg(&spi->dev, "Unable to set dma callback\n"); |
a5f6abd4 WB |
1075 | return -EPERM; |
1076 | } | |
bb90eb00 BW |
1077 | dma_disable_irq(drv_data->dma_channel); |
1078 | drv_data->dma_requested = 1; | |
a5f6abd4 WB |
1079 | } |
1080 | ||
1081 | /* | |
1082 | * Notice: for blackfin, the speed_hz is the value of register | |
1083 | * SPI_BAUD, not the real baudrate | |
1084 | */ | |
1085 | chip->baud = hz_to_spi_baud(spi->max_speed_hz); | |
2cf36834 | 1086 | chip->flag = 1 << (spi->chip_select); |
a5f6abd4 WB |
1087 | chip->chip_select_num = spi->chip_select; |
1088 | ||
42c78b2b MH |
1089 | if (chip->chip_select_num == 0) { |
1090 | ret = gpio_request(chip->cs_gpio, spi->modalias); | |
1091 | if (ret) { | |
1092 | if (drv_data->dma_requested) | |
1093 | free_dma(drv_data->dma_channel); | |
1094 | return ret; | |
1095 | } | |
1096 | gpio_direction_output(chip->cs_gpio, 1); | |
1097 | } | |
1098 | ||
a5f6abd4 WB |
1099 | switch (chip->bits_per_word) { |
1100 | case 8: | |
1101 | chip->n_bytes = 1; | |
1102 | chip->width = CFG_SPI_WORDSIZE8; | |
1103 | chip->read = chip->cs_change_per_word ? | |
138f97cd | 1104 | bfin_spi_u8_cs_chg_reader : bfin_spi_u8_reader; |
a5f6abd4 | 1105 | chip->write = chip->cs_change_per_word ? |
138f97cd | 1106 | bfin_spi_u8_cs_chg_writer : bfin_spi_u8_writer; |
a5f6abd4 | 1107 | chip->duplex = chip->cs_change_per_word ? |
138f97cd | 1108 | bfin_spi_u8_cs_chg_duplex : bfin_spi_u8_duplex; |
a5f6abd4 WB |
1109 | break; |
1110 | ||
1111 | case 16: | |
1112 | chip->n_bytes = 2; | |
1113 | chip->width = CFG_SPI_WORDSIZE16; | |
1114 | chip->read = chip->cs_change_per_word ? | |
138f97cd | 1115 | bfin_spi_u16_cs_chg_reader : bfin_spi_u16_reader; |
a5f6abd4 | 1116 | chip->write = chip->cs_change_per_word ? |
138f97cd | 1117 | bfin_spi_u16_cs_chg_writer : bfin_spi_u16_writer; |
a5f6abd4 | 1118 | chip->duplex = chip->cs_change_per_word ? |
138f97cd | 1119 | bfin_spi_u16_cs_chg_duplex : bfin_spi_u16_duplex; |
a5f6abd4 WB |
1120 | break; |
1121 | ||
1122 | default: | |
1123 | dev_err(&spi->dev, "%d bits_per_word is not supported\n", | |
1124 | chip->bits_per_word); | |
138f97cd MF |
1125 | if (chip_info) |
1126 | kfree(chip); | |
a5f6abd4 WB |
1127 | return -ENODEV; |
1128 | } | |
1129 | ||
898eb71c | 1130 | dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n", |
a5f6abd4 | 1131 | spi->modalias, chip->width, chip->enable_dma); |
88b40369 | 1132 | dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n", |
a5f6abd4 WB |
1133 | chip->ctl_reg, chip->flag); |
1134 | ||
1135 | spi_set_ctldata(spi, chip); | |
1136 | ||
12e17c42 SZ |
1137 | dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num); |
1138 | if ((chip->chip_select_num > 0) | |
1139 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1140 | peripheral_request(ssel[spi->master->bus_num] | |
aab0d83e | 1141 | [chip->chip_select_num-1], spi->modalias); |
12e17c42 | 1142 | |
138f97cd | 1143 | bfin_spi_cs_deactive(drv_data, chip); |
07612e5f | 1144 | |
a5f6abd4 WB |
1145 | return 0; |
1146 | } | |
1147 | ||
1148 | /* | |
1149 | * callback for spi framework. | |
1150 | * clean driver specific data | |
1151 | */ | |
138f97cd | 1152 | static void bfin_spi_cleanup(struct spi_device *spi) |
a5f6abd4 | 1153 | { |
27bb9e79 | 1154 | struct chip_data *chip = spi_get_ctldata(spi); |
a5f6abd4 | 1155 | |
e7d02e3c MF |
1156 | if (!chip) |
1157 | return; | |
1158 | ||
12e17c42 SZ |
1159 | if ((chip->chip_select_num > 0) |
1160 | && (chip->chip_select_num <= spi->master->num_chipselect)) | |
1161 | peripheral_free(ssel[spi->master->bus_num] | |
1162 | [chip->chip_select_num-1]); | |
1163 | ||
42c78b2b MH |
1164 | if (chip->chip_select_num == 0) |
1165 | gpio_free(chip->cs_gpio); | |
1166 | ||
a5f6abd4 WB |
1167 | kfree(chip); |
1168 | } | |
1169 | ||
138f97cd | 1170 | static inline int bfin_spi_init_queue(struct driver_data *drv_data) |
a5f6abd4 WB |
1171 | { |
1172 | INIT_LIST_HEAD(&drv_data->queue); | |
1173 | spin_lock_init(&drv_data->lock); | |
1174 | ||
1175 | drv_data->run = QUEUE_STOPPED; | |
1176 | drv_data->busy = 0; | |
1177 | ||
1178 | /* init transfer tasklet */ | |
1179 | tasklet_init(&drv_data->pump_transfers, | |
138f97cd | 1180 | bfin_spi_pump_transfers, (unsigned long)drv_data); |
a5f6abd4 WB |
1181 | |
1182 | /* init messages workqueue */ | |
138f97cd | 1183 | INIT_WORK(&drv_data->pump_messages, bfin_spi_pump_messages); |
6c7377ab KS |
1184 | drv_data->workqueue = create_singlethread_workqueue( |
1185 | dev_name(drv_data->master->dev.parent)); | |
a5f6abd4 WB |
1186 | if (drv_data->workqueue == NULL) |
1187 | return -EBUSY; | |
1188 | ||
1189 | return 0; | |
1190 | } | |
1191 | ||
138f97cd | 1192 | static inline int bfin_spi_start_queue(struct driver_data *drv_data) |
a5f6abd4 WB |
1193 | { |
1194 | unsigned long flags; | |
1195 | ||
1196 | spin_lock_irqsave(&drv_data->lock, flags); | |
1197 | ||
1198 | if (drv_data->run == QUEUE_RUNNING || drv_data->busy) { | |
1199 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1200 | return -EBUSY; | |
1201 | } | |
1202 | ||
1203 | drv_data->run = QUEUE_RUNNING; | |
1204 | drv_data->cur_msg = NULL; | |
1205 | drv_data->cur_transfer = NULL; | |
1206 | drv_data->cur_chip = NULL; | |
1207 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1208 | ||
1209 | queue_work(drv_data->workqueue, &drv_data->pump_messages); | |
1210 | ||
1211 | return 0; | |
1212 | } | |
1213 | ||
138f97cd | 1214 | static inline int bfin_spi_stop_queue(struct driver_data *drv_data) |
a5f6abd4 WB |
1215 | { |
1216 | unsigned long flags; | |
1217 | unsigned limit = 500; | |
1218 | int status = 0; | |
1219 | ||
1220 | spin_lock_irqsave(&drv_data->lock, flags); | |
1221 | ||
1222 | /* | |
1223 | * This is a bit lame, but is optimized for the common execution path. | |
1224 | * A wait_queue on the drv_data->busy could be used, but then the common | |
1225 | * execution path (pump_messages) would be required to call wake_up or | |
1226 | * friends on every SPI message. Do this instead | |
1227 | */ | |
1228 | drv_data->run = QUEUE_STOPPED; | |
1229 | while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) { | |
1230 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1231 | msleep(10); | |
1232 | spin_lock_irqsave(&drv_data->lock, flags); | |
1233 | } | |
1234 | ||
1235 | if (!list_empty(&drv_data->queue) || drv_data->busy) | |
1236 | status = -EBUSY; | |
1237 | ||
1238 | spin_unlock_irqrestore(&drv_data->lock, flags); | |
1239 | ||
1240 | return status; | |
1241 | } | |
1242 | ||
138f97cd | 1243 | static inline int bfin_spi_destroy_queue(struct driver_data *drv_data) |
a5f6abd4 WB |
1244 | { |
1245 | int status; | |
1246 | ||
138f97cd | 1247 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1248 | if (status != 0) |
1249 | return status; | |
1250 | ||
1251 | destroy_workqueue(drv_data->workqueue); | |
1252 | ||
1253 | return 0; | |
1254 | } | |
1255 | ||
138f97cd | 1256 | static int __init bfin_spi_probe(struct platform_device *pdev) |
a5f6abd4 WB |
1257 | { |
1258 | struct device *dev = &pdev->dev; | |
1259 | struct bfin5xx_spi_master *platform_info; | |
1260 | struct spi_master *master; | |
1261 | struct driver_data *drv_data = 0; | |
a32c691d | 1262 | struct resource *res; |
a5f6abd4 WB |
1263 | int status = 0; |
1264 | ||
1265 | platform_info = dev->platform_data; | |
1266 | ||
1267 | /* Allocate master with space for drv_data */ | |
1268 | master = spi_alloc_master(dev, sizeof(struct driver_data) + 16); | |
1269 | if (!master) { | |
1270 | dev_err(&pdev->dev, "can not alloc spi_master\n"); | |
1271 | return -ENOMEM; | |
1272 | } | |
131b17d4 | 1273 | |
a5f6abd4 WB |
1274 | drv_data = spi_master_get_devdata(master); |
1275 | drv_data->master = master; | |
1276 | drv_data->master_info = platform_info; | |
1277 | drv_data->pdev = pdev; | |
003d9226 | 1278 | drv_data->pin_req = platform_info->pin_req; |
a5f6abd4 | 1279 | |
e7db06b5 DB |
1280 | /* the spi->mode bits supported by this driver: */ |
1281 | master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST; | |
1282 | ||
a5f6abd4 WB |
1283 | master->bus_num = pdev->id; |
1284 | master->num_chipselect = platform_info->num_chipselect; | |
138f97cd MF |
1285 | master->cleanup = bfin_spi_cleanup; |
1286 | master->setup = bfin_spi_setup; | |
1287 | master->transfer = bfin_spi_transfer; | |
a5f6abd4 | 1288 | |
a32c691d BW |
1289 | /* Find and map our resources */ |
1290 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1291 | if (res == NULL) { | |
1292 | dev_err(dev, "Cannot get IORESOURCE_MEM\n"); | |
1293 | status = -ENOENT; | |
1294 | goto out_error_get_res; | |
1295 | } | |
1296 | ||
f452126c BW |
1297 | drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1)); |
1298 | if (drv_data->regs_base == NULL) { | |
a32c691d BW |
1299 | dev_err(dev, "Cannot map IO\n"); |
1300 | status = -ENXIO; | |
1301 | goto out_error_ioremap; | |
1302 | } | |
1303 | ||
bb90eb00 BW |
1304 | drv_data->dma_channel = platform_get_irq(pdev, 0); |
1305 | if (drv_data->dma_channel < 0) { | |
a32c691d BW |
1306 | dev_err(dev, "No DMA channel specified\n"); |
1307 | status = -ENOENT; | |
1308 | goto out_error_no_dma_ch; | |
1309 | } | |
1310 | ||
a5f6abd4 | 1311 | /* Initial and start queue */ |
138f97cd | 1312 | status = bfin_spi_init_queue(drv_data); |
a5f6abd4 | 1313 | if (status != 0) { |
a32c691d | 1314 | dev_err(dev, "problem initializing queue\n"); |
a5f6abd4 WB |
1315 | goto out_error_queue_alloc; |
1316 | } | |
a32c691d | 1317 | |
138f97cd | 1318 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 | 1319 | if (status != 0) { |
a32c691d | 1320 | dev_err(dev, "problem starting queue\n"); |
a5f6abd4 WB |
1321 | goto out_error_queue_alloc; |
1322 | } | |
1323 | ||
f9e522ca VM |
1324 | status = peripheral_request_list(drv_data->pin_req, DRV_NAME); |
1325 | if (status != 0) { | |
1326 | dev_err(&pdev->dev, ": Requesting Peripherals failed\n"); | |
1327 | goto out_error_queue_alloc; | |
1328 | } | |
1329 | ||
a5f6abd4 WB |
1330 | /* Register with the SPI framework */ |
1331 | platform_set_drvdata(pdev, drv_data); | |
1332 | status = spi_register_master(master); | |
1333 | if (status != 0) { | |
a32c691d | 1334 | dev_err(dev, "problem registering spi master\n"); |
a5f6abd4 WB |
1335 | goto out_error_queue_alloc; |
1336 | } | |
a32c691d | 1337 | |
f452126c | 1338 | dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n", |
bb90eb00 BW |
1339 | DRV_DESC, DRV_VERSION, drv_data->regs_base, |
1340 | drv_data->dma_channel); | |
a5f6abd4 WB |
1341 | return status; |
1342 | ||
cc2f81a6 | 1343 | out_error_queue_alloc: |
138f97cd | 1344 | bfin_spi_destroy_queue(drv_data); |
a32c691d | 1345 | out_error_no_dma_ch: |
bb90eb00 | 1346 | iounmap((void *) drv_data->regs_base); |
a32c691d BW |
1347 | out_error_ioremap: |
1348 | out_error_get_res: | |
a5f6abd4 | 1349 | spi_master_put(master); |
cc2f81a6 | 1350 | |
a5f6abd4 WB |
1351 | return status; |
1352 | } | |
1353 | ||
1354 | /* stop hardware and remove the driver */ | |
138f97cd | 1355 | static int __devexit bfin_spi_remove(struct platform_device *pdev) |
a5f6abd4 WB |
1356 | { |
1357 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1358 | int status = 0; | |
1359 | ||
1360 | if (!drv_data) | |
1361 | return 0; | |
1362 | ||
1363 | /* Remove the queue */ | |
138f97cd | 1364 | status = bfin_spi_destroy_queue(drv_data); |
a5f6abd4 WB |
1365 | if (status != 0) |
1366 | return status; | |
1367 | ||
1368 | /* Disable the SSP at the peripheral and SOC level */ | |
1369 | bfin_spi_disable(drv_data); | |
1370 | ||
1371 | /* Release DMA */ | |
1372 | if (drv_data->master_info->enable_dma) { | |
bb90eb00 BW |
1373 | if (dma_channel_active(drv_data->dma_channel)) |
1374 | free_dma(drv_data->dma_channel); | |
a5f6abd4 WB |
1375 | } |
1376 | ||
1377 | /* Disconnect from the SPI framework */ | |
1378 | spi_unregister_master(drv_data->master); | |
1379 | ||
003d9226 | 1380 | peripheral_free_list(drv_data->pin_req); |
cc2f81a6 | 1381 | |
a5f6abd4 WB |
1382 | /* Prevent double remove */ |
1383 | platform_set_drvdata(pdev, NULL); | |
1384 | ||
1385 | return 0; | |
1386 | } | |
1387 | ||
1388 | #ifdef CONFIG_PM | |
138f97cd | 1389 | static int bfin_spi_suspend(struct platform_device *pdev, pm_message_t state) |
a5f6abd4 WB |
1390 | { |
1391 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1392 | int status = 0; | |
1393 | ||
138f97cd | 1394 | status = bfin_spi_stop_queue(drv_data); |
a5f6abd4 WB |
1395 | if (status != 0) |
1396 | return status; | |
1397 | ||
1398 | /* stop hardware */ | |
1399 | bfin_spi_disable(drv_data); | |
1400 | ||
1401 | return 0; | |
1402 | } | |
1403 | ||
138f97cd | 1404 | static int bfin_spi_resume(struct platform_device *pdev) |
a5f6abd4 WB |
1405 | { |
1406 | struct driver_data *drv_data = platform_get_drvdata(pdev); | |
1407 | int status = 0; | |
1408 | ||
1409 | /* Enable the SPI interface */ | |
1410 | bfin_spi_enable(drv_data); | |
1411 | ||
1412 | /* Start the queue running */ | |
138f97cd | 1413 | status = bfin_spi_start_queue(drv_data); |
a5f6abd4 WB |
1414 | if (status != 0) { |
1415 | dev_err(&pdev->dev, "problem starting queue (%d)\n", status); | |
1416 | return status; | |
1417 | } | |
1418 | ||
1419 | return 0; | |
1420 | } | |
1421 | #else | |
138f97cd MF |
1422 | #define bfin_spi_suspend NULL |
1423 | #define bfin_spi_resume NULL | |
a5f6abd4 WB |
1424 | #endif /* CONFIG_PM */ |
1425 | ||
7e38c3c4 | 1426 | MODULE_ALIAS("platform:bfin-spi"); |
138f97cd | 1427 | static struct platform_driver bfin_spi_driver = { |
fc3ba952 | 1428 | .driver = { |
a32c691d | 1429 | .name = DRV_NAME, |
88b40369 BW |
1430 | .owner = THIS_MODULE, |
1431 | }, | |
138f97cd MF |
1432 | .suspend = bfin_spi_suspend, |
1433 | .resume = bfin_spi_resume, | |
1434 | .remove = __devexit_p(bfin_spi_remove), | |
a5f6abd4 WB |
1435 | }; |
1436 | ||
138f97cd | 1437 | static int __init bfin_spi_init(void) |
a5f6abd4 | 1438 | { |
138f97cd | 1439 | return platform_driver_probe(&bfin_spi_driver, bfin_spi_probe); |
a5f6abd4 | 1440 | } |
138f97cd | 1441 | module_init(bfin_spi_init); |
a5f6abd4 | 1442 | |
138f97cd | 1443 | static void __exit bfin_spi_exit(void) |
a5f6abd4 | 1444 | { |
138f97cd | 1445 | platform_driver_unregister(&bfin_spi_driver); |
a5f6abd4 | 1446 | } |
138f97cd | 1447 | module_exit(bfin_spi_exit); |