projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
spi: spi_bfin: bugfix for 8..16 bit word sizes
[deliverable/linux.git] / drivers / spi / spi_bfin5xx.c
CommitLineData
a5f6abd4 1/*
131b17d4
BW		 2 * File: drivers/spi/bfin5xx_spi.c
3 * Maintainer:
4 * Bryan Wu <bryan.wu@analog.com>
5 * Original Author:
6 * Luke Yang (Analog Devices Inc.)
a5f6abd4 7 *
131b17d4
BW		 8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
a5f6abd4
WB		 11 *
12 * Modified:
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
131b17d4 15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
a32c691d
BW		 16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
a5f6abd4 18 *
131b17d4 19 * Copyright 2004-2007 Analog Devices Inc.
a5f6abd4
WB		 20 *
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
24 * any later version.
25 *
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
30 *
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
35 */
36
37#include <linux/init.h>
38#include <linux/module.h>
131b17d4 39#include <linux/delay.h>
a5f6abd4 40#include <linux/device.h>
131b17d4 41#include <linux/io.h>
a5f6abd4 42#include <linux/ioport.h>
131b17d4 43#include <linux/irq.h>
a5f6abd4
WB		 44#include <linux/errno.h>
45#include <linux/interrupt.h>
46#include <linux/platform_device.h>
47#include <linux/dma-mapping.h>
48#include <linux/spi/spi.h>
49#include <linux/workqueue.h>
a5f6abd4 50
a5f6abd4 51#include <asm/dma.h>
131b17d4 52#include <asm/portmux.h>
a5f6abd4
WB		 53#include <asm/bfin5xx_spi.h>
54
a32c691d
BW		 55#define DRV_NAME "bfin-spi"
56#define DRV_AUTHOR "Bryan Wu, Luke Yang"
57#define DRV_DESC "Blackfin BF5xx on-chip SPI Contoller Driver"
58#define DRV_VERSION "1.0"
59
60MODULE_AUTHOR(DRV_AUTHOR);
61MODULE_DESCRIPTION(DRV_DESC);
a5f6abd4
WB		 62MODULE_LICENSE("GPL");
63
bb90eb00 64#define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
a5f6abd4 65
bb90eb00
BW		 66#define START_STATE ((void *)0)
67#define RUNNING_STATE ((void *)1)
68#define DONE_STATE ((void *)2)
69#define ERROR_STATE ((void *)-1)
70#define QUEUE_RUNNING 0
71#define QUEUE_STOPPED 1
a5f6abd4
WB		 72
73struct driver_data {
74 /* Driver model hookup */
75 struct platform_device *pdev;
76
77 /* SPI framework hookup */
78 struct spi_master *master;
79
bb90eb00
BW		 80 /* Regs base of SPI controller */
81 u32 regs_base;
82
a5f6abd4
WB		 83 /* BFIN hookup */
84 struct bfin5xx_spi_master *master_info;
85
86 /* Driver message queue */
87 struct workqueue_struct *workqueue;
88 struct work_struct pump_messages;
89 spinlock_t lock;
90 struct list_head queue;
91 int busy;
92 int run;
93
94 /* Message Transfer pump */
95 struct tasklet_struct pump_transfers;
96
97 /* Current message transfer state info */
98 struct spi_message *cur_msg;
99 struct spi_transfer *cur_transfer;
100 struct chip_data *cur_chip;
101 size_t len_in_bytes;
102 size_t len;
103 void *tx;
104 void *tx_end;
105 void *rx;
106 void *rx_end;
bb90eb00
BW		 107
108 /* DMA stuffs */
109 int dma_channel;
a5f6abd4 110 int dma_mapped;
bb90eb00 111 int dma_requested;
a5f6abd4
WB		 112 dma_addr_t rx_dma;
113 dma_addr_t tx_dma;
bb90eb00 114
a5f6abd4
WB		 115 size_t rx_map_len;
116 size_t tx_map_len;
117 u8 n_bytes;
fad91c89 118 int cs_change;
a5f6abd4
WB		 119 void (*write) (struct driver_data *);
120 void (*read) (struct driver_data *);
121 void (*duplex) (struct driver_data *);
122};
123
124struct chip_data {
125 u16 ctl_reg;
126 u16 baud;
127 u16 flag;
128
129 u8 chip_select_num;
130 u8 n_bytes;
88b40369 131 u8 width; /* 0 or 1 */
a5f6abd4
WB		 132 u8 enable_dma;
133 u8 bits_per_word; /* 8 or 16 */
134 u8 cs_change_per_word;
135 u8 cs_chg_udelay;
136 void (*write) (struct driver_data *);
137 void (*read) (struct driver_data *);
138 void (*duplex) (struct driver_data *);
139};
140
bb90eb00
BW		 141#define DEFINE_SPI_REG(reg, off) \
142static inline u16 read_##reg(struct driver_data *drv_data) \
143 { return bfin_read16(drv_data->regs_base + off); } \
144static inline void write_##reg(struct driver_data *drv_data, u16 v) \
145 { bfin_write16(drv_data->regs_base + off, v); }
146
147DEFINE_SPI_REG(CTRL, 0x00)
148DEFINE_SPI_REG(FLAG, 0x04)
149DEFINE_SPI_REG(STAT, 0x08)
150DEFINE_SPI_REG(TDBR, 0x0C)
151DEFINE_SPI_REG(RDBR, 0x10)
152DEFINE_SPI_REG(BAUD, 0x14)
153DEFINE_SPI_REG(SHAW, 0x18)
154
88b40369 155static void bfin_spi_enable(struct driver_data *drv_data)
a5f6abd4
WB		 156{
157 u16 cr;
158
bb90eb00
BW		 159 cr = read_CTRL(drv_data);
160 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
a5f6abd4
WB		 161}
162
88b40369 163static void bfin_spi_disable(struct driver_data *drv_data)
a5f6abd4
WB		 164{
165 u16 cr;
166
bb90eb00
BW		 167 cr = read_CTRL(drv_data);
168 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
a5f6abd4
WB		 169}
170
171/* Caculate the SPI_BAUD register value based on input HZ */
172static u16 hz_to_spi_baud(u32 speed_hz)
173{
174 u_long sclk = get_sclk();
175 u16 spi_baud = (sclk / (2 * speed_hz));
176
177 if ((sclk % (2 * speed_hz)) > 0)
178 spi_baud++;
179
a5f6abd4
WB		 180 return spi_baud;
181}
182
183static int flush(struct driver_data *drv_data)
184{
185 unsigned long limit = loops_per_jiffy << 1;
186
187 /* wait for stop and clear stat */
bb90eb00 188 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
a5f6abd4
WB		 189 continue;
190
bb90eb00 191 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4
WB		 192
193 return limit;
194}
195
fad91c89 196/* Chip select operation functions for cs_change flag */
bb90eb00 197static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 198{
bb90eb00 199 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 200
201 flag |= chip->flag;
202 flag &= ~(chip->flag << 8);
203
bb90eb00 204 write_FLAG(drv_data, flag);
fad91c89
BW		 205}
206
bb90eb00 207static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
fad91c89 208{
bb90eb00 209 u16 flag = read_FLAG(drv_data);
fad91c89
BW		 210
211 flag |= (chip->flag << 8);
212
bb90eb00 213 write_FLAG(drv_data, flag);
fad91c89
BW		 214}
215
7c4ef094 216#define MAX_SPI_SSEL 7
5fec5b5a 217
a5f6abd4 218/* stop controller and re-config current chip*/
5fec5b5a 219static int restore_state(struct driver_data *drv_data)
a5f6abd4
WB		 220{
221 struct chip_data *chip = drv_data->cur_chip;
5fec5b5a 222 int ret = 0;
12e17c42 223
a5f6abd4 224 /* Clear status and disable clock */
bb90eb00 225 write_STAT(drv_data, BIT_STAT_CLR);
a5f6abd4 226 bfin_spi_disable(drv_data);
88b40369 227 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
a5f6abd4 228
5fec5b5a 229 /* Load the registers */
bb90eb00
BW		 230 cs_deactive(drv_data, chip);
231 write_BAUD(drv_data, chip->baud);
cc487e73
SZ		 232 chip->ctl_reg &= (~BIT_CTL_TIMOD);
233 chip->ctl_reg |= (chip->width << 8);
bb90eb00 234 write_CTRL(drv_data, chip->ctl_reg);
cc487e73
SZ		 235
236 bfin_spi_enable(drv_data);
5fec5b5a 237
5fec5b5a
BW		 238 if (ret)
239 dev_dbg(&drv_data->pdev->dev,
240 ": request chip select number %d failed\n",
241 chip->chip_select_num);
242
243 return ret;
a5f6abd4
WB		 244}
245
246/* used to kick off transfer in rx mode */
bb90eb00 247static unsigned short dummy_read(struct driver_data *drv_data)
a5f6abd4
WB		 248{
249 unsigned short tmp;
bb90eb00 250 tmp = read_RDBR(drv_data);
a5f6abd4
WB		 251 return tmp;
252}
253
254static void null_writer(struct driver_data *drv_data)
255{
256 u8 n_bytes = drv_data->n_bytes;
257
258 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 259 write_TDBR(drv_data, 0);
260 while ((read_STAT(drv_data) & BIT_STAT_TXS))
a5f6abd4
WB		 261 continue;
262 drv_data->tx += n_bytes;
263 }
264}
265
266static void null_reader(struct driver_data *drv_data)
267{
268 u8 n_bytes = drv_data->n_bytes;
bb90eb00 269 dummy_read(drv_data);
a5f6abd4
WB		 270
271 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 272 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 273 continue;
bb90eb00 274 dummy_read(drv_data);
a5f6abd4
WB		 275 drv_data->rx += n_bytes;
276 }
277}
278
279static void u8_writer(struct driver_data *drv_data)
280{
131b17d4 281 dev_dbg(&drv_data->pdev->dev,
bb90eb00 282 "cr8-s is 0x%x\n", read_STAT(drv_data));
cc487e73 283
3f479a65 284 /* poll for SPI completion before start */
bb90eb00 285 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 286 continue;
287
a5f6abd4 288 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 289 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
290 while (read_STAT(drv_data) & BIT_STAT_TXS)
a5f6abd4
WB		 291 continue;
292 ++drv_data->tx;
293 }
a5f6abd4
WB		 294}
295
296static void u8_cs_chg_writer(struct driver_data *drv_data)
297{
298 struct chip_data *chip = drv_data->cur_chip;
299
3f479a65 300 /* poll for SPI completion before start */
bb90eb00 301 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 302 continue;
303
a5f6abd4 304 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 305 cs_active(drv_data, chip);
a5f6abd4 306
bb90eb00
BW		 307 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
308 while (read_STAT(drv_data) & BIT_STAT_TXS)
a5f6abd4 309 continue;
bb90eb00 310 cs_deactive(drv_data, chip);
5fec5b5a 311
a5f6abd4
WB		 312 if (chip->cs_chg_udelay)
313 udelay(chip->cs_chg_udelay);
314 ++drv_data->tx;
315 }
a5f6abd4
WB		 316}
317
318static void u8_reader(struct driver_data *drv_data)
319{
131b17d4 320 dev_dbg(&drv_data->pdev->dev,
bb90eb00 321 "cr-8 is 0x%x\n", read_STAT(drv_data));
a5f6abd4 322
3f479a65 323 /* poll for SPI completion before start */
bb90eb00 324 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 325 continue;
326
a5f6abd4 327 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 328 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 329
bb90eb00 330 dummy_read(drv_data);
cc487e73 331
a5f6abd4 332 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 333 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 334 continue;
bb90eb00 335 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 336 ++drv_data->rx;
337 }
338
bb90eb00 339 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 340 continue;
bb90eb00 341 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 342 ++drv_data->rx;
343}
344
345static void u8_cs_chg_reader(struct driver_data *drv_data)
346{
347 struct chip_data *chip = drv_data->cur_chip;
348
3f479a65 349 /* poll for SPI completion before start */
bb90eb00 350 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 351 continue;
352
cc487e73 353 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 354 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 355
bb90eb00
BW		 356 cs_active(drv_data, chip);
357 dummy_read(drv_data);
cc487e73
SZ		 358
359 while (drv_data->rx < drv_data->rx_end - 1) {
bb90eb00 360 cs_deactive(drv_data, chip);
5fec5b5a 361
a5f6abd4
WB		 362 if (chip->cs_chg_udelay)
363 udelay(chip->cs_chg_udelay);
cc487e73 364
bb90eb00 365 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
cc487e73 366 continue;
bb90eb00
BW		 367 cs_active(drv_data, chip);
368 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 369 ++drv_data->rx;
370 }
bb90eb00 371 cs_deactive(drv_data, chip);
5fec5b5a 372
bb90eb00 373 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
cc487e73 374 continue;
bb90eb00 375 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 376 ++drv_data->rx;
a5f6abd4
WB		 377}
378
379static void u8_duplex(struct driver_data *drv_data)
380{
3f479a65 381 /* poll for SPI completion before start */
bb90eb00 382 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 383 continue;
384
a5f6abd4
WB		 385 /* in duplex mode, clk is triggered by writing of TDBR */
386 while (drv_data->rx < drv_data->rx_end) {
bb90eb00
BW		 387 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
388 while (read_STAT(drv_data) & BIT_STAT_TXS)
a5f6abd4 389 continue;
bb90eb00 390 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 391 continue;
bb90eb00 392 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 393 ++drv_data->rx;
394 ++drv_data->tx;
395 }
396}
397
398static void u8_cs_chg_duplex(struct driver_data *drv_data)
399{
400 struct chip_data *chip = drv_data->cur_chip;
401
3f479a65 402 /* poll for SPI completion before start */
bb90eb00 403 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 404 continue;
405
a5f6abd4 406 while (drv_data->rx < drv_data->rx_end) {
bb90eb00 407 cs_active(drv_data, chip);
5fec5b5a 408
bb90eb00
BW		 409 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
410 while (read_STAT(drv_data) & BIT_STAT_TXS)
a5f6abd4 411 continue;
bb90eb00 412 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 413 continue;
bb90eb00
BW		 414 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
415 cs_deactive(drv_data, chip);
5fec5b5a 416
a5f6abd4
WB		 417 if (chip->cs_chg_udelay)
418 udelay(chip->cs_chg_udelay);
419 ++drv_data->rx;
420 ++drv_data->tx;
421 }
a5f6abd4
WB		 422}
423
424static void u16_writer(struct driver_data *drv_data)
425{
131b17d4 426 dev_dbg(&drv_data->pdev->dev,
bb90eb00 427 "cr16 is 0x%x\n", read_STAT(drv_data));
88b40369 428
3f479a65 429 /* poll for SPI completion before start */
bb90eb00 430 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 431 continue;
432
a5f6abd4 433 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 434 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
435 while ((read_STAT(drv_data) & BIT_STAT_TXS))
a5f6abd4
WB		 436 continue;
437 drv_data->tx += 2;
438 }
a5f6abd4
WB		 439}
440
441static void u16_cs_chg_writer(struct driver_data *drv_data)
442{
443 struct chip_data *chip = drv_data->cur_chip;
444
3f479a65 445 /* poll for SPI completion before start */
bb90eb00 446 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 447 continue;
448
a5f6abd4 449 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 450 cs_active(drv_data, chip);
a5f6abd4 451
bb90eb00
BW		 452 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
453 while ((read_STAT(drv_data) & BIT_STAT_TXS))
a5f6abd4 454 continue;
bb90eb00 455 cs_deactive(drv_data, chip);
5fec5b5a 456
a5f6abd4
WB		 457 if (chip->cs_chg_udelay)
458 udelay(chip->cs_chg_udelay);
459 drv_data->tx += 2;
460 }
a5f6abd4
WB		 461}
462
463static void u16_reader(struct driver_data *drv_data)
464{
88b40369 465 dev_dbg(&drv_data->pdev->dev,
bb90eb00 466 "cr-16 is 0x%x\n", read_STAT(drv_data));
cc487e73 467
3f479a65 468 /* poll for SPI completion before start */
bb90eb00 469 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 470 continue;
471
cc487e73 472 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 473 write_TDBR(drv_data, 0xFFFF);
cc487e73 474
bb90eb00 475 dummy_read(drv_data);
a5f6abd4
WB		 476
477 while (drv_data->rx < (drv_data->rx_end - 2)) {
bb90eb00 478 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 479 continue;
bb90eb00 480 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 481 drv_data->rx += 2;
482 }
483
bb90eb00 484 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 485 continue;
bb90eb00 486 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
a5f6abd4
WB		 487 drv_data->rx += 2;
488}
489
490static void u16_cs_chg_reader(struct driver_data *drv_data)
491{
492 struct chip_data *chip = drv_data->cur_chip;
493
3f479a65 494 /* poll for SPI completion before start */
bb90eb00 495 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 496 continue;
497
cc487e73 498 /* clear TDBR buffer before read(else it will be shifted out) */
bb90eb00 499 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 500
bb90eb00
BW		 501 cs_active(drv_data, chip);
502 dummy_read(drv_data);
cc487e73 503
c3061abb 504 while (drv_data->rx < drv_data->rx_end - 2) {
bb90eb00 505 cs_deactive(drv_data, chip);
5fec5b5a 506
a5f6abd4
WB		 507 if (chip->cs_chg_udelay)
508 udelay(chip->cs_chg_udelay);
cc487e73 509
bb90eb00 510 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
cc487e73 511 continue;
bb90eb00
BW		 512 cs_active(drv_data, chip);
513 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 514 drv_data->rx += 2;
515 }
bb90eb00 516 cs_deactive(drv_data, chip);
cc487e73 517
bb90eb00 518 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
cc487e73 519 continue;
bb90eb00 520 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
cc487e73 521 drv_data->rx += 2;
a5f6abd4
WB		 522}
523
524static void u16_duplex(struct driver_data *drv_data)
525{
3f479a65 526 /* poll for SPI completion before start */
bb90eb00 527 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 528 continue;
529
a5f6abd4
WB		 530 /* in duplex mode, clk is triggered by writing of TDBR */
531 while (drv_data->tx < drv_data->tx_end) {
bb90eb00
BW		 532 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
533 while (read_STAT(drv_data) & BIT_STAT_TXS)
a5f6abd4 534 continue;
bb90eb00 535 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 536 continue;
bb90eb00 537 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
a5f6abd4
WB		 538 drv_data->rx += 2;
539 drv_data->tx += 2;
540 }
541}
542
543static void u16_cs_chg_duplex(struct driver_data *drv_data)
544{
545 struct chip_data *chip = drv_data->cur_chip;
546
3f479a65 547 /* poll for SPI completion before start */
bb90eb00 548 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 549 continue;
550
a5f6abd4 551 while (drv_data->tx < drv_data->tx_end) {
bb90eb00 552 cs_active(drv_data, chip);
a5f6abd4 553
bb90eb00
BW		 554 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
555 while (read_STAT(drv_data) & BIT_STAT_TXS)
a5f6abd4 556 continue;
bb90eb00 557 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
a5f6abd4 558 continue;
bb90eb00
BW		 559 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
560 cs_deactive(drv_data, chip);
5fec5b5a 561
a5f6abd4
WB		 562 if (chip->cs_chg_udelay)
563 udelay(chip->cs_chg_udelay);
564 drv_data->rx += 2;
565 drv_data->tx += 2;
566 }
a5f6abd4
WB		 567}
568
569/* test if ther is more transfer to be done */
570static void *next_transfer(struct driver_data *drv_data)
571{
572 struct spi_message *msg = drv_data->cur_msg;
573 struct spi_transfer *trans = drv_data->cur_transfer;
574
575 /* Move to next transfer */
576 if (trans->transfer_list.next != &msg->transfers) {
577 drv_data->cur_transfer =
578 list_entry(trans->transfer_list.next,
579 struct spi_transfer, transfer_list);
580 return RUNNING_STATE;
581 } else
582 return DONE_STATE;
583}
584
585/*
586 * caller already set message->status;
587 * dma and pio irqs are blocked give finished message back
588 */
589static void giveback(struct driver_data *drv_data)
590{
fad91c89 591 struct chip_data *chip = drv_data->cur_chip;
a5f6abd4
WB		 592 struct spi_transfer *last_transfer;
593 unsigned long flags;
594 struct spi_message *msg;
595
596 spin_lock_irqsave(&drv_data->lock, flags);
597 msg = drv_data->cur_msg;
598 drv_data->cur_msg = NULL;
599 drv_data->cur_transfer = NULL;
600 drv_data->cur_chip = NULL;
601 queue_work(drv_data->workqueue, &drv_data->pump_messages);
602 spin_unlock_irqrestore(&drv_data->lock, flags);
603
604 last_transfer = list_entry(msg->transfers.prev,
605 struct spi_transfer, transfer_list);
606
607 msg->state = NULL;
608
609 /* disable chip select signal. And not stop spi in autobuffer mode */
610 if (drv_data->tx_dma != 0xFFFF) {
bb90eb00 611 cs_deactive(drv_data, chip);
a5f6abd4
WB		 612 bfin_spi_disable(drv_data);
613 }
614
fad91c89 615 if (!drv_data->cs_change)
bb90eb00 616 cs_deactive(drv_data, chip);
fad91c89 617
a5f6abd4
WB		 618 if (msg->complete)
619 msg->complete(msg->context);
620}
621
88b40369 622static irqreturn_t dma_irq_handler(int irq, void *dev_id)
a5f6abd4
WB		 623{
624 struct driver_data *drv_data = (struct driver_data *)dev_id;
fad91c89 625 struct chip_data *chip = drv_data->cur_chip;
bb90eb00 626 struct spi_message *msg = drv_data->cur_msg;
a5f6abd4 627
88b40369 628 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
bb90eb00 629 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4 630
d6fe89b0 631 /* Wait for DMA to complete */
bb90eb00 632 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
d6fe89b0
BW		 633 continue;
634
a5f6abd4 635 /*
d6fe89b0
BW		 636 * wait for the last transaction shifted out. HRM states:
637 * at this point there may still be data in the SPI DMA FIFO waiting
638 * to be transmitted ... software needs to poll TXS in the SPI_STAT
639 * register until it goes low for 2 successive reads
a5f6abd4
WB		 640 */
641 if (drv_data->tx != NULL) {
bb90eb00
BW		 642 while ((read_STAT(drv_data) & TXS) ||
643 (read_STAT(drv_data) & TXS))
a5f6abd4
WB		 644 continue;
645 }
646
bb90eb00 647 while (!(read_STAT(drv_data) & SPIF))
a5f6abd4
WB		 648 continue;
649
a5f6abd4
WB		 650 msg->actual_length += drv_data->len_in_bytes;
651
fad91c89 652 if (drv_data->cs_change)
bb90eb00 653 cs_deactive(drv_data, chip);
fad91c89 654
a5f6abd4
WB		 655 /* Move to next transfer */
656 msg->state = next_transfer(drv_data);
657
658 /* Schedule transfer tasklet */
659 tasklet_schedule(&drv_data->pump_transfers);
660
661 /* free the irq handler before next transfer */
88b40369
BW		 662 dev_dbg(&drv_data->pdev->dev,
663 "disable dma channel irq%d\n",
bb90eb00
BW		 664 drv_data->dma_channel);
665 dma_disable_irq(drv_data->dma_channel);
a5f6abd4
WB		 666
667 return IRQ_HANDLED;
668}
669
670static void pump_transfers(unsigned long data)
671{
672 struct driver_data *drv_data = (struct driver_data *)data;
673 struct spi_message *message = NULL;
674 struct spi_transfer *transfer = NULL;
675 struct spi_transfer *previous = NULL;
676 struct chip_data *chip = NULL;
88b40369
BW		 677 u8 width;
678 u16 cr, dma_width, dma_config;
a5f6abd4
WB		 679 u32 tranf_success = 1;
680
681 /* Get current state information */
682 message = drv_data->cur_msg;
683 transfer = drv_data->cur_transfer;
684 chip = drv_data->cur_chip;
a5f6abd4
WB		 685 /*
686 * if msg is error or done, report it back using complete() callback
687 */
688
689 /* Handle for abort */
690 if (message->state == ERROR_STATE) {
691 message->status = -EIO;
692 giveback(drv_data);
693 return;
694 }
695
696 /* Handle end of message */
697 if (message->state == DONE_STATE) {
698 message->status = 0;
699 giveback(drv_data);
700 return;
701 }
702
703 /* Delay if requested at end of transfer */
704 if (message->state == RUNNING_STATE) {
705 previous = list_entry(transfer->transfer_list.prev,
706 struct spi_transfer, transfer_list);
707 if (previous->delay_usecs)
708 udelay(previous->delay_usecs);
709 }
710
711 /* Setup the transfer state based on the type of transfer */
712 if (flush(drv_data) == 0) {
713 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
714 message->status = -EIO;
715 giveback(drv_data);
716 return;
717 }
718
719 if (transfer->tx_buf != NULL) {
720 drv_data->tx = (void *)transfer->tx_buf;
721 drv_data->tx_end = drv_data->tx + transfer->len;
88b40369
BW		 722 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
723 transfer->tx_buf, drv_data->tx_end);
a5f6abd4
WB		 724 } else {
725 drv_data->tx = NULL;
726 }
727
728 if (transfer->rx_buf != NULL) {
729 drv_data->rx = transfer->rx_buf;
730 drv_data->rx_end = drv_data->rx + transfer->len;
88b40369
BW		 731 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
732 transfer->rx_buf, drv_data->rx_end);
a5f6abd4
WB		 733 } else {
734 drv_data->rx = NULL;
735 }
736
737 drv_data->rx_dma = transfer->rx_dma;
738 drv_data->tx_dma = transfer->tx_dma;
739 drv_data->len_in_bytes = transfer->len;
fad91c89 740 drv_data->cs_change = transfer->cs_change;
a5f6abd4
WB		 741
742 width = chip->width;
743 if (width == CFG_SPI_WORDSIZE16) {
744 drv_data->len = (transfer->len) >> 1;
745 } else {
746 drv_data->len = transfer->len;
747 }
748 drv_data->write = drv_data->tx ? chip->write : null_writer;
749 drv_data->read = drv_data->rx ? chip->read : null_reader;
750 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
131b17d4
BW		 751 dev_dbg(&drv_data->pdev->dev, "transfer: ",
752 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
753 drv_data->write, chip->write, null_writer);
a5f6abd4
WB		 754
755 /* speed and width has been set on per message */
756 message->state = RUNNING_STATE;
757 dma_config = 0;
758
bb90eb00
BW		 759 write_STAT(drv_data, BIT_STAT_CLR);
760 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
761 cs_active(drv_data, chip);
a5f6abd4 762
88b40369
BW		 763 dev_dbg(&drv_data->pdev->dev,
764 "now pumping a transfer: width is %d, len is %d\n",
765 width, transfer->len);
a5f6abd4
WB		 766
767 /*
768 * Try to map dma buffer and do a dma transfer if
769 * successful use different way to r/w according to
770 * drv_data->cur_chip->enable_dma
771 */
772 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
773
bb90eb00
BW		 774 disable_dma(drv_data->dma_channel);
775 clear_dma_irqstat(drv_data->dma_channel);
a5f6abd4
WB		 776
777 /* config dma channel */
88b40369 778 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
a5f6abd4 779 if (width == CFG_SPI_WORDSIZE16) {
bb90eb00
BW		 780 set_dma_x_count(drv_data->dma_channel, drv_data->len);
781 set_dma_x_modify(drv_data->dma_channel, 2);
a5f6abd4
WB		 782 dma_width = WDSIZE_16;
783 } else {
bb90eb00
BW		 784 set_dma_x_count(drv_data->dma_channel, drv_data->len);
785 set_dma_x_modify(drv_data->dma_channel, 1);
a5f6abd4
WB		 786 dma_width = WDSIZE_8;
787 }
788
3f479a65 789 /* poll for SPI completion before start */
bb90eb00 790 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
3f479a65
SZ		 791 continue;
792
a5f6abd4
WB		 793 /* dirty hack for autobuffer DMA mode */
794 if (drv_data->tx_dma == 0xFFFF) {
88b40369
BW		 795 dev_dbg(&drv_data->pdev->dev,
796 "doing autobuffer DMA out.\n");
a5f6abd4 797
cc487e73 798 /* set SPI transfer mode */
bb90eb00 799 write_CTRL(drv_data, (cr | CFG_SPI_DMAWRITE));
cc487e73 800
a5f6abd4
WB		 801 /* no irq in autobuffer mode */
802 dma_config =
803 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
bb90eb00
BW		 804 set_dma_config(drv_data->dma_channel, dma_config);
805 set_dma_start_addr(drv_data->dma_channel,
a32c691d 806 (unsigned long)drv_data->tx);
bb90eb00 807 enable_dma(drv_data->dma_channel);
a5f6abd4
WB		 808
809 /* just return here, there can only be one transfer in this mode */
810 message->status = 0;
811 giveback(drv_data);
812 return;
813 }
814
815 /* In dma mode, rx or tx must be NULL in one transfer */
816 if (drv_data->rx != NULL) {
817 /* set transfer mode, and enable SPI */
88b40369 818 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
a5f6abd4 819
cc487e73 820 /* set SPI transfer mode */
bb90eb00 821 write_CTRL(drv_data, (cr | CFG_SPI_DMAREAD));
a5f6abd4
WB		 822
823 /* clear tx reg soformer data is not shifted out */
bb90eb00 824 write_TDBR(drv_data, 0xFFFF);
a5f6abd4 825
bb90eb00 826 set_dma_x_count(drv_data->dma_channel, drv_data->len);
a5f6abd4
WB		 827
828 /* start dma */
bb90eb00 829 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 830 dma_config = (WNR | RESTART | dma_width | DI_EN);
bb90eb00
BW		 831 set_dma_config(drv_data->dma_channel, dma_config);
832 set_dma_start_addr(drv_data->dma_channel,
a32c691d 833 (unsigned long)drv_data->rx);
bb90eb00 834 enable_dma(drv_data->dma_channel);
a5f6abd4 835
a5f6abd4 836 } else if (drv_data->tx != NULL) {
88b40369 837 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
a5f6abd4 838
cc487e73 839 /* set SPI transfer mode */
bb90eb00 840 write_CTRL(drv_data, (cr | CFG_SPI_DMAWRITE));
cc487e73 841
a5f6abd4 842 /* start dma */
bb90eb00 843 dma_enable_irq(drv_data->dma_channel);
a5f6abd4 844 dma_config = (RESTART | dma_width | DI_EN);
bb90eb00
BW		 845 set_dma_config(drv_data->dma_channel, dma_config);
846 set_dma_start_addr(drv_data->dma_channel,
a32c691d 847 (unsigned long)drv_data->tx);
bb90eb00 848 enable_dma(drv_data->dma_channel);
a5f6abd4
WB		 849 }
850 } else {
851 /* IO mode write then read */
88b40369 852 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
a5f6abd4 853
a5f6abd4
WB		 854 if (drv_data->tx != NULL && drv_data->rx != NULL) {
855 /* full duplex mode */
856 BUG_ON((drv_data->tx_end - drv_data->tx) !=
857 (drv_data->rx_end - drv_data->rx));
88b40369
BW		 858 dev_dbg(&drv_data->pdev->dev,
859 "IO duplex: cr is 0x%x\n", cr);
a5f6abd4 860
cc487e73 861 /* set SPI transfer mode */
bb90eb00 862 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 863
864 drv_data->duplex(drv_data);
865
866 if (drv_data->tx != drv_data->tx_end)
867 tranf_success = 0;
868 } else if (drv_data->tx != NULL) {
869 /* write only half duplex */
131b17d4 870 dev_dbg(&drv_data->pdev->dev,
88b40369 871 "IO write: cr is 0x%x\n", cr);
a5f6abd4 872
cc487e73 873 /* set SPI transfer mode */
bb90eb00 874 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
a5f6abd4
WB		 875
876 drv_data->write(drv_data);
877
878 if (drv_data->tx != drv_data->tx_end)
879 tranf_success = 0;
880 } else if (drv_data->rx != NULL) {
881 /* read only half duplex */
131b17d4 882 dev_dbg(&drv_data->pdev->dev,
88b40369 883 "IO read: cr is 0x%x\n", cr);
a5f6abd4 884
cc487e73 885 /* set SPI transfer mode */
bb90eb00 886 write_CTRL(drv_data, (cr | CFG_SPI_READ));
a5f6abd4
WB		 887
888 drv_data->read(drv_data);
889 if (drv_data->rx != drv_data->rx_end)
890 tranf_success = 0;
891 }
892
893 if (!tranf_success) {
131b17d4 894 dev_dbg(&drv_data->pdev->dev,
88b40369 895 "IO write error!\n");
a5f6abd4
WB		 896 message->state = ERROR_STATE;
897 } else {
898 /* Update total byte transfered */
899 message->actual_length += drv_data->len;
900
901 /* Move to next transfer of this msg */
902 message->state = next_transfer(drv_data);
903 }
904
905 /* Schedule next transfer tasklet */
906 tasklet_schedule(&drv_data->pump_transfers);
907
908 }
909}
910
911/* pop a msg from queue and kick off real transfer */
912static void pump_messages(struct work_struct *work)
913{
131b17d4 914 struct driver_data *drv_data;
a5f6abd4
WB		 915 unsigned long flags;
916
131b17d4
BW		 917 drv_data = container_of(work, struct driver_data, pump_messages);
918
a5f6abd4
WB		 919 /* Lock queue and check for queue work */
920 spin_lock_irqsave(&drv_data->lock, flags);
921 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
922 /* pumper kicked off but no work to do */
923 drv_data->busy = 0;
924 spin_unlock_irqrestore(&drv_data->lock, flags);
925 return;
926 }
927
928 /* Make sure we are not already running a message */
929 if (drv_data->cur_msg) {
930 spin_unlock_irqrestore(&drv_data->lock, flags);
931 return;
932 }
933
934 /* Extract head of queue */
935 drv_data->cur_msg = list_entry(drv_data->queue.next,
936 struct spi_message, queue);
5fec5b5a
BW		 937
938 /* Setup the SSP using the per chip configuration */
939 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
940 if (restore_state(drv_data)) {
941 spin_unlock_irqrestore(&drv_data->lock, flags);
942 return;
943 };
944
a5f6abd4
WB		 945 list_del_init(&drv_data->cur_msg->queue);
946
947 /* Initial message state */
948 drv_data->cur_msg->state = START_STATE;
949 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
950 struct spi_transfer, transfer_list);
951
5fec5b5a
BW		 952 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
953 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
954 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
955 drv_data->cur_chip->ctl_reg);
131b17d4
BW		 956
957 dev_dbg(&drv_data->pdev->dev,
88b40369
BW		 958 "the first transfer len is %d\n",
959 drv_data->cur_transfer->len);
a5f6abd4
WB		 960
961 /* Mark as busy and launch transfers */
962 tasklet_schedule(&drv_data->pump_transfers);
963
964 drv_data->busy = 1;
965 spin_unlock_irqrestore(&drv_data->lock, flags);
966}
967
968/*
969 * got a msg to transfer, queue it in drv_data->queue.
970 * And kick off message pumper
971 */
972static int transfer(struct spi_device *spi, struct spi_message *msg)
973{
974 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
975 unsigned long flags;
976
977 spin_lock_irqsave(&drv_data->lock, flags);
978
979 if (drv_data->run == QUEUE_STOPPED) {
980 spin_unlock_irqrestore(&drv_data->lock, flags);
981 return -ESHUTDOWN;
982 }
983
984 msg->actual_length = 0;
985 msg->status = -EINPROGRESS;
986 msg->state = START_STATE;
987
88b40369 988 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
a5f6abd4
WB		 989 list_add_tail(&msg->queue, &drv_data->queue);
990
991 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
992 queue_work(drv_data->workqueue, &drv_data->pump_messages);
993
994 spin_unlock_irqrestore(&drv_data->lock, flags);
995
996 return 0;
997}
998
12e17c42
SZ		 999#define MAX_SPI_SSEL 7
1000
1001static u16 ssel[3][MAX_SPI_SSEL] = {
1002 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1003 P_SPI0_SSEL4, P_SPI0_SSEL5,
1004 P_SPI0_SSEL6, P_SPI0_SSEL7},
1005
1006 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1007 P_SPI1_SSEL4, P_SPI1_SSEL5,
1008 P_SPI1_SSEL6, P_SPI1_SSEL7},
1009
1010 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1011 P_SPI2_SSEL4, P_SPI2_SSEL5,
1012 P_SPI2_SSEL6, P_SPI2_SSEL7},
1013};
1014
a5f6abd4
WB		 1015/* first setup for new devices */
1016static int setup(struct spi_device *spi)
1017{
1018 struct bfin5xx_spi_chip *chip_info = NULL;
1019 struct chip_data *chip;
1020 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1021 u8 spi_flg;
1022
1023 /* Abort device setup if requested features are not supported */
1024 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1025 dev_err(&spi->dev, "requested mode not fully supported\n");
1026 return -EINVAL;
1027 }
1028
1029 /* Zero (the default) here means 8 bits */
1030 if (!spi->bits_per_word)
1031 spi->bits_per_word = 8;
1032
1033 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1034 return -EINVAL;
1035
1036 /* Only alloc (or use chip_info) on first setup */
1037 chip = spi_get_ctldata(spi);
1038 if (chip == NULL) {
1039 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1040 if (!chip)
1041 return -ENOMEM;
1042
1043 chip->enable_dma = 0;
1044 chip_info = spi->controller_data;
1045 }
1046
1047 /* chip_info isn't always needed */
1048 if (chip_info) {
2ed35516
MF		 1049 /* Make sure people stop trying to set fields via ctl_reg
1050 * when they should actually be using common SPI framework.
1051 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1052 * Not sure if a user actually needs/uses any of these,
1053 * but let's assume (for now) they do.
1054 */
1055 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1056 dev_err(&spi->dev, "do not set bits in ctl_reg "
1057 "that the SPI framework manages\n");
1058 return -EINVAL;
1059 }
1060
a5f6abd4
WB		 1061 chip->enable_dma = chip_info->enable_dma != 0
1062 && drv_data->master_info->enable_dma;
1063 chip->ctl_reg = chip_info->ctl_reg;
1064 chip->bits_per_word = chip_info->bits_per_word;
1065 chip->cs_change_per_word = chip_info->cs_change_per_word;
1066 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1067 }
1068
1069 /* translate common spi framework into our register */
1070 if (spi->mode & SPI_CPOL)
1071 chip->ctl_reg |= CPOL;
1072 if (spi->mode & SPI_CPHA)
1073 chip->ctl_reg |= CPHA;
1074 if (spi->mode & SPI_LSB_FIRST)
1075 chip->ctl_reg |= LSBF;
1076 /* we dont support running in slave mode (yet?) */
1077 chip->ctl_reg |= MSTR;
1078
1079 /*
1080 * if any one SPI chip is registered and wants DMA, request the
1081 * DMA channel for it
1082 */
bb90eb00 1083 if (chip->enable_dma && !drv_data->dma_requested) {
a5f6abd4 1084 /* register dma irq handler */
bb90eb00 1085 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
88b40369
BW		 1086 dev_dbg(&spi->dev,
1087 "Unable to request BlackFin SPI DMA channel\n");
a5f6abd4
WB		 1088 return -ENODEV;
1089 }
bb90eb00
BW		 1090 if (set_dma_callback(drv_data->dma_channel,
1091 (void *)dma_irq_handler, drv_data) < 0) {
88b40369 1092 dev_dbg(&spi->dev, "Unable to set dma callback\n");
a5f6abd4
WB		 1093 return -EPERM;
1094 }
bb90eb00
BW		 1095 dma_disable_irq(drv_data->dma_channel);
1096 drv_data->dma_requested = 1;
a5f6abd4
WB		 1097 }
1098
1099 /*
1100 * Notice: for blackfin, the speed_hz is the value of register
1101 * SPI_BAUD, not the real baudrate
1102 */
1103 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1104 spi_flg = ~(1 << (spi->chip_select));
1105 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1106 chip->chip_select_num = spi->chip_select;
1107
1108 switch (chip->bits_per_word) {
1109 case 8:
1110 chip->n_bytes = 1;
1111 chip->width = CFG_SPI_WORDSIZE8;
1112 chip->read = chip->cs_change_per_word ?
1113 u8_cs_chg_reader : u8_reader;
1114 chip->write = chip->cs_change_per_word ?
1115 u8_cs_chg_writer : u8_writer;
1116 chip->duplex = chip->cs_change_per_word ?
1117 u8_cs_chg_duplex : u8_duplex;
1118 break;
1119
1120 case 16:
1121 chip->n_bytes = 2;
1122 chip->width = CFG_SPI_WORDSIZE16;
1123 chip->read = chip->cs_change_per_word ?
1124 u16_cs_chg_reader : u16_reader;
1125 chip->write = chip->cs_change_per_word ?
1126 u16_cs_chg_writer : u16_writer;
1127 chip->duplex = chip->cs_change_per_word ?
1128 u16_cs_chg_duplex : u16_duplex;
1129 break;
1130
1131 default:
1132 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1133 chip->bits_per_word);
1134 kfree(chip);
1135 return -ENODEV;
1136 }
1137
898eb71c 1138 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
a5f6abd4 1139 spi->modalias, chip->width, chip->enable_dma);
88b40369 1140 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
a5f6abd4
WB		 1141 chip->ctl_reg, chip->flag);
1142
1143 spi_set_ctldata(spi, chip);
1144
12e17c42
SZ		 1145 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1146 if ((chip->chip_select_num > 0)
1147 && (chip->chip_select_num <= spi->master->num_chipselect))
1148 peripheral_request(ssel[spi->master->bus_num]
1149 [chip->chip_select_num-1], DRV_NAME);
1150
a5f6abd4
WB		 1151 return 0;
1152}
1153
1154/*
1155 * callback for spi framework.
1156 * clean driver specific data
1157 */
88b40369 1158static void cleanup(struct spi_device *spi)
a5f6abd4 1159{
27bb9e79 1160 struct chip_data *chip = spi_get_ctldata(spi);
a5f6abd4 1161
12e17c42
SZ		 1162 if ((chip->chip_select_num > 0)
1163 && (chip->chip_select_num <= spi->master->num_chipselect))
1164 peripheral_free(ssel[spi->master->bus_num]
1165 [chip->chip_select_num-1]);
1166
a5f6abd4
WB		 1167 kfree(chip);
1168}
1169
1170static inline int init_queue(struct driver_data *drv_data)
1171{
1172 INIT_LIST_HEAD(&drv_data->queue);
1173 spin_lock_init(&drv_data->lock);
1174
1175 drv_data->run = QUEUE_STOPPED;
1176 drv_data->busy = 0;
1177
1178 /* init transfer tasklet */
1179 tasklet_init(&drv_data->pump_transfers,
1180 pump_transfers, (unsigned long)drv_data);
1181
1182 /* init messages workqueue */
1183 INIT_WORK(&drv_data->pump_messages, pump_messages);
1184 drv_data->workqueue =
49dce689 1185 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
a5f6abd4
WB		 1186 if (drv_data->workqueue == NULL)
1187 return -EBUSY;
1188
1189 return 0;
1190}
1191
1192static inline int start_queue(struct driver_data *drv_data)
1193{
1194 unsigned long flags;
1195
1196 spin_lock_irqsave(&drv_data->lock, flags);
1197
1198 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1199 spin_unlock_irqrestore(&drv_data->lock, flags);
1200 return -EBUSY;
1201 }
1202
1203 drv_data->run = QUEUE_RUNNING;
1204 drv_data->cur_msg = NULL;
1205 drv_data->cur_transfer = NULL;
1206 drv_data->cur_chip = NULL;
1207 spin_unlock_irqrestore(&drv_data->lock, flags);
1208
1209 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1210
1211 return 0;
1212}
1213
1214static inline int stop_queue(struct driver_data *drv_data)
1215{
1216 unsigned long flags;
1217 unsigned limit = 500;
1218 int status = 0;
1219
1220 spin_lock_irqsave(&drv_data->lock, flags);
1221
1222 /*
1223 * This is a bit lame, but is optimized for the common execution path.
1224 * A wait_queue on the drv_data->busy could be used, but then the common
1225 * execution path (pump_messages) would be required to call wake_up or
1226 * friends on every SPI message. Do this instead
1227 */
1228 drv_data->run = QUEUE_STOPPED;
1229 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1230 spin_unlock_irqrestore(&drv_data->lock, flags);
1231 msleep(10);
1232 spin_lock_irqsave(&drv_data->lock, flags);
1233 }
1234
1235 if (!list_empty(&drv_data->queue) || drv_data->busy)
1236 status = -EBUSY;
1237
1238 spin_unlock_irqrestore(&drv_data->lock, flags);
1239
1240 return status;
1241}
1242
1243static inline int destroy_queue(struct driver_data *drv_data)
1244{
1245 int status;
1246
1247 status = stop_queue(drv_data);
1248 if (status != 0)
1249 return status;
1250
1251 destroy_workqueue(drv_data->workqueue);
1252
1253 return 0;
1254}
1255
7c4ef094 1256static int setup_pin_mux(int action, int bus_num)
cc2f81a6
MH		 1257{
1258
7c4ef094
SZ		 1259 u16 pin_req[3][4] = {
1260 {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
1261 {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
1262 {P_SPI2_SCK, P_SPI2_MISO, P_SPI2_MOSI, 0},
1263 };
cc2f81a6
MH		 1264
1265 if (action) {
7c4ef094 1266 if (peripheral_request_list(pin_req[bus_num], DRV_NAME))
cc2f81a6
MH		 1267 return -EFAULT;
1268 } else {
7c4ef094 1269 peripheral_free_list(pin_req[bus_num]);
cc2f81a6
MH		 1270 }
1271
1272 return 0;
1273}
1274
a5f6abd4
WB		 1275static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1276{
1277 struct device *dev = &pdev->dev;
1278 struct bfin5xx_spi_master *platform_info;
1279 struct spi_master *master;
1280 struct driver_data *drv_data = 0;
a32c691d 1281 struct resource *res;
a5f6abd4
WB		 1282 int status = 0;
1283
1284 platform_info = dev->platform_data;
1285
1286 /* Allocate master with space for drv_data */
1287 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1288 if (!master) {
1289 dev_err(&pdev->dev, "can not alloc spi_master\n");
1290 return -ENOMEM;
1291 }
131b17d4 1292
a5f6abd4
WB		 1293 drv_data = spi_master_get_devdata(master);
1294 drv_data->master = master;
1295 drv_data->master_info = platform_info;
1296 drv_data->pdev = pdev;
1297
1298 master->bus_num = pdev->id;
1299 master->num_chipselect = platform_info->num_chipselect;
1300 master->cleanup = cleanup;
1301 master->setup = setup;
1302 master->transfer = transfer;
1303
a32c691d
BW		 1304 /* Find and map our resources */
1305 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1306 if (res == NULL) {
1307 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1308 status = -ENOENT;
1309 goto out_error_get_res;
1310 }
1311
bb90eb00
BW		 1312 drv_data->regs_base = (u32) ioremap(res->start,
1313 (res->end - res->start + 1));
1314 if (!drv_data->regs_base) {
a32c691d
BW		 1315 dev_err(dev, "Cannot map IO\n");
1316 status = -ENXIO;
1317 goto out_error_ioremap;
1318 }
1319
bb90eb00
BW		 1320 drv_data->dma_channel = platform_get_irq(pdev, 0);
1321 if (drv_data->dma_channel < 0) {
a32c691d
BW		 1322 dev_err(dev, "No DMA channel specified\n");
1323 status = -ENOENT;
1324 goto out_error_no_dma_ch;
1325 }
1326
a5f6abd4
WB		 1327 /* Initial and start queue */
1328 status = init_queue(drv_data);
1329 if (status != 0) {
a32c691d 1330 dev_err(dev, "problem initializing queue\n");
a5f6abd4
WB		 1331 goto out_error_queue_alloc;
1332 }
a32c691d 1333
a5f6abd4
WB		 1334 status = start_queue(drv_data);
1335 if (status != 0) {
a32c691d 1336 dev_err(dev, "problem starting queue\n");
a5f6abd4
WB		 1337 goto out_error_queue_alloc;
1338 }
1339
1340 /* Register with the SPI framework */
1341 platform_set_drvdata(pdev, drv_data);
1342 status = spi_register_master(master);
1343 if (status != 0) {
a32c691d 1344 dev_err(dev, "problem registering spi master\n");
a5f6abd4
WB		 1345 goto out_error_queue_alloc;
1346 }
a32c691d 1347
7c4ef094
SZ		 1348 if (setup_pin_mux(1, master->bus_num)) {
1349 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1350 goto out_error;
1351 }
1352
bb90eb00
BW		 1353 dev_info(dev, "%s, Version %s, regs_base@0x%08x, dma channel@%d\n",
1354 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1355 drv_data->dma_channel);
a5f6abd4
WB		 1356 return status;
1357
cc2f81a6 1358out_error_queue_alloc:
a5f6abd4 1359 destroy_queue(drv_data);
a32c691d 1360out_error_no_dma_ch:
bb90eb00 1361 iounmap((void *) drv_data->regs_base);
a32c691d
BW		 1362out_error_ioremap:
1363out_error_get_res:
cc2f81a6 1364out_error:
a5f6abd4 1365 spi_master_put(master);
cc2f81a6 1366
a5f6abd4
WB		 1367 return status;
1368}
1369
1370/* stop hardware and remove the driver */
1371static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1372{
1373 struct driver_data *drv_data = platform_get_drvdata(pdev);
1374 int status = 0;
1375
1376 if (!drv_data)
1377 return 0;
1378
1379 /* Remove the queue */
1380 status = destroy_queue(drv_data);
1381 if (status != 0)
1382 return status;
1383
1384 /* Disable the SSP at the peripheral and SOC level */
1385 bfin_spi_disable(drv_data);
1386
1387 /* Release DMA */
1388 if (drv_data->master_info->enable_dma) {
bb90eb00
BW		 1389 if (dma_channel_active(drv_data->dma_channel))
1390 free_dma(drv_data->dma_channel);
a5f6abd4
WB		 1391 }
1392
1393 /* Disconnect from the SPI framework */
1394 spi_unregister_master(drv_data->master);
1395
7c4ef094 1396 setup_pin_mux(0, drv_data->master->bus_num);
cc2f81a6 1397
a5f6abd4
WB		 1398 /* Prevent double remove */
1399 platform_set_drvdata(pdev, NULL);
1400
1401 return 0;
1402}
1403
1404#ifdef CONFIG_PM
1405static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1406{
1407 struct driver_data *drv_data = platform_get_drvdata(pdev);
1408 int status = 0;
1409
1410 status = stop_queue(drv_data);
1411 if (status != 0)
1412 return status;
1413
1414 /* stop hardware */
1415 bfin_spi_disable(drv_data);
1416
1417 return 0;
1418}
1419
1420static int bfin5xx_spi_resume(struct platform_device *pdev)
1421{
1422 struct driver_data *drv_data = platform_get_drvdata(pdev);
1423 int status = 0;
1424
1425 /* Enable the SPI interface */
1426 bfin_spi_enable(drv_data);
1427
1428 /* Start the queue running */
1429 status = start_queue(drv_data);
1430 if (status != 0) {
1431 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1432 return status;
1433 }
1434
1435 return 0;
1436}
1437#else
1438#define bfin5xx_spi_suspend NULL
1439#define bfin5xx_spi_resume NULL
1440#endif /* CONFIG_PM */
1441
fc3ba952 1442MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
a5f6abd4 1443static struct platform_driver bfin5xx_spi_driver = {
fc3ba952 1444 .driver = {
a32c691d 1445 .name = DRV_NAME,
88b40369
BW		 1446 .owner = THIS_MODULE,
1447 },
1448 .suspend = bfin5xx_spi_suspend,
1449 .resume = bfin5xx_spi_resume,
1450 .remove = __devexit_p(bfin5xx_spi_remove),
a5f6abd4
WB		 1451};
1452
1453static int __init bfin5xx_spi_init(void)
1454{
88b40369 1455 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
a5f6abd4 1456}
a5f6abd4
WB		 1457module_init(bfin5xx_spi_init);
1458
1459static void __exit bfin5xx_spi_exit(void)
1460{
1461 platform_driver_unregister(&bfin5xx_spi_driver);
1462}
a5f6abd4 1463module_exit(bfin5xx_spi_exit);
Linux kernel - Deliverables
This page took 0.174572 seconds and 5 git commands to generate.