Commit | Line | Data |
---|---|---|
ccf06998 | 1 | /* |
b36ece83 | 2 | * Freescale SPI controller driver. |
ccf06998 KG |
3 | * |
4 | * Maintainer: Kumar Gala | |
5 | * | |
6 | * Copyright (C) 2006 Polycom, Inc. | |
b36ece83 | 7 | * Copyright 2010 Freescale Semiconductor, Inc. |
ccf06998 | 8 | * |
4c1fba44 AV |
9 | * CPM SPI and QE buffer descriptors mode support: |
10 | * Copyright (c) 2009 MontaVista Software, Inc. | |
11 | * Author: Anton Vorontsov <avorontsov@ru.mvista.com> | |
12 | * | |
ccf06998 KG |
13 | * This program is free software; you can redistribute it and/or modify it |
14 | * under the terms of the GNU General Public License as published by the | |
15 | * Free Software Foundation; either version 2 of the License, or (at your | |
16 | * option) any later version. | |
17 | */ | |
18 | #include <linux/module.h> | |
ccf06998 KG |
19 | #include <linux/types.h> |
20 | #include <linux/kernel.h> | |
ccf06998 KG |
21 | #include <linux/interrupt.h> |
22 | #include <linux/delay.h> | |
23 | #include <linux/irq.h> | |
ccf06998 KG |
24 | #include <linux/spi/spi.h> |
25 | #include <linux/spi/spi_bitbang.h> | |
26 | #include <linux/platform_device.h> | |
27 | #include <linux/fsl_devices.h> | |
4c1fba44 AV |
28 | #include <linux/dma-mapping.h> |
29 | #include <linux/mm.h> | |
30 | #include <linux/mutex.h> | |
35b4b3c0 AV |
31 | #include <linux/of.h> |
32 | #include <linux/of_platform.h> | |
33 | #include <linux/gpio.h> | |
34 | #include <linux/of_gpio.h> | |
ccf06998 | 35 | |
35b4b3c0 | 36 | #include <sysdev/fsl_soc.h> |
4c1fba44 AV |
37 | #include <asm/cpm.h> |
38 | #include <asm/qe.h> | |
b36ece83 MH |
39 | |
40 | #include "spi_fsl_lib.h" | |
ccf06998 | 41 | |
4c1fba44 AV |
42 | /* CPM1 and CPM2 are mutually exclusive. */ |
43 | #ifdef CONFIG_CPM1 | |
44 | #include <asm/cpm1.h> | |
45 | #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_CH_SPI, 0) | |
46 | #else | |
47 | #include <asm/cpm2.h> | |
48 | #define CPM_SPI_CMD mk_cr_cmd(CPM_CR_SPI_PAGE, CPM_CR_SPI_SBLOCK, 0, 0) | |
49 | #endif | |
50 | ||
ccf06998 | 51 | /* SPI Controller registers */ |
b36ece83 | 52 | struct fsl_spi_reg { |
ccf06998 KG |
53 | u8 res1[0x20]; |
54 | __be32 mode; | |
55 | __be32 event; | |
56 | __be32 mask; | |
57 | __be32 command; | |
58 | __be32 transmit; | |
59 | __be32 receive; | |
60 | }; | |
61 | ||
62 | /* SPI Controller mode register definitions */ | |
2a485d7a | 63 | #define SPMODE_LOOP (1 << 30) |
ccf06998 KG |
64 | #define SPMODE_CI_INACTIVEHIGH (1 << 29) |
65 | #define SPMODE_CP_BEGIN_EDGECLK (1 << 28) | |
66 | #define SPMODE_DIV16 (1 << 27) | |
67 | #define SPMODE_REV (1 << 26) | |
68 | #define SPMODE_MS (1 << 25) | |
69 | #define SPMODE_ENABLE (1 << 24) | |
70 | #define SPMODE_LEN(x) ((x) << 20) | |
71 | #define SPMODE_PM(x) ((x) << 16) | |
f29ba280 | 72 | #define SPMODE_OP (1 << 14) |
c9bfcb31 | 73 | #define SPMODE_CG(x) ((x) << 7) |
ccf06998 KG |
74 | |
75 | /* | |
76 | * Default for SPI Mode: | |
b36ece83 | 77 | * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk |
ccf06998 KG |
78 | */ |
79 | #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \ | |
80 | SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf)) | |
81 | ||
82 | /* SPIE register values */ | |
83 | #define SPIE_NE 0x00000200 /* Not empty */ | |
84 | #define SPIE_NF 0x00000100 /* Not full */ | |
85 | ||
86 | /* SPIM register values */ | |
87 | #define SPIM_NE 0x00000200 /* Not empty */ | |
88 | #define SPIM_NF 0x00000100 /* Not full */ | |
89 | ||
4c1fba44 AV |
90 | #define SPIE_TXB 0x00000200 /* Last char is written to tx fifo */ |
91 | #define SPIE_RXB 0x00000100 /* Last char is written to rx buf */ | |
92 | ||
93 | /* SPCOM register values */ | |
94 | #define SPCOM_STR (1 << 23) /* Start transmit */ | |
95 | ||
96 | #define SPI_PRAM_SIZE 0x100 | |
97 | #define SPI_MRBLR ((unsigned int)PAGE_SIZE) | |
98 | ||
b36ece83 MH |
99 | static void *fsl_dummy_rx; |
100 | static DEFINE_MUTEX(fsl_dummy_rx_lock); | |
101 | static int fsl_dummy_rx_refcnt; | |
ccf06998 | 102 | |
b36ece83 | 103 | static void fsl_spi_change_mode(struct spi_device *spi) |
a35c1710 AV |
104 | { |
105 | struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master); | |
106 | struct spi_mpc8xxx_cs *cs = spi->controller_state; | |
b36ece83 MH |
107 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
108 | __be32 __iomem *mode = ®_base->mode; | |
a35c1710 AV |
109 | unsigned long flags; |
110 | ||
111 | if (cs->hw_mode == mpc8xxx_spi_read_reg(mode)) | |
112 | return; | |
113 | ||
114 | /* Turn off IRQs locally to minimize time that SPI is disabled. */ | |
115 | local_irq_save(flags); | |
116 | ||
117 | /* Turn off SPI unit prior changing mode */ | |
118 | mpc8xxx_spi_write_reg(mode, cs->hw_mode & ~SPMODE_ENABLE); | |
a35c1710 | 119 | |
4c1fba44 AV |
120 | /* When in CPM mode, we need to reinit tx and rx. */ |
121 | if (mspi->flags & SPI_CPM_MODE) { | |
122 | if (mspi->flags & SPI_QE) { | |
123 | qe_issue_cmd(QE_INIT_TX_RX, mspi->subblock, | |
124 | QE_CR_PROTOCOL_UNSPECIFIED, 0); | |
125 | } else { | |
126 | cpm_command(CPM_SPI_CMD, CPM_CR_INIT_TRX); | |
127 | if (mspi->flags & SPI_CPM1) { | |
128 | out_be16(&mspi->pram->rbptr, | |
129 | in_be16(&mspi->pram->rbase)); | |
130 | out_be16(&mspi->pram->tbptr, | |
131 | in_be16(&mspi->pram->tbase)); | |
132 | } | |
133 | } | |
134 | } | |
f9218c2a | 135 | mpc8xxx_spi_write_reg(mode, cs->hw_mode); |
a35c1710 AV |
136 | local_irq_restore(flags); |
137 | } | |
138 | ||
b36ece83 | 139 | static void fsl_spi_chipselect(struct spi_device *spi, int value) |
ccf06998 | 140 | { |
575c5807 | 141 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); |
364fdbc0 AV |
142 | struct fsl_spi_platform_data *pdata = spi->dev.parent->platform_data; |
143 | bool pol = spi->mode & SPI_CS_HIGH; | |
575c5807 | 144 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 | 145 | |
ccf06998 | 146 | if (value == BITBANG_CS_INACTIVE) { |
364fdbc0 AV |
147 | if (pdata->cs_control) |
148 | pdata->cs_control(spi, !pol); | |
ccf06998 KG |
149 | } |
150 | ||
151 | if (value == BITBANG_CS_ACTIVE) { | |
575c5807 AV |
152 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
153 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
154 | mpc8xxx_spi->get_rx = cs->get_rx; | |
155 | mpc8xxx_spi->get_tx = cs->get_tx; | |
c9bfcb31 | 156 | |
b36ece83 | 157 | fsl_spi_change_mode(spi); |
a35c1710 | 158 | |
364fdbc0 AV |
159 | if (pdata->cs_control) |
160 | pdata->cs_control(spi, pol); | |
ccf06998 KG |
161 | } |
162 | } | |
163 | ||
b36ece83 MH |
164 | static int mspi_apply_cpu_mode_quirks(struct spi_mpc8xxx_cs *cs, |
165 | struct spi_device *spi, | |
166 | struct mpc8xxx_spi *mpc8xxx_spi, | |
167 | int bits_per_word) | |
ccf06998 | 168 | { |
c9bfcb31 JT |
169 | cs->rx_shift = 0; |
170 | cs->tx_shift = 0; | |
ccf06998 | 171 | if (bits_per_word <= 8) { |
575c5807 AV |
172 | cs->get_rx = mpc8xxx_spi_rx_buf_u8; |
173 | cs->get_tx = mpc8xxx_spi_tx_buf_u8; | |
87ec0e98 | 174 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
c9bfcb31 JT |
175 | cs->rx_shift = 16; |
176 | cs->tx_shift = 24; | |
f29ba280 | 177 | } |
ccf06998 | 178 | } else if (bits_per_word <= 16) { |
575c5807 AV |
179 | cs->get_rx = mpc8xxx_spi_rx_buf_u16; |
180 | cs->get_tx = mpc8xxx_spi_tx_buf_u16; | |
87ec0e98 | 181 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
c9bfcb31 JT |
182 | cs->rx_shift = 16; |
183 | cs->tx_shift = 16; | |
f29ba280 | 184 | } |
ccf06998 | 185 | } else if (bits_per_word <= 32) { |
575c5807 AV |
186 | cs->get_rx = mpc8xxx_spi_rx_buf_u32; |
187 | cs->get_tx = mpc8xxx_spi_tx_buf_u32; | |
ccf06998 KG |
188 | } else |
189 | return -EINVAL; | |
190 | ||
87ec0e98 | 191 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE && |
0398fb70 | 192 | spi->mode & SPI_LSB_FIRST) { |
c9bfcb31 | 193 | cs->tx_shift = 0; |
35cc0b97 | 194 | if (bits_per_word <= 8) |
c9bfcb31 | 195 | cs->rx_shift = 8; |
35cc0b97 | 196 | else |
c9bfcb31 | 197 | cs->rx_shift = 0; |
35cc0b97 | 198 | } |
575c5807 AV |
199 | mpc8xxx_spi->rx_shift = cs->rx_shift; |
200 | mpc8xxx_spi->tx_shift = cs->tx_shift; | |
201 | mpc8xxx_spi->get_rx = cs->get_rx; | |
202 | mpc8xxx_spi->get_tx = cs->get_tx; | |
ccf06998 | 203 | |
0398fb70 JT |
204 | return bits_per_word; |
205 | } | |
206 | ||
b36ece83 MH |
207 | static int mspi_apply_qe_mode_quirks(struct spi_mpc8xxx_cs *cs, |
208 | struct spi_device *spi, | |
209 | int bits_per_word) | |
0398fb70 JT |
210 | { |
211 | /* QE uses Little Endian for words > 8 | |
212 | * so transform all words > 8 into 8 bits | |
213 | * Unfortnatly that doesn't work for LSB so | |
214 | * reject these for now */ | |
215 | /* Note: 32 bits word, LSB works iff | |
216 | * tfcr/rfcr is set to CPMFCR_GBL */ | |
217 | if (spi->mode & SPI_LSB_FIRST && | |
218 | bits_per_word > 8) | |
219 | return -EINVAL; | |
220 | if (bits_per_word > 8) | |
221 | return 8; /* pretend its 8 bits */ | |
222 | return bits_per_word; | |
223 | } | |
224 | ||
b36ece83 MH |
225 | static int fsl_spi_setup_transfer(struct spi_device *spi, |
226 | struct spi_transfer *t) | |
0398fb70 JT |
227 | { |
228 | struct mpc8xxx_spi *mpc8xxx_spi; | |
b36ece83 | 229 | int bits_per_word = 0; |
0398fb70 | 230 | u8 pm; |
b36ece83 | 231 | u32 hz = 0; |
0398fb70 JT |
232 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
233 | ||
234 | mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
235 | ||
236 | if (t) { | |
237 | bits_per_word = t->bits_per_word; | |
238 | hz = t->speed_hz; | |
0398fb70 JT |
239 | } |
240 | ||
241 | /* spi_transfer level calls that work per-word */ | |
242 | if (!bits_per_word) | |
243 | bits_per_word = spi->bits_per_word; | |
244 | ||
245 | /* Make sure its a bit width we support [4..16, 32] */ | |
246 | if ((bits_per_word < 4) | |
247 | || ((bits_per_word > 16) && (bits_per_word != 32))) | |
248 | return -EINVAL; | |
249 | ||
250 | if (!hz) | |
251 | hz = spi->max_speed_hz; | |
252 | ||
253 | if (!(mpc8xxx_spi->flags & SPI_CPM_MODE)) | |
254 | bits_per_word = mspi_apply_cpu_mode_quirks(cs, spi, | |
255 | mpc8xxx_spi, | |
256 | bits_per_word); | |
257 | else if (mpc8xxx_spi->flags & SPI_QE) | |
258 | bits_per_word = mspi_apply_qe_mode_quirks(cs, spi, | |
259 | bits_per_word); | |
260 | ||
261 | if (bits_per_word < 0) | |
262 | return bits_per_word; | |
263 | ||
ccf06998 KG |
264 | if (bits_per_word == 32) |
265 | bits_per_word = 0; | |
266 | else | |
267 | bits_per_word = bits_per_word - 1; | |
268 | ||
32421daa | 269 | /* mask out bits we are going to set */ |
c9bfcb31 JT |
270 | cs->hw_mode &= ~(SPMODE_LEN(0xF) | SPMODE_DIV16 |
271 | | SPMODE_PM(0xF)); | |
272 | ||
273 | cs->hw_mode |= SPMODE_LEN(bits_per_word); | |
274 | ||
575c5807 | 275 | if ((mpc8xxx_spi->spibrg / hz) > 64) { |
53604dbe | 276 | cs->hw_mode |= SPMODE_DIV16; |
4f4517c4 | 277 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 64) + 1; |
fd8a11e1 AV |
278 | |
279 | WARN_ONCE(pm > 16, "%s: Requested speed is too low: %d Hz. " | |
280 | "Will use %d Hz instead.\n", dev_name(&spi->dev), | |
575c5807 | 281 | hz, mpc8xxx_spi->spibrg / 1024); |
fd8a11e1 | 282 | if (pm > 16) |
53604dbe | 283 | pm = 16; |
b36ece83 | 284 | } else { |
4f4517c4 | 285 | pm = (mpc8xxx_spi->spibrg - 1) / (hz * 4) + 1; |
b36ece83 | 286 | } |
a61f5345 CG |
287 | if (pm) |
288 | pm--; | |
289 | ||
290 | cs->hw_mode |= SPMODE_PM(pm); | |
a35c1710 | 291 | |
b36ece83 | 292 | fsl_spi_change_mode(spi); |
c9bfcb31 JT |
293 | return 0; |
294 | } | |
ccf06998 | 295 | |
b36ece83 | 296 | static void fsl_spi_cpm_bufs_start(struct mpc8xxx_spi *mspi) |
c9bfcb31 | 297 | { |
4c1fba44 AV |
298 | struct cpm_buf_desc __iomem *tx_bd = mspi->tx_bd; |
299 | struct cpm_buf_desc __iomem *rx_bd = mspi->rx_bd; | |
300 | unsigned int xfer_len = min(mspi->count, SPI_MRBLR); | |
301 | unsigned int xfer_ofs; | |
b36ece83 | 302 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
ccf06998 | 303 | |
4c1fba44 AV |
304 | xfer_ofs = mspi->xfer_in_progress->len - mspi->count; |
305 | ||
37880c90 | 306 | if (mspi->rx_dma == mspi->dma_dummy_rx) |
307 | out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma); | |
308 | else | |
309 | out_be32(&rx_bd->cbd_bufaddr, mspi->rx_dma + xfer_ofs); | |
4c1fba44 AV |
310 | out_be16(&rx_bd->cbd_datlen, 0); |
311 | out_be16(&rx_bd->cbd_sc, BD_SC_EMPTY | BD_SC_INTRPT | BD_SC_WRAP); | |
312 | ||
37880c90 | 313 | if (mspi->tx_dma == mspi->dma_dummy_tx) |
314 | out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma); | |
315 | else | |
316 | out_be32(&tx_bd->cbd_bufaddr, mspi->tx_dma + xfer_ofs); | |
4c1fba44 AV |
317 | out_be16(&tx_bd->cbd_datlen, xfer_len); |
318 | out_be16(&tx_bd->cbd_sc, BD_SC_READY | BD_SC_INTRPT | BD_SC_WRAP | | |
319 | BD_SC_LAST); | |
320 | ||
321 | /* start transfer */ | |
b36ece83 | 322 | mpc8xxx_spi_write_reg(®_base->command, SPCOM_STR); |
4c1fba44 AV |
323 | } |
324 | ||
b36ece83 | 325 | static int fsl_spi_cpm_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
326 | struct spi_transfer *t, bool is_dma_mapped) |
327 | { | |
328 | struct device *dev = mspi->dev; | |
b36ece83 | 329 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
330 | |
331 | if (is_dma_mapped) { | |
332 | mspi->map_tx_dma = 0; | |
333 | mspi->map_rx_dma = 0; | |
334 | } else { | |
335 | mspi->map_tx_dma = 1; | |
336 | mspi->map_rx_dma = 1; | |
337 | } | |
338 | ||
339 | if (!t->tx_buf) { | |
340 | mspi->tx_dma = mspi->dma_dummy_tx; | |
341 | mspi->map_tx_dma = 0; | |
342 | } | |
343 | ||
344 | if (!t->rx_buf) { | |
345 | mspi->rx_dma = mspi->dma_dummy_rx; | |
346 | mspi->map_rx_dma = 0; | |
347 | } | |
348 | ||
349 | if (mspi->map_tx_dma) { | |
350 | void *nonconst_tx = (void *)mspi->tx; /* shut up gcc */ | |
351 | ||
352 | mspi->tx_dma = dma_map_single(dev, nonconst_tx, t->len, | |
353 | DMA_TO_DEVICE); | |
354 | if (dma_mapping_error(dev, mspi->tx_dma)) { | |
355 | dev_err(dev, "unable to map tx dma\n"); | |
356 | return -ENOMEM; | |
357 | } | |
f9218c2a | 358 | } else if (t->tx_buf) { |
4c1fba44 AV |
359 | mspi->tx_dma = t->tx_dma; |
360 | } | |
361 | ||
362 | if (mspi->map_rx_dma) { | |
363 | mspi->rx_dma = dma_map_single(dev, mspi->rx, t->len, | |
364 | DMA_FROM_DEVICE); | |
365 | if (dma_mapping_error(dev, mspi->rx_dma)) { | |
366 | dev_err(dev, "unable to map rx dma\n"); | |
367 | goto err_rx_dma; | |
368 | } | |
f9218c2a | 369 | } else if (t->rx_buf) { |
4c1fba44 AV |
370 | mspi->rx_dma = t->rx_dma; |
371 | } | |
372 | ||
373 | /* enable rx ints */ | |
b36ece83 | 374 | mpc8xxx_spi_write_reg(®_base->mask, SPIE_RXB); |
4c1fba44 AV |
375 | |
376 | mspi->xfer_in_progress = t; | |
377 | mspi->count = t->len; | |
378 | ||
379 | /* start CPM transfers */ | |
b36ece83 | 380 | fsl_spi_cpm_bufs_start(mspi); |
4c1fba44 AV |
381 | |
382 | return 0; | |
383 | ||
384 | err_rx_dma: | |
385 | if (mspi->map_tx_dma) | |
386 | dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE); | |
387 | return -ENOMEM; | |
388 | } | |
389 | ||
b36ece83 | 390 | static void fsl_spi_cpm_bufs_complete(struct mpc8xxx_spi *mspi) |
4c1fba44 AV |
391 | { |
392 | struct device *dev = mspi->dev; | |
393 | struct spi_transfer *t = mspi->xfer_in_progress; | |
394 | ||
395 | if (mspi->map_tx_dma) | |
396 | dma_unmap_single(dev, mspi->tx_dma, t->len, DMA_TO_DEVICE); | |
338ff298 | 397 | if (mspi->map_rx_dma) |
4c1fba44 AV |
398 | dma_unmap_single(dev, mspi->rx_dma, t->len, DMA_FROM_DEVICE); |
399 | mspi->xfer_in_progress = NULL; | |
400 | } | |
401 | ||
b36ece83 | 402 | static int fsl_spi_cpu_bufs(struct mpc8xxx_spi *mspi, |
4c1fba44 AV |
403 | struct spi_transfer *t, unsigned int len) |
404 | { | |
405 | u32 word; | |
b36ece83 | 406 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
407 | |
408 | mspi->count = len; | |
409 | ||
410 | /* enable rx ints */ | |
b36ece83 | 411 | mpc8xxx_spi_write_reg(®_base->mask, SPIM_NE); |
4c1fba44 AV |
412 | |
413 | /* transmit word */ | |
414 | word = mspi->get_tx(mspi); | |
b36ece83 | 415 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
4c1fba44 AV |
416 | |
417 | return 0; | |
418 | } | |
419 | ||
b36ece83 | 420 | static int fsl_spi_bufs(struct spi_device *spi, struct spi_transfer *t, |
4c1fba44 AV |
421 | bool is_dma_mapped) |
422 | { | |
423 | struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master); | |
b36ece83 | 424 | struct fsl_spi_reg *reg_base; |
4c1fba44 AV |
425 | unsigned int len = t->len; |
426 | u8 bits_per_word; | |
427 | int ret; | |
c9bfcb31 | 428 | |
b36ece83 | 429 | reg_base = mpc8xxx_spi->reg_base; |
c9bfcb31 JT |
430 | bits_per_word = spi->bits_per_word; |
431 | if (t->bits_per_word) | |
432 | bits_per_word = t->bits_per_word; | |
4c1fba44 | 433 | |
aa77d96b PK |
434 | if (bits_per_word > 8) { |
435 | /* invalid length? */ | |
436 | if (len & 1) | |
437 | return -EINVAL; | |
c9bfcb31 | 438 | len /= 2; |
aa77d96b PK |
439 | } |
440 | if (bits_per_word > 16) { | |
441 | /* invalid length? */ | |
442 | if (len & 1) | |
443 | return -EINVAL; | |
c9bfcb31 | 444 | len /= 2; |
aa77d96b | 445 | } |
aa77d96b | 446 | |
4c1fba44 AV |
447 | mpc8xxx_spi->tx = t->tx_buf; |
448 | mpc8xxx_spi->rx = t->rx_buf; | |
c9bfcb31 | 449 | |
4c1fba44 | 450 | INIT_COMPLETION(mpc8xxx_spi->done); |
c9bfcb31 | 451 | |
4c1fba44 | 452 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 453 | ret = fsl_spi_cpm_bufs(mpc8xxx_spi, t, is_dma_mapped); |
4c1fba44 | 454 | else |
b36ece83 | 455 | ret = fsl_spi_cpu_bufs(mpc8xxx_spi, t, len); |
4c1fba44 AV |
456 | if (ret) |
457 | return ret; | |
c9bfcb31 | 458 | |
575c5807 | 459 | wait_for_completion(&mpc8xxx_spi->done); |
c9bfcb31 JT |
460 | |
461 | /* disable rx ints */ | |
b36ece83 | 462 | mpc8xxx_spi_write_reg(®_base->mask, 0); |
c9bfcb31 | 463 | |
4c1fba44 | 464 | if (mpc8xxx_spi->flags & SPI_CPM_MODE) |
b36ece83 | 465 | fsl_spi_cpm_bufs_complete(mpc8xxx_spi); |
4c1fba44 | 466 | |
575c5807 | 467 | return mpc8xxx_spi->count; |
c9bfcb31 JT |
468 | } |
469 | ||
b36ece83 | 470 | static void fsl_spi_do_one_msg(struct spi_message *m) |
c9bfcb31 | 471 | { |
b9b9af11 AV |
472 | struct spi_device *spi = m->spi; |
473 | struct spi_transfer *t; | |
474 | unsigned int cs_change; | |
475 | const int nsecs = 50; | |
476 | int status; | |
477 | ||
478 | cs_change = 1; | |
479 | status = 0; | |
480 | list_for_each_entry(t, &m->transfers, transfer_list) { | |
481 | if (t->bits_per_word || t->speed_hz) { | |
482 | /* Don't allow changes if CS is active */ | |
483 | status = -EINVAL; | |
484 | ||
485 | if (cs_change) | |
b36ece83 | 486 | status = fsl_spi_setup_transfer(spi, t); |
b9b9af11 | 487 | if (status < 0) |
c9bfcb31 | 488 | break; |
b9b9af11 | 489 | } |
c9bfcb31 | 490 | |
b9b9af11 | 491 | if (cs_change) { |
b36ece83 | 492 | fsl_spi_chipselect(spi, BITBANG_CS_ACTIVE); |
b9b9af11 AV |
493 | ndelay(nsecs); |
494 | } | |
495 | cs_change = t->cs_change; | |
496 | if (t->len) | |
b36ece83 | 497 | status = fsl_spi_bufs(spi, t, m->is_dma_mapped); |
b9b9af11 AV |
498 | if (status) { |
499 | status = -EMSGSIZE; | |
500 | break; | |
c9bfcb31 | 501 | } |
b9b9af11 | 502 | m->actual_length += t->len; |
c9bfcb31 | 503 | |
b9b9af11 AV |
504 | if (t->delay_usecs) |
505 | udelay(t->delay_usecs); | |
c9bfcb31 | 506 | |
b9b9af11 | 507 | if (cs_change) { |
c9bfcb31 | 508 | ndelay(nsecs); |
b36ece83 | 509 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 | 510 | ndelay(nsecs); |
c9bfcb31 | 511 | } |
b9b9af11 AV |
512 | } |
513 | ||
514 | m->status = status; | |
515 | m->complete(m->context); | |
516 | ||
517 | if (status || !cs_change) { | |
518 | ndelay(nsecs); | |
b36ece83 | 519 | fsl_spi_chipselect(spi, BITBANG_CS_INACTIVE); |
b9b9af11 AV |
520 | } |
521 | ||
b36ece83 | 522 | fsl_spi_setup_transfer(spi, NULL); |
ccf06998 KG |
523 | } |
524 | ||
b36ece83 | 525 | static int fsl_spi_setup(struct spi_device *spi) |
ccf06998 | 526 | { |
575c5807 | 527 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 528 | struct fsl_spi_reg *reg_base; |
ccf06998 | 529 | int retval; |
c9bfcb31 | 530 | u32 hw_mode; |
575c5807 | 531 | struct spi_mpc8xxx_cs *cs = spi->controller_state; |
ccf06998 KG |
532 | |
533 | if (!spi->max_speed_hz) | |
534 | return -EINVAL; | |
535 | ||
c9bfcb31 JT |
536 | if (!cs) { |
537 | cs = kzalloc(sizeof *cs, GFP_KERNEL); | |
538 | if (!cs) | |
539 | return -ENOMEM; | |
540 | spi->controller_state = cs; | |
541 | } | |
575c5807 | 542 | mpc8xxx_spi = spi_master_get_devdata(spi->master); |
ccf06998 | 543 | |
b36ece83 MH |
544 | reg_base = mpc8xxx_spi->reg_base; |
545 | ||
88393161 | 546 | hw_mode = cs->hw_mode; /* Save original settings */ |
b36ece83 | 547 | cs->hw_mode = mpc8xxx_spi_read_reg(®_base->mode); |
c9bfcb31 JT |
548 | /* mask out bits we are going to set */ |
549 | cs->hw_mode &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH | |
550 | | SPMODE_REV | SPMODE_LOOP); | |
551 | ||
552 | if (spi->mode & SPI_CPHA) | |
553 | cs->hw_mode |= SPMODE_CP_BEGIN_EDGECLK; | |
554 | if (spi->mode & SPI_CPOL) | |
555 | cs->hw_mode |= SPMODE_CI_INACTIVEHIGH; | |
556 | if (!(spi->mode & SPI_LSB_FIRST)) | |
557 | cs->hw_mode |= SPMODE_REV; | |
558 | if (spi->mode & SPI_LOOP) | |
559 | cs->hw_mode |= SPMODE_LOOP; | |
560 | ||
b36ece83 | 561 | retval = fsl_spi_setup_transfer(spi, NULL); |
c9bfcb31 JT |
562 | if (retval < 0) { |
563 | cs->hw_mode = hw_mode; /* Restore settings */ | |
ccf06998 | 564 | return retval; |
c9bfcb31 | 565 | } |
ccf06998 KG |
566 | return 0; |
567 | } | |
568 | ||
b36ece83 | 569 | static void fsl_spi_cpm_irq(struct mpc8xxx_spi *mspi, u32 events) |
ccf06998 | 570 | { |
4c1fba44 | 571 | u16 len; |
b36ece83 | 572 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
ccf06998 | 573 | |
4c1fba44 AV |
574 | dev_dbg(mspi->dev, "%s: bd datlen %d, count %d\n", __func__, |
575 | in_be16(&mspi->rx_bd->cbd_datlen), mspi->count); | |
ccf06998 | 576 | |
4c1fba44 AV |
577 | len = in_be16(&mspi->rx_bd->cbd_datlen); |
578 | if (len > mspi->count) { | |
579 | WARN_ON(1); | |
580 | len = mspi->count; | |
581 | } | |
ccf06998 | 582 | |
4c1fba44 | 583 | /* Clear the events */ |
b36ece83 | 584 | mpc8xxx_spi_write_reg(®_base->event, events); |
ccf06998 | 585 | |
4c1fba44 AV |
586 | mspi->count -= len; |
587 | if (mspi->count) | |
b36ece83 | 588 | fsl_spi_cpm_bufs_start(mspi); |
4c1fba44 AV |
589 | else |
590 | complete(&mspi->done); | |
591 | } | |
592 | ||
b36ece83 | 593 | static void fsl_spi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events) |
4c1fba44 | 594 | { |
b36ece83 MH |
595 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
596 | ||
4c1fba44 AV |
597 | /* We need handle RX first */ |
598 | if (events & SPIE_NE) { | |
b36ece83 | 599 | u32 rx_data = mpc8xxx_spi_read_reg(®_base->receive); |
4c1fba44 AV |
600 | |
601 | if (mspi->rx) | |
602 | mspi->get_rx(rx_data, mspi); | |
ccf06998 KG |
603 | } |
604 | ||
4c1fba44 | 605 | if ((events & SPIE_NF) == 0) |
ccf06998 | 606 | /* spin until TX is done */ |
4c1fba44 | 607 | while (((events = |
b36ece83 | 608 | mpc8xxx_spi_read_reg(®_base->event)) & |
ccf06998 | 609 | SPIE_NF) == 0) |
9effb959 | 610 | cpu_relax(); |
ccf06998 | 611 | |
4c1fba44 | 612 | /* Clear the events */ |
b36ece83 | 613 | mpc8xxx_spi_write_reg(®_base->event, events); |
4c1fba44 AV |
614 | |
615 | mspi->count -= 1; | |
616 | if (mspi->count) { | |
617 | u32 word = mspi->get_tx(mspi); | |
618 | ||
b36ece83 | 619 | mpc8xxx_spi_write_reg(®_base->transmit, word); |
ccf06998 | 620 | } else { |
4c1fba44 | 621 | complete(&mspi->done); |
ccf06998 | 622 | } |
4c1fba44 | 623 | } |
ccf06998 | 624 | |
b36ece83 | 625 | static irqreturn_t fsl_spi_irq(s32 irq, void *context_data) |
4c1fba44 AV |
626 | { |
627 | struct mpc8xxx_spi *mspi = context_data; | |
628 | irqreturn_t ret = IRQ_NONE; | |
629 | u32 events; | |
b36ece83 | 630 | struct fsl_spi_reg *reg_base = mspi->reg_base; |
4c1fba44 AV |
631 | |
632 | /* Get interrupt events(tx/rx) */ | |
b36ece83 | 633 | events = mpc8xxx_spi_read_reg(®_base->event); |
4c1fba44 AV |
634 | if (events) |
635 | ret = IRQ_HANDLED; | |
636 | ||
637 | dev_dbg(mspi->dev, "%s: events %x\n", __func__, events); | |
638 | ||
639 | if (mspi->flags & SPI_CPM_MODE) | |
b36ece83 | 640 | fsl_spi_cpm_irq(mspi, events); |
4c1fba44 | 641 | else |
b36ece83 | 642 | fsl_spi_cpu_irq(mspi, events); |
ccf06998 KG |
643 | |
644 | return ret; | |
645 | } | |
4c1fba44 | 646 | |
b36ece83 | 647 | static void *fsl_spi_alloc_dummy_rx(void) |
c9bfcb31 | 648 | { |
b36ece83 | 649 | mutex_lock(&fsl_dummy_rx_lock); |
c9bfcb31 | 650 | |
b36ece83 MH |
651 | if (!fsl_dummy_rx) |
652 | fsl_dummy_rx = kmalloc(SPI_MRBLR, GFP_KERNEL); | |
653 | if (fsl_dummy_rx) | |
654 | fsl_dummy_rx_refcnt++; | |
c9bfcb31 | 655 | |
b36ece83 | 656 | mutex_unlock(&fsl_dummy_rx_lock); |
c9bfcb31 | 657 | |
b36ece83 | 658 | return fsl_dummy_rx; |
c9bfcb31 JT |
659 | } |
660 | ||
b36ece83 | 661 | static void fsl_spi_free_dummy_rx(void) |
c9bfcb31 | 662 | { |
b36ece83 | 663 | mutex_lock(&fsl_dummy_rx_lock); |
ccf06998 | 664 | |
b36ece83 | 665 | switch (fsl_dummy_rx_refcnt) { |
4c1fba44 AV |
666 | case 0: |
667 | WARN_ON(1); | |
668 | break; | |
669 | case 1: | |
b36ece83 MH |
670 | kfree(fsl_dummy_rx); |
671 | fsl_dummy_rx = NULL; | |
4c1fba44 AV |
672 | /* fall through */ |
673 | default: | |
b36ece83 | 674 | fsl_dummy_rx_refcnt--; |
4c1fba44 AV |
675 | break; |
676 | } | |
677 | ||
b36ece83 | 678 | mutex_unlock(&fsl_dummy_rx_lock); |
4c1fba44 AV |
679 | } |
680 | ||
b36ece83 | 681 | static unsigned long fsl_spi_cpm_get_pram(struct mpc8xxx_spi *mspi) |
4c1fba44 AV |
682 | { |
683 | struct device *dev = mspi->dev; | |
61c7a080 | 684 | struct device_node *np = dev->of_node; |
4c1fba44 AV |
685 | const u32 *iprop; |
686 | int size; | |
687 | unsigned long spi_base_ofs; | |
688 | unsigned long pram_ofs = -ENOMEM; | |
689 | ||
690 | /* Can't use of_address_to_resource(), QE muram isn't at 0. */ | |
691 | iprop = of_get_property(np, "reg", &size); | |
692 | ||
693 | /* QE with a fixed pram location? */ | |
694 | if (mspi->flags & SPI_QE && iprop && size == sizeof(*iprop) * 4) | |
695 | return cpm_muram_alloc_fixed(iprop[2], SPI_PRAM_SIZE); | |
696 | ||
697 | /* QE but with a dynamic pram location? */ | |
698 | if (mspi->flags & SPI_QE) { | |
699 | pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64); | |
700 | qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, mspi->subblock, | |
701 | QE_CR_PROTOCOL_UNSPECIFIED, pram_ofs); | |
702 | return pram_ofs; | |
703 | } | |
704 | ||
705 | /* CPM1 and CPM2 pram must be at a fixed addr. */ | |
706 | if (!iprop || size != sizeof(*iprop) * 4) | |
707 | return -ENOMEM; | |
708 | ||
709 | spi_base_ofs = cpm_muram_alloc_fixed(iprop[2], 2); | |
710 | if (IS_ERR_VALUE(spi_base_ofs)) | |
711 | return -ENOMEM; | |
712 | ||
713 | if (mspi->flags & SPI_CPM2) { | |
714 | pram_ofs = cpm_muram_alloc(SPI_PRAM_SIZE, 64); | |
715 | if (!IS_ERR_VALUE(pram_ofs)) { | |
716 | u16 __iomem *spi_base = cpm_muram_addr(spi_base_ofs); | |
717 | ||
718 | out_be16(spi_base, pram_ofs); | |
719 | } | |
720 | } else { | |
721 | struct spi_pram __iomem *pram = cpm_muram_addr(spi_base_ofs); | |
722 | u16 rpbase = in_be16(&pram->rpbase); | |
723 | ||
724 | /* Microcode relocation patch applied? */ | |
725 | if (rpbase) | |
726 | pram_ofs = rpbase; | |
727 | else | |
728 | return spi_base_ofs; | |
729 | } | |
730 | ||
731 | cpm_muram_free(spi_base_ofs); | |
732 | return pram_ofs; | |
733 | } | |
734 | ||
b36ece83 | 735 | static int fsl_spi_cpm_init(struct mpc8xxx_spi *mspi) |
4c1fba44 AV |
736 | { |
737 | struct device *dev = mspi->dev; | |
61c7a080 | 738 | struct device_node *np = dev->of_node; |
4c1fba44 AV |
739 | const u32 *iprop; |
740 | int size; | |
741 | unsigned long pram_ofs; | |
742 | unsigned long bds_ofs; | |
743 | ||
744 | if (!(mspi->flags & SPI_CPM_MODE)) | |
745 | return 0; | |
746 | ||
b36ece83 | 747 | if (!fsl_spi_alloc_dummy_rx()) |
4c1fba44 AV |
748 | return -ENOMEM; |
749 | ||
750 | if (mspi->flags & SPI_QE) { | |
751 | iprop = of_get_property(np, "cell-index", &size); | |
752 | if (iprop && size == sizeof(*iprop)) | |
753 | mspi->subblock = *iprop; | |
754 | ||
755 | switch (mspi->subblock) { | |
756 | default: | |
757 | dev_warn(dev, "cell-index unspecified, assuming SPI1"); | |
758 | /* fall through */ | |
759 | case 0: | |
760 | mspi->subblock = QE_CR_SUBBLOCK_SPI1; | |
761 | break; | |
762 | case 1: | |
763 | mspi->subblock = QE_CR_SUBBLOCK_SPI2; | |
764 | break; | |
765 | } | |
766 | } | |
767 | ||
b36ece83 | 768 | pram_ofs = fsl_spi_cpm_get_pram(mspi); |
4c1fba44 AV |
769 | if (IS_ERR_VALUE(pram_ofs)) { |
770 | dev_err(dev, "can't allocate spi parameter ram\n"); | |
771 | goto err_pram; | |
772 | } | |
773 | ||
774 | bds_ofs = cpm_muram_alloc(sizeof(*mspi->tx_bd) + | |
775 | sizeof(*mspi->rx_bd), 8); | |
776 | if (IS_ERR_VALUE(bds_ofs)) { | |
777 | dev_err(dev, "can't allocate bds\n"); | |
778 | goto err_bds; | |
779 | } | |
780 | ||
781 | mspi->dma_dummy_tx = dma_map_single(dev, empty_zero_page, PAGE_SIZE, | |
782 | DMA_TO_DEVICE); | |
783 | if (dma_mapping_error(dev, mspi->dma_dummy_tx)) { | |
784 | dev_err(dev, "unable to map dummy tx buffer\n"); | |
785 | goto err_dummy_tx; | |
786 | } | |
787 | ||
b36ece83 | 788 | mspi->dma_dummy_rx = dma_map_single(dev, fsl_dummy_rx, SPI_MRBLR, |
4c1fba44 AV |
789 | DMA_FROM_DEVICE); |
790 | if (dma_mapping_error(dev, mspi->dma_dummy_rx)) { | |
791 | dev_err(dev, "unable to map dummy rx buffer\n"); | |
792 | goto err_dummy_rx; | |
793 | } | |
794 | ||
795 | mspi->pram = cpm_muram_addr(pram_ofs); | |
796 | ||
797 | mspi->tx_bd = cpm_muram_addr(bds_ofs); | |
798 | mspi->rx_bd = cpm_muram_addr(bds_ofs + sizeof(*mspi->tx_bd)); | |
799 | ||
800 | /* Initialize parameter ram. */ | |
801 | out_be16(&mspi->pram->tbase, cpm_muram_offset(mspi->tx_bd)); | |
802 | out_be16(&mspi->pram->rbase, cpm_muram_offset(mspi->rx_bd)); | |
803 | out_8(&mspi->pram->tfcr, CPMFCR_EB | CPMFCR_GBL); | |
804 | out_8(&mspi->pram->rfcr, CPMFCR_EB | CPMFCR_GBL); | |
805 | out_be16(&mspi->pram->mrblr, SPI_MRBLR); | |
806 | out_be32(&mspi->pram->rstate, 0); | |
807 | out_be32(&mspi->pram->rdp, 0); | |
808 | out_be16(&mspi->pram->rbptr, 0); | |
809 | out_be16(&mspi->pram->rbc, 0); | |
810 | out_be32(&mspi->pram->rxtmp, 0); | |
811 | out_be32(&mspi->pram->tstate, 0); | |
812 | out_be32(&mspi->pram->tdp, 0); | |
813 | out_be16(&mspi->pram->tbptr, 0); | |
814 | out_be16(&mspi->pram->tbc, 0); | |
815 | out_be32(&mspi->pram->txtmp, 0); | |
816 | ||
817 | return 0; | |
818 | ||
819 | err_dummy_rx: | |
820 | dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE); | |
821 | err_dummy_tx: | |
822 | cpm_muram_free(bds_ofs); | |
823 | err_bds: | |
824 | cpm_muram_free(pram_ofs); | |
825 | err_pram: | |
b36ece83 | 826 | fsl_spi_free_dummy_rx(); |
4c1fba44 AV |
827 | return -ENOMEM; |
828 | } | |
829 | ||
b36ece83 | 830 | static void fsl_spi_cpm_free(struct mpc8xxx_spi *mspi) |
4c1fba44 AV |
831 | { |
832 | struct device *dev = mspi->dev; | |
833 | ||
834 | dma_unmap_single(dev, mspi->dma_dummy_rx, SPI_MRBLR, DMA_FROM_DEVICE); | |
835 | dma_unmap_single(dev, mspi->dma_dummy_tx, PAGE_SIZE, DMA_TO_DEVICE); | |
836 | cpm_muram_free(cpm_muram_offset(mspi->tx_bd)); | |
837 | cpm_muram_free(cpm_muram_offset(mspi->pram)); | |
b36ece83 | 838 | fsl_spi_free_dummy_rx(); |
4c1fba44 AV |
839 | } |
840 | ||
b36ece83 | 841 | static void fsl_spi_remove(struct mpc8xxx_spi *mspi) |
87ec0e98 | 842 | { |
b36ece83 MH |
843 | iounmap(mspi->reg_base); |
844 | fsl_spi_cpm_free(mspi); | |
87ec0e98 AV |
845 | } |
846 | ||
b36ece83 MH |
847 | static struct spi_master * __devinit fsl_spi_probe(struct device *dev, |
848 | struct resource *mem, unsigned int irq) | |
ccf06998 | 849 | { |
35b4b3c0 | 850 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
ccf06998 | 851 | struct spi_master *master; |
575c5807 | 852 | struct mpc8xxx_spi *mpc8xxx_spi; |
b36ece83 | 853 | struct fsl_spi_reg *reg_base; |
ccf06998 KG |
854 | u32 regval; |
855 | int ret = 0; | |
856 | ||
575c5807 | 857 | master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi)); |
ccf06998 KG |
858 | if (master == NULL) { |
859 | ret = -ENOMEM; | |
860 | goto err; | |
861 | } | |
862 | ||
35b4b3c0 | 863 | dev_set_drvdata(dev, master); |
ccf06998 | 864 | |
b36ece83 MH |
865 | ret = mpc8xxx_spi_probe(dev, mem, irq); |
866 | if (ret) | |
867 | goto err_probe; | |
e7db06b5 | 868 | |
b36ece83 | 869 | master->setup = fsl_spi_setup; |
575c5807 AV |
870 | |
871 | mpc8xxx_spi = spi_master_get_devdata(master); | |
b36ece83 MH |
872 | mpc8xxx_spi->spi_do_one_msg = fsl_spi_do_one_msg; |
873 | mpc8xxx_spi->spi_remove = fsl_spi_remove; | |
874 | ||
575c5807 | 875 | |
b36ece83 | 876 | ret = fsl_spi_cpm_init(mpc8xxx_spi); |
4c1fba44 AV |
877 | if (ret) |
878 | goto err_cpm_init; | |
879 | ||
87ec0e98 | 880 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) { |
575c5807 AV |
881 | mpc8xxx_spi->rx_shift = 16; |
882 | mpc8xxx_spi->tx_shift = 24; | |
f29ba280 JT |
883 | } |
884 | ||
b36ece83 MH |
885 | mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem)); |
886 | if (mpc8xxx_spi->reg_base == NULL) { | |
ccf06998 | 887 | ret = -ENOMEM; |
4c1fba44 | 888 | goto err_ioremap; |
ccf06998 KG |
889 | } |
890 | ||
ccf06998 | 891 | /* Register for SPI Interrupt */ |
b36ece83 MH |
892 | ret = request_irq(mpc8xxx_spi->irq, fsl_spi_irq, |
893 | 0, "fsl_spi", mpc8xxx_spi); | |
ccf06998 KG |
894 | |
895 | if (ret != 0) | |
b36ece83 | 896 | goto free_irq; |
ccf06998 | 897 | |
b36ece83 | 898 | reg_base = mpc8xxx_spi->reg_base; |
ccf06998 KG |
899 | |
900 | /* SPI controller initializations */ | |
b36ece83 MH |
901 | mpc8xxx_spi_write_reg(®_base->mode, 0); |
902 | mpc8xxx_spi_write_reg(®_base->mask, 0); | |
903 | mpc8xxx_spi_write_reg(®_base->command, 0); | |
904 | mpc8xxx_spi_write_reg(®_base->event, 0xffffffff); | |
ccf06998 KG |
905 | |
906 | /* Enable SPI interface */ | |
907 | regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE; | |
87ec0e98 | 908 | if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) |
f29ba280 JT |
909 | regval |= SPMODE_OP; |
910 | ||
b36ece83 | 911 | mpc8xxx_spi_write_reg(®_base->mode, regval); |
c9bfcb31 JT |
912 | |
913 | ret = spi_register_master(master); | |
914 | if (ret < 0) | |
915 | goto unreg_master; | |
ccf06998 | 916 | |
b36ece83 | 917 | dev_info(dev, "at 0x%p (irq = %d), %s mode\n", reg_base, |
87ec0e98 | 918 | mpc8xxx_spi->irq, mpc8xxx_spi_strmode(mpc8xxx_spi->flags)); |
ccf06998 | 919 | |
35b4b3c0 | 920 | return master; |
ccf06998 | 921 | |
c9bfcb31 | 922 | unreg_master: |
575c5807 | 923 | free_irq(mpc8xxx_spi->irq, mpc8xxx_spi); |
b36ece83 MH |
924 | free_irq: |
925 | iounmap(mpc8xxx_spi->reg_base); | |
4c1fba44 | 926 | err_ioremap: |
b36ece83 | 927 | fsl_spi_cpm_free(mpc8xxx_spi); |
4c1fba44 | 928 | err_cpm_init: |
b36ece83 | 929 | err_probe: |
ccf06998 | 930 | spi_master_put(master); |
ccf06998 | 931 | err: |
35b4b3c0 | 932 | return ERR_PTR(ret); |
ccf06998 KG |
933 | } |
934 | ||
b36ece83 | 935 | static void fsl_spi_cs_control(struct spi_device *spi, bool on) |
35b4b3c0 AV |
936 | { |
937 | struct device *dev = spi->dev.parent; | |
575c5807 | 938 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(dev->platform_data); |
35b4b3c0 AV |
939 | u16 cs = spi->chip_select; |
940 | int gpio = pinfo->gpios[cs]; | |
941 | bool alow = pinfo->alow_flags[cs]; | |
942 | ||
943 | gpio_set_value(gpio, on ^ alow); | |
944 | } | |
945 | ||
b36ece83 | 946 | static int of_fsl_spi_get_chipselects(struct device *dev) |
35b4b3c0 | 947 | { |
61c7a080 | 948 | struct device_node *np = dev->of_node; |
35b4b3c0 | 949 | struct fsl_spi_platform_data *pdata = dev->platform_data; |
575c5807 | 950 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
951 | unsigned int ngpios; |
952 | int i = 0; | |
953 | int ret; | |
954 | ||
955 | ngpios = of_gpio_count(np); | |
956 | if (!ngpios) { | |
957 | /* | |
958 | * SPI w/o chip-select line. One SPI device is still permitted | |
959 | * though. | |
960 | */ | |
961 | pdata->max_chipselect = 1; | |
962 | return 0; | |
963 | } | |
964 | ||
02141546 | 965 | pinfo->gpios = kmalloc(ngpios * sizeof(*pinfo->gpios), GFP_KERNEL); |
35b4b3c0 AV |
966 | if (!pinfo->gpios) |
967 | return -ENOMEM; | |
02141546 | 968 | memset(pinfo->gpios, -1, ngpios * sizeof(*pinfo->gpios)); |
35b4b3c0 | 969 | |
02141546 | 970 | pinfo->alow_flags = kzalloc(ngpios * sizeof(*pinfo->alow_flags), |
35b4b3c0 AV |
971 | GFP_KERNEL); |
972 | if (!pinfo->alow_flags) { | |
973 | ret = -ENOMEM; | |
974 | goto err_alloc_flags; | |
975 | } | |
976 | ||
977 | for (; i < ngpios; i++) { | |
978 | int gpio; | |
979 | enum of_gpio_flags flags; | |
980 | ||
981 | gpio = of_get_gpio_flags(np, i, &flags); | |
982 | if (!gpio_is_valid(gpio)) { | |
983 | dev_err(dev, "invalid gpio #%d: %d\n", i, gpio); | |
783058fd | 984 | ret = gpio; |
35b4b3c0 AV |
985 | goto err_loop; |
986 | } | |
987 | ||
988 | ret = gpio_request(gpio, dev_name(dev)); | |
989 | if (ret) { | |
990 | dev_err(dev, "can't request gpio #%d: %d\n", i, ret); | |
991 | goto err_loop; | |
992 | } | |
993 | ||
994 | pinfo->gpios[i] = gpio; | |
995 | pinfo->alow_flags[i] = flags & OF_GPIO_ACTIVE_LOW; | |
996 | ||
997 | ret = gpio_direction_output(pinfo->gpios[i], | |
998 | pinfo->alow_flags[i]); | |
999 | if (ret) { | |
1000 | dev_err(dev, "can't set output direction for gpio " | |
1001 | "#%d: %d\n", i, ret); | |
1002 | goto err_loop; | |
1003 | } | |
1004 | } | |
1005 | ||
1006 | pdata->max_chipselect = ngpios; | |
b36ece83 | 1007 | pdata->cs_control = fsl_spi_cs_control; |
35b4b3c0 AV |
1008 | |
1009 | return 0; | |
1010 | ||
1011 | err_loop: | |
1012 | while (i >= 0) { | |
1013 | if (gpio_is_valid(pinfo->gpios[i])) | |
1014 | gpio_free(pinfo->gpios[i]); | |
1015 | i--; | |
1016 | } | |
1017 | ||
1018 | kfree(pinfo->alow_flags); | |
1019 | pinfo->alow_flags = NULL; | |
1020 | err_alloc_flags: | |
1021 | kfree(pinfo->gpios); | |
1022 | pinfo->gpios = NULL; | |
1023 | return ret; | |
1024 | } | |
1025 | ||
b36ece83 | 1026 | static int of_fsl_spi_free_chipselects(struct device *dev) |
35b4b3c0 AV |
1027 | { |
1028 | struct fsl_spi_platform_data *pdata = dev->platform_data; | |
575c5807 | 1029 | struct mpc8xxx_spi_probe_info *pinfo = to_of_pinfo(pdata); |
35b4b3c0 AV |
1030 | int i; |
1031 | ||
1032 | if (!pinfo->gpios) | |
1033 | return 0; | |
1034 | ||
1035 | for (i = 0; i < pdata->max_chipselect; i++) { | |
1036 | if (gpio_is_valid(pinfo->gpios[i])) | |
1037 | gpio_free(pinfo->gpios[i]); | |
1038 | } | |
1039 | ||
1040 | kfree(pinfo->gpios); | |
1041 | kfree(pinfo->alow_flags); | |
1042 | return 0; | |
1043 | } | |
1044 | ||
b36ece83 MH |
1045 | static int __devinit of_fsl_spi_probe(struct platform_device *ofdev, |
1046 | const struct of_device_id *ofid) | |
35b4b3c0 AV |
1047 | { |
1048 | struct device *dev = &ofdev->dev; | |
61c7a080 | 1049 | struct device_node *np = ofdev->dev.of_node; |
35b4b3c0 AV |
1050 | struct spi_master *master; |
1051 | struct resource mem; | |
1052 | struct resource irq; | |
35b4b3c0 AV |
1053 | int ret = -ENOMEM; |
1054 | ||
b36ece83 MH |
1055 | ret = of_mpc8xxx_spi_probe(ofdev, ofid); |
1056 | if (ret) | |
1057 | return ret; | |
35b4b3c0 | 1058 | |
b36ece83 | 1059 | ret = of_fsl_spi_get_chipselects(dev); |
35b4b3c0 AV |
1060 | if (ret) |
1061 | goto err; | |
1062 | ||
1063 | ret = of_address_to_resource(np, 0, &mem); | |
1064 | if (ret) | |
1065 | goto err; | |
1066 | ||
1067 | ret = of_irq_to_resource(np, 0, &irq); | |
1068 | if (!ret) { | |
1069 | ret = -EINVAL; | |
1070 | goto err; | |
1071 | } | |
1072 | ||
b36ece83 | 1073 | master = fsl_spi_probe(dev, &mem, irq.start); |
35b4b3c0 AV |
1074 | if (IS_ERR(master)) { |
1075 | ret = PTR_ERR(master); | |
1076 | goto err; | |
1077 | } | |
1078 | ||
35b4b3c0 AV |
1079 | return 0; |
1080 | ||
1081 | err: | |
b36ece83 | 1082 | of_fsl_spi_free_chipselects(dev); |
35b4b3c0 AV |
1083 | return ret; |
1084 | } | |
1085 | ||
b36ece83 | 1086 | static int __devexit of_fsl_spi_remove(struct platform_device *ofdev) |
35b4b3c0 AV |
1087 | { |
1088 | int ret; | |
1089 | ||
575c5807 | 1090 | ret = mpc8xxx_spi_remove(&ofdev->dev); |
35b4b3c0 AV |
1091 | if (ret) |
1092 | return ret; | |
b36ece83 | 1093 | of_fsl_spi_free_chipselects(&ofdev->dev); |
35b4b3c0 AV |
1094 | return 0; |
1095 | } | |
1096 | ||
b36ece83 | 1097 | static const struct of_device_id of_fsl_spi_match[] = { |
35b4b3c0 | 1098 | { .compatible = "fsl,spi" }, |
b36ece83 | 1099 | {} |
35b4b3c0 | 1100 | }; |
b36ece83 | 1101 | MODULE_DEVICE_TABLE(of, of_fsl_spi_match); |
35b4b3c0 | 1102 | |
b36ece83 | 1103 | static struct of_platform_driver of_fsl_spi_driver = { |
4018294b | 1104 | .driver = { |
b36ece83 | 1105 | .name = "fsl_spi", |
4018294b | 1106 | .owner = THIS_MODULE, |
b36ece83 | 1107 | .of_match_table = of_fsl_spi_match, |
4018294b | 1108 | }, |
b36ece83 MH |
1109 | .probe = of_fsl_spi_probe, |
1110 | .remove = __devexit_p(of_fsl_spi_remove), | |
35b4b3c0 AV |
1111 | }; |
1112 | ||
1113 | #ifdef CONFIG_MPC832x_RDB | |
1114 | /* | |
b36ece83 | 1115 | * XXX XXX XXX |
35b4b3c0 AV |
1116 | * This is "legacy" platform driver, was used by the MPC8323E-RDB boards |
1117 | * only. The driver should go away soon, since newer MPC8323E-RDB's device | |
1118 | * tree can work with OpenFirmware driver. But for now we support old trees | |
1119 | * as well. | |
1120 | */ | |
575c5807 | 1121 | static int __devinit plat_mpc8xxx_spi_probe(struct platform_device *pdev) |
35b4b3c0 AV |
1122 | { |
1123 | struct resource *mem; | |
e9a172f0 | 1124 | int irq; |
35b4b3c0 AV |
1125 | struct spi_master *master; |
1126 | ||
1127 | if (!pdev->dev.platform_data) | |
1128 | return -EINVAL; | |
1129 | ||
1130 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1131 | if (!mem) | |
1132 | return -EINVAL; | |
1133 | ||
1134 | irq = platform_get_irq(pdev, 0); | |
e9a172f0 | 1135 | if (irq <= 0) |
35b4b3c0 AV |
1136 | return -EINVAL; |
1137 | ||
b36ece83 | 1138 | master = fsl_spi_probe(&pdev->dev, mem, irq); |
35b4b3c0 AV |
1139 | if (IS_ERR(master)) |
1140 | return PTR_ERR(master); | |
1141 | return 0; | |
1142 | } | |
1143 | ||
575c5807 | 1144 | static int __devexit plat_mpc8xxx_spi_remove(struct platform_device *pdev) |
35b4b3c0 | 1145 | { |
575c5807 | 1146 | return mpc8xxx_spi_remove(&pdev->dev); |
35b4b3c0 AV |
1147 | } |
1148 | ||
575c5807 AV |
1149 | MODULE_ALIAS("platform:mpc8xxx_spi"); |
1150 | static struct platform_driver mpc8xxx_spi_driver = { | |
1151 | .probe = plat_mpc8xxx_spi_probe, | |
b3a08945 | 1152 | .remove = __devexit_p(plat_mpc8xxx_spi_remove), |
ccf06998 | 1153 | .driver = { |
575c5807 | 1154 | .name = "mpc8xxx_spi", |
7e38c3c4 | 1155 | .owner = THIS_MODULE, |
ccf06998 KG |
1156 | }, |
1157 | }; | |
1158 | ||
35b4b3c0 AV |
1159 | static bool legacy_driver_failed; |
1160 | ||
1161 | static void __init legacy_driver_register(void) | |
1162 | { | |
575c5807 | 1163 | legacy_driver_failed = platform_driver_register(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
1164 | } |
1165 | ||
1166 | static void __exit legacy_driver_unregister(void) | |
1167 | { | |
1168 | if (legacy_driver_failed) | |
1169 | return; | |
575c5807 | 1170 | platform_driver_unregister(&mpc8xxx_spi_driver); |
35b4b3c0 AV |
1171 | } |
1172 | #else | |
1173 | static void __init legacy_driver_register(void) {} | |
1174 | static void __exit legacy_driver_unregister(void) {} | |
1175 | #endif /* CONFIG_MPC832x_RDB */ | |
1176 | ||
b36ece83 | 1177 | static int __init fsl_spi_init(void) |
ccf06998 | 1178 | { |
35b4b3c0 | 1179 | legacy_driver_register(); |
b36ece83 | 1180 | return of_register_platform_driver(&of_fsl_spi_driver); |
ccf06998 | 1181 | } |
b36ece83 | 1182 | module_init(fsl_spi_init); |
ccf06998 | 1183 | |
b36ece83 | 1184 | static void __exit fsl_spi_exit(void) |
ccf06998 | 1185 | { |
b36ece83 | 1186 | of_unregister_platform_driver(&of_fsl_spi_driver); |
35b4b3c0 | 1187 | legacy_driver_unregister(); |
ccf06998 | 1188 | } |
b36ece83 | 1189 | module_exit(fsl_spi_exit); |
ccf06998 KG |
1190 | |
1191 | MODULE_AUTHOR("Kumar Gala"); | |
b36ece83 | 1192 | MODULE_DESCRIPTION("Simple Freescale SPI Driver"); |
ccf06998 | 1193 | MODULE_LICENSE("GPL"); |