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spi/dw_spi: change to EXPORT_SYMBOL_GPL for exported APIs
[deliverable/linux.git] / drivers / spi / spi_imx.c
CommitLineData
b5f3294f
SH		 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2008 Juergen Beisert
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the
16 * Free Software Foundation
17 * 51 Franklin Street, Fifth Floor
18 * Boston, MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/completion.h>
23#include <linux/delay.h>
24#include <linux/err.h>
25#include <linux/gpio.h>
26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/irq.h>
30#include <linux/kernel.h>
31#include <linux/module.h>
32#include <linux/platform_device.h>
5a0e3ad6 33#include <linux/slab.h>
b5f3294f
SH		 34#include <linux/spi/spi.h>
35#include <linux/spi/spi_bitbang.h>
36#include <linux/types.h>
37
38#include <mach/spi.h>
39
40#define DRIVER_NAME "spi_imx"
41
42#define MXC_CSPIRXDATA 0x00
43#define MXC_CSPITXDATA 0x04
44#define MXC_CSPICTRL 0x08
45#define MXC_CSPIINT 0x0c
46#define MXC_RESET 0x1c
47
ce1807b2
DM		 48#define MX3_CSPISTAT 0x14
49#define MX3_CSPISTAT_RR (1 << 3)
50
b5f3294f
SH		 51/* generic defines to abstract from the different register layouts */
52#define MXC_INT_RR (1 << 0) /* Receive data ready interrupt */
53#define MXC_INT_TE (1 << 1) /* Transmit FIFO empty interrupt */
54
6cdeb002 55struct spi_imx_config {
b5f3294f
SH		 56 unsigned int speed_hz;
57 unsigned int bpw;
58 unsigned int mode;
3b2aa89e 59 u8 cs;
b5f3294f
SH		 60};
61
f4ba6315
UKK		 62enum spi_imx_devtype {
63 SPI_IMX_VER_IMX1,
64 SPI_IMX_VER_0_0,
65 SPI_IMX_VER_0_4,
66 SPI_IMX_VER_0_5,
67 SPI_IMX_VER_0_7,
0b599603 68 SPI_IMX_VER_2_3,
f4ba6315
UKK		 69};
70
71struct spi_imx_data;
72
73struct spi_imx_devtype_data {
74 void (*intctrl)(struct spi_imx_data *, int);
75 int (*config)(struct spi_imx_data *, struct spi_imx_config *);
76 void (*trigger)(struct spi_imx_data *);
77 int (*rx_available)(struct spi_imx_data *);
1723e66b 78 void (*reset)(struct spi_imx_data *);
6ff554e0 79 unsigned int fifosize;
f4ba6315
UKK		 80};
81
6cdeb002 82struct spi_imx_data {
b5f3294f
SH		 83 struct spi_bitbang bitbang;
84
85 struct completion xfer_done;
86 void *base;
87 int irq;
88 struct clk *clk;
89 unsigned long spi_clk;
90 int *chipselect;
91
92 unsigned int count;
6cdeb002
UKK		 93 void (*tx)(struct spi_imx_data *);
94 void (*rx)(struct spi_imx_data *);
b5f3294f
SH		 95 void *rx_buf;
96 const void *tx_buf;
97 unsigned int txfifo; /* number of words pushed in tx FIFO */
98
f4ba6315 99 struct spi_imx_devtype_data devtype_data;
b5f3294f
SH		 100};
101
102#define MXC_SPI_BUF_RX(type) \
6cdeb002 103static void spi_imx_buf_rx_##type(struct spi_imx_data *spi_imx) \
b5f3294f 104{ \
6cdeb002 105 unsigned int val = readl(spi_imx->base + MXC_CSPIRXDATA); \
b5f3294f 106 \
6cdeb002
UKK		 107 if (spi_imx->rx_buf) { \
108 *(type *)spi_imx->rx_buf = val; \
109 spi_imx->rx_buf += sizeof(type); \
b5f3294f
SH		 110 } \
111}
112
113#define MXC_SPI_BUF_TX(type) \
6cdeb002 114static void spi_imx_buf_tx_##type(struct spi_imx_data *spi_imx) \
b5f3294f
SH		 115{ \
116 type val = 0; \
117 \
6cdeb002
UKK		 118 if (spi_imx->tx_buf) { \
119 val = *(type *)spi_imx->tx_buf; \
120 spi_imx->tx_buf += sizeof(type); \
b5f3294f
SH		 121 } \
122 \
6cdeb002 123 spi_imx->count -= sizeof(type); \
b5f3294f 124 \
6cdeb002 125 writel(val, spi_imx->base + MXC_CSPITXDATA); \
b5f3294f
SH		 126}
127
128MXC_SPI_BUF_RX(u8)
129MXC_SPI_BUF_TX(u8)
130MXC_SPI_BUF_RX(u16)
131MXC_SPI_BUF_TX(u16)
132MXC_SPI_BUF_RX(u32)
133MXC_SPI_BUF_TX(u32)
134
135/* First entry is reserved, second entry is valid only if SDHC_SPIEN is set
136 * (which is currently not the case in this driver)
137 */
138static int mxc_clkdivs[] = {0, 3, 4, 6, 8, 12, 16, 24, 32, 48, 64, 96, 128, 192,
139 256, 384, 512, 768, 1024};
140
141/* MX21, MX27 */
6cdeb002 142static unsigned int spi_imx_clkdiv_1(unsigned int fin,
b5f3294f
SH		 143 unsigned int fspi)
144{
145 int i, max;
146
147 if (cpu_is_mx21())
148 max = 18;
149 else
150 max = 16;
151
152 for (i = 2; i < max; i++)
153 if (fspi * mxc_clkdivs[i] >= fin)
154 return i;
155
156 return max;
157}
158
0b599603 159/* MX1, MX31, MX35, MX51 CSPI */
6cdeb002 160static unsigned int spi_imx_clkdiv_2(unsigned int fin,
b5f3294f
SH		 161 unsigned int fspi)
162{
163 int i, div = 4;
164
165 for (i = 0; i < 7; i++) {
166 if (fspi * div >= fin)
167 return i;
168 div <<= 1;
169 }
170
171 return 7;
172}
173
0b599603
UKK		 174#define SPI_IMX2_3_CTRL 0x08
175#define SPI_IMX2_3_CTRL_ENABLE (1 << 0)
176#define SPI_IMX2_3_CTRL_XCH (1 << 2)
177#define SPI_IMX2_3_CTRL_MODE(cs) (1 << ((cs) + 4))
178#define SPI_IMX2_3_CTRL_POSTDIV_OFFSET 8
179#define SPI_IMX2_3_CTRL_PREDIV_OFFSET 12
180#define SPI_IMX2_3_CTRL_CS(cs) ((cs) << 18)
181#define SPI_IMX2_3_CTRL_BL_OFFSET 20
182
183#define SPI_IMX2_3_CONFIG 0x0c
184#define SPI_IMX2_3_CONFIG_SCLKPHA(cs) (1 << ((cs) + 0))
185#define SPI_IMX2_3_CONFIG_SCLKPOL(cs) (1 << ((cs) + 4))
186#define SPI_IMX2_3_CONFIG_SBBCTRL(cs) (1 << ((cs) + 8))
187#define SPI_IMX2_3_CONFIG_SSBPOL(cs) (1 << ((cs) + 12))
188
189#define SPI_IMX2_3_INT 0x10
190#define SPI_IMX2_3_INT_TEEN (1 << 0)
191#define SPI_IMX2_3_INT_RREN (1 << 3)
192
193#define SPI_IMX2_3_STAT 0x18
194#define SPI_IMX2_3_STAT_RR (1 << 3)
195
196/* MX51 eCSPI */
197static unsigned int spi_imx2_3_clkdiv(unsigned int fin, unsigned int fspi)
198{
199 /*
200 * there are two 4-bit dividers, the pre-divider divides by
201 * $pre, the post-divider by 2^$post
202 */
203 unsigned int pre, post;
204
205 if (unlikely(fspi > fin))
206 return 0;
207
208 post = fls(fin) - fls(fspi);
209 if (fin > fspi << post)
210 post++;
211
212 /* now we have: (fin <= fspi << post) with post being minimal */
213
214 post = max(4U, post) - 4;
215 if (unlikely(post > 0xf)) {
216 pr_err("%s: cannot set clock freq: %u (base freq: %u)\n",
217 __func__, fspi, fin);
218 return 0xff;
219 }
220
221 pre = DIV_ROUND_UP(fin, fspi << post) - 1;
222
223 pr_debug("%s: fin: %u, fspi: %u, post: %u, pre: %u\n",
224 __func__, fin, fspi, post, pre);
225 return (pre << SPI_IMX2_3_CTRL_PREDIV_OFFSET) |
226 (post << SPI_IMX2_3_CTRL_POSTDIV_OFFSET);
227}
228
229static void __maybe_unused spi_imx2_3_intctrl(struct spi_imx_data *spi_imx, int enable)
230{
231 unsigned val = 0;
232
233 if (enable & MXC_INT_TE)
234 val |= SPI_IMX2_3_INT_TEEN;
235
236 if (enable & MXC_INT_RR)
237 val |= SPI_IMX2_3_INT_RREN;
238
239 writel(val, spi_imx->base + SPI_IMX2_3_INT);
240}
241
242static void __maybe_unused spi_imx2_3_trigger(struct spi_imx_data *spi_imx)
243{
244 u32 reg;
245
246 reg = readl(spi_imx->base + SPI_IMX2_3_CTRL);
247 reg |= SPI_IMX2_3_CTRL_XCH;
248 writel(reg, spi_imx->base + SPI_IMX2_3_CTRL);
249}
250
251static int __maybe_unused spi_imx2_3_config(struct spi_imx_data *spi_imx,
252 struct spi_imx_config *config)
253{
254 u32 ctrl = SPI_IMX2_3_CTRL_ENABLE, cfg = 0;
255
256 /* set master mode */
257 ctrl |= SPI_IMX2_3_CTRL_MODE(config->cs);
258
259 /* set clock speed */
260 ctrl |= spi_imx2_3_clkdiv(spi_imx->spi_clk, config->speed_hz);
261
262 /* set chip select to use */
263 ctrl |= SPI_IMX2_3_CTRL_CS(config->cs);
264
265 ctrl |= (config->bpw - 1) << SPI_IMX2_3_CTRL_BL_OFFSET;
266
267 cfg |= SPI_IMX2_3_CONFIG_SBBCTRL(config->cs);
268
269 if (config->mode & SPI_CPHA)
270 cfg |= SPI_IMX2_3_CONFIG_SCLKPHA(config->cs);
271
272 if (config->mode & SPI_CPOL)
273 cfg |= SPI_IMX2_3_CONFIG_SCLKPOL(config->cs);
274
275 if (config->mode & SPI_CS_HIGH)
276 cfg |= SPI_IMX2_3_CONFIG_SSBPOL(config->cs);
277
278 writel(ctrl, spi_imx->base + SPI_IMX2_3_CTRL);
279 writel(cfg, spi_imx->base + SPI_IMX2_3_CONFIG);
280
281 return 0;
282}
283
284static int __maybe_unused spi_imx2_3_rx_available(struct spi_imx_data *spi_imx)
285{
286 return readl(spi_imx->base + SPI_IMX2_3_STAT) & SPI_IMX2_3_STAT_RR;
287}
288
289static void __maybe_unused spi_imx2_3_reset(struct spi_imx_data *spi_imx)
290{
291 /* drain receive buffer */
292 while (spi_imx2_3_rx_available(spi_imx))
293 readl(spi_imx->base + MXC_CSPIRXDATA);
294}
295
b5f3294f
SH		 296#define MX31_INTREG_TEEN (1 << 0)
297#define MX31_INTREG_RREN (1 << 3)
298
299#define MX31_CSPICTRL_ENABLE (1 << 0)
300#define MX31_CSPICTRL_MASTER (1 << 1)
301#define MX31_CSPICTRL_XCH (1 << 2)
302#define MX31_CSPICTRL_POL (1 << 4)
303#define MX31_CSPICTRL_PHA (1 << 5)
304#define MX31_CSPICTRL_SSCTL (1 << 6)
305#define MX31_CSPICTRL_SSPOL (1 << 7)
306#define MX31_CSPICTRL_BC_SHIFT 8
307#define MX35_CSPICTRL_BL_SHIFT 20
308#define MX31_CSPICTRL_CS_SHIFT 24
309#define MX35_CSPICTRL_CS_SHIFT 12
310#define MX31_CSPICTRL_DR_SHIFT 16
311
312#define MX31_CSPISTATUS 0x14
313#define MX31_STATUS_RR (1 << 3)
314
315/* These functions also work for the i.MX35, but be aware that
316 * the i.MX35 has a slightly different register layout for bits
317 * we do not use here.
318 */
f4ba6315 319static void __maybe_unused mx31_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 320{
321 unsigned int val = 0;
322
323 if (enable & MXC_INT_TE)
324 val |= MX31_INTREG_TEEN;
325 if (enable & MXC_INT_RR)
326 val |= MX31_INTREG_RREN;
327
6cdeb002 328 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 329}
330
f4ba6315 331static void __maybe_unused mx31_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 332{
333 unsigned int reg;
334
6cdeb002 335 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 336 reg |= MX31_CSPICTRL_XCH;
6cdeb002 337 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 338}
339
1723e66b 340static int __maybe_unused spi_imx0_4_config(struct spi_imx_data *spi_imx,
6cdeb002 341 struct spi_imx_config *config)
b5f3294f
SH		 342{
343 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
3b2aa89e 344 int cs = spi_imx->chipselect[config->cs];
b5f3294f 345
6cdeb002 346 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 347 MX31_CSPICTRL_DR_SHIFT;
348
1723e66b 349 reg |= (config->bpw - 1) << MX31_CSPICTRL_BC_SHIFT;
b5f3294f
SH		 350
351 if (config->mode & SPI_CPHA)
352 reg |= MX31_CSPICTRL_PHA;
353 if (config->mode & SPI_CPOL)
354 reg |= MX31_CSPICTRL_POL;
355 if (config->mode & SPI_CS_HIGH)
356 reg |= MX31_CSPICTRL_SSPOL;
3b2aa89e
UKK		 357 if (cs < 0)
358 reg |= (cs + 32) << MX31_CSPICTRL_CS_SHIFT;
b5f3294f 359
6cdeb002 360 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 361
362 return 0;
363}
364
1723e66b
UKK		 365static int __maybe_unused spi_imx0_7_config(struct spi_imx_data *spi_imx,
366 struct spi_imx_config *config)
367{
368 unsigned int reg = MX31_CSPICTRL_ENABLE | MX31_CSPICTRL_MASTER;
3b2aa89e 369 int cs = spi_imx->chipselect[config->cs];
1723e66b
UKK		 370
371 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
372 MX31_CSPICTRL_DR_SHIFT;
373
374 reg |= (config->bpw - 1) << MX35_CSPICTRL_BL_SHIFT;
375 reg |= MX31_CSPICTRL_SSCTL;
376
377 if (config->mode & SPI_CPHA)
378 reg |= MX31_CSPICTRL_PHA;
379 if (config->mode & SPI_CPOL)
380 reg |= MX31_CSPICTRL_POL;
381 if (config->mode & SPI_CS_HIGH)
382 reg |= MX31_CSPICTRL_SSPOL;
3b2aa89e
UKK		 383 if (cs < 0)
384 reg |= (cs + 32) << MX35_CSPICTRL_CS_SHIFT;
1723e66b
UKK		 385
386 writel(reg, spi_imx->base + MXC_CSPICTRL);
387
388 return 0;
389}
390
f4ba6315 391static int __maybe_unused mx31_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 392{
6cdeb002 393 return readl(spi_imx->base + MX31_CSPISTATUS) & MX31_STATUS_RR;
b5f3294f
SH		 394}
395
1723e66b
UKK		 396static void __maybe_unused spi_imx0_4_reset(struct spi_imx_data *spi_imx)
397{
398 /* drain receive buffer */
399 while (readl(spi_imx->base + MX3_CSPISTAT) & MX3_CSPISTAT_RR)
400 readl(spi_imx->base + MXC_CSPIRXDATA);
401}
402
b5f3294f
SH		 403#define MX27_INTREG_RR (1 << 4)
404#define MX27_INTREG_TEEN (1 << 9)
405#define MX27_INTREG_RREN (1 << 13)
406
407#define MX27_CSPICTRL_POL (1 << 5)
408#define MX27_CSPICTRL_PHA (1 << 6)
409#define MX27_CSPICTRL_SSPOL (1 << 8)
410#define MX27_CSPICTRL_XCH (1 << 9)
411#define MX27_CSPICTRL_ENABLE (1 << 10)
412#define MX27_CSPICTRL_MASTER (1 << 11)
413#define MX27_CSPICTRL_DR_SHIFT 14
414#define MX27_CSPICTRL_CS_SHIFT 19
415
f4ba6315 416static void __maybe_unused mx27_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 417{
418 unsigned int val = 0;
419
420 if (enable & MXC_INT_TE)
421 val |= MX27_INTREG_TEEN;
422 if (enable & MXC_INT_RR)
423 val |= MX27_INTREG_RREN;
424
6cdeb002 425 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 426}
427
f4ba6315 428static void __maybe_unused mx27_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 429{
430 unsigned int reg;
431
6cdeb002 432 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 433 reg |= MX27_CSPICTRL_XCH;
6cdeb002 434 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 435}
436
f4ba6315 437static int __maybe_unused mx27_config(struct spi_imx_data *spi_imx,
6cdeb002 438 struct spi_imx_config *config)
b5f3294f
SH		 439{
440 unsigned int reg = MX27_CSPICTRL_ENABLE | MX27_CSPICTRL_MASTER;
3b2aa89e 441 int cs = spi_imx->chipselect[config->cs];
b5f3294f 442
6cdeb002 443 reg |= spi_imx_clkdiv_1(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 444 MX27_CSPICTRL_DR_SHIFT;
445 reg |= config->bpw - 1;
446
447 if (config->mode & SPI_CPHA)
448 reg |= MX27_CSPICTRL_PHA;
449 if (config->mode & SPI_CPOL)
450 reg |= MX27_CSPICTRL_POL;
451 if (config->mode & SPI_CS_HIGH)
452 reg |= MX27_CSPICTRL_SSPOL;
3b2aa89e
UKK		 453 if (cs < 0)
454 reg |= (cs + 32) << MX27_CSPICTRL_CS_SHIFT;
b5f3294f 455
6cdeb002 456 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 457
458 return 0;
459}
460
f4ba6315 461static int __maybe_unused mx27_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 462{
6cdeb002 463 return readl(spi_imx->base + MXC_CSPIINT) & MX27_INTREG_RR;
b5f3294f
SH		 464}
465
1723e66b
UKK		 466static void __maybe_unused spi_imx0_0_reset(struct spi_imx_data *spi_imx)
467{
468 writel(1, spi_imx->base + MXC_RESET);
469}
470
b5f3294f
SH		 471#define MX1_INTREG_RR (1 << 3)
472#define MX1_INTREG_TEEN (1 << 8)
473#define MX1_INTREG_RREN (1 << 11)
474
475#define MX1_CSPICTRL_POL (1 << 4)
476#define MX1_CSPICTRL_PHA (1 << 5)
477#define MX1_CSPICTRL_XCH (1 << 8)
478#define MX1_CSPICTRL_ENABLE (1 << 9)
479#define MX1_CSPICTRL_MASTER (1 << 10)
480#define MX1_CSPICTRL_DR_SHIFT 13
481
f4ba6315 482static void __maybe_unused mx1_intctrl(struct spi_imx_data *spi_imx, int enable)
b5f3294f
SH		 483{
484 unsigned int val = 0;
485
486 if (enable & MXC_INT_TE)
487 val |= MX1_INTREG_TEEN;
488 if (enable & MXC_INT_RR)
489 val |= MX1_INTREG_RREN;
490
6cdeb002 491 writel(val, spi_imx->base + MXC_CSPIINT);
b5f3294f
SH		 492}
493
f4ba6315 494static void __maybe_unused mx1_trigger(struct spi_imx_data *spi_imx)
b5f3294f
SH		 495{
496 unsigned int reg;
497
6cdeb002 498 reg = readl(spi_imx->base + MXC_CSPICTRL);
b5f3294f 499 reg |= MX1_CSPICTRL_XCH;
6cdeb002 500 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 501}
502
f4ba6315 503static int __maybe_unused mx1_config(struct spi_imx_data *spi_imx,
6cdeb002 504 struct spi_imx_config *config)
b5f3294f
SH		 505{
506 unsigned int reg = MX1_CSPICTRL_ENABLE | MX1_CSPICTRL_MASTER;
507
6cdeb002 508 reg |= spi_imx_clkdiv_2(spi_imx->spi_clk, config->speed_hz) <<
b5f3294f
SH		 509 MX1_CSPICTRL_DR_SHIFT;
510 reg |= config->bpw - 1;
511
512 if (config->mode & SPI_CPHA)
513 reg |= MX1_CSPICTRL_PHA;
514 if (config->mode & SPI_CPOL)
515 reg |= MX1_CSPICTRL_POL;
516
6cdeb002 517 writel(reg, spi_imx->base + MXC_CSPICTRL);
b5f3294f
SH		 518
519 return 0;
520}
521
f4ba6315 522static int __maybe_unused mx1_rx_available(struct spi_imx_data *spi_imx)
b5f3294f 523{
6cdeb002 524 return readl(spi_imx->base + MXC_CSPIINT) & MX1_INTREG_RR;
b5f3294f
SH		 525}
526
1723e66b
UKK		 527static void __maybe_unused mx1_reset(struct spi_imx_data *spi_imx)
528{
529 writel(1, spi_imx->base + MXC_RESET);
530}
531
f4ba6315
UKK		 532/*
533 * These version numbers are taken from the Freescale driver. Unfortunately it
534 * doesn't support i.MX1, so this entry doesn't match the scheme. :-(
535 */
536static struct spi_imx_devtype_data spi_imx_devtype_data[] __devinitdata = {
537#ifdef CONFIG_SPI_IMX_VER_IMX1
538 [SPI_IMX_VER_IMX1] = {
539 .intctrl = mx1_intctrl,
540 .config = mx1_config,
541 .trigger = mx1_trigger,
542 .rx_available = mx1_rx_available,
1723e66b 543 .reset = mx1_reset,
6ff554e0 544 .fifosize = 8,
f4ba6315
UKK		 545 },
546#endif
547#ifdef CONFIG_SPI_IMX_VER_0_0
548 [SPI_IMX_VER_0_0] = {
549 .intctrl = mx27_intctrl,
550 .config = mx27_config,
551 .trigger = mx27_trigger,
552 .rx_available = mx27_rx_available,
1723e66b 553 .reset = spi_imx0_0_reset,
6ff554e0 554 .fifosize = 8,
f4ba6315
UKK		 555 },
556#endif
557#ifdef CONFIG_SPI_IMX_VER_0_4
558 [SPI_IMX_VER_0_4] = {
559 .intctrl = mx31_intctrl,
1723e66b 560 .config = spi_imx0_4_config,
f4ba6315
UKK		 561 .trigger = mx31_trigger,
562 .rx_available = mx31_rx_available,
1723e66b 563 .reset = spi_imx0_4_reset,
6ff554e0 564 .fifosize = 8,
f4ba6315
UKK		 565 },
566#endif
567#ifdef CONFIG_SPI_IMX_VER_0_7
568 [SPI_IMX_VER_0_7] = {
569 .intctrl = mx31_intctrl,
1723e66b 570 .config = spi_imx0_7_config,
f4ba6315
UKK		 571 .trigger = mx31_trigger,
572 .rx_available = mx31_rx_available,
1723e66b 573 .reset = spi_imx0_4_reset,
6ff554e0 574 .fifosize = 8,
f4ba6315
UKK		 575 },
576#endif
0b599603
UKK		 577#ifdef CONFIG_SPI_IMX_VER_2_3
578 [SPI_IMX_VER_2_3] = {
579 .intctrl = spi_imx2_3_intctrl,
580 .config = spi_imx2_3_config,
581 .trigger = spi_imx2_3_trigger,
582 .rx_available = spi_imx2_3_rx_available,
583 .reset = spi_imx2_3_reset,
6ff554e0 584 .fifosize = 64,
0b599603
UKK		 585 },
586#endif
f4ba6315
UKK		 587};
588
6cdeb002 589static void spi_imx_chipselect(struct spi_device *spi, int is_active)
b5f3294f 590{
6cdeb002 591 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
6cdeb002 592 int gpio = spi_imx->chipselect[spi->chip_select];
e6a0a8bf
UKK		 593 int active = is_active != BITBANG_CS_INACTIVE;
594 int dev_is_lowactive = !(spi->mode & SPI_CS_HIGH);
b5f3294f 595
e6a0a8bf 596 if (gpio < 0)
b5f3294f 597 return;
b5f3294f 598
e6a0a8bf 599 gpio_set_value(gpio, dev_is_lowactive ^ active);
b5f3294f
SH		 600}
601
6cdeb002 602static void spi_imx_push(struct spi_imx_data *spi_imx)
b5f3294f 603{
6ff554e0 604 while (spi_imx->txfifo < spi_imx->devtype_data.fifosize) {
6cdeb002 605 if (!spi_imx->count)
b5f3294f 606 break;
6cdeb002
UKK		 607 spi_imx->tx(spi_imx);
608 spi_imx->txfifo++;
b5f3294f
SH		 609 }
610
f4ba6315 611 spi_imx->devtype_data.trigger(spi_imx);
b5f3294f
SH		 612}
613
6cdeb002 614static irqreturn_t spi_imx_isr(int irq, void *dev_id)
b5f3294f 615{
6cdeb002 616 struct spi_imx_data *spi_imx = dev_id;
b5f3294f 617
f4ba6315 618 while (spi_imx->devtype_data.rx_available(spi_imx)) {
6cdeb002
UKK		 619 spi_imx->rx(spi_imx);
620 spi_imx->txfifo--;
b5f3294f
SH		 621 }
622
6cdeb002
UKK		 623 if (spi_imx->count) {
624 spi_imx_push(spi_imx);
b5f3294f
SH		 625 return IRQ_HANDLED;
626 }
627
6cdeb002 628 if (spi_imx->txfifo) {
b5f3294f
SH		 629 /* No data left to push, but still waiting for rx data,
630 * enable receive data available interrupt.
631 */
f4ba6315
UKK		 632 spi_imx->devtype_data.intctrl(
633 spi_imx, MXC_INT_RR);
b5f3294f
SH		 634 return IRQ_HANDLED;
635 }
636
f4ba6315 637 spi_imx->devtype_data.intctrl(spi_imx, 0);
6cdeb002 638 complete(&spi_imx->xfer_done);
b5f3294f
SH		 639
640 return IRQ_HANDLED;
641}
642
6cdeb002 643static int spi_imx_setupxfer(struct spi_device *spi,
b5f3294f
SH		 644 struct spi_transfer *t)
645{
6cdeb002
UKK		 646 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
647 struct spi_imx_config config;
b5f3294f
SH		 648
649 config.bpw = t ? t->bits_per_word : spi->bits_per_word;
650 config.speed_hz = t ? t->speed_hz : spi->max_speed_hz;
651 config.mode = spi->mode;
3b2aa89e 652 config.cs = spi->chip_select;
b5f3294f 653
462d26b5
SH		 654 if (!config.speed_hz)
655 config.speed_hz = spi->max_speed_hz;
656 if (!config.bpw)
657 config.bpw = spi->bits_per_word;
658 if (!config.speed_hz)
659 config.speed_hz = spi->max_speed_hz;
660
e6a0a8bf
UKK		 661 /* Initialize the functions for transfer */
662 if (config.bpw <= 8) {
663 spi_imx->rx = spi_imx_buf_rx_u8;
664 spi_imx->tx = spi_imx_buf_tx_u8;
665 } else if (config.bpw <= 16) {
666 spi_imx->rx = spi_imx_buf_rx_u16;
667 spi_imx->tx = spi_imx_buf_tx_u16;
668 } else if (config.bpw <= 32) {
669 spi_imx->rx = spi_imx_buf_rx_u32;
670 spi_imx->tx = spi_imx_buf_tx_u32;
671 } else
672 BUG();
673
f4ba6315 674 spi_imx->devtype_data.config(spi_imx, &config);
b5f3294f
SH		 675
676 return 0;
677}
678
6cdeb002 679static int spi_imx_transfer(struct spi_device *spi,
b5f3294f
SH		 680 struct spi_transfer *transfer)
681{
6cdeb002 682 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
b5f3294f 683
6cdeb002
UKK		 684 spi_imx->tx_buf = transfer->tx_buf;
685 spi_imx->rx_buf = transfer->rx_buf;
686 spi_imx->count = transfer->len;
687 spi_imx->txfifo = 0;
b5f3294f 688
6cdeb002 689 init_completion(&spi_imx->xfer_done);
b5f3294f 690
6cdeb002 691 spi_imx_push(spi_imx);
b5f3294f 692
f4ba6315 693 spi_imx->devtype_data.intctrl(spi_imx, MXC_INT_TE);
b5f3294f 694
6cdeb002 695 wait_for_completion(&spi_imx->xfer_done);
b5f3294f
SH		 696
697 return transfer->len;
698}
699
6cdeb002 700static int spi_imx_setup(struct spi_device *spi)
b5f3294f 701{
6c23e5d4
SH		 702 struct spi_imx_data *spi_imx = spi_master_get_devdata(spi->master);
703 int gpio = spi_imx->chipselect[spi->chip_select];
704
f4d4ecfe 705 dev_dbg(&spi->dev, "%s: mode %d, %u bpw, %d hz\n", __func__,
b5f3294f
SH		 706 spi->mode, spi->bits_per_word, spi->max_speed_hz);
707
6c23e5d4
SH		 708 if (gpio >= 0)
709 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
710
6cdeb002 711 spi_imx_chipselect(spi, BITBANG_CS_INACTIVE);
b5f3294f
SH		 712
713 return 0;
714}
715
6cdeb002 716static void spi_imx_cleanup(struct spi_device *spi)
b5f3294f
SH		 717{
718}
719
f4ba6315
UKK		 720static struct platform_device_id spi_imx_devtype[] = {
721 {
f4ba6315
UKK		 722 .name = "imx1-cspi",
723 .driver_data = SPI_IMX_VER_IMX1,
724 }, {
725 .name = "imx21-cspi",
726 .driver_data = SPI_IMX_VER_0_0,
727 }, {
728 .name = "imx25-cspi",
729 .driver_data = SPI_IMX_VER_0_7,
730 }, {
731 .name = "imx27-cspi",
732 .driver_data = SPI_IMX_VER_0_0,
733 }, {
734 .name = "imx31-cspi",
735 .driver_data = SPI_IMX_VER_0_4,
736 }, {
737 .name = "imx35-cspi",
738 .driver_data = SPI_IMX_VER_0_7,
0b599603
UKK		 739 }, {
740 .name = "imx51-cspi",
741 .driver_data = SPI_IMX_VER_0_7,
742 }, {
743 .name = "imx51-ecspi",
744 .driver_data = SPI_IMX_VER_2_3,
f4ba6315
UKK		 745 }, {
746 /* sentinel */
747 }
748};
749
965346e3 750static int __devinit spi_imx_probe(struct platform_device *pdev)
b5f3294f
SH		 751{
752 struct spi_imx_master *mxc_platform_info;
753 struct spi_master *master;
6cdeb002 754 struct spi_imx_data *spi_imx;
b5f3294f
SH		 755 struct resource *res;
756 int i, ret;
757
980f3bee 758 mxc_platform_info = dev_get_platdata(&pdev->dev);
b5f3294f
SH		 759 if (!mxc_platform_info) {
760 dev_err(&pdev->dev, "can't get the platform data\n");
761 return -EINVAL;
762 }
763
6cdeb002 764 master = spi_alloc_master(&pdev->dev, sizeof(struct spi_imx_data));
b5f3294f
SH		 765 if (!master)
766 return -ENOMEM;
767
768 platform_set_drvdata(pdev, master);
769
770 master->bus_num = pdev->id;
771 master->num_chipselect = mxc_platform_info->num_chipselect;
772
6cdeb002
UKK		 773 spi_imx = spi_master_get_devdata(master);
774 spi_imx->bitbang.master = spi_master_get(master);
775 spi_imx->chipselect = mxc_platform_info->chipselect;
b5f3294f
SH		 776
777 for (i = 0; i < master->num_chipselect; i++) {
6cdeb002 778 if (spi_imx->chipselect[i] < 0)
b5f3294f 779 continue;
6cdeb002 780 ret = gpio_request(spi_imx->chipselect[i], DRIVER_NAME);
b5f3294f 781 if (ret) {
bbd050af
JO		 782 while (i > 0) {
783 i--;
6cdeb002 784 if (spi_imx->chipselect[i] >= 0)
bbd050af
JO		 785 gpio_free(spi_imx->chipselect[i]);
786 }
787 dev_err(&pdev->dev, "can't get cs gpios\n");
b5f3294f
SH		 788 goto out_master_put;
789 }
b5f3294f
SH		 790 }
791
6cdeb002
UKK		 792 spi_imx->bitbang.chipselect = spi_imx_chipselect;
793 spi_imx->bitbang.setup_transfer = spi_imx_setupxfer;
794 spi_imx->bitbang.txrx_bufs = spi_imx_transfer;
795 spi_imx->bitbang.master->setup = spi_imx_setup;
796 spi_imx->bitbang.master->cleanup = spi_imx_cleanup;
3910f2cf 797 spi_imx->bitbang.master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
b5f3294f 798
6cdeb002 799 init_completion(&spi_imx->xfer_done);
b5f3294f 800
89342174
UKK		 801 spi_imx->devtype_data =
802 spi_imx_devtype_data[pdev->id_entry->driver_data];
f4ba6315 803
b5f3294f
SH		 804 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
805 if (!res) {
806 dev_err(&pdev->dev, "can't get platform resource\n");
807 ret = -ENOMEM;
808 goto out_gpio_free;
809 }
810
811 if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
812 dev_err(&pdev->dev, "request_mem_region failed\n");
813 ret = -EBUSY;
814 goto out_gpio_free;
815 }
816
6cdeb002
UKK		 817 spi_imx->base = ioremap(res->start, resource_size(res));
818 if (!spi_imx->base) {
b5f3294f
SH		 819 ret = -EINVAL;
820 goto out_release_mem;
821 }
822
6cdeb002 823 spi_imx->irq = platform_get_irq(pdev, 0);
60f675a1 824 if (spi_imx->irq <= 0) {
b5f3294f
SH		 825 ret = -EINVAL;
826 goto out_iounmap;
827 }
828
6cdeb002 829 ret = request_irq(spi_imx->irq, spi_imx_isr, 0, DRIVER_NAME, spi_imx);
b5f3294f 830 if (ret) {
6cdeb002 831 dev_err(&pdev->dev, "can't get irq%d: %d\n", spi_imx->irq, ret);
b5f3294f
SH		 832 goto out_iounmap;
833 }
834
6cdeb002
UKK		 835 spi_imx->clk = clk_get(&pdev->dev, NULL);
836 if (IS_ERR(spi_imx->clk)) {
b5f3294f 837 dev_err(&pdev->dev, "unable to get clock\n");
6cdeb002 838 ret = PTR_ERR(spi_imx->clk);
b5f3294f
SH		 839 goto out_free_irq;
840 }
841
6cdeb002
UKK		 842 clk_enable(spi_imx->clk);
843 spi_imx->spi_clk = clk_get_rate(spi_imx->clk);
b5f3294f 844
1723e66b 845 spi_imx->devtype_data.reset(spi_imx);
ce1807b2 846
f4ba6315 847 spi_imx->devtype_data.intctrl(spi_imx, 0);
b5f3294f 848
6cdeb002 849 ret = spi_bitbang_start(&spi_imx->bitbang);
b5f3294f
SH		 850 if (ret) {
851 dev_err(&pdev->dev, "bitbang start failed with %d\n", ret);
852 goto out_clk_put;
853 }
854
855 dev_info(&pdev->dev, "probed\n");
856
857 return ret;
858
859out_clk_put:
6cdeb002
UKK		 860 clk_disable(spi_imx->clk);
861 clk_put(spi_imx->clk);
b5f3294f 862out_free_irq:
6cdeb002 863 free_irq(spi_imx->irq, spi_imx);
b5f3294f 864out_iounmap:
6cdeb002 865 iounmap(spi_imx->base);
b5f3294f
SH		 866out_release_mem:
867 release_mem_region(res->start, resource_size(res));
868out_gpio_free:
869 for (i = 0; i < master->num_chipselect; i++)
6cdeb002
UKK		 870 if (spi_imx->chipselect[i] >= 0)
871 gpio_free(spi_imx->chipselect[i]);
b5f3294f
SH		 872out_master_put:
873 spi_master_put(master);
874 kfree(master);
875 platform_set_drvdata(pdev, NULL);
876 return ret;
877}
878
965346e3 879static int __devexit spi_imx_remove(struct platform_device *pdev)
b5f3294f
SH		 880{
881 struct spi_master *master = platform_get_drvdata(pdev);
882 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
6cdeb002 883 struct spi_imx_data *spi_imx = spi_master_get_devdata(master);
b5f3294f
SH		 884 int i;
885
6cdeb002 886 spi_bitbang_stop(&spi_imx->bitbang);
b5f3294f 887
6cdeb002
UKK		 888 writel(0, spi_imx->base + MXC_CSPICTRL);
889 clk_disable(spi_imx->clk);
890 clk_put(spi_imx->clk);
891 free_irq(spi_imx->irq, spi_imx);
892 iounmap(spi_imx->base);
b5f3294f
SH		 893
894 for (i = 0; i < master->num_chipselect; i++)
6cdeb002
UKK		 895 if (spi_imx->chipselect[i] >= 0)
896 gpio_free(spi_imx->chipselect[i]);
b5f3294f
SH		 897
898 spi_master_put(master);
899
900 release_mem_region(res->start, resource_size(res));
901
902 platform_set_drvdata(pdev, NULL);
903
904 return 0;
905}
906
6cdeb002 907static struct platform_driver spi_imx_driver = {
b5f3294f
SH		 908 .driver = {
909 .name = DRIVER_NAME,
910 .owner = THIS_MODULE,
911 },
f4ba6315 912 .id_table = spi_imx_devtype,
6cdeb002 913 .probe = spi_imx_probe,
965346e3 914 .remove = __devexit_p(spi_imx_remove),
b5f3294f
SH		 915};
916
6cdeb002 917static int __init spi_imx_init(void)
b5f3294f 918{
6cdeb002 919 return platform_driver_register(&spi_imx_driver);
b5f3294f
SH		 920}
921
6cdeb002 922static void __exit spi_imx_exit(void)
b5f3294f 923{
6cdeb002 924 platform_driver_unregister(&spi_imx_driver);
b5f3294f
SH		 925}
926
6cdeb002
UKK		 927module_init(spi_imx_init);
928module_exit(spi_imx_exit);
b5f3294f
SH		 929
930MODULE_DESCRIPTION("SPI Master Controller driver");
931MODULE_AUTHOR("Sascha Hauer, Pengutronix");
932MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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