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spi/s3c64xx: Include moved header
[deliverable/linux.git] / drivers / spi / spi_s3c64xx.c
CommitLineData
230d42d4
JB		 1/* linux/drivers/spi/spi_s3c64xx.c
2 *
3 * Copyright (C) 2009 Samsung Electronics Ltd.
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 */
20
21#include <linux/init.h>
22#include <linux/module.h>
23#include <linux/workqueue.h>
24#include <linux/delay.h>
25#include <linux/clk.h>
26#include <linux/dma-mapping.h>
27#include <linux/platform_device.h>
28#include <linux/spi/spi.h>
29
30#include <mach/dma.h>
e6b873c9 31#include <plat/s3c64xx-spi.h>
230d42d4
JB		 32
33/* Registers and bit-fields */
34
35#define S3C64XX_SPI_CH_CFG 0x00
36#define S3C64XX_SPI_CLK_CFG 0x04
37#define S3C64XX_SPI_MODE_CFG 0x08
38#define S3C64XX_SPI_SLAVE_SEL 0x0C
39#define S3C64XX_SPI_INT_EN 0x10
40#define S3C64XX_SPI_STATUS 0x14
41#define S3C64XX_SPI_TX_DATA 0x18
42#define S3C64XX_SPI_RX_DATA 0x1C
43#define S3C64XX_SPI_PACKET_CNT 0x20
44#define S3C64XX_SPI_PENDING_CLR 0x24
45#define S3C64XX_SPI_SWAP_CFG 0x28
46#define S3C64XX_SPI_FB_CLK 0x2C
47
48#define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
49#define S3C64XX_SPI_CH_SW_RST (1<<5)
50#define S3C64XX_SPI_CH_SLAVE (1<<4)
51#define S3C64XX_SPI_CPOL_L (1<<3)
52#define S3C64XX_SPI_CPHA_B (1<<2)
53#define S3C64XX_SPI_CH_RXCH_ON (1<<1)
54#define S3C64XX_SPI_CH_TXCH_ON (1<<0)
55
56#define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
57#define S3C64XX_SPI_CLKSEL_SRCSHFT 9
58#define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
59#define S3C64XX_SPI_PSR_MASK 0xff
60
61#define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
62#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
63#define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
64#define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
65#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
66#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
67#define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
68#define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
69#define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
70#define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
71#define S3C64XX_SPI_MODE_4BURST (1<<0)
72
73#define S3C64XX_SPI_SLAVE_AUTO (1<<1)
74#define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
75
76#define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL)
77
78#define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \
79 (c)->regs + S3C64XX_SPI_SLAVE_SEL)
80
81#define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
82#define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
83#define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
84#define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
85#define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
86#define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
87#define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
88
89#define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
90#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
91#define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
92#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
93#define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
94#define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
95
96#define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
97
98#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
99#define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
100#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
101#define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
102#define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
103
104#define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
105#define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
106#define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
107#define S3C64XX_SPI_SWAP_RX_EN (1<<4)
108#define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
109#define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
110#define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
111#define S3C64XX_SPI_SWAP_TX_EN (1<<0)
112
113#define S3C64XX_SPI_FBCLK_MSK (3<<0)
114
115#define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \
116 (((i)->fifo_lvl_mask + 1))) \
117 ? 1 : 0)
118
119#define S3C64XX_SPI_ST_TX_DONE(v, i) ((((v) >> (i)->rx_lvl_offset) & \
120 (((i)->fifo_lvl_mask + 1) << 1)) \
121 ? 1 : 0)
122#define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask)
123#define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask)
124
125#define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
126#define S3C64XX_SPI_TRAILCNT_OFF 19
127
128#define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
129
130#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
131
132#define SUSPND (1<<0)
133#define SPIBUSY (1<<1)
134#define RXBUSY (1<<2)
135#define TXBUSY (1<<3)
136
137/**
138 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
139 * @clk: Pointer to the spi clock.
b0d5d6e5 140 * @src_clk: Pointer to the clock used to generate SPI signals.
230d42d4
JB		 141 * @master: Pointer to the SPI Protocol master.
142 * @workqueue: Work queue for the SPI xfer requests.
143 * @cntrlr_info: Platform specific data for the controller this driver manages.
144 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint.
145 * @work: Work
146 * @queue: To log SPI xfer requests.
147 * @lock: Controller specific lock.
148 * @state: Set of FLAGS to indicate status.
149 * @rx_dmach: Controller's DMA channel for Rx.
150 * @tx_dmach: Controller's DMA channel for Tx.
151 * @sfr_start: BUS address of SPI controller regs.
152 * @regs: Pointer to ioremap'ed controller registers.
153 * @xfer_completion: To indicate completion of xfer task.
154 * @cur_mode: Stores the active configuration of the controller.
155 * @cur_bpw: Stores the active bits per word settings.
156 * @cur_speed: Stores the active xfer clock speed.
157 */
158struct s3c64xx_spi_driver_data {
159 void __iomem *regs;
160 struct clk *clk;
b0d5d6e5 161 struct clk *src_clk;
230d42d4
JB		 162 struct platform_device *pdev;
163 struct spi_master *master;
164 struct workqueue_struct *workqueue;
ad7de729 165 struct s3c64xx_spi_info *cntrlr_info;
230d42d4
JB		 166 struct spi_device *tgl_spi;
167 struct work_struct work;
168 struct list_head queue;
169 spinlock_t lock;
170 enum dma_ch rx_dmach;
171 enum dma_ch tx_dmach;
172 unsigned long sfr_start;
173 struct completion xfer_completion;
174 unsigned state;
175 unsigned cur_mode, cur_bpw;
176 unsigned cur_speed;
177};
178
179static struct s3c2410_dma_client s3c64xx_spi_dma_client = {
180 .name = "samsung-spi-dma",
181};
182
183static void flush_fifo(struct s3c64xx_spi_driver_data *sdd)
184{
ad7de729 185 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
230d42d4
JB		 186 void __iomem *regs = sdd->regs;
187 unsigned long loops;
188 u32 val;
189
190 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
191
192 val = readl(regs + S3C64XX_SPI_CH_CFG);
193 val |= S3C64XX_SPI_CH_SW_RST;
194 val &= ~S3C64XX_SPI_CH_HS_EN;
195 writel(val, regs + S3C64XX_SPI_CH_CFG);
196
197 /* Flush TxFIFO*/
198 loops = msecs_to_loops(1);
199 do {
200 val = readl(regs + S3C64XX_SPI_STATUS);
201 } while (TX_FIFO_LVL(val, sci) && loops--);
202
203 /* Flush RxFIFO*/
204 loops = msecs_to_loops(1);
205 do {
206 val = readl(regs + S3C64XX_SPI_STATUS);
207 if (RX_FIFO_LVL(val, sci))
208 readl(regs + S3C64XX_SPI_RX_DATA);
209 else
210 break;
211 } while (loops--);
212
213 val = readl(regs + S3C64XX_SPI_CH_CFG);
214 val &= ~S3C64XX_SPI_CH_SW_RST;
215 writel(val, regs + S3C64XX_SPI_CH_CFG);
216
217 val = readl(regs + S3C64XX_SPI_MODE_CFG);
218 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
219 writel(val, regs + S3C64XX_SPI_MODE_CFG);
220
221 val = readl(regs + S3C64XX_SPI_CH_CFG);
222 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
223 writel(val, regs + S3C64XX_SPI_CH_CFG);
224}
225
226static void enable_datapath(struct s3c64xx_spi_driver_data *sdd,
227 struct spi_device *spi,
228 struct spi_transfer *xfer, int dma_mode)
229{
ad7de729 230 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
230d42d4
JB		 231 void __iomem *regs = sdd->regs;
232 u32 modecfg, chcfg;
233
234 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
235 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
236
237 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
238 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
239
240 if (dma_mode) {
241 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
242 } else {
243 /* Always shift in data in FIFO, even if xfer is Tx only,
244 * this helps setting PCKT_CNT value for generating clocks
245 * as exactly needed.
246 */
247 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
248 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
249 | S3C64XX_SPI_PACKET_CNT_EN,
250 regs + S3C64XX_SPI_PACKET_CNT);
251 }
252
253 if (xfer->tx_buf != NULL) {
254 sdd->state |= TXBUSY;
255 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
256 if (dma_mode) {
257 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
258 s3c2410_dma_config(sdd->tx_dmach, 1);
259 s3c2410_dma_enqueue(sdd->tx_dmach, (void *)sdd,
260 xfer->tx_dma, xfer->len);
261 s3c2410_dma_ctrl(sdd->tx_dmach, S3C2410_DMAOP_START);
262 } else {
263 unsigned char *buf = (unsigned char *) xfer->tx_buf;
264 int i = 0;
265 while (i < xfer->len)
266 writeb(buf[i++], regs + S3C64XX_SPI_TX_DATA);
267 }
268 }
269
270 if (xfer->rx_buf != NULL) {
271 sdd->state |= RXBUSY;
272
273 if (sci->high_speed && sdd->cur_speed >= 30000000UL
274 && !(sdd->cur_mode & SPI_CPHA))
275 chcfg |= S3C64XX_SPI_CH_HS_EN;
276
277 if (dma_mode) {
278 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
279 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
280 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
281 | S3C64XX_SPI_PACKET_CNT_EN,
282 regs + S3C64XX_SPI_PACKET_CNT);
283 s3c2410_dma_config(sdd->rx_dmach, 1);
284 s3c2410_dma_enqueue(sdd->rx_dmach, (void *)sdd,
285 xfer->rx_dma, xfer->len);
286 s3c2410_dma_ctrl(sdd->rx_dmach, S3C2410_DMAOP_START);
287 }
288 }
289
290 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
291 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
292}
293
294static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd,
295 struct spi_device *spi)
296{
297 struct s3c64xx_spi_csinfo *cs;
298
299 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */
300 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */
301 /* Deselect the last toggled device */
302 cs = sdd->tgl_spi->controller_data;
303 cs->set_level(spi->mode & SPI_CS_HIGH ? 0 : 1);
304 }
305 sdd->tgl_spi = NULL;
306 }
307
308 cs = spi->controller_data;
309 cs->set_level(spi->mode & SPI_CS_HIGH ? 1 : 0);
310}
311
312static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd,
313 struct spi_transfer *xfer, int dma_mode)
314{
ad7de729 315 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
230d42d4
JB		 316 void __iomem *regs = sdd->regs;
317 unsigned long val;
318 int ms;
319
320 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
321 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
322 ms += 5; /* some tolerance */
323
324 if (dma_mode) {
325 val = msecs_to_jiffies(ms) + 10;
326 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
327 } else {
328 val = msecs_to_loops(ms);
329 do {
330 val = readl(regs + S3C64XX_SPI_STATUS);
331 } while (RX_FIFO_LVL(val, sci) < xfer->len && --val);
332 }
333
334 if (!val)
335 return -EIO;
336
337 if (dma_mode) {
338 u32 status;
339
340 /*
341 * DmaTx returns after simply writing data in the FIFO,
342 * w/o waiting for real transmission on the bus to finish.
343 * DmaRx returns only after Dma read data from FIFO which
344 * needs bus transmission to finish, so we don't worry if
345 * Xfer involved Rx(with or without Tx).
346 */
347 if (xfer->rx_buf == NULL) {
348 val = msecs_to_loops(10);
349 status = readl(regs + S3C64XX_SPI_STATUS);
350 while ((TX_FIFO_LVL(status, sci)
351 || !S3C64XX_SPI_ST_TX_DONE(status, sci))
352 && --val) {
353 cpu_relax();
354 status = readl(regs + S3C64XX_SPI_STATUS);
355 }
356
357 if (!val)
358 return -EIO;
359 }
360 } else {
361 unsigned char *buf;
362 int i;
363
364 /* If it was only Tx */
365 if (xfer->rx_buf == NULL) {
366 sdd->state &= ~TXBUSY;
367 return 0;
368 }
369
370 i = 0;
371 buf = xfer->rx_buf;
372 while (i < xfer->len)
373 buf[i++] = readb(regs + S3C64XX_SPI_RX_DATA);
374
375 sdd->state &= ~RXBUSY;
376 }
377
378 return 0;
379}
380
381static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd,
382 struct spi_device *spi)
383{
384 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
385
386 if (sdd->tgl_spi == spi)
387 sdd->tgl_spi = NULL;
388
389 cs->set_level(spi->mode & SPI_CS_HIGH ? 0 : 1);
390}
391
392static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
393{
230d42d4
JB		 394 void __iomem *regs = sdd->regs;
395 u32 val;
396
397 /* Disable Clock */
398 val = readl(regs + S3C64XX_SPI_CLK_CFG);
399 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
400 writel(val, regs + S3C64XX_SPI_CLK_CFG);
401
402 /* Set Polarity and Phase */
403 val = readl(regs + S3C64XX_SPI_CH_CFG);
404 val &= ~(S3C64XX_SPI_CH_SLAVE |
405 S3C64XX_SPI_CPOL_L |
406 S3C64XX_SPI_CPHA_B);
407
408 if (sdd->cur_mode & SPI_CPOL)
409 val |= S3C64XX_SPI_CPOL_L;
410
411 if (sdd->cur_mode & SPI_CPHA)
412 val |= S3C64XX_SPI_CPHA_B;
413
414 writel(val, regs + S3C64XX_SPI_CH_CFG);
415
416 /* Set Channel & DMA Mode */
417 val = readl(regs + S3C64XX_SPI_MODE_CFG);
418 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
419 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
420
421 switch (sdd->cur_bpw) {
422 case 32:
423 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
424 break;
425 case 16:
426 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
427 break;
428 default:
429 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
430 break;
431 }
432 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; /* Always 8bits wide */
433
434 writel(val, regs + S3C64XX_SPI_MODE_CFG);
435
436 /* Configure Clock */
437 val = readl(regs + S3C64XX_SPI_CLK_CFG);
438 val &= ~S3C64XX_SPI_PSR_MASK;
b0d5d6e5 439 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
230d42d4
JB		 440 & S3C64XX_SPI_PSR_MASK);
441 writel(val, regs + S3C64XX_SPI_CLK_CFG);
442
443 /* Enable Clock */
444 val = readl(regs + S3C64XX_SPI_CLK_CFG);
445 val |= S3C64XX_SPI_ENCLK_ENABLE;
446 writel(val, regs + S3C64XX_SPI_CLK_CFG);
447}
448
449void s3c64xx_spi_dma_rxcb(struct s3c2410_dma_chan *chan, void *buf_id,
450 int size, enum s3c2410_dma_buffresult res)
451{
452 struct s3c64xx_spi_driver_data *sdd = buf_id;
453 unsigned long flags;
454
455 spin_lock_irqsave(&sdd->lock, flags);
456
457 if (res == S3C2410_RES_OK)
458 sdd->state &= ~RXBUSY;
459 else
460 dev_err(&sdd->pdev->dev, "DmaAbrtRx-%d\n", size);
461
462 /* If the other done */
463 if (!(sdd->state & TXBUSY))
464 complete(&sdd->xfer_completion);
465
466 spin_unlock_irqrestore(&sdd->lock, flags);
467}
468
469void s3c64xx_spi_dma_txcb(struct s3c2410_dma_chan *chan, void *buf_id,
470 int size, enum s3c2410_dma_buffresult res)
471{
472 struct s3c64xx_spi_driver_data *sdd = buf_id;
473 unsigned long flags;
474
475 spin_lock_irqsave(&sdd->lock, flags);
476
477 if (res == S3C2410_RES_OK)
478 sdd->state &= ~TXBUSY;
479 else
480 dev_err(&sdd->pdev->dev, "DmaAbrtTx-%d \n", size);
481
482 /* If the other done */
483 if (!(sdd->state & RXBUSY))
484 complete(&sdd->xfer_completion);
485
486 spin_unlock_irqrestore(&sdd->lock, flags);
487}
488
489#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
490
491static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd,
492 struct spi_message *msg)
493{
494 struct device *dev = &sdd->pdev->dev;
495 struct spi_transfer *xfer;
496
497 if (msg->is_dma_mapped)
498 return 0;
499
500 /* First mark all xfer unmapped */
501 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
502 xfer->rx_dma = XFER_DMAADDR_INVALID;
503 xfer->tx_dma = XFER_DMAADDR_INVALID;
504 }
505
506 /* Map until end or first fail */
507 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
508
509 if (xfer->tx_buf != NULL) {
510 xfer->tx_dma = dma_map_single(dev, xfer->tx_buf,
511 xfer->len, DMA_TO_DEVICE);
512 if (dma_mapping_error(dev, xfer->tx_dma)) {
513 dev_err(dev, "dma_map_single Tx failed\n");
514 xfer->tx_dma = XFER_DMAADDR_INVALID;
515 return -ENOMEM;
516 }
517 }
518
519 if (xfer->rx_buf != NULL) {
520 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf,
521 xfer->len, DMA_FROM_DEVICE);
522 if (dma_mapping_error(dev, xfer->rx_dma)) {
523 dev_err(dev, "dma_map_single Rx failed\n");
524 dma_unmap_single(dev, xfer->tx_dma,
525 xfer->len, DMA_TO_DEVICE);
526 xfer->tx_dma = XFER_DMAADDR_INVALID;
527 xfer->rx_dma = XFER_DMAADDR_INVALID;
528 return -ENOMEM;
529 }
530 }
531 }
532
533 return 0;
534}
535
536static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd,
537 struct spi_message *msg)
538{
539 struct device *dev = &sdd->pdev->dev;
540 struct spi_transfer *xfer;
541
542 if (msg->is_dma_mapped)
543 return;
544
545 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
546
547 if (xfer->rx_buf != NULL
548 && xfer->rx_dma != XFER_DMAADDR_INVALID)
549 dma_unmap_single(dev, xfer->rx_dma,
550 xfer->len, DMA_FROM_DEVICE);
551
552 if (xfer->tx_buf != NULL
553 && xfer->tx_dma != XFER_DMAADDR_INVALID)
554 dma_unmap_single(dev, xfer->tx_dma,
555 xfer->len, DMA_TO_DEVICE);
556 }
557}
558
559static void handle_msg(struct s3c64xx_spi_driver_data *sdd,
560 struct spi_message *msg)
561{
ad7de729 562 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
230d42d4
JB		 563 struct spi_device *spi = msg->spi;
564 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
565 struct spi_transfer *xfer;
566 int status = 0, cs_toggle = 0;
567 u32 speed;
568 u8 bpw;
569
570 /* If Master's(controller) state differs from that needed by Slave */
571 if (sdd->cur_speed != spi->max_speed_hz
572 || sdd->cur_mode != spi->mode
573 || sdd->cur_bpw != spi->bits_per_word) {
574 sdd->cur_bpw = spi->bits_per_word;
575 sdd->cur_speed = spi->max_speed_hz;
576 sdd->cur_mode = spi->mode;
577 s3c64xx_spi_config(sdd);
578 }
579
580 /* Map all the transfers if needed */
581 if (s3c64xx_spi_map_mssg(sdd, msg)) {
582 dev_err(&spi->dev,
583 "Xfer: Unable to map message buffers!\n");
584 status = -ENOMEM;
585 goto out;
586 }
587
588 /* Configure feedback delay */
589 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
590
591 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
592
593 unsigned long flags;
594 int use_dma;
595
596 INIT_COMPLETION(sdd->xfer_completion);
597
598 /* Only BPW and Speed may change across transfers */
599 bpw = xfer->bits_per_word ? : spi->bits_per_word;
600 speed = xfer->speed_hz ? : spi->max_speed_hz;
601
602 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
603 sdd->cur_bpw = bpw;
604 sdd->cur_speed = speed;
605 s3c64xx_spi_config(sdd);
606 }
607
608 /* Polling method for xfers not bigger than FIFO capacity */
609 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1))
610 use_dma = 0;
611 else
612 use_dma = 1;
613
614 spin_lock_irqsave(&sdd->lock, flags);
615
616 /* Pending only which is to be done */
617 sdd->state &= ~RXBUSY;
618 sdd->state &= ~TXBUSY;
619
620 enable_datapath(sdd, spi, xfer, use_dma);
621
622 /* Slave Select */
623 enable_cs(sdd, spi);
624
625 /* Start the signals */
626 S3C64XX_SPI_ACT(sdd);
627
628 spin_unlock_irqrestore(&sdd->lock, flags);
629
630 status = wait_for_xfer(sdd, xfer, use_dma);
631
632 /* Quiese the signals */
633 S3C64XX_SPI_DEACT(sdd);
634
635 if (status) {
636 dev_err(&spi->dev, "I/O Error: \
637 rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
638 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
639 (sdd->state & RXBUSY) ? 'f' : 'p',
640 (sdd->state & TXBUSY) ? 'f' : 'p',
641 xfer->len);
642
643 if (use_dma) {
644 if (xfer->tx_buf != NULL
645 && (sdd->state & TXBUSY))
646 s3c2410_dma_ctrl(sdd->tx_dmach,
647 S3C2410_DMAOP_FLUSH);
648 if (xfer->rx_buf != NULL
649 && (sdd->state & RXBUSY))
650 s3c2410_dma_ctrl(sdd->rx_dmach,
651 S3C2410_DMAOP_FLUSH);
652 }
653
654 goto out;
655 }
656
657 if (xfer->delay_usecs)
658 udelay(xfer->delay_usecs);
659
660 if (xfer->cs_change) {
661 /* Hint that the next mssg is gonna be
662 for the same device */
663 if (list_is_last(&xfer->transfer_list,
664 &msg->transfers))
665 cs_toggle = 1;
666 else
667 disable_cs(sdd, spi);
668 }
669
670 msg->actual_length += xfer->len;
671
672 flush_fifo(sdd);
673 }
674
675out:
676 if (!cs_toggle || status)
677 disable_cs(sdd, spi);
678 else
679 sdd->tgl_spi = spi;
680
681 s3c64xx_spi_unmap_mssg(sdd, msg);
682
683 msg->status = status;
684
685 if (msg->complete)
686 msg->complete(msg->context);
687}
688
689static int acquire_dma(struct s3c64xx_spi_driver_data *sdd)
690{
691 if (s3c2410_dma_request(sdd->rx_dmach,
692 &s3c64xx_spi_dma_client, NULL) < 0) {
693 dev_err(&sdd->pdev->dev, "cannot get RxDMA\n");
694 return 0;
695 }
696 s3c2410_dma_set_buffdone_fn(sdd->rx_dmach, s3c64xx_spi_dma_rxcb);
697 s3c2410_dma_devconfig(sdd->rx_dmach, S3C2410_DMASRC_HW,
698 sdd->sfr_start + S3C64XX_SPI_RX_DATA);
699
700 if (s3c2410_dma_request(sdd->tx_dmach,
701 &s3c64xx_spi_dma_client, NULL) < 0) {
702 dev_err(&sdd->pdev->dev, "cannot get TxDMA\n");
703 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
704 return 0;
705 }
706 s3c2410_dma_set_buffdone_fn(sdd->tx_dmach, s3c64xx_spi_dma_txcb);
707 s3c2410_dma_devconfig(sdd->tx_dmach, S3C2410_DMASRC_MEM,
708 sdd->sfr_start + S3C64XX_SPI_TX_DATA);
709
710 return 1;
711}
712
713static void s3c64xx_spi_work(struct work_struct *work)
714{
715 struct s3c64xx_spi_driver_data *sdd = container_of(work,
716 struct s3c64xx_spi_driver_data, work);
717 unsigned long flags;
718
719 /* Acquire DMA channels */
720 while (!acquire_dma(sdd))
721 msleep(10);
722
723 spin_lock_irqsave(&sdd->lock, flags);
724
725 while (!list_empty(&sdd->queue)
726 && !(sdd->state & SUSPND)) {
727
728 struct spi_message *msg;
729
730 msg = container_of(sdd->queue.next, struct spi_message, queue);
731
732 list_del_init(&msg->queue);
733
734 /* Set Xfer busy flag */
735 sdd->state |= SPIBUSY;
736
737 spin_unlock_irqrestore(&sdd->lock, flags);
738
739 handle_msg(sdd, msg);
740
741 spin_lock_irqsave(&sdd->lock, flags);
742
743 sdd->state &= ~SPIBUSY;
744 }
745
746 spin_unlock_irqrestore(&sdd->lock, flags);
747
748 /* Free DMA channels */
749 s3c2410_dma_free(sdd->tx_dmach, &s3c64xx_spi_dma_client);
750 s3c2410_dma_free(sdd->rx_dmach, &s3c64xx_spi_dma_client);
751}
752
753static int s3c64xx_spi_transfer(struct spi_device *spi,
754 struct spi_message *msg)
755{
756 struct s3c64xx_spi_driver_data *sdd;
757 unsigned long flags;
758
759 sdd = spi_master_get_devdata(spi->master);
760
761 spin_lock_irqsave(&sdd->lock, flags);
762
763 if (sdd->state & SUSPND) {
764 spin_unlock_irqrestore(&sdd->lock, flags);
765 return -ESHUTDOWN;
766 }
767
768 msg->status = -EINPROGRESS;
769 msg->actual_length = 0;
770
771 list_add_tail(&msg->queue, &sdd->queue);
772
773 queue_work(sdd->workqueue, &sdd->work);
774
775 spin_unlock_irqrestore(&sdd->lock, flags);
776
777 return 0;
778}
779
780/*
781 * Here we only check the validity of requested configuration
782 * and save the configuration in a local data-structure.
783 * The controller is actually configured only just before we
784 * get a message to transfer.
785 */
786static int s3c64xx_spi_setup(struct spi_device *spi)
787{
788 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
789 struct s3c64xx_spi_driver_data *sdd;
ad7de729 790 struct s3c64xx_spi_info *sci;
230d42d4
JB		 791 struct spi_message *msg;
792 u32 psr, speed;
793 unsigned long flags;
794 int err = 0;
795
796 if (cs == NULL || cs->set_level == NULL) {
797 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
798 return -ENODEV;
799 }
800
801 sdd = spi_master_get_devdata(spi->master);
802 sci = sdd->cntrlr_info;
803
804 spin_lock_irqsave(&sdd->lock, flags);
805
806 list_for_each_entry(msg, &sdd->queue, queue) {
807 /* Is some mssg is already queued for this device */
808 if (msg->spi == spi) {
809 dev_err(&spi->dev,
810 "setup: attempt while mssg in queue!\n");
811 spin_unlock_irqrestore(&sdd->lock, flags);
812 return -EBUSY;
813 }
814 }
815
816 if (sdd->state & SUSPND) {
817 spin_unlock_irqrestore(&sdd->lock, flags);
818 dev_err(&spi->dev,
819 "setup: SPI-%d not active!\n", spi->master->bus_num);
820 return -ESHUTDOWN;
821 }
822
823 spin_unlock_irqrestore(&sdd->lock, flags);
824
825 if (spi->bits_per_word != 8
826 && spi->bits_per_word != 16
827 && spi->bits_per_word != 32) {
828 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n",
829 spi->bits_per_word);
830 err = -EINVAL;
831 goto setup_exit;
832 }
833
834 /* Check if we can provide the requested rate */
b0d5d6e5 835 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); /* Max possible */
230d42d4
JB		 836
837 if (spi->max_speed_hz > speed)
838 spi->max_speed_hz = speed;
839
b0d5d6e5 840 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
230d42d4
JB		 841 psr &= S3C64XX_SPI_PSR_MASK;
842 if (psr == S3C64XX_SPI_PSR_MASK)
843 psr--;
844
b0d5d6e5 845 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
230d42d4
JB		 846 if (spi->max_speed_hz < speed) {
847 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
848 psr++;
849 } else {
850 err = -EINVAL;
851 goto setup_exit;
852 }
853 }
854
b0d5d6e5 855 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
230d42d4
JB		 856 if (spi->max_speed_hz >= speed)
857 spi->max_speed_hz = speed;
858 else
859 err = -EINVAL;
860
861setup_exit:
862
863 /* setup() returns with device de-selected */
864 disable_cs(sdd, spi);
865
866 return err;
867}
868
869static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel)
870{
ad7de729 871 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
230d42d4
JB		 872 void __iomem *regs = sdd->regs;
873 unsigned int val;
874
875 sdd->cur_speed = 0;
876
877 S3C64XX_SPI_DEACT(sdd);
878
879 /* Disable Interrupts - we use Polling if not DMA mode */
880 writel(0, regs + S3C64XX_SPI_INT_EN);
881
882 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
883 regs + S3C64XX_SPI_CLK_CFG);
884 writel(0, regs + S3C64XX_SPI_MODE_CFG);
885 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
886
887 /* Clear any irq pending bits */
888 writel(readl(regs + S3C64XX_SPI_PENDING_CLR),
889 regs + S3C64XX_SPI_PENDING_CLR);
890
891 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
892
893 val = readl(regs + S3C64XX_SPI_MODE_CFG);
894 val &= ~S3C64XX_SPI_MODE_4BURST;
895 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
896 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
897 writel(val, regs + S3C64XX_SPI_MODE_CFG);
898
899 flush_fifo(sdd);
900}
901
902static int __init s3c64xx_spi_probe(struct platform_device *pdev)
903{
904 struct resource *mem_res, *dmatx_res, *dmarx_res;
905 struct s3c64xx_spi_driver_data *sdd;
ad7de729 906 struct s3c64xx_spi_info *sci;
230d42d4
JB		 907 struct spi_master *master;
908 int ret;
909
910 if (pdev->id < 0) {
911 dev_err(&pdev->dev,
912 "Invalid platform device id-%d\n", pdev->id);
913 return -ENODEV;
914 }
915
916 if (pdev->dev.platform_data == NULL) {
917 dev_err(&pdev->dev, "platform_data missing!\n");
918 return -ENODEV;
919 }
920
921 /* Check for availability of necessary resource */
922
923 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
924 if (dmatx_res == NULL) {
925 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n");
926 return -ENXIO;
927 }
928
929 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
930 if (dmarx_res == NULL) {
931 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n");
932 return -ENXIO;
933 }
934
935 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
936 if (mem_res == NULL) {
937 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
938 return -ENXIO;
939 }
940
941 master = spi_alloc_master(&pdev->dev,
942 sizeof(struct s3c64xx_spi_driver_data));
943 if (master == NULL) {
944 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
945 return -ENOMEM;
946 }
947
948 sci = pdev->dev.platform_data;
949
950 platform_set_drvdata(pdev, master);
951
952 sdd = spi_master_get_devdata(master);
953 sdd->master = master;
954 sdd->cntrlr_info = sci;
955 sdd->pdev = pdev;
956 sdd->sfr_start = mem_res->start;
957 sdd->tx_dmach = dmatx_res->start;
958 sdd->rx_dmach = dmarx_res->start;
959
960 sdd->cur_bpw = 8;
961
962 master->bus_num = pdev->id;
963 master->setup = s3c64xx_spi_setup;
964 master->transfer = s3c64xx_spi_transfer;
965 master->num_chipselect = sci->num_cs;
966 master->dma_alignment = 8;
967 /* the spi->mode bits understood by this driver: */
968 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
969
970 if (request_mem_region(mem_res->start,
971 resource_size(mem_res), pdev->name) == NULL) {
972 dev_err(&pdev->dev, "Req mem region failed\n");
973 ret = -ENXIO;
974 goto err0;
975 }
976
977 sdd->regs = ioremap(mem_res->start, resource_size(mem_res));
978 if (sdd->regs == NULL) {
979 dev_err(&pdev->dev, "Unable to remap IO\n");
980 ret = -ENXIO;
981 goto err1;
982 }
983
984 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) {
985 dev_err(&pdev->dev, "Unable to config gpio\n");
986 ret = -EBUSY;
987 goto err2;
988 }
989
990 /* Setup clocks */
991 sdd->clk = clk_get(&pdev->dev, "spi");
992 if (IS_ERR(sdd->clk)) {
993 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
994 ret = PTR_ERR(sdd->clk);
995 goto err3;
996 }
997
998 if (clk_enable(sdd->clk)) {
999 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1000 ret = -EBUSY;
1001 goto err4;
1002 }
1003
b0d5d6e5
JB		 1004 sdd->src_clk = clk_get(&pdev->dev, sci->src_clk_name);
1005 if (IS_ERR(sdd->src_clk)) {
230d42d4
JB		 1006 dev_err(&pdev->dev,
1007 "Unable to acquire clock '%s'\n", sci->src_clk_name);
b0d5d6e5 1008 ret = PTR_ERR(sdd->src_clk);
230d42d4
JB		 1009 goto err5;
1010 }
1011
b0d5d6e5 1012 if (clk_enable(sdd->src_clk)) {
230d42d4
JB		 1013 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n",
1014 sci->src_clk_name);
1015 ret = -EBUSY;
1016 goto err6;
1017 }
1018
1019 sdd->workqueue = create_singlethread_workqueue(
1020 dev_name(master->dev.parent));
1021 if (sdd->workqueue == NULL) {
1022 dev_err(&pdev->dev, "Unable to create workqueue\n");
1023 ret = -ENOMEM;
1024 goto err7;
1025 }
1026
1027 /* Setup Deufult Mode */
1028 s3c64xx_spi_hwinit(sdd, pdev->id);
1029
1030 spin_lock_init(&sdd->lock);
1031 init_completion(&sdd->xfer_completion);
1032 INIT_WORK(&sdd->work, s3c64xx_spi_work);
1033 INIT_LIST_HEAD(&sdd->queue);
1034
1035 if (spi_register_master(master)) {
1036 dev_err(&pdev->dev, "cannot register SPI master\n");
1037 ret = -EBUSY;
1038 goto err8;
1039 }
1040
1041 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d \
1042 with %d Slaves attached\n",
1043 pdev->id, master->num_chipselect);
1044 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\
1045 \tDMA=[Rx-%d, Tx-%d]\n",
1046 mem_res->end, mem_res->start,
1047 sdd->rx_dmach, sdd->tx_dmach);
1048
1049 return 0;
1050
1051err8:
1052 destroy_workqueue(sdd->workqueue);
1053err7:
b0d5d6e5 1054 clk_disable(sdd->src_clk);
230d42d4 1055err6:
b0d5d6e5 1056 clk_put(sdd->src_clk);
230d42d4
JB		 1057err5:
1058 clk_disable(sdd->clk);
1059err4:
1060 clk_put(sdd->clk);
1061err3:
1062err2:
1063 iounmap((void *) sdd->regs);
1064err1:
1065 release_mem_region(mem_res->start, resource_size(mem_res));
1066err0:
1067 platform_set_drvdata(pdev, NULL);
1068 spi_master_put(master);
1069
1070 return ret;
1071}
1072
1073static int s3c64xx_spi_remove(struct platform_device *pdev)
1074{
1075 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1076 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
230d42d4
JB		 1077 struct resource *mem_res;
1078 unsigned long flags;
1079
1080 spin_lock_irqsave(&sdd->lock, flags);
1081 sdd->state |= SUSPND;
1082 spin_unlock_irqrestore(&sdd->lock, flags);
1083
1084 while (sdd->state & SPIBUSY)
1085 msleep(10);
1086
1087 spi_unregister_master(master);
1088
1089 destroy_workqueue(sdd->workqueue);
1090
b0d5d6e5
JB		 1091 clk_disable(sdd->src_clk);
1092 clk_put(sdd->src_clk);
230d42d4
JB		 1093
1094 clk_disable(sdd->clk);
1095 clk_put(sdd->clk);
1096
1097 iounmap((void *) sdd->regs);
1098
1099 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ef6c680d
JB		 1100 if (mem_res != NULL)
1101 release_mem_region(mem_res->start, resource_size(mem_res));
230d42d4
JB		 1102
1103 platform_set_drvdata(pdev, NULL);
1104 spi_master_put(master);
1105
1106 return 0;
1107}
1108
1109#ifdef CONFIG_PM
1110static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1111{
1112 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1113 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
230d42d4
JB		 1114 unsigned long flags;
1115
1116 spin_lock_irqsave(&sdd->lock, flags);
1117 sdd->state |= SUSPND;
1118 spin_unlock_irqrestore(&sdd->lock, flags);
1119
1120 while (sdd->state & SPIBUSY)
1121 msleep(10);
1122
1123 /* Disable the clock */
b0d5d6e5 1124 clk_disable(sdd->src_clk);
230d42d4
JB		 1125 clk_disable(sdd->clk);
1126
1127 sdd->cur_speed = 0; /* Output Clock is stopped */
1128
1129 return 0;
1130}
1131
1132static int s3c64xx_spi_resume(struct platform_device *pdev)
1133{
1134 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
1135 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
ad7de729 1136 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
230d42d4
JB		 1137 unsigned long flags;
1138
1139 sci->cfg_gpio(pdev);
1140
1141 /* Enable the clock */
b0d5d6e5 1142 clk_enable(sdd->src_clk);
230d42d4
JB		 1143 clk_enable(sdd->clk);
1144
1145 s3c64xx_spi_hwinit(sdd, pdev->id);
1146
1147 spin_lock_irqsave(&sdd->lock, flags);
1148 sdd->state &= ~SUSPND;
1149 spin_unlock_irqrestore(&sdd->lock, flags);
1150
1151 return 0;
1152}
1153#else
1154#define s3c64xx_spi_suspend NULL
1155#define s3c64xx_spi_resume NULL
1156#endif /* CONFIG_PM */
1157
1158static struct platform_driver s3c64xx_spi_driver = {
1159 .driver = {
1160 .name = "s3c64xx-spi",
1161 .owner = THIS_MODULE,
1162 },
1163 .remove = s3c64xx_spi_remove,
1164 .suspend = s3c64xx_spi_suspend,
1165 .resume = s3c64xx_spi_resume,
1166};
1167MODULE_ALIAS("platform:s3c64xx-spi");
1168
1169static int __init s3c64xx_spi_init(void)
1170{
1171 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe);
1172}
1173module_init(s3c64xx_spi_init);
1174
1175static void __exit s3c64xx_spi_exit(void)
1176{
1177 platform_driver_unregister(&s3c64xx_spi_driver);
1178}
1179module_exit(s3c64xx_spi_exit);
1180
1181MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1182MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1183MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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