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61e115a5 MB |
1 | /* |
2 | * Sonics Silicon Backplane | |
3 | * Broadcom MIPS core driver | |
4 | * | |
5 | * Copyright 2005, Broadcom Corporation | |
eb032b98 | 6 | * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
61e115a5 MB |
7 | * |
8 | * Licensed under the GNU/GPL. See COPYING for details. | |
9 | */ | |
10 | ||
11 | #include <linux/ssb/ssb.h> | |
12 | ||
13 | #include <linux/serial.h> | |
14 | #include <linux/serial_core.h> | |
15 | #include <linux/serial_reg.h> | |
16 | #include <linux/time.h> | |
17 | ||
18 | #include "ssb_private.h" | |
19 | ||
20 | ||
21 | static inline u32 mips_read32(struct ssb_mipscore *mcore, | |
22 | u16 offset) | |
23 | { | |
24 | return ssb_read32(mcore->dev, offset); | |
25 | } | |
26 | ||
27 | static inline void mips_write32(struct ssb_mipscore *mcore, | |
28 | u16 offset, | |
29 | u32 value) | |
30 | { | |
31 | ssb_write32(mcore->dev, offset, value); | |
32 | } | |
33 | ||
34 | static const u32 ipsflag_irq_mask[] = { | |
35 | 0, | |
36 | SSB_IPSFLAG_IRQ1, | |
37 | SSB_IPSFLAG_IRQ2, | |
38 | SSB_IPSFLAG_IRQ3, | |
39 | SSB_IPSFLAG_IRQ4, | |
40 | }; | |
41 | ||
42 | static const u32 ipsflag_irq_shift[] = { | |
43 | 0, | |
44 | SSB_IPSFLAG_IRQ1_SHIFT, | |
45 | SSB_IPSFLAG_IRQ2_SHIFT, | |
46 | SSB_IPSFLAG_IRQ3_SHIFT, | |
47 | SSB_IPSFLAG_IRQ4_SHIFT, | |
48 | }; | |
49 | ||
50 | static inline u32 ssb_irqflag(struct ssb_device *dev) | |
51 | { | |
ea4bbfd0 | 52 | u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG); |
53 | if (tpsflag) | |
54 | return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG; | |
55 | else | |
56 | /* not irq supported */ | |
57 | return 0x3f; | |
58 | } | |
59 | ||
60 | static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag) | |
61 | { | |
62 | struct ssb_bus *bus = rdev->bus; | |
63 | int i; | |
64 | for (i = 0; i < bus->nr_devices; i++) { | |
65 | struct ssb_device *dev; | |
66 | dev = &(bus->devices[i]); | |
67 | if (ssb_irqflag(dev) == irqflag) | |
68 | return dev; | |
69 | } | |
70 | return NULL; | |
61e115a5 MB |
71 | } |
72 | ||
73 | /* Get the MIPS IRQ assignment for a specified device. | |
74 | * If unassigned, 0 is returned. | |
ea4bbfd0 | 75 | * If disabled, 5 is returned. |
76 | * If not supported, 6 is returned. | |
61e115a5 MB |
77 | */ |
78 | unsigned int ssb_mips_irq(struct ssb_device *dev) | |
79 | { | |
80 | struct ssb_bus *bus = dev->bus; | |
ea4bbfd0 | 81 | struct ssb_device *mdev = bus->mipscore.dev; |
61e115a5 MB |
82 | u32 irqflag; |
83 | u32 ipsflag; | |
84 | u32 tmp; | |
85 | unsigned int irq; | |
86 | ||
87 | irqflag = ssb_irqflag(dev); | |
ea4bbfd0 | 88 | if (irqflag == 0x3f) |
89 | return 6; | |
61e115a5 MB |
90 | ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG); |
91 | for (irq = 1; irq <= 4; irq++) { | |
92 | tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]); | |
93 | if (tmp == irqflag) | |
94 | break; | |
95 | } | |
ea4bbfd0 | 96 | if (irq == 5) { |
97 | if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)) | |
98 | irq = 0; | |
99 | } | |
61e115a5 MB |
100 | |
101 | return irq; | |
102 | } | |
103 | ||
104 | static void clear_irq(struct ssb_bus *bus, unsigned int irq) | |
105 | { | |
106 | struct ssb_device *dev = bus->mipscore.dev; | |
107 | ||
108 | /* Clear the IRQ in the MIPScore backplane registers */ | |
109 | if (irq == 0) { | |
110 | ssb_write32(dev, SSB_INTVEC, 0); | |
111 | } else { | |
112 | ssb_write32(dev, SSB_IPSFLAG, | |
113 | ssb_read32(dev, SSB_IPSFLAG) | | |
114 | ipsflag_irq_mask[irq]); | |
115 | } | |
116 | } | |
117 | ||
118 | static void set_irq(struct ssb_device *dev, unsigned int irq) | |
119 | { | |
120 | unsigned int oldirq = ssb_mips_irq(dev); | |
121 | struct ssb_bus *bus = dev->bus; | |
122 | struct ssb_device *mdev = bus->mipscore.dev; | |
123 | u32 irqflag = ssb_irqflag(dev); | |
124 | ||
ea4bbfd0 | 125 | BUG_ON(oldirq == 6); |
126 | ||
61e115a5 MB |
127 | dev->irq = irq + 2; |
128 | ||
61e115a5 MB |
129 | /* clear the old irq */ |
130 | if (oldirq == 0) | |
131 | ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))); | |
ea4bbfd0 | 132 | else if (oldirq != 5) |
61e115a5 MB |
133 | clear_irq(bus, oldirq); |
134 | ||
135 | /* assign the new one */ | |
2633da23 MB |
136 | if (irq == 0) { |
137 | ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC))); | |
138 | } else { | |
ea4bbfd0 | 139 | u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG); |
140 | if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) { | |
141 | u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]; | |
142 | struct ssb_device *olddev = find_device(dev, oldipsflag); | |
143 | if (olddev) | |
144 | set_irq(olddev, 0); | |
145 | } | |
2633da23 | 146 | irqflag <<= ipsflag_irq_shift[irq]; |
ea4bbfd0 | 147 | irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]); |
2633da23 MB |
148 | ssb_write32(mdev, SSB_IPSFLAG, irqflag); |
149 | } | |
ea4bbfd0 | 150 | ssb_dprintk(KERN_INFO PFX |
151 | "set_irq: core 0x%04x, irq %d => %d\n", | |
152 | dev->id.coreid, oldirq+2, irq+2); | |
153 | } | |
154 | ||
155 | static void print_irq(struct ssb_device *dev, unsigned int irq) | |
156 | { | |
157 | int i; | |
158 | static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"}; | |
159 | ssb_dprintk(KERN_INFO PFX | |
160 | "core 0x%04x, irq :", dev->id.coreid); | |
161 | for (i = 0; i <= 6; i++) { | |
162 | ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" "); | |
163 | } | |
164 | ssb_dprintk("\n"); | |
165 | } | |
166 | ||
167 | static void dump_irq(struct ssb_bus *bus) | |
168 | { | |
169 | int i; | |
170 | for (i = 0; i < bus->nr_devices; i++) { | |
171 | struct ssb_device *dev; | |
172 | dev = &(bus->devices[i]); | |
173 | print_irq(dev, ssb_mips_irq(dev)); | |
174 | } | |
61e115a5 MB |
175 | } |
176 | ||
177 | static void ssb_mips_serial_init(struct ssb_mipscore *mcore) | |
178 | { | |
179 | struct ssb_bus *bus = mcore->dev->bus; | |
180 | ||
0362063b | 181 | if (ssb_extif_available(&bus->extif)) |
61e115a5 | 182 | mcore->nr_serial_ports = ssb_extif_serial_init(&bus->extif, mcore->serial_ports); |
0362063b | 183 | else if (ssb_chipco_available(&bus->chipco)) |
61e115a5 MB |
184 | mcore->nr_serial_ports = ssb_chipco_serial_init(&bus->chipco, mcore->serial_ports); |
185 | else | |
186 | mcore->nr_serial_ports = 0; | |
187 | } | |
188 | ||
189 | static void ssb_mips_flash_detect(struct ssb_mipscore *mcore) | |
190 | { | |
191 | struct ssb_bus *bus = mcore->dev->bus; | |
f1ab57e3 | 192 | struct ssb_pflash *pflash = &mcore->pflash; |
61e115a5 | 193 | |
902d9e0f | 194 | /* When there is no chipcommon on the bus there is 4MB flash */ |
0362063b | 195 | if (!ssb_chipco_available(&bus->chipco)) { |
f1ab57e3 RM |
196 | pflash->present = true; |
197 | pflash->buswidth = 2; | |
198 | pflash->window = SSB_FLASH1; | |
199 | pflash->window_size = SSB_FLASH1_SZ; | |
902d9e0f RM |
200 | return; |
201 | } | |
202 | ||
203 | /* There is ChipCommon, so use it to read info about flash */ | |
204 | switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) { | |
205 | case SSB_CHIPCO_FLASHT_STSER: | |
206 | case SSB_CHIPCO_FLASHT_ATSER: | |
72a525cb RM |
207 | pr_debug("Found serial flash\n"); |
208 | ssb_sflash_init(&bus->chipco); | |
902d9e0f RM |
209 | break; |
210 | case SSB_CHIPCO_FLASHT_PARA: | |
211 | pr_debug("Found parallel flash\n"); | |
f1ab57e3 RM |
212 | pflash->present = true; |
213 | pflash->window = SSB_FLASH2; | |
214 | pflash->window_size = SSB_FLASH2_SZ; | |
61e115a5 MB |
215 | if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG) |
216 | & SSB_CHIPCO_CFG_DS16) == 0) | |
f1ab57e3 | 217 | pflash->buswidth = 1; |
902d9e0f | 218 | else |
f1ab57e3 | 219 | pflash->buswidth = 2; |
902d9e0f | 220 | break; |
61e115a5 MB |
221 | } |
222 | } | |
223 | ||
224 | u32 ssb_cpu_clock(struct ssb_mipscore *mcore) | |
225 | { | |
226 | struct ssb_bus *bus = mcore->dev->bus; | |
227 | u32 pll_type, n, m, rate = 0; | |
228 | ||
d486a5b4 HM |
229 | if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU) |
230 | return ssb_pmu_get_cpu_clock(&bus->chipco); | |
231 | ||
0362063b | 232 | if (ssb_extif_available(&bus->extif)) { |
61e115a5 | 233 | ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m); |
0362063b | 234 | } else if (ssb_chipco_available(&bus->chipco)) { |
61e115a5 MB |
235 | ssb_chipco_get_clockcpu(&bus->chipco, &pll_type, &n, &m); |
236 | } else | |
237 | return 0; | |
238 | ||
239 | if ((pll_type == SSB_PLLTYPE_5) || (bus->chip_id == 0x5365)) { | |
240 | rate = 200000000; | |
241 | } else { | |
242 | rate = ssb_calc_clock_rate(pll_type, n, m); | |
243 | } | |
244 | ||
245 | if (pll_type == SSB_PLLTYPE_6) { | |
246 | rate *= 2; | |
247 | } | |
248 | ||
249 | return rate; | |
250 | } | |
251 | ||
252 | void ssb_mipscore_init(struct ssb_mipscore *mcore) | |
253 | { | |
7007d00c | 254 | struct ssb_bus *bus; |
61e115a5 MB |
255 | struct ssb_device *dev; |
256 | unsigned long hz, ns; | |
257 | unsigned int irq, i; | |
258 | ||
259 | if (!mcore->dev) | |
260 | return; /* We don't have a MIPS core */ | |
261 | ||
262 | ssb_dprintk(KERN_INFO PFX "Initializing MIPS core...\n"); | |
263 | ||
7007d00c | 264 | bus = mcore->dev->bus; |
61e115a5 MB |
265 | hz = ssb_clockspeed(bus); |
266 | if (!hz) | |
267 | hz = 100000000; | |
268 | ns = 1000000000 / hz; | |
269 | ||
0362063b | 270 | if (ssb_extif_available(&bus->extif)) |
61e115a5 | 271 | ssb_extif_timing_init(&bus->extif, ns); |
0362063b | 272 | else if (ssb_chipco_available(&bus->chipco)) |
61e115a5 MB |
273 | ssb_chipco_timing_init(&bus->chipco, ns); |
274 | ||
275 | /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */ | |
276 | for (irq = 2, i = 0; i < bus->nr_devices; i++) { | |
ea4bbfd0 | 277 | int mips_irq; |
61e115a5 | 278 | dev = &(bus->devices[i]); |
ea4bbfd0 | 279 | mips_irq = ssb_mips_irq(dev); |
280 | if (mips_irq > 4) | |
281 | dev->irq = 0; | |
282 | else | |
283 | dev->irq = mips_irq + 2; | |
284 | if (dev->irq > 5) | |
285 | continue; | |
61e115a5 MB |
286 | switch (dev->id.coreid) { |
287 | case SSB_DEV_USB11_HOST: | |
288 | /* shouldn't need a separate irq line for non-4710, most of them have a proper | |
289 | * external usb controller on the pci */ | |
290 | if ((bus->chip_id == 0x4710) && (irq <= 4)) { | |
291 | set_irq(dev, irq++); | |
61e115a5 | 292 | } |
ea4bbfd0 | 293 | break; |
61e115a5 MB |
294 | case SSB_DEV_PCI: |
295 | case SSB_DEV_ETHERNET: | |
aab547ce | 296 | case SSB_DEV_ETHERNET_GBIT: |
61e115a5 MB |
297 | case SSB_DEV_80211: |
298 | case SSB_DEV_USB20_HOST: | |
299 | /* These devices get their own IRQ line if available, the rest goes on IRQ0 */ | |
300 | if (irq <= 4) { | |
301 | set_irq(dev, irq++); | |
302 | break; | |
303 | } | |
83e34f03 JF |
304 | /* fallthrough */ |
305 | case SSB_DEV_EXTIF: | |
306 | set_irq(dev, 0); | |
307 | break; | |
61e115a5 MB |
308 | } |
309 | } | |
ea4bbfd0 | 310 | ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); |
311 | dump_irq(bus); | |
61e115a5 MB |
312 | |
313 | ssb_mips_serial_init(mcore); | |
314 | ssb_mips_flash_detect(mcore); | |
315 | } |