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61e115a5 MB |
1 | /* |
2 | * Sonics Silicon Backplane | |
3 | * Broadcom PCI-core driver | |
4 | * | |
5 | * Copyright 2005, Broadcom Corporation | |
6 | * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de> | |
7 | * | |
8 | * Licensed under the GNU/GPL. See COPYING for details. | |
9 | */ | |
10 | ||
11 | #include <linux/ssb/ssb.h> | |
12 | #include <linux/pci.h> | |
13 | #include <linux/delay.h> | |
7cb44615 | 14 | #include <linux/ssb/ssb_embedded.h> |
61e115a5 MB |
15 | |
16 | #include "ssb_private.h" | |
17 | ||
18 | ||
19 | static inline | |
20 | u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) | |
21 | { | |
22 | return ssb_read32(pc->dev, offset); | |
23 | } | |
24 | ||
25 | static inline | |
26 | void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value) | |
27 | { | |
28 | ssb_write32(pc->dev, offset, value); | |
29 | } | |
30 | ||
7cb44615 MB |
31 | static inline |
32 | u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset) | |
33 | { | |
34 | return ssb_read16(pc->dev, offset); | |
35 | } | |
36 | ||
37 | static inline | |
38 | void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value) | |
39 | { | |
40 | ssb_write16(pc->dev, offset, value); | |
41 | } | |
42 | ||
61e115a5 MB |
43 | /************************************************** |
44 | * Code for hostmode operation. | |
45 | **************************************************/ | |
46 | ||
47 | #ifdef CONFIG_SSB_PCICORE_HOSTMODE | |
48 | ||
49 | #include <asm/paccess.h> | |
50 | /* Probe a 32bit value on the bus and catch bus exceptions. | |
51 | * Returns nonzero on a bus exception. | |
52 | * This is MIPS specific */ | |
53 | #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) | |
54 | ||
55 | /* Assume one-hot slot wiring */ | |
56 | #define SSB_PCI_SLOT_MAX 16 | |
57 | ||
58 | /* Global lock is OK, as we won't have more than one extpci anyway. */ | |
59 | static DEFINE_SPINLOCK(cfgspace_lock); | |
60 | /* Core to access the external PCI config space. Can only have one. */ | |
61 | static struct ssb_pcicore *extpci_core; | |
62 | ||
61e115a5 MB |
63 | |
64 | static u32 get_cfgspace_addr(struct ssb_pcicore *pc, | |
65 | unsigned int bus, unsigned int dev, | |
66 | unsigned int func, unsigned int off) | |
67 | { | |
68 | u32 addr = 0; | |
69 | u32 tmp; | |
70 | ||
7cb44615 MB |
71 | /* We do only have one cardbus device behind the bridge. */ |
72 | if (pc->cardbusmode && (dev >= 1)) | |
61e115a5 | 73 | goto out; |
7cb44615 | 74 | |
61e115a5 MB |
75 | if (bus == 0) { |
76 | /* Type 0 transaction */ | |
77 | if (unlikely(dev >= SSB_PCI_SLOT_MAX)) | |
78 | goto out; | |
79 | /* Slide the window */ | |
80 | tmp = SSB_PCICORE_SBTOPCI_CFG0; | |
81 | tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK); | |
82 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp); | |
83 | /* Calculate the address */ | |
84 | addr = SSB_PCI_CFG; | |
85 | addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK); | |
86 | addr |= (func << 8); | |
87 | addr |= (off & ~3); | |
88 | } else { | |
89 | /* Type 1 transaction */ | |
90 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, | |
91 | SSB_PCICORE_SBTOPCI_CFG1); | |
92 | /* Calculate the address */ | |
93 | addr = SSB_PCI_CFG; | |
94 | addr |= (bus << 16); | |
95 | addr |= (dev << 11); | |
96 | addr |= (func << 8); | |
97 | addr |= (off & ~3); | |
98 | } | |
99 | out: | |
100 | return addr; | |
101 | } | |
102 | ||
103 | static int ssb_extpci_read_config(struct ssb_pcicore *pc, | |
104 | unsigned int bus, unsigned int dev, | |
105 | unsigned int func, unsigned int off, | |
106 | void *buf, int len) | |
107 | { | |
108 | int err = -EINVAL; | |
109 | u32 addr, val; | |
110 | void __iomem *mmio; | |
111 | ||
112 | SSB_WARN_ON(!pc->hostmode); | |
113 | if (unlikely(len != 1 && len != 2 && len != 4)) | |
114 | goto out; | |
115 | addr = get_cfgspace_addr(pc, bus, dev, func, off); | |
116 | if (unlikely(!addr)) | |
117 | goto out; | |
118 | err = -ENOMEM; | |
119 | mmio = ioremap_nocache(addr, len); | |
120 | if (!mmio) | |
121 | goto out; | |
122 | ||
123 | if (mips_busprobe32(val, mmio)) { | |
124 | val = 0xffffffff; | |
125 | goto unmap; | |
126 | } | |
127 | ||
128 | val = readl(mmio); | |
129 | val >>= (8 * (off & 3)); | |
130 | ||
131 | switch (len) { | |
132 | case 1: | |
133 | *((u8 *)buf) = (u8)val; | |
134 | break; | |
135 | case 2: | |
136 | *((u16 *)buf) = (u16)val; | |
137 | break; | |
138 | case 4: | |
139 | *((u32 *)buf) = (u32)val; | |
140 | break; | |
141 | } | |
142 | err = 0; | |
143 | unmap: | |
144 | iounmap(mmio); | |
145 | out: | |
146 | return err; | |
147 | } | |
148 | ||
149 | static int ssb_extpci_write_config(struct ssb_pcicore *pc, | |
150 | unsigned int bus, unsigned int dev, | |
151 | unsigned int func, unsigned int off, | |
152 | const void *buf, int len) | |
153 | { | |
154 | int err = -EINVAL; | |
155 | u32 addr, val = 0; | |
156 | void __iomem *mmio; | |
157 | ||
158 | SSB_WARN_ON(!pc->hostmode); | |
159 | if (unlikely(len != 1 && len != 2 && len != 4)) | |
160 | goto out; | |
161 | addr = get_cfgspace_addr(pc, bus, dev, func, off); | |
162 | if (unlikely(!addr)) | |
163 | goto out; | |
164 | err = -ENOMEM; | |
165 | mmio = ioremap_nocache(addr, len); | |
166 | if (!mmio) | |
167 | goto out; | |
168 | ||
169 | if (mips_busprobe32(val, mmio)) { | |
170 | val = 0xffffffff; | |
171 | goto unmap; | |
172 | } | |
173 | ||
174 | switch (len) { | |
175 | case 1: | |
176 | val = readl(mmio); | |
177 | val &= ~(0xFF << (8 * (off & 3))); | |
178 | val |= *((const u8 *)buf) << (8 * (off & 3)); | |
179 | break; | |
180 | case 2: | |
181 | val = readl(mmio); | |
182 | val &= ~(0xFFFF << (8 * (off & 3))); | |
183 | val |= *((const u16 *)buf) << (8 * (off & 3)); | |
184 | break; | |
185 | case 4: | |
186 | val = *((const u32 *)buf); | |
187 | break; | |
188 | } | |
189 | writel(val, mmio); | |
190 | ||
191 | err = 0; | |
192 | unmap: | |
193 | iounmap(mmio); | |
194 | out: | |
195 | return err; | |
196 | } | |
197 | ||
198 | static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn, | |
199 | int reg, int size, u32 *val) | |
200 | { | |
201 | unsigned long flags; | |
202 | int err; | |
203 | ||
204 | spin_lock_irqsave(&cfgspace_lock, flags); | |
205 | err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn), | |
206 | PCI_FUNC(devfn), reg, val, size); | |
207 | spin_unlock_irqrestore(&cfgspace_lock, flags); | |
208 | ||
209 | return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; | |
210 | } | |
211 | ||
212 | static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn, | |
213 | int reg, int size, u32 val) | |
214 | { | |
215 | unsigned long flags; | |
216 | int err; | |
217 | ||
218 | spin_lock_irqsave(&cfgspace_lock, flags); | |
219 | err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn), | |
220 | PCI_FUNC(devfn), reg, &val, size); | |
221 | spin_unlock_irqrestore(&cfgspace_lock, flags); | |
222 | ||
223 | return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; | |
224 | } | |
225 | ||
226 | static struct pci_ops ssb_pcicore_pciops = { | |
227 | .read = ssb_pcicore_read_config, | |
228 | .write = ssb_pcicore_write_config, | |
229 | }; | |
230 | ||
231 | static struct resource ssb_pcicore_mem_resource = { | |
232 | .name = "SSB PCIcore external memory", | |
233 | .start = SSB_PCI_DMA, | |
234 | .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1, | |
fc71acc8 | 235 | .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED, |
61e115a5 MB |
236 | }; |
237 | ||
238 | static struct resource ssb_pcicore_io_resource = { | |
239 | .name = "SSB PCIcore external I/O", | |
240 | .start = 0x100, | |
241 | .end = 0x7FF, | |
fc71acc8 | 242 | .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED, |
61e115a5 MB |
243 | }; |
244 | ||
245 | static struct pci_controller ssb_pcicore_controller = { | |
246 | .pci_ops = &ssb_pcicore_pciops, | |
247 | .io_resource = &ssb_pcicore_io_resource, | |
248 | .mem_resource = &ssb_pcicore_mem_resource, | |
249 | .mem_offset = 0x24000000, | |
250 | }; | |
251 | ||
aab547ce MB |
252 | static u32 ssb_pcicore_pcibus_iobase = 0x100; |
253 | static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA; | |
254 | ||
255 | /* This function is called when doing a pci_enable_device(). | |
256 | * We must first check if the device is a device on the PCI-core bridge. */ | |
257 | int ssb_pcicore_plat_dev_init(struct pci_dev *d) | |
258 | { | |
259 | struct resource *res; | |
260 | int pos, size; | |
261 | u32 *base; | |
262 | ||
263 | if (d->bus->ops != &ssb_pcicore_pciops) { | |
264 | /* This is not a device on the PCI-core bridge. */ | |
265 | return -ENODEV; | |
266 | } | |
267 | ||
268 | ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", | |
269 | pci_name(d)); | |
270 | ||
271 | /* Fix up resource bases */ | |
272 | for (pos = 0; pos < 6; pos++) { | |
273 | res = &d->resource[pos]; | |
274 | if (res->flags & IORESOURCE_IO) | |
275 | base = &ssb_pcicore_pcibus_iobase; | |
276 | else | |
277 | base = &ssb_pcicore_pcibus_membase; | |
278 | res->flags |= IORESOURCE_PCI_FIXED; | |
279 | if (res->end) { | |
280 | size = res->end - res->start + 1; | |
281 | if (*base & (size - 1)) | |
282 | *base = (*base + size) & ~(size - 1); | |
283 | res->start = *base; | |
284 | res->end = res->start + size - 1; | |
285 | *base += size; | |
286 | pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start); | |
287 | } | |
288 | /* Fix up PCI bridge BAR0 only */ | |
289 | if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0) | |
290 | break; | |
291 | } | |
292 | /* Fix up interrupt lines */ | |
293 | d->irq = ssb_mips_irq(extpci_core->dev) + 2; | |
294 | pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); | |
295 | ||
296 | return 0; | |
297 | } | |
298 | ||
299 | /* Early PCI fixup for a device on the PCI-core bridge. */ | |
300 | static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) | |
301 | { | |
302 | u8 lat; | |
303 | ||
304 | if (dev->bus->ops != &ssb_pcicore_pciops) { | |
305 | /* This is not a device on the PCI-core bridge. */ | |
306 | return; | |
307 | } | |
308 | if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) | |
309 | return; | |
310 | ||
311 | ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev)); | |
312 | ||
313 | /* Enable PCI bridge bus mastering and memory space */ | |
314 | pci_set_master(dev); | |
315 | if (pcibios_enable_device(dev, ~0) < 0) { | |
316 | ssb_printk(KERN_ERR "PCI: SSB bridge enable failed\n"); | |
317 | return; | |
318 | } | |
319 | ||
320 | /* Enable PCI bridge BAR1 prefetch and burst */ | |
321 | pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); | |
322 | ||
323 | /* Make sure our latency is high enough to handle the devices behind us */ | |
324 | lat = 168; | |
325 | ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n", | |
326 | pci_name(dev), lat); | |
327 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); | |
328 | } | |
329 | DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge); | |
330 | ||
331 | /* PCI device IRQ mapping. */ | |
332 | int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) | |
333 | { | |
334 | if (dev->bus->ops != &ssb_pcicore_pciops) { | |
335 | /* This is not a device on the PCI-core bridge. */ | |
336 | return -ENODEV; | |
337 | } | |
338 | return ssb_mips_irq(extpci_core->dev) + 2; | |
339 | } | |
340 | ||
61e115a5 MB |
341 | static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) |
342 | { | |
343 | u32 val; | |
344 | ||
345 | if (WARN_ON(extpci_core)) | |
346 | return; | |
347 | extpci_core = pc; | |
348 | ||
349 | ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n"); | |
350 | /* Reset devices on the external PCI bus */ | |
351 | val = SSB_PCICORE_CTL_RST_OE; | |
352 | val |= SSB_PCICORE_CTL_CLK_OE; | |
353 | pcicore_write32(pc, SSB_PCICORE_CTL, val); | |
354 | val |= SSB_PCICORE_CTL_CLK; /* Clock on */ | |
355 | pcicore_write32(pc, SSB_PCICORE_CTL, val); | |
356 | udelay(150); /* Assertion time demanded by the PCI standard */ | |
357 | val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ | |
358 | pcicore_write32(pc, SSB_PCICORE_CTL, val); | |
359 | val = SSB_PCICORE_ARBCTL_INTERN; | |
360 | pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); | |
361 | udelay(1); /* Assertion time demanded by the PCI standard */ | |
362 | ||
7cb44615 MB |
363 | if (pc->dev->bus->has_cardbus_slot) { |
364 | ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n"); | |
365 | pc->cardbusmode = 1; | |
366 | /* GPIO 1 resets the bridge */ | |
367 | ssb_gpio_out(pc->dev->bus, 1, 1); | |
368 | ssb_gpio_outen(pc->dev->bus, 1, 1); | |
369 | pcicore_write16(pc, SSB_PCICORE_SPROM(0), | |
370 | pcicore_read16(pc, SSB_PCICORE_SPROM(0)) | |
371 | | 0x0400); | |
372 | } | |
61e115a5 MB |
373 | |
374 | /* 64MB I/O window */ | |
375 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, | |
376 | SSB_PCICORE_SBTOPCI_IO); | |
377 | /* 64MB config space */ | |
378 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, | |
379 | SSB_PCICORE_SBTOPCI_CFG0); | |
380 | /* 1GB memory window */ | |
381 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, | |
382 | SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); | |
383 | ||
384 | /* Enable PCI bridge BAR0 prefetch and burst */ | |
385 | val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; | |
386 | ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); | |
387 | /* Clear error conditions */ | |
388 | val = 0; | |
389 | ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); | |
390 | ||
391 | /* Enable PCI interrupts */ | |
392 | pcicore_write32(pc, SSB_PCICORE_IMASK, | |
393 | SSB_PCICORE_IMASK_INTA); | |
394 | ||
395 | /* Ok, ready to run, register it to the system. | |
396 | * The following needs change, if we want to port hostmode | |
397 | * to non-MIPS platform. */ | |
fc71acc8 MB |
398 | ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000); |
399 | set_io_port_base(ssb_pcicore_controller.io_map_base); | |
61e115a5 MB |
400 | /* Give some time to the PCI controller to configure itself with the new |
401 | * values. Not waiting at this point causes crashes of the machine. */ | |
402 | mdelay(10); | |
403 | register_pci_controller(&ssb_pcicore_controller); | |
404 | } | |
405 | ||
406 | static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) | |
407 | { | |
408 | struct ssb_bus *bus = pc->dev->bus; | |
409 | u16 chipid_top; | |
410 | u32 tmp; | |
411 | ||
412 | chipid_top = (bus->chip_id & 0xFF00); | |
413 | if (chipid_top != 0x4700 && | |
414 | chipid_top != 0x5300) | |
415 | return 0; | |
416 | ||
2d8d4fdf | 417 | if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI) |
61e115a5 MB |
418 | return 0; |
419 | ||
420 | /* The 200-pin BCM4712 package does not bond out PCI. Even when | |
421 | * PCI is bonded out, some boards may leave the pins floating. */ | |
422 | if (bus->chip_id == 0x4712) { | |
423 | if (bus->chip_package == SSB_CHIPPACK_BCM4712S) | |
424 | return 0; | |
425 | if (bus->chip_package == SSB_CHIPPACK_BCM4712M) | |
426 | return 0; | |
427 | } | |
428 | if (bus->chip_id == 0x5350) | |
429 | return 0; | |
430 | ||
431 | return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE))); | |
432 | } | |
433 | #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ | |
434 | ||
435 | ||
436 | /************************************************** | |
437 | * Generic and Clientmode operation code. | |
438 | **************************************************/ | |
439 | ||
440 | static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) | |
441 | { | |
442 | /* Disable PCI interrupts. */ | |
443 | ssb_write32(pc->dev, SSB_INTVEC, 0); | |
444 | } | |
445 | ||
446 | void ssb_pcicore_init(struct ssb_pcicore *pc) | |
447 | { | |
448 | struct ssb_device *dev = pc->dev; | |
449 | struct ssb_bus *bus; | |
450 | ||
451 | if (!dev) | |
452 | return; | |
453 | bus = dev->bus; | |
454 | if (!ssb_device_is_enabled(dev)) | |
455 | ssb_device_enable(dev, 0); | |
456 | ||
457 | #ifdef CONFIG_SSB_PCICORE_HOSTMODE | |
458 | pc->hostmode = pcicore_is_in_hostmode(pc); | |
459 | if (pc->hostmode) | |
460 | ssb_pcicore_init_hostmode(pc); | |
461 | #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ | |
462 | if (!pc->hostmode) | |
463 | ssb_pcicore_init_clientmode(pc); | |
464 | } | |
465 | ||
466 | static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) | |
467 | { | |
468 | pcicore_write32(pc, 0x130, address); | |
469 | return pcicore_read32(pc, 0x134); | |
470 | } | |
471 | ||
472 | static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data) | |
473 | { | |
474 | pcicore_write32(pc, 0x130, address); | |
475 | pcicore_write32(pc, 0x134, data); | |
476 | } | |
477 | ||
478 | static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, | |
479 | u8 address, u16 data) | |
480 | { | |
481 | const u16 mdio_control = 0x128; | |
482 | const u16 mdio_data = 0x12C; | |
483 | u32 v; | |
484 | int i; | |
485 | ||
486 | v = 0x80; /* Enable Preamble Sequence */ | |
487 | v |= 0x2; /* MDIO Clock Divisor */ | |
488 | pcicore_write32(pc, mdio_control, v); | |
489 | ||
490 | v = (1 << 30); /* Start of Transaction */ | |
491 | v |= (1 << 28); /* Write Transaction */ | |
492 | v |= (1 << 17); /* Turnaround */ | |
493 | v |= (u32)device << 22; | |
494 | v |= (u32)address << 18; | |
495 | v |= data; | |
496 | pcicore_write32(pc, mdio_data, v); | |
497 | /* Wait for the device to complete the transaction */ | |
498 | udelay(10); | |
499 | for (i = 0; i < 10; i++) { | |
500 | v = pcicore_read32(pc, mdio_control); | |
501 | if (v & 0x100 /* Trans complete */) | |
502 | break; | |
503 | msleep(1); | |
504 | } | |
505 | pcicore_write32(pc, mdio_control, 0); | |
506 | } | |
507 | ||
508 | static void ssb_broadcast_value(struct ssb_device *dev, | |
509 | u32 address, u32 data) | |
510 | { | |
511 | /* This is used for both, PCI and ChipCommon core, so be careful. */ | |
512 | BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR); | |
513 | BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA); | |
514 | ||
515 | ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address); | |
516 | ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */ | |
517 | ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data); | |
518 | ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */ | |
519 | } | |
520 | ||
521 | static void ssb_commit_settings(struct ssb_bus *bus) | |
522 | { | |
523 | struct ssb_device *dev; | |
524 | ||
525 | dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev; | |
526 | if (WARN_ON(!dev)) | |
527 | return; | |
528 | /* This forces an update of the cached registers. */ | |
529 | ssb_broadcast_value(dev, 0xFD8, 0); | |
530 | } | |
531 | ||
532 | int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, | |
533 | struct ssb_device *dev) | |
534 | { | |
535 | struct ssb_device *pdev = pc->dev; | |
536 | struct ssb_bus *bus; | |
537 | int err = 0; | |
538 | u32 tmp; | |
539 | ||
540 | might_sleep(); | |
541 | ||
542 | if (!pdev) | |
543 | goto out; | |
544 | bus = pdev->bus; | |
545 | ||
546 | /* Enable interrupts for this device. */ | |
547 | if (bus->host_pci && | |
548 | ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) { | |
549 | u32 coremask; | |
550 | ||
551 | /* Calculate the "coremask" for the device. */ | |
552 | coremask = (1 << dev->core_index); | |
553 | ||
554 | err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); | |
555 | if (err) | |
556 | goto out; | |
557 | tmp |= coremask << 8; | |
558 | err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp); | |
559 | if (err) | |
560 | goto out; | |
561 | } else { | |
562 | u32 intvec; | |
563 | ||
564 | intvec = ssb_read32(pdev, SSB_INTVEC); | |
51e8b885 MB |
565 | tmp = ssb_read32(dev, SSB_TPSFLAG); |
566 | tmp &= SSB_TPSFLAG_BPFLAG; | |
567 | intvec |= (1 << tmp); | |
61e115a5 MB |
568 | ssb_write32(pdev, SSB_INTVEC, intvec); |
569 | } | |
570 | ||
571 | /* Setup PCIcore operation. */ | |
572 | if (pc->setup_done) | |
573 | goto out; | |
574 | if (pdev->id.coreid == SSB_DEV_PCI) { | |
575 | tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); | |
576 | tmp |= SSB_PCICORE_SBTOPCI_PREF; | |
577 | tmp |= SSB_PCICORE_SBTOPCI_BURST; | |
578 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); | |
579 | ||
580 | if (pdev->id.revision < 5) { | |
581 | tmp = ssb_read32(pdev, SSB_IMCFGLO); | |
582 | tmp &= ~SSB_IMCFGLO_SERTO; | |
583 | tmp |= 2; | |
584 | tmp &= ~SSB_IMCFGLO_REQTO; | |
585 | tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; | |
586 | ssb_write32(pdev, SSB_IMCFGLO, tmp); | |
587 | ssb_commit_settings(bus); | |
588 | } else if (pdev->id.revision >= 11) { | |
589 | tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); | |
590 | tmp |= SSB_PCICORE_SBTOPCI_MRM; | |
591 | pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); | |
592 | } | |
593 | } else { | |
594 | WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); | |
595 | //TODO: Better make defines for all these magic PCIE values. | |
596 | if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) { | |
597 | /* TLP Workaround register. */ | |
598 | tmp = ssb_pcie_read(pc, 0x4); | |
599 | tmp |= 0x8; | |
600 | ssb_pcie_write(pc, 0x4, tmp); | |
601 | } | |
602 | if (pdev->id.revision == 0) { | |
603 | const u8 serdes_rx_device = 0x1F; | |
604 | ||
605 | ssb_pcie_mdio_write(pc, serdes_rx_device, | |
606 | 2 /* Timer */, 0x8128); | |
607 | ssb_pcie_mdio_write(pc, serdes_rx_device, | |
608 | 6 /* CDR */, 0x0100); | |
609 | ssb_pcie_mdio_write(pc, serdes_rx_device, | |
610 | 7 /* CDR BW */, 0x1466); | |
611 | } else if (pdev->id.revision == 1) { | |
612 | /* DLLP Link Control register. */ | |
613 | tmp = ssb_pcie_read(pc, 0x100); | |
614 | tmp |= 0x40; | |
615 | ssb_pcie_write(pc, 0x100, tmp); | |
616 | } | |
617 | } | |
618 | pc->setup_done = 1; | |
619 | out: | |
620 | return err; | |
621 | } | |
622 | EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable); |