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Don't build bcm43xx if SSB is static and b43 PCI-SSB bridge is enabled.
[deliverable/linux.git] / drivers / ssb / driver_pcicore.c
CommitLineData
61e115a5
MB		 1/*
2 * Sonics Silicon Backplane
3 * Broadcom PCI-core driver
4 *
5 * Copyright 2005, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
7 *
8 * Licensed under the GNU/GPL. See COPYING for details.
9 */
10
11#include <linux/ssb/ssb.h>
12#include <linux/pci.h>
13#include <linux/delay.h>
7cb44615 14#include <linux/ssb/ssb_embedded.h>
61e115a5
MB		 15
16#include "ssb_private.h"
17
18
19static inline
20u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
21{
22 return ssb_read32(pc->dev, offset);
23}
24
25static inline
26void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value)
27{
28 ssb_write32(pc->dev, offset, value);
29}
30
7cb44615
MB		 31static inline
32u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset)
33{
34 return ssb_read16(pc->dev, offset);
35}
36
37static inline
38void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value)
39{
40 ssb_write16(pc->dev, offset, value);
41}
42
61e115a5
MB		 43/**************************************************
44 * Code for hostmode operation.
45 **************************************************/
46
47#ifdef CONFIG_SSB_PCICORE_HOSTMODE
48
49#include <asm/paccess.h>
50/* Probe a 32bit value on the bus and catch bus exceptions.
51 * Returns nonzero on a bus exception.
52 * This is MIPS specific */
53#define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
54
55/* Assume one-hot slot wiring */
56#define SSB_PCI_SLOT_MAX 16
57
58/* Global lock is OK, as we won't have more than one extpci anyway. */
59static DEFINE_SPINLOCK(cfgspace_lock);
60/* Core to access the external PCI config space. Can only have one. */
61static struct ssb_pcicore *extpci_core;
62
63static u32 ssb_pcicore_pcibus_iobase = 0x100;
64static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
65
66int pcibios_plat_dev_init(struct pci_dev *d)
67{
68 struct resource *res;
69 int pos, size;
70 u32 *base;
71
72 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
73 pci_name(d));
74
75 /* Fix up resource bases */
76 for (pos = 0; pos < 6; pos++) {
77 res = &d->resource[pos];
78 if (res->flags & IORESOURCE_IO)
79 base = &ssb_pcicore_pcibus_iobase;
80 else
81 base = &ssb_pcicore_pcibus_membase;
fc71acc8 82 res->flags |= IORESOURCE_PCI_FIXED;
61e115a5
MB		 83 if (res->end) {
84 size = res->end - res->start + 1;
85 if (*base & (size - 1))
86 *base = (*base + size) & ~(size - 1);
87 res->start = *base;
88 res->end = res->start + size - 1;
89 *base += size;
90 pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
91 }
92 /* Fix up PCI bridge BAR0 only */
93 if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
94 break;
95 }
96 /* Fix up interrupt lines */
97 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
98 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
99
100 return 0;
101}
102
103static void __init ssb_fixup_pcibridge(struct pci_dev *dev)
104{
fc71acc8
MB		 105 u8 lat;
106
61e115a5
MB		 107 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0)
108 return;
109
fc71acc8 110 ssb_printk(KERN_INFO "PCI: Fixing up bridge %s\n", pci_name(dev));
61e115a5
MB		 111
112 /* Enable PCI bridge bus mastering and memory space */
113 pci_set_master(dev);
114 pcibios_enable_device(dev, ~0);
115
116 /* Enable PCI bridge BAR1 prefetch and burst */
117 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
118
119 /* Make sure our latency is high enough to handle the devices behind us */
fc71acc8
MB		 120 lat = 168;
121 ssb_printk(KERN_INFO "PCI: Fixing latency timer of device %s to %u\n",
122 pci_name(dev), lat);
123 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
61e115a5
MB		 124}
125DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
126
127int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
128{
129 return ssb_mips_irq(extpci_core->dev) + 2;
130}
131
132static u32 get_cfgspace_addr(struct ssb_pcicore *pc,
133 unsigned int bus, unsigned int dev,
134 unsigned int func, unsigned int off)
135{
136 u32 addr = 0;
137 u32 tmp;
138
7cb44615
MB		 139 /* We do only have one cardbus device behind the bridge. */
140 if (pc->cardbusmode && (dev >= 1))
61e115a5 141 goto out;
7cb44615 142
61e115a5
MB		 143 if (bus == 0) {
144 /* Type 0 transaction */
145 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
146 goto out;
147 /* Slide the window */
148 tmp = SSB_PCICORE_SBTOPCI_CFG0;
149 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK);
150 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp);
151 /* Calculate the address */
152 addr = SSB_PCI_CFG;
153 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK);
154 addr |= (func << 8);
155 addr |= (off & ~3);
156 } else {
157 /* Type 1 transaction */
158 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
159 SSB_PCICORE_SBTOPCI_CFG1);
160 /* Calculate the address */
161 addr = SSB_PCI_CFG;
162 addr |= (bus << 16);
163 addr |= (dev << 11);
164 addr |= (func << 8);
165 addr |= (off & ~3);
166 }
167out:
168 return addr;
169}
170
171static int ssb_extpci_read_config(struct ssb_pcicore *pc,
172 unsigned int bus, unsigned int dev,
173 unsigned int func, unsigned int off,
174 void *buf, int len)
175{
176 int err = -EINVAL;
177 u32 addr, val;
178 void __iomem *mmio;
179
180 SSB_WARN_ON(!pc->hostmode);
181 if (unlikely(len != 1 && len != 2 && len != 4))
182 goto out;
183 addr = get_cfgspace_addr(pc, bus, dev, func, off);
184 if (unlikely(!addr))
185 goto out;
186 err = -ENOMEM;
187 mmio = ioremap_nocache(addr, len);
188 if (!mmio)
189 goto out;
190
191 if (mips_busprobe32(val, mmio)) {
192 val = 0xffffffff;
193 goto unmap;
194 }
195
196 val = readl(mmio);
197 val >>= (8 * (off & 3));
198
199 switch (len) {
200 case 1:
201 *((u8 *)buf) = (u8)val;
202 break;
203 case 2:
204 *((u16 *)buf) = (u16)val;
205 break;
206 case 4:
207 *((u32 *)buf) = (u32)val;
208 break;
209 }
210 err = 0;
211unmap:
212 iounmap(mmio);
213out:
214 return err;
215}
216
217static int ssb_extpci_write_config(struct ssb_pcicore *pc,
218 unsigned int bus, unsigned int dev,
219 unsigned int func, unsigned int off,
220 const void *buf, int len)
221{
222 int err = -EINVAL;
223 u32 addr, val = 0;
224 void __iomem *mmio;
225
226 SSB_WARN_ON(!pc->hostmode);
227 if (unlikely(len != 1 && len != 2 && len != 4))
228 goto out;
229 addr = get_cfgspace_addr(pc, bus, dev, func, off);
230 if (unlikely(!addr))
231 goto out;
232 err = -ENOMEM;
233 mmio = ioremap_nocache(addr, len);
234 if (!mmio)
235 goto out;
236
237 if (mips_busprobe32(val, mmio)) {
238 val = 0xffffffff;
239 goto unmap;
240 }
241
242 switch (len) {
243 case 1:
244 val = readl(mmio);
245 val &= ~(0xFF << (8 * (off & 3)));
246 val |= *((const u8 *)buf) << (8 * (off & 3));
247 break;
248 case 2:
249 val = readl(mmio);
250 val &= ~(0xFFFF << (8 * (off & 3)));
251 val |= *((const u16 *)buf) << (8 * (off & 3));
252 break;
253 case 4:
254 val = *((const u32 *)buf);
255 break;
256 }
257 writel(val, mmio);
258
259 err = 0;
260unmap:
261 iounmap(mmio);
262out:
263 return err;
264}
265
266static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn,
267 int reg, int size, u32 *val)
268{
269 unsigned long flags;
270 int err;
271
272 spin_lock_irqsave(&cfgspace_lock, flags);
273 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn),
274 PCI_FUNC(devfn), reg, val, size);
275 spin_unlock_irqrestore(&cfgspace_lock, flags);
276
277 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
278}
279
280static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn,
281 int reg, int size, u32 val)
282{
283 unsigned long flags;
284 int err;
285
286 spin_lock_irqsave(&cfgspace_lock, flags);
287 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn),
288 PCI_FUNC(devfn), reg, &val, size);
289 spin_unlock_irqrestore(&cfgspace_lock, flags);
290
291 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
292}
293
294static struct pci_ops ssb_pcicore_pciops = {
295 .read = ssb_pcicore_read_config,
296 .write = ssb_pcicore_write_config,
297};
298
299static struct resource ssb_pcicore_mem_resource = {
300 .name = "SSB PCIcore external memory",
301 .start = SSB_PCI_DMA,
302 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1,
fc71acc8 303 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED,
61e115a5
MB		 304};
305
306static struct resource ssb_pcicore_io_resource = {
307 .name = "SSB PCIcore external I/O",
308 .start = 0x100,
309 .end = 0x7FF,
fc71acc8 310 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED,
61e115a5
MB		 311};
312
313static struct pci_controller ssb_pcicore_controller = {
314 .pci_ops = &ssb_pcicore_pciops,
315 .io_resource = &ssb_pcicore_io_resource,
316 .mem_resource = &ssb_pcicore_mem_resource,
317 .mem_offset = 0x24000000,
318};
319
320static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
321{
322 u32 val;
323
324 if (WARN_ON(extpci_core))
325 return;
326 extpci_core = pc;
327
328 ssb_dprintk(KERN_INFO PFX "PCIcore in host mode found\n");
329 /* Reset devices on the external PCI bus */
330 val = SSB_PCICORE_CTL_RST_OE;
331 val |= SSB_PCICORE_CTL_CLK_OE;
332 pcicore_write32(pc, SSB_PCICORE_CTL, val);
333 val |= SSB_PCICORE_CTL_CLK; /* Clock on */
334 pcicore_write32(pc, SSB_PCICORE_CTL, val);
335 udelay(150); /* Assertion time demanded by the PCI standard */
336 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
337 pcicore_write32(pc, SSB_PCICORE_CTL, val);
338 val = SSB_PCICORE_ARBCTL_INTERN;
339 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
340 udelay(1); /* Assertion time demanded by the PCI standard */
341
7cb44615
MB		 342 if (pc->dev->bus->has_cardbus_slot) {
343 ssb_dprintk(KERN_INFO PFX "CardBus slot detected\n");
344 pc->cardbusmode = 1;
345 /* GPIO 1 resets the bridge */
346 ssb_gpio_out(pc->dev->bus, 1, 1);
347 ssb_gpio_outen(pc->dev->bus, 1, 1);
348 pcicore_write16(pc, SSB_PCICORE_SPROM(0),
349 pcicore_read16(pc, SSB_PCICORE_SPROM(0))
350 | 0x0400);
351 }
61e115a5
MB		 352
353 /* 64MB I/O window */
354 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0,
355 SSB_PCICORE_SBTOPCI_IO);
356 /* 64MB config space */
357 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1,
358 SSB_PCICORE_SBTOPCI_CFG0);
359 /* 1GB memory window */
360 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
361 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
362
363 /* Enable PCI bridge BAR0 prefetch and burst */
364 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
365 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2);
366 /* Clear error conditions */
367 val = 0;
368 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2);
369
370 /* Enable PCI interrupts */
371 pcicore_write32(pc, SSB_PCICORE_IMASK,
372 SSB_PCICORE_IMASK_INTA);
373
374 /* Ok, ready to run, register it to the system.
375 * The following needs change, if we want to port hostmode
376 * to non-MIPS platform. */
fc71acc8
MB		 377 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000);
378 set_io_port_base(ssb_pcicore_controller.io_map_base);
61e115a5
MB		 379 /* Give some time to the PCI controller to configure itself with the new
380 * values. Not waiting at this point causes crashes of the machine. */
381 mdelay(10);
382 register_pci_controller(&ssb_pcicore_controller);
383}
384
385static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
386{
387 struct ssb_bus *bus = pc->dev->bus;
388 u16 chipid_top;
389 u32 tmp;
390
391 chipid_top = (bus->chip_id & 0xFF00);
392 if (chipid_top != 0x4700 &&
393 chipid_top != 0x5300)
394 return 0;
395
396 if (bus->sprom.r1.boardflags_lo & SSB_PCICORE_BFL_NOPCI)
397 return 0;
398
399 /* The 200-pin BCM4712 package does not bond out PCI. Even when
400 * PCI is bonded out, some boards may leave the pins floating. */
401 if (bus->chip_id == 0x4712) {
402 if (bus->chip_package == SSB_CHIPPACK_BCM4712S)
403 return 0;
404 if (bus->chip_package == SSB_CHIPPACK_BCM4712M)
405 return 0;
406 }
407 if (bus->chip_id == 0x5350)
408 return 0;
409
410 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE)));
411}
412#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
413
414
415/**************************************************
416 * Generic and Clientmode operation code.
417 **************************************************/
418
419static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
420{
421 /* Disable PCI interrupts. */
422 ssb_write32(pc->dev, SSB_INTVEC, 0);
423}
424
425void ssb_pcicore_init(struct ssb_pcicore *pc)
426{
427 struct ssb_device *dev = pc->dev;
428 struct ssb_bus *bus;
429
430 if (!dev)
431 return;
432 bus = dev->bus;
433 if (!ssb_device_is_enabled(dev))
434 ssb_device_enable(dev, 0);
435
436#ifdef CONFIG_SSB_PCICORE_HOSTMODE
437 pc->hostmode = pcicore_is_in_hostmode(pc);
438 if (pc->hostmode)
439 ssb_pcicore_init_hostmode(pc);
440#endif /* CONFIG_SSB_PCICORE_HOSTMODE */
441 if (!pc->hostmode)
442 ssb_pcicore_init_clientmode(pc);
443}
444
445static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address)
446{
447 pcicore_write32(pc, 0x130, address);
448 return pcicore_read32(pc, 0x134);
449}
450
451static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data)
452{
453 pcicore_write32(pc, 0x130, address);
454 pcicore_write32(pc, 0x134, data);
455}
456
457static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
458 u8 address, u16 data)
459{
460 const u16 mdio_control = 0x128;
461 const u16 mdio_data = 0x12C;
462 u32 v;
463 int i;
464
465 v = 0x80; /* Enable Preamble Sequence */
466 v |= 0x2; /* MDIO Clock Divisor */
467 pcicore_write32(pc, mdio_control, v);
468
469 v = (1 << 30); /* Start of Transaction */
470 v |= (1 << 28); /* Write Transaction */
471 v |= (1 << 17); /* Turnaround */
472 v |= (u32)device << 22;
473 v |= (u32)address << 18;
474 v |= data;
475 pcicore_write32(pc, mdio_data, v);
476 /* Wait for the device to complete the transaction */
477 udelay(10);
478 for (i = 0; i < 10; i++) {
479 v = pcicore_read32(pc, mdio_control);
480 if (v & 0x100 /* Trans complete */)
481 break;
482 msleep(1);
483 }
484 pcicore_write32(pc, mdio_control, 0);
485}
486
487static void ssb_broadcast_value(struct ssb_device *dev,
488 u32 address, u32 data)
489{
490 /* This is used for both, PCI and ChipCommon core, so be careful. */
491 BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
492 BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
493
494 ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
495 ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
496 ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
497 ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
498}
499
500static void ssb_commit_settings(struct ssb_bus *bus)
501{
502 struct ssb_device *dev;
503
504 dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
505 if (WARN_ON(!dev))
506 return;
507 /* This forces an update of the cached registers. */
508 ssb_broadcast_value(dev, 0xFD8, 0);
509}
510
511int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
512 struct ssb_device *dev)
513{
514 struct ssb_device *pdev = pc->dev;
515 struct ssb_bus *bus;
516 int err = 0;
517 u32 tmp;
518
519 might_sleep();
520
521 if (!pdev)
522 goto out;
523 bus = pdev->bus;
524
525 /* Enable interrupts for this device. */
526 if (bus->host_pci &&
527 ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
528 u32 coremask;
529
530 /* Calculate the "coremask" for the device. */
531 coremask = (1 << dev->core_index);
532
533 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
534 if (err)
535 goto out;
536 tmp |= coremask << 8;
537 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp);
538 if (err)
539 goto out;
540 } else {
541 u32 intvec;
542
543 intvec = ssb_read32(pdev, SSB_INTVEC);
544 if ((bus->chip_id & 0xFF00) == 0x4400) {
545 /* Workaround: On the BCM44XX the BPFLAG routing
546 * bit is wrong. Use a hardcoded constant. */
547 intvec |= 0x00000002;
548 } else {
549 tmp = ssb_read32(dev, SSB_TPSFLAG);
550 tmp &= SSB_TPSFLAG_BPFLAG;
551 intvec |= tmp;
552 }
553 ssb_write32(pdev, SSB_INTVEC, intvec);
554 }
555
556 /* Setup PCIcore operation. */
557 if (pc->setup_done)
558 goto out;
559 if (pdev->id.coreid == SSB_DEV_PCI) {
560 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
561 tmp |= SSB_PCICORE_SBTOPCI_PREF;
562 tmp |= SSB_PCICORE_SBTOPCI_BURST;
563 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
564
565 if (pdev->id.revision < 5) {
566 tmp = ssb_read32(pdev, SSB_IMCFGLO);
567 tmp &= ~SSB_IMCFGLO_SERTO;
568 tmp |= 2;
569 tmp &= ~SSB_IMCFGLO_REQTO;
570 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
571 ssb_write32(pdev, SSB_IMCFGLO, tmp);
572 ssb_commit_settings(bus);
573 } else if (pdev->id.revision >= 11) {
574 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
575 tmp |= SSB_PCICORE_SBTOPCI_MRM;
576 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
577 }
578 } else {
579 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
580 //TODO: Better make defines for all these magic PCIE values.
581 if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
582 /* TLP Workaround register. */
583 tmp = ssb_pcie_read(pc, 0x4);
584 tmp |= 0x8;
585 ssb_pcie_write(pc, 0x4, tmp);
586 }
587 if (pdev->id.revision == 0) {
588 const u8 serdes_rx_device = 0x1F;
589
590 ssb_pcie_mdio_write(pc, serdes_rx_device,
591 2 /* Timer */, 0x8128);
592 ssb_pcie_mdio_write(pc, serdes_rx_device,
593 6 /* CDR */, 0x0100);
594 ssb_pcie_mdio_write(pc, serdes_rx_device,
595 7 /* CDR BW */, 0x1466);
596 } else if (pdev->id.revision == 1) {
597 /* DLLP Link Control register. */
598 tmp = ssb_pcie_read(pc, 0x100);
599 tmp |= 0x40;
600 ssb_pcie_write(pc, 0x100, tmp);
601 }
602 }
603 pc->setup_done = 1;
604out:
605 return err;
606}
607EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable);
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