[deliverable/linux.git] / drivers / staging / brcm80211 / brcmsmac / phy / phy_hal.h

/*
 * Copyright (c) 2010 Broadcom Corporation
 *
 * Permission to use, copy, modify, and/or distribute this software for any
 * purpose with or without fee is hereby granted, provided that the above
 * copyright notice and this permission notice appear in all copies.
 *
 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
 */

/*
 * phy_hal.h:  functionality exported from the phy to higher layers
 */

#ifndef _BRCM_PHY_HAL_H_
#define _BRCM_PHY_HAL_H_

#include <aiutils.h>
#include <d11.h>
#include <phy_shim.h>
#include <net/mac80211.h>	/* struct wiphy */
#include "brcmu_wifi.h"		/* chanspec_t */

#define	IDCODE_VER_MASK		0x0000000f
#define	IDCODE_VER_SHIFT	0
#define	IDCODE_MFG_MASK		0x00000fff
#define	IDCODE_MFG_SHIFT	0
#define	IDCODE_ID_MASK		0x0ffff000
#define	IDCODE_ID_SHIFT		12
#define	IDCODE_REV_MASK		0xf0000000
#define	IDCODE_REV_SHIFT	28

#define	NORADIO_ID		0xe4f5
#define	NORADIO_IDCODE		0x4e4f5246

#define BCM2055_ID		0x2055
#define BCM2055_IDCODE		0x02055000
#define BCM2055A0_IDCODE	0x1205517f

#define BCM2056_ID		0x2056
#define BCM2056_IDCODE		0x02056000
#define BCM2056A0_IDCODE	0x1205617f

#define BCM2057_ID		0x2057
#define BCM2057_IDCODE		0x02057000
#define BCM2057A0_IDCODE	0x1205717f

#define BCM2064_ID		0x2064
#define BCM2064_IDCODE		0x02064000
#define BCM2064A0_IDCODE	0x0206417f

#define PHY_TPC_HW_OFF		false
#define PHY_TPC_HW_ON		true

#define PHY_PERICAL_DRIVERUP	1
#define PHY_PERICAL_WATCHDOG	2
#define PHY_PERICAL_PHYINIT	3
#define PHY_PERICAL_JOIN_BSS	4
#define PHY_PERICAL_START_IBSS	5
#define PHY_PERICAL_UP_BSS	6
#define PHY_PERICAL_CHAN	7
#define PHY_FULLCAL	8

#define PHY_PERICAL_DISABLE	0
#define PHY_PERICAL_SPHASE	1
#define PHY_PERICAL_MPHASE	2
#define PHY_PERICAL_MANUAL	3

#define PHY_HOLD_FOR_ASSOC	1
#define PHY_HOLD_FOR_SCAN	2
#define PHY_HOLD_FOR_RM		4
#define PHY_HOLD_FOR_PLT	8
#define PHY_HOLD_FOR_MUTE	16
#define PHY_HOLD_FOR_NOT_ASSOC 0x20

#define PHY_MUTE_FOR_PREISM	1
#define PHY_MUTE_ALL		0xffffffff

#define PHY_NOISE_FIXED_VAL 		(-95)
#define PHY_NOISE_FIXED_VAL_NPHY       	(-92)
#define PHY_NOISE_FIXED_VAL_LCNPHY     	(-92)

#define PHY_MODE_CAL		0x0002
#define PHY_MODE_NOISEM		0x0004

#define WLC_TXPWR_DB_FACTOR	4

/* a large TX Power as an init value to factor out of min() calculations,
 * keep low enough to fit in an s8, units are .25 dBm
 */
#define WLC_TXPWR_MAX		(127)	/* ~32 dBm = 1,500 mW */

#define WLC_NUM_RATES_CCK           4
#define WLC_NUM_RATES_OFDM          8
#define WLC_NUM_RATES_MCS_1_STREAM  8
#define WLC_NUM_RATES_MCS_2_STREAM  8
#define WLC_NUM_RATES_MCS_3_STREAM  8
#define WLC_NUM_RATES_MCS_4_STREAM  8

#define	WLC_RSSI_INVALID	 0	/* invalid RSSI value */

struct txpwr_limits {
	u8 cck[WLC_NUM_RATES_CCK];
	u8 ofdm[WLC_NUM_RATES_OFDM];

	u8 ofdm_cdd[WLC_NUM_RATES_OFDM];

	u8 ofdm_40_siso[WLC_NUM_RATES_OFDM];
	u8 ofdm_40_cdd[WLC_NUM_RATES_OFDM];

	u8 mcs_20_siso[WLC_NUM_RATES_MCS_1_STREAM];
	u8 mcs_20_cdd[WLC_NUM_RATES_MCS_1_STREAM];
	u8 mcs_20_stbc[WLC_NUM_RATES_MCS_1_STREAM];
	u8 mcs_20_mimo[WLC_NUM_RATES_MCS_2_STREAM];

	u8 mcs_40_siso[WLC_NUM_RATES_MCS_1_STREAM];
	u8 mcs_40_cdd[WLC_NUM_RATES_MCS_1_STREAM];
	u8 mcs_40_stbc[WLC_NUM_RATES_MCS_1_STREAM];
	u8 mcs_40_mimo[WLC_NUM_RATES_MCS_2_STREAM];
	u8 mcs32;
};

struct tx_power {
	u32 flags;
	chanspec_t chanspec;	/* txpwr report for this channel */
	chanspec_t local_chanspec;	/* channel on which we are associated */
	u8 local_max;	/* local max according to the AP */
	u8 local_constraint;	/* local constraint according to the AP */
	s8 antgain[2];	/* Ant gain for each band - from SROM */
	u8 rf_cores;		/* count of RF Cores being reported */
	u8 est_Pout[4];	/* Latest tx power out estimate per RF chain */
	u8 est_Pout_act[4];	/* Latest tx power out estimate per RF chain
				 * without adjustment
				 */
	u8 est_Pout_cck;	/* Latest CCK tx power out estimate */
	u8 tx_power_max[4];	/* Maximum target power among all rates */
	u8 tx_power_max_rate_ind[4];	/* Index of the rate with the max target power */
	u8 user_limit[WL_TX_POWER_RATES];	/* User limit */
	u8 reg_limit[WL_TX_POWER_RATES];	/* Regulatory power limit */
	u8 board_limit[WL_TX_POWER_RATES];	/* Max power board can support (SROM) */
	u8 target[WL_TX_POWER_RATES];	/* Latest target power */
};

struct tx_inst_power {
	u8 txpwr_est_Pout[2];	/* Latest estimate for 2.4 and 5 Ghz */
	u8 txpwr_est_Pout_gofdm;	/* Pwr estimate for 2.4 OFDM */
};

struct chanvec {
	u8 vec[MAXCHANNEL / NBBY];
};

struct rpc_info;

struct phy_pub;

struct shared_phy_params {
	struct si_pub *sih;
	void *physhim;
	uint unit;
	uint corerev;
	uint bustype;
	uint buscorerev;
	char *vars;
	u16 vid;
	u16 did;
	uint chip;
	uint chiprev;
	uint chippkg;
	uint sromrev;
	uint boardtype;
	uint boardrev;
	uint boardvendor;
	u32 boardflags;
	u32 boardflags2;
};


extern shared_phy_t *wlc_phy_shared_attach(shared_phy_params_t *shp);
extern void wlc_phy_shared_detach(shared_phy_t *phy_sh);
extern wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype,
				 char *vars, struct wiphy *wiphy);
extern void wlc_phy_detach(wlc_phy_t *ppi);

extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype,
				   u16 *phyrev, u16 *radioid,
				   u16 *radiover);
extern bool wlc_phy_get_encore(wlc_phy_t *pih);
extern u32 wlc_phy_get_coreflags(wlc_phy_t *pih);

extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate);
extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate);
extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec);
extern void wlc_phy_watchdog(wlc_phy_t *ppi);
extern int wlc_phy_down(wlc_phy_t *ppi);
extern u32 wlc_phy_clk_bwbits(wlc_phy_t *pih);
extern void wlc_phy_cal_init(wlc_phy_t *ppi);
extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init);

extern void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec);
extern chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi);
extern void wlc_phy_chanspec_radio_set(wlc_phy_t *ppi, chanspec_t newch);
extern u16 wlc_phy_bw_state_get(wlc_phy_t *ppi);
extern void wlc_phy_bw_state_set(wlc_phy_t *ppi, u16 bw);

extern void wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx);
extern void wlc_phy_por_inform(wlc_phy_t *ppi);
extern void wlc_phy_noise_sample_intr(wlc_phy_t *ppi);
extern bool wlc_phy_bist_check_phy(wlc_phy_t *ppi);

extern void wlc_phy_set_deaf(wlc_phy_t *ppi, bool user_flag);

extern void wlc_phy_switch_radio(wlc_phy_t *ppi, bool on);
extern void wlc_phy_anacore(wlc_phy_t *ppi, bool on);


extern void wlc_phy_BSSinit(wlc_phy_t *ppi, bool bonlyap, int rssi);

extern void wlc_phy_chanspec_ch14_widefilter_set(wlc_phy_t *ppi,
						 bool wide_filter);
extern void wlc_phy_chanspec_band_validch(wlc_phy_t *ppi, uint band,
					  chanvec_t *channels);
extern chanspec_t wlc_phy_chanspec_band_firstch(wlc_phy_t *ppi, uint band);

extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan,
				      u8 *_min_, u8 *_max_, int rate);
extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan,
					      u8 *_max_, u8 *_min_);
extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t *ppi, uint band, s32 *,
					    s32 *, u32 *);
extern void wlc_phy_txpower_limit_set(wlc_phy_t *ppi, struct txpwr_limits *,
				      chanspec_t chanspec);
extern int wlc_phy_txpower_get(wlc_phy_t *ppi, uint *qdbm, bool *override);
extern int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override);
extern void wlc_phy_txpower_target_set(wlc_phy_t *ppi, struct txpwr_limits *);
extern bool wlc_phy_txpower_hw_ctrl_get(wlc_phy_t *ppi);
extern void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl);
extern u8 wlc_phy_txpower_get_target_min(wlc_phy_t *ppi);
extern u8 wlc_phy_txpower_get_target_max(wlc_phy_t *ppi);
extern bool wlc_phy_txpower_ipa_ison(wlc_phy_t *pih);

extern void wlc_phy_stf_chain_init(wlc_phy_t *pih, u8 txchain,
				   u8 rxchain);
extern void wlc_phy_stf_chain_set(wlc_phy_t *pih, u8 txchain,
				  u8 rxchain);
extern void wlc_phy_stf_chain_get(wlc_phy_t *pih, u8 *txchain,
				  u8 *rxchain);
extern u8 wlc_phy_stf_chain_active_get(wlc_phy_t *pih);
extern s8 wlc_phy_stf_ssmode_get(wlc_phy_t *pih, chanspec_t chanspec);
extern void wlc_phy_ldpc_override_set(wlc_phy_t *ppi, bool val);

extern void wlc_phy_cal_perical(wlc_phy_t *ppi, u8 reason);
extern void wlc_phy_noise_sample_request_external(wlc_phy_t *ppi);
extern void wlc_phy_edcrs_lock(wlc_phy_t *pih, bool lock);
extern void wlc_phy_cal_papd_recal(wlc_phy_t *ppi);

extern void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val);
extern void wlc_phy_clear_tssi(wlc_phy_t *ppi);
extern void wlc_phy_hold_upd(wlc_phy_t *ppi, mbool id, bool val);
extern void wlc_phy_mute_upd(wlc_phy_t *ppi, bool val, mbool flags);

extern void wlc_phy_antsel_type_set(wlc_phy_t *ppi, u8 antsel_type);

extern void wlc_phy_txpower_get_current(wlc_phy_t *ppi, tx_power_t *power,
					uint channel);

extern void wlc_phy_initcal_enable(wlc_phy_t *pih, bool initcal);
extern bool wlc_phy_test_ison(wlc_phy_t *ppi);
extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent);
extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war);
extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt);
extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap);

extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end);

extern void wlc_phy_freqtrack_start(wlc_phy_t *ppi);
extern void wlc_phy_freqtrack_end(wlc_phy_t *ppi);

extern const u8 *wlc_phy_get_ofdm_rate_lookup(void);

extern s8 wlc_phy_get_tx_power_offset_by_mcs(wlc_phy_t *ppi,
					       u8 mcs_offset);
extern s8 wlc_phy_get_tx_power_offset(wlc_phy_t *ppi, u8 tbl_offset);
#endif				/* _BRCM_PHY_HAL_H_ */
Commit	Line	Data
a9533e7e HP	1	/*
	2	* Copyright (c) 2010 Broadcom Corporation
	3	*
	4	* Permission to use, copy, modify, and/or distribute this software for any
	5	* purpose with or without fee is hereby granted, provided that the above
	6	* copyright notice and this permission notice appear in all copies.
	7	*
	8	* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
	9	* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
	10	* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
	11	* SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
	12	* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
	13	* OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
	14	* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
	15	*/
	16
434c14ef	17	/*
f8557965	18	* phy_hal.h: functionality exported from the phy to higher layers
434c14ef RV	19	*/
434c14ef RV	20
f8557965 RV	21	#ifndef _BRCM_PHY_HAL_H_
f8557965 RV	22	#define _BRCM_PHY_HAL_H_
a9533e7e	23
27302e8f	24	#include <aiutils.h>
a9533e7e	25	#include <d11.h>
cc3cea5a	26	#include <phy_shim.h>
8c2c8216	27	#include <net/mac80211.h> /* struct wiphy */
f97e956a	28	#include "brcmu_wifi.h" /* chanspec_t */
a9533e7e HP	29
	30	#define IDCODE_VER_MASK 0x0000000f
	31	#define IDCODE_VER_SHIFT 0
	32	#define IDCODE_MFG_MASK 0x00000fff
	33	#define IDCODE_MFG_SHIFT 0
	34	#define IDCODE_ID_MASK 0x0ffff000
	35	#define IDCODE_ID_SHIFT 12
	36	#define IDCODE_REV_MASK 0xf0000000
	37	#define IDCODE_REV_SHIFT 28
	38
	39	#define NORADIO_ID 0xe4f5
	40	#define NORADIO_IDCODE 0x4e4f5246
	41
	42	#define BCM2055_ID 0x2055
	43	#define BCM2055_IDCODE 0x02055000
	44	#define BCM2055A0_IDCODE 0x1205517f
	45
	46	#define BCM2056_ID 0x2056
	47	#define BCM2056_IDCODE 0x02056000
	48	#define BCM2056A0_IDCODE 0x1205617f
	49
	50	#define BCM2057_ID 0x2057
	51	#define BCM2057_IDCODE 0x02057000
	52	#define BCM2057A0_IDCODE 0x1205717f
	53
	54	#define BCM2064_ID 0x2064
	55	#define BCM2064_IDCODE 0x02064000
	56	#define BCM2064A0_IDCODE 0x0206417f
	57
0965ae88	58	#define PHY_TPC_HW_OFF false
0f0881b0	59	#define PHY_TPC_HW_ON true
a9533e7e HP	60
	61	#define PHY_PERICAL_DRIVERUP 1
	62	#define PHY_PERICAL_WATCHDOG 2
	63	#define PHY_PERICAL_PHYINIT 3
	64	#define PHY_PERICAL_JOIN_BSS 4
	65	#define PHY_PERICAL_START_IBSS 5
	66	#define PHY_PERICAL_UP_BSS 6
	67	#define PHY_PERICAL_CHAN 7
	68	#define PHY_FULLCAL 8
	69
	70	#define PHY_PERICAL_DISABLE 0
	71	#define PHY_PERICAL_SPHASE 1
	72	#define PHY_PERICAL_MPHASE 2
	73	#define PHY_PERICAL_MANUAL 3
	74
	75	#define PHY_HOLD_FOR_ASSOC 1
	76	#define PHY_HOLD_FOR_SCAN 2
	77	#define PHY_HOLD_FOR_RM 4
	78	#define PHY_HOLD_FOR_PLT 8
	79	#define PHY_HOLD_FOR_MUTE 16
	80	#define PHY_HOLD_FOR_NOT_ASSOC 0x20
	81
	82	#define PHY_MUTE_FOR_PREISM 1
	83	#define PHY_MUTE_ALL 0xffffffff
	84
	85	#define PHY_NOISE_FIXED_VAL (-95)
	86	#define PHY_NOISE_FIXED_VAL_NPHY (-92)
	87	#define PHY_NOISE_FIXED_VAL_LCNPHY (-92)
	88
	89	#define PHY_MODE_CAL 0x0002
	90	#define PHY_MODE_NOISEM 0x0004
	91
	92	#define WLC_TXPWR_DB_FACTOR 4
	93
434c14ef RV	94	/* a large TX Power as an init value to factor out of min() calculations,
	95	* keep low enough to fit in an s8, units are .25 dBm
	96	*/
	97	#define WLC_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
	98
a9533e7e HP	99	#define WLC_NUM_RATES_CCK 4
	100	#define WLC_NUM_RATES_OFDM 8
	101	#define WLC_NUM_RATES_MCS_1_STREAM 8
	102	#define WLC_NUM_RATES_MCS_2_STREAM 8
	103	#define WLC_NUM_RATES_MCS_3_STREAM 8
	104	#define WLC_NUM_RATES_MCS_4_STREAM 8
434c14ef RV	105
	106	#define WLC_RSSI_INVALID 0 /* invalid RSSI value */
	107
939e1ef5	108	struct txpwr_limits {
e868ab03 GKH	109	u8 cck[WLC_NUM_RATES_CCK];
e868ab03 GKH	110	u8 ofdm[WLC_NUM_RATES_OFDM];
a9533e7e	111
e868ab03	112	u8 ofdm_cdd[WLC_NUM_RATES_OFDM];
a9533e7e	113
e868ab03 GKH	114	u8 ofdm_40_siso[WLC_NUM_RATES_OFDM];
e868ab03 GKH	115	u8 ofdm_40_cdd[WLC_NUM_RATES_OFDM];
a9533e7e	116
e868ab03 GKH	117	u8 mcs_20_siso[WLC_NUM_RATES_MCS_1_STREAM];
	118	u8 mcs_20_cdd[WLC_NUM_RATES_MCS_1_STREAM];
	119	u8 mcs_20_stbc[WLC_NUM_RATES_MCS_1_STREAM];
	120	u8 mcs_20_mimo[WLC_NUM_RATES_MCS_2_STREAM];
a9533e7e	121
e868ab03 GKH	122	u8 mcs_40_siso[WLC_NUM_RATES_MCS_1_STREAM];
	123	u8 mcs_40_cdd[WLC_NUM_RATES_MCS_1_STREAM];
	124	u8 mcs_40_stbc[WLC_NUM_RATES_MCS_1_STREAM];
	125	u8 mcs_40_mimo[WLC_NUM_RATES_MCS_2_STREAM];
	126	u8 mcs32;
939e1ef5	127	};
a9533e7e	128
939e1ef5	129	struct tx_power {
434c14ef RV	130	u32 flags;
	131	chanspec_t chanspec; /* txpwr report for this channel */
	132	chanspec_t local_chanspec; /* channel on which we are associated */
	133	u8 local_max; /* local max according to the AP */
	134	u8 local_constraint; /* local constraint according to the AP */
	135	s8 antgain[2]; /* Ant gain for each band - from SROM */
	136	u8 rf_cores; /* count of RF Cores being reported */
	137	u8 est_Pout[4]; /* Latest tx power out estimate per RF chain */
	138	u8 est_Pout_act[4]; /* Latest tx power out estimate per RF chain
	139	* without adjustment
	140	*/
	141	u8 est_Pout_cck; /* Latest CCK tx power out estimate */
	142	u8 tx_power_max[4]; /* Maximum target power among all rates */
	143	u8 tx_power_max_rate_ind[4]; /* Index of the rate with the max target power */
	144	u8 user_limit[WL_TX_POWER_RATES]; /* User limit */
	145	u8 reg_limit[WL_TX_POWER_RATES]; /* Regulatory power limit */
	146	u8 board_limit[WL_TX_POWER_RATES]; /* Max power board can support (SROM) */
	147	u8 target[WL_TX_POWER_RATES]; /* Latest target power */
939e1ef5	148	};
434c14ef	149
939e1ef5	150	struct tx_inst_power {
434c14ef RV	151	u8 txpwr_est_Pout[2]; /* Latest estimate for 2.4 and 5 Ghz */
434c14ef RV	152	u8 txpwr_est_Pout_gofdm; /* Pwr estimate for 2.4 OFDM */
939e1ef5	153	};
434c14ef	154
939e1ef5	155	struct chanvec {
e868ab03	156	u8 vec[MAXCHANNEL / NBBY];
939e1ef5	157	};
a9533e7e HP	158
a9533e7e HP	159	struct rpc_info;
a9533e7e HP	160
	161	struct phy_pub;
	162
939e1ef5	163	struct shared_phy_params {
d5f27a8f	164	struct si_pub *sih;
a9533e7e HP	165	void *physhim;
	166	uint unit;
	167	uint corerev;
	168	uint bustype;
	169	uint buscorerev;
	170	char *vars;
7d4df48e GKH	171	u16 vid;
7d4df48e GKH	172	u16 did;
a9533e7e HP	173	uint chip;
	174	uint chiprev;
	175	uint chippkg;
	176	uint sromrev;
	177	uint boardtype;
	178	uint boardrev;
	179	uint boardvendor;
66cbd3ab GKH	180	u32 boardflags;
66cbd3ab GKH	181	u32 boardflags2;
939e1ef5	182	};
a9533e7e	183
a9533e7e	184
7cc4a4c0 JC	185	extern shared_phy_t wlc_phy_shared_attach(shared_phy_params_t shp);
	186	extern void wlc_phy_shared_detach(shared_phy_t *phy_sh);
	187	extern wlc_phy_t wlc_phy_attach(shared_phy_t sh, void *regs, int bandtype,
8c2c8216	188	char vars, struct wiphy wiphy);
7cc4a4c0 JC	189	extern void wlc_phy_detach(wlc_phy_t *ppi);
7cc4a4c0 JC	190
7d4df48e GKH	191	extern bool wlc_phy_get_phyversion(wlc_phy_t pih, u16 phytype,
	192	u16 phyrev, u16 radioid,
	193	u16 *radiover);
7cc4a4c0	194	extern bool wlc_phy_get_encore(wlc_phy_t *pih);
66cbd3ab	195	extern u32 wlc_phy_get_coreflags(wlc_phy_t *pih);
7cc4a4c0 JC	196
	197	extern void wlc_phy_hw_clk_state_upd(wlc_phy_t *ppi, bool newstate);
	198	extern void wlc_phy_hw_state_upd(wlc_phy_t *ppi, bool newstate);
	199	extern void wlc_phy_init(wlc_phy_t *ppi, chanspec_t chanspec);
	200	extern void wlc_phy_watchdog(wlc_phy_t *ppi);
	201	extern int wlc_phy_down(wlc_phy_t *ppi);
66cbd3ab	202	extern u32 wlc_phy_clk_bwbits(wlc_phy_t *pih);
7cc4a4c0 JC	203	extern void wlc_phy_cal_init(wlc_phy_t *ppi);
	204	extern void wlc_phy_antsel_init(wlc_phy_t *ppi, bool lut_init);
	205
	206	extern void wlc_phy_chanspec_set(wlc_phy_t *ppi, chanspec_t chanspec);
	207	extern chanspec_t wlc_phy_chanspec_get(wlc_phy_t *ppi);
	208	extern void wlc_phy_chanspec_radio_set(wlc_phy_t *ppi, chanspec_t newch);
7d4df48e GKH	209	extern u16 wlc_phy_bw_state_get(wlc_phy_t *ppi);
7d4df48e GKH	210	extern void wlc_phy_bw_state_set(wlc_phy_t *ppi, u16 bw);
7cc4a4c0 JC	211
	212	extern void wlc_phy_rssi_compute(wlc_phy_t pih, void ctx);
	213	extern void wlc_phy_por_inform(wlc_phy_t *ppi);
	214	extern void wlc_phy_noise_sample_intr(wlc_phy_t *ppi);
	215	extern bool wlc_phy_bist_check_phy(wlc_phy_t *ppi);
	216
	217	extern void wlc_phy_set_deaf(wlc_phy_t *ppi, bool user_flag);
	218
	219	extern void wlc_phy_switch_radio(wlc_phy_t *ppi, bool on);
	220	extern void wlc_phy_anacore(wlc_phy_t *ppi, bool on);
a9533e7e	221
a9533e7e	222
7cc4a4c0	223	extern void wlc_phy_BSSinit(wlc_phy_t *ppi, bool bonlyap, int rssi);
a9533e7e	224
7cc4a4c0	225	extern void wlc_phy_chanspec_ch14_widefilter_set(wlc_phy_t *ppi,
a9533e7e	226	bool wide_filter);
7cc4a4c0 JC	227	extern void wlc_phy_chanspec_band_validch(wlc_phy_t *ppi, uint band,
	228	chanvec_t *channels);
	229	extern chanspec_t wlc_phy_chanspec_band_firstch(wlc_phy_t *ppi, uint band);
	230
	231	extern void wlc_phy_txpower_sromlimit(wlc_phy_t *ppi, uint chan,
e868ab03	232	u8 _min_, u8 _max_, int rate);
7cc4a4c0	233	extern void wlc_phy_txpower_sromlimit_max_get(wlc_phy_t *ppi, uint chan,
e868ab03	234	u8 _max_, u8 _min_);
3e26416e GKH	235	extern void wlc_phy_txpower_boardlimit_band(wlc_phy_t ppi, uint band, s32 ,
3e26416e GKH	236	s32 , u32 );
7cc4a4c0	237	extern void wlc_phy_txpower_limit_set(wlc_phy_t ppi, struct txpwr_limits ,
a9533e7e	238	chanspec_t chanspec);
7cc4a4c0 JC	239	extern int wlc_phy_txpower_get(wlc_phy_t ppi, uint qdbm, bool *override);
	240	extern int wlc_phy_txpower_set(wlc_phy_t *ppi, uint qdbm, bool override);
	241	extern void wlc_phy_txpower_target_set(wlc_phy_t ppi, struct txpwr_limits );
	242	extern bool wlc_phy_txpower_hw_ctrl_get(wlc_phy_t *ppi);
	243	extern void wlc_phy_txpower_hw_ctrl_set(wlc_phy_t *ppi, bool hwpwrctrl);
e868ab03 GKH	244	extern u8 wlc_phy_txpower_get_target_min(wlc_phy_t *ppi);
e868ab03 GKH	245	extern u8 wlc_phy_txpower_get_target_max(wlc_phy_t *ppi);
7cc4a4c0 JC	246	extern bool wlc_phy_txpower_ipa_ison(wlc_phy_t *pih);
7cc4a4c0 JC	247
e868ab03 GKH	248	extern void wlc_phy_stf_chain_init(wlc_phy_t *pih, u8 txchain,
	249	u8 rxchain);
	250	extern void wlc_phy_stf_chain_set(wlc_phy_t *pih, u8 txchain,
	251	u8 rxchain);
	252	extern void wlc_phy_stf_chain_get(wlc_phy_t pih, u8 txchain,
	253	u8 *rxchain);
	254	extern u8 wlc_phy_stf_chain_active_get(wlc_phy_t *pih);
562c8850	255	extern s8 wlc_phy_stf_ssmode_get(wlc_phy_t *pih, chanspec_t chanspec);
7cc4a4c0 JC	256	extern void wlc_phy_ldpc_override_set(wlc_phy_t *ppi, bool val);
7cc4a4c0 JC	257
e868ab03	258	extern void wlc_phy_cal_perical(wlc_phy_t *ppi, u8 reason);
7cc4a4c0 JC	259	extern void wlc_phy_noise_sample_request_external(wlc_phy_t *ppi);
	260	extern void wlc_phy_edcrs_lock(wlc_phy_t *pih, bool lock);
	261	extern void wlc_phy_cal_papd_recal(wlc_phy_t *ppi);
	262
e868ab03	263	extern void wlc_phy_ant_rxdiv_set(wlc_phy_t *ppi, u8 val);
7cc4a4c0 JC	264	extern void wlc_phy_clear_tssi(wlc_phy_t *ppi);
	265	extern void wlc_phy_hold_upd(wlc_phy_t *ppi, mbool id, bool val);
	266	extern void wlc_phy_mute_upd(wlc_phy_t *ppi, bool val, mbool flags);
	267
e868ab03	268	extern void wlc_phy_antsel_type_set(wlc_phy_t *ppi, u8 antsel_type);
7cc4a4c0 JC	269
7cc4a4c0 JC	270	extern void wlc_phy_txpower_get_current(wlc_phy_t ppi, tx_power_t power,
a9533e7e HP	271	uint channel);
a9533e7e HP	272
7cc4a4c0 JC	273	extern void wlc_phy_initcal_enable(wlc_phy_t *pih, bool initcal);
7cc4a4c0 JC	274	extern bool wlc_phy_test_ison(wlc_phy_t *ppi);
e868ab03	275	extern void wlc_phy_txpwr_percent_set(wlc_phy_t *ppi, u8 txpwr_percent);
7cc4a4c0 JC	276	extern void wlc_phy_ofdm_rateset_war(wlc_phy_t *pih, bool war);
7cc4a4c0 JC	277	extern void wlc_phy_bf_preempt_enable(wlc_phy_t *pih, bool bf_preempt);
66cbd3ab	278	extern void wlc_phy_machwcap_set(wlc_phy_t *ppi, u32 machwcap);
a9533e7e	279
7cc4a4c0	280	extern void wlc_phy_runbist_config(wlc_phy_t *ppi, bool start_end);
a9533e7e	281
7cc4a4c0 JC	282	extern void wlc_phy_freqtrack_start(wlc_phy_t *ppi);
7cc4a4c0 JC	283	extern void wlc_phy_freqtrack_end(wlc_phy_t *ppi);
a9533e7e	284
e868ab03	285	extern const u8 *wlc_phy_get_ofdm_rate_lookup(void);
a9533e7e	286
562c8850	287	extern s8 wlc_phy_get_tx_power_offset_by_mcs(wlc_phy_t *ppi,
e868ab03	288	u8 mcs_offset);
562c8850	289	extern s8 wlc_phy_get_tx_power_offset(wlc_phy_t *ppi, u8 tbl_offset);
f8557965	290	#endif /* _BRCM_PHY_HAL_H_ */