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Staging: Add initial release of brcm80211 - Broadcom 802.11n wireless LAN driver.
[deliverable/linux.git] / drivers / staging / brcm80211 / sys / wlc_bmac.c
CommitLineData
a9533e7e
HP		 1/*
2 * Copyright (c) 2010 Broadcom Corporation
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
11 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
13 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
14 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17#ifndef WLC_LOW
18#error "This file needs WLC_LOW"
19#endif
20
21#include <wlc_cfg.h>
22#include <typedefs.h>
23#include <bcmdefs.h>
24#include <osl.h>
25#include <proto/802.11.h>
26#include <bcmwifi.h>
27#include <bcmutils.h>
28#include <siutils.h>
29#include <bcmendian.h>
30#include <wlioctl.h>
31#include <sbconfig.h>
32#include <sbchipc.h>
33#include <pcicfg.h>
34#include <sbhndpio.h>
35#include <sbhnddma.h>
36#include <hnddma.h>
37#include <hndpmu.h>
38#include <d11.h>
39#include <wlc_rate.h>
40#include <wlc_pub.h>
41#include <wlc_channel.h>
42#include <bcmsrom.h>
43#include <wlc_key.h>
44/* BMAC_NOTE: a WLC_HIGH compile include of wlc.h adds in more structures and type
45 * dependencies. Need to include these to files to allow a clean include of wlc.h
46 * with WLC_HIGH defined.
47 * At some point we may be able to skip the include of wlc.h and instead just
48 * define a stub wlc_info and band struct to allow rpc calls to get the rpc handle.
49 */
50#include <wlc_mac80211.h>
51#include <wlc_bmac.h>
52#include <wlc_phy_shim.h>
53#include <wlc_phy_hal.h>
54#include <wl_export.h>
55#include "wl_ucode.h"
56#include "d11ucode_ext.h"
57#ifdef BCMSDIO
58#include <bcmsdh.h>
59#endif
60#include <bcmotp.h>
61
62/* BMAC_NOTE: With WLC_HIGH defined, some fns in this file make calls to high level
63 * functions defined in the headers below. We should be eliminating those calls and
64 * will be able to delete these include lines.
65 */
66#include <wlc_antsel.h>
67
68#include <pcie_core.h>
69
70#include <wlc_alloc.h>
71
72#define TIMER_INTERVAL_WATCHDOG_BMAC 1000 /* watchdog timer, in unit of ms */
73
74#define SYNTHPU_DLY_APHY_US 3700 /* a phy synthpu_dly time in us */
75#define SYNTHPU_DLY_BPHY_US 1050 /* b/g phy synthpu_dly time in us, default */
76#define SYNTHPU_DLY_NPHY_US 2048 /* n phy REV3 synthpu_dly time in us, default */
77#define SYNTHPU_DLY_LPPHY_US 300 /* lpphy synthpu_dly time in us */
78
79#define SYNTHPU_DLY_PHY_US_QT 100 /* QT synthpu_dly time in us */
80
81#ifndef BMAC_DUP_TO_REMOVE
82#define WLC_RM_WAIT_TX_SUSPEND 4 /* Wait Tx Suspend */
83
84#define ANTCNT 10 /* vanilla M_MAX_ANTCNT value */
85
86#endif /* BMAC_DUP_TO_REMOVE */
87
88#define DMAREG(wlc_hw, direction, fifonum) (D11REV_LT(wlc_hw->corerev, 11) ? \
89 ((direction == DMA_TX) ? \
90 (void*)(uintptr)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].xmt) : \
91 (void*)(uintptr)&(wlc_hw->regs->fifo.f32regs.dmaregs[fifonum].rcv)) : \
92 ((direction == DMA_TX) ? \
93 (void*)(uintptr)&(wlc_hw->regs->fifo.f64regs[fifonum].dmaxmt) : \
94 (void*)(uintptr)&(wlc_hw->regs->fifo.f64regs[fifonum].dmarcv)))
95
96/*
97 * The following table lists the buffer memory allocated to xmt fifos in HW.
98 * the size is in units of 256bytes(one block), total size is HW dependent
99 * ucode has default fifo partition, sw can overwrite if necessary
100 *
101 * This is documented in twiki under the topic UcodeTxFifo. Please ensure
102 * the twiki is updated before making changes.
103 */
104
105#define XMTFIFOTBL_STARTREV 20 /* Starting corerev for the fifo size table */
106
107static uint16 xmtfifo_sz[][NFIFO] = {
108 {20, 192, 192, 21, 17, 5}, /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
109 {9, 58, 22, 14, 14, 5}, /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
110 {20, 192, 192, 21, 17, 5}, /* corerev 22: 5120, 49152, 49152, 5376, 4352, 1280 */
111 {20, 192, 192, 21, 17, 5}, /* corerev 23: 5120, 49152, 49152, 5376, 4352, 1280 */
112 {9, 58, 22, 14, 14, 5}, /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
113};
114
115static void wlc_clkctl_clk(wlc_hw_info_t * wlc, uint mode);
116static void wlc_coreinit(wlc_info_t * wlc);
117
118/* used by wlc_wakeucode_init() */
119static void wlc_write_inits(wlc_hw_info_t * wlc_hw, const d11init_t * inits);
120static void wlc_ucode_write(wlc_hw_info_t * wlc_hw, const uint32 ucode[],
121 const uint nbytes);
122static void wlc_ucode_download(wlc_hw_info_t * wlc);
123static void wlc_ucode_txant_set(wlc_hw_info_t * wlc_hw);
124
125/* used by wlc_dpc() */
126static bool wlc_bmac_dotxstatus(wlc_hw_info_t * wlc, tx_status_t * txs,
127 uint32 s2);
128static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t * wlc);
129static bool wlc_bmac_txstatus(wlc_hw_info_t * wlc, bool bound, bool * fatal);
130static bool wlc_bmac_recv(wlc_hw_info_t * wlc_hw, uint fifo, bool bound);
131
132/* used by wlc_down() */
133static void wlc_flushqueues(wlc_info_t * wlc);
134
135static void wlc_write_mhf(wlc_hw_info_t * wlc_hw, uint16 * mhfs);
136static void wlc_mctrl_reset(wlc_hw_info_t * wlc_hw);
137static void wlc_corerev_fifofixup(wlc_hw_info_t * wlc_hw);
138
139/* Low Level Prototypes */
140static uint16 wlc_bmac_read_objmem(wlc_hw_info_t * wlc_hw, uint offset,
141 uint32 sel);
142static void wlc_bmac_write_objmem(wlc_hw_info_t * wlc_hw, uint offset, uint16 v,
143 uint32 sel);
144static bool wlc_bmac_attach_dmapio(wlc_info_t * wlc, uint j, bool wme);
145static void wlc_bmac_detach_dmapio(wlc_hw_info_t * wlc_hw);
146static void wlc_ucode_bsinit(wlc_hw_info_t * wlc_hw);
147static bool wlc_validboardtype(wlc_hw_info_t * wlc);
148static bool wlc_isgoodchip(wlc_hw_info_t * wlc_hw);
149static char *wlc_get_macaddr(wlc_hw_info_t * wlc_hw);
150static void wlc_mhfdef(wlc_info_t * wlc, uint16 * mhfs, uint16 mhf2_init);
151static void wlc_mctrl_write(wlc_hw_info_t * wlc_hw);
152static void wlc_ucode_mute_override_set(wlc_hw_info_t * wlc_hw);
153static void wlc_ucode_mute_override_clear(wlc_hw_info_t * wlc_hw);
154static uint32 wlc_wlintrsoff(wlc_info_t * wlc);
155static void wlc_wlintrsrestore(wlc_info_t * wlc, uint32 macintmask);
156static void wlc_gpio_init(wlc_info_t * wlc);
157static void wlc_write_hw_bcntemplate0(wlc_hw_info_t * wlc_hw, void *bcn,
158 int len);
159static void wlc_write_hw_bcntemplate1(wlc_hw_info_t * wlc_hw, void *bcn,
160 int len);
161static void wlc_bmac_bsinit(wlc_info_t * wlc, chanspec_t chanspec);
162static uint32 wlc_setband_inact(wlc_info_t * wlc, uint bandunit);
163static void wlc_bmac_setband(wlc_hw_info_t * wlc_hw, uint bandunit,
164 chanspec_t chanspec);
165static void wlc_bmac_update_slot_timing(wlc_hw_info_t * wlc_hw, bool shortslot);
166static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t * wlc_hw);
167static uint16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t * wlc_hw,
168 uint8 rate);
169
170/* === Low Level functions === */
171
172void wlc_bmac_set_shortslot(wlc_hw_info_t * wlc_hw, bool shortslot)
173{
174 wlc_hw->shortslot = shortslot;
175
176 if (BAND_2G(wlc_hw->band->bandtype) && wlc_hw->up) {
177 wlc_suspend_mac_and_wait(wlc_hw->wlc);
178 wlc_bmac_update_slot_timing(wlc_hw, shortslot);
179 wlc_enable_mac(wlc_hw->wlc);
180 }
181}
182
183/*
184 * Update the slot timing for standard 11b/g (20us slots)
185 * or shortslot 11g (9us slots)
186 * The PSM needs to be suspended for this call.
187 */
188static void wlc_bmac_update_slot_timing(wlc_hw_info_t * wlc_hw, bool shortslot)
189{
190 osl_t *osh;
191 d11regs_t *regs;
192
193 osh = wlc_hw->osh;
194 regs = wlc_hw->regs;
195
196 if (shortslot) {
197 /* 11g short slot: 11a timing */
198 W_REG(osh, &regs->ifs_slot, 0x0207); /* APHY_SLOT_TIME */
199 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
200 } else {
201 /* 11g long slot: 11b timing */
202 W_REG(osh, &regs->ifs_slot, 0x0212); /* BPHY_SLOT_TIME */
203 wlc_bmac_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
204 }
205}
206
207static void WLBANDINITFN(wlc_ucode_bsinit) (wlc_hw_info_t * wlc_hw) {
208 /* init microcode host flags */
209 wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
210
211 /* do band-specific ucode IHR, SHM, and SCR inits */
212 if (D11REV_IS(wlc_hw->corerev, 23)) {
213 if (WLCISNPHY(wlc_hw->band)) {
214 wlc_write_inits(wlc_hw, d11n0bsinitvals16);
215 } else {
216 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
217 __func__, wlc_hw->unit, wlc_hw->corerev));
218 }
219 } else {
220 if (D11REV_IS(wlc_hw->corerev, 24)) {
221 if (WLCISLCNPHY(wlc_hw->band)) {
222 wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
223 } else
224 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n", __func__, wlc_hw->unit, wlc_hw->corerev));
225 } else {
226 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
227 __func__, wlc_hw->unit, wlc_hw->corerev));
228 }
229 }
230}
231
232/* switch to new band but leave it inactive */
233static uint32 WLBANDINITFN(wlc_setband_inact) (wlc_info_t * wlc, uint bandunit) {
234 wlc_hw_info_t *wlc_hw = wlc->hw;
235 uint32 macintmask;
236 uint32 tmp;
237
238 WL_TRACE(("wl%d: wlc_setband_inact\n", wlc_hw->unit));
239
240 ASSERT(bandunit != wlc_hw->band->bandunit);
241 ASSERT(si_iscoreup(wlc_hw->sih));
242 ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
243 0);
244
245 /* disable interrupts */
246 macintmask = wl_intrsoff(wlc->wl);
247
248 /* radio off */
249 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
250
251 ASSERT(wlc_hw->clk);
252
253 if (D11REV_LT(wlc_hw->corerev, 17))
254 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
255
256 wlc_bmac_core_phy_clk(wlc_hw, OFF);
257
258 wlc_setxband(wlc_hw, bandunit);
259
260 return (macintmask);
261}
262
263/* Process received frames */
264/*
265 * Return TRUE if more frames need to be processed. FALSE otherwise.
266 * Param 'bound' indicates max. # frames to process before break out.
267 */
268static bool BCMFASTPATH
269wlc_bmac_recv(wlc_hw_info_t * wlc_hw, uint fifo, bool bound)
270{
271 void *p;
272 void *head = NULL;
273 void *tail = NULL;
274 uint n = 0;
275 uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
276 uint32 tsf_h, tsf_l;
277 wlc_d11rxhdr_t *wlc_rxhdr = NULL;
278
279 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
280 /* gather received frames */
281 while ((p = dma_rx(wlc_hw->di[fifo]))) {
282
283 if (!tail)
284 head = tail = p;
285 else {
286 PKTSETLINK(tail, p);
287 tail = p;
288 }
289
290 /* !give others some time to run! */
291 if (++n >= bound_limit)
292 break;
293 }
294
295 /* get the TSF REG reading */
296 wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
297
298 /* post more rbufs */
299 dma_rxfill(wlc_hw->di[fifo]);
300
301 /* process each frame */
302 while ((p = head) != NULL) {
303 head = PKTLINK(head);
304 PKTSETLINK(p, NULL);
305
306 /* record the tsf_l in wlc_rxd11hdr */
307 wlc_rxhdr = (wlc_d11rxhdr_t *) PKTDATA(p);
308 wlc_rxhdr->tsf_l = htol32(tsf_l);
309
310 /* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
311 wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
312
313 wlc_recv(wlc_hw->wlc, p);
314 }
315
316 return (n >= bound_limit);
317}
318
319/* second-level interrupt processing
320 * Return TRUE if another dpc needs to be re-scheduled. FALSE otherwise.
321 * Param 'bounded' indicates if applicable loops should be bounded.
322 */
323bool BCMFASTPATH wlc_dpc(wlc_info_t * wlc, bool bounded)
324{
325 uint32 macintstatus;
326 wlc_hw_info_t *wlc_hw = wlc->hw;
327 d11regs_t *regs = wlc_hw->regs;
328 bool fatal = FALSE;
329
330 if (DEVICEREMOVED(wlc)) {
331 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
332 wl_down(wlc->wl);
333 return FALSE;
334 }
335
336 /* grab and clear the saved software intstatus bits */
337 macintstatus = wlc->macintstatus;
338 wlc->macintstatus = 0;
339
340 WL_TRACE(("wl%d: wlc_dpc: macintstatus 0x%x\n", wlc_hw->unit,
341 macintstatus));
342
343 if (macintstatus & MI_PRQ) {
344 /* Process probe request FIFO */
345 ASSERT(0 && "PRQ Interrupt in non-MBSS");
346 }
347
348 /* BCN template is available */
349 /* ZZZ: Use AP_ACTIVE ? */
350 if (AP_ENAB(wlc->pub) && (!APSTA_ENAB(wlc->pub) || wlc->aps_associated)
351 && (macintstatus & MI_BCNTPL)) {
352 wlc_update_beacon(wlc);
353 }
354
355 /* PMQ entry addition */
356 if (macintstatus & MI_PMQ) {
357 }
358
359 /* tx status */
360 if (macintstatus & MI_TFS) {
361 if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
362 wlc->macintstatus |= MI_TFS;
363 if (fatal) {
364 WL_ERROR(("MI_TFS: fatal\n"));
365 goto fatal;
366 }
367 }
368
369 if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
370 wlc_tbtt(wlc, regs);
371
372 /* ATIM window end */
373 if (macintstatus & MI_ATIMWINEND) {
374 WL_TRACE(("wlc_isr: end of ATIM window\n"));
375
376 OR_REG(wlc_hw->osh, &regs->maccommand, wlc->qvalid);
377 wlc->qvalid = 0;
378 }
379
380 /* phy tx error */
381 if (macintstatus & MI_PHYTXERR) {
382 WLCNTINCR(wlc->pub->_cnt->txphyerr);
383 }
384
385 /* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
386 if (macintstatus & MI_DMAINT) {
387 if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
388 wlc->macintstatus |= MI_DMAINT;
389 }
390 }
391
392 /* TX FIFO suspend/flush completion */
393 if (macintstatus & MI_TXSTOP) {
394 if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
395 /* WL_ERROR(("dpc: fifo_suspend_comlete\n")); */
396 }
397 }
398
399 /* noise sample collected */
400 if (macintstatus & MI_BG_NOISE) {
401 wlc_phy_noise_sample_intr(wlc_hw->band->pi);
402 }
403
404 if (macintstatus & MI_GP0) {
405 WL_ERROR(("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now));
406
407 printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
408 __func__, CHIPID(wlc_hw->sih->chip),
409 CHIPREV(wlc_hw->sih->chiprev));
410
411 WLCNTINCR(wlc->pub->_cnt->psmwds);
412
413 /* big hammer */
414 wl_init(wlc->wl);
415 }
416
417 /* gptimer timeout */
418 if (macintstatus & MI_TO) {
419 W_REG(wlc_hw->osh, &regs->gptimer, 0);
420 }
421
422 if (macintstatus & MI_RFDISABLE) {
423#if defined(BCMDBG)
424 uint32 rfd = R_REG(wlc_hw->osh, &regs->phydebug) & PDBG_RFD;
425#endif
426
427 WL_ERROR(("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n", wlc_hw->unit, rfd));
428
429 WLCNTINCR(wlc->pub->_cnt->rfdisable);
430 }
431
432 /* send any enq'd tx packets. Just makes sure to jump start tx */
433 if (!pktq_empty(&wlc->active_queue->q))
434 wlc_send_q(wlc, wlc->active_queue);
435
436 ASSERT(wlc_ps_check(wlc));
437
438 /* make sure the bound indication and the implementation are in sync */
439 ASSERT(bounded == TRUE || wlc->macintstatus == 0);
440
441 /* it isn't done and needs to be resched if macintstatus is non-zero */
442 return (wlc->macintstatus != 0);
443
444 fatal:
445 wl_init(wlc->wl);
446 return (wlc->macintstatus != 0);
447}
448
449/* common low-level watchdog code */
450void wlc_bmac_watchdog(void *arg)
451{
452 wlc_info_t *wlc = (wlc_info_t *) arg;
453 wlc_hw_info_t *wlc_hw = wlc->hw;
454
455 WL_TRACE(("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit));
456
457 if (!wlc_hw->up)
458 return;
459
460 /* increment second count */
461 wlc_hw->now++;
462
463 /* Check for FIFO error interrupts */
464 wlc_bmac_fifoerrors(wlc_hw);
465
466 /* make sure RX dma has buffers */
467 dma_rxfill(wlc->hw->di[RX_FIFO]);
468 if (D11REV_IS(wlc_hw->corerev, 4)) {
469 dma_rxfill(wlc->hw->di[RX_TXSTATUS_FIFO]);
470 }
471
472 wlc_phy_watchdog(wlc_hw->band->pi);
473}
474
475void
476wlc_bmac_set_chanspec(wlc_hw_info_t * wlc_hw, chanspec_t chanspec, bool mute,
477 struct txpwr_limits *txpwr)
478{
479 uint bandunit;
480
481 WL_TRACE(("wl%d: wlc_bmac_set_chanspec 0x%x\n", wlc_hw->unit,
482 chanspec));
483
484 wlc_hw->chanspec = chanspec;
485
486 /* Switch bands if necessary */
487 if (NBANDS_HW(wlc_hw) > 1) {
488 bandunit = CHSPEC_WLCBANDUNIT(chanspec);
489 if (wlc_hw->band->bandunit != bandunit) {
490 /* wlc_bmac_setband disables other bandunit,
491 * use light band switch if not up yet
492 */
493 if (wlc_hw->up) {
494 wlc_phy_chanspec_radio_set(wlc_hw->
495 bandstate[bandunit]->
496 pi, chanspec);
497 wlc_bmac_setband(wlc_hw, bandunit, chanspec);
498 } else {
499 wlc_setxband(wlc_hw, bandunit);
500 }
501 }
502 }
503
504 wlc_phy_initcal_enable(wlc_hw->band->pi, !mute);
505
506 if (!wlc_hw->up) {
507 if (wlc_hw->clk)
508 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr,
509 chanspec);
510 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
511 } else {
512 wlc_phy_chanspec_set(wlc_hw->band->pi, chanspec);
513 wlc_phy_txpower_limit_set(wlc_hw->band->pi, txpwr, chanspec);
514
515 /* Update muting of the channel */
516 wlc_bmac_mute(wlc_hw, mute, 0);
517 }
518}
519
520int wlc_bmac_revinfo_get(wlc_hw_info_t * wlc_hw, wlc_bmac_revinfo_t * revinfo)
521{
522 si_t *sih = wlc_hw->sih;
523 uint idx;
524
525 revinfo->vendorid = wlc_hw->vendorid;
526 revinfo->deviceid = wlc_hw->deviceid;
527
528 revinfo->boardrev = wlc_hw->boardrev;
529 revinfo->corerev = wlc_hw->corerev;
530 revinfo->sromrev = wlc_hw->sromrev;
531 revinfo->chiprev = sih->chiprev;
532 revinfo->chip = sih->chip;
533 revinfo->chippkg = sih->chippkg;
534 revinfo->boardtype = sih->boardtype;
535 revinfo->boardvendor = sih->boardvendor;
536 revinfo->bustype = sih->bustype;
537 revinfo->buscoretype = sih->buscoretype;
538 revinfo->buscorerev = sih->buscorerev;
539 revinfo->issim = sih->issim;
540
541 revinfo->nbands = NBANDS_HW(wlc_hw);
542
543 for (idx = 0; idx < NBANDS_HW(wlc_hw); idx++) {
544 wlc_hwband_t *band = wlc_hw->bandstate[idx];
545 revinfo->band[idx].bandunit = band->bandunit;
546 revinfo->band[idx].bandtype = band->bandtype;
547 revinfo->band[idx].phytype = band->phytype;
548 revinfo->band[idx].phyrev = band->phyrev;
549 revinfo->band[idx].radioid = band->radioid;
550 revinfo->band[idx].radiorev = band->radiorev;
551 revinfo->band[idx].abgphy_encore = band->abgphy_encore;
552 revinfo->band[idx].anarev = 0;
553
554 }
555 return 0;
556}
557
558int wlc_bmac_state_get(wlc_hw_info_t * wlc_hw, wlc_bmac_state_t * state)
559{
560 state->machwcap = wlc_hw->machwcap;
561
562 return 0;
563}
564
565static bool
566BCMATTACHFN(wlc_bmac_attach_dmapio) (wlc_info_t * wlc, uint j, bool wme) {
567 uint i;
568 char name[8];
569 /* ucode host flag 2 needed for pio mode, independent of band and fifo */
570 uint16 pio_mhf2 = 0;
571 wlc_hw_info_t *wlc_hw = wlc->hw;
572 uint unit = wlc_hw->unit;
573 wlc_tunables_t *tune = wlc->pub->tunables;
574
575 /* name and offsets for dma_attach */
576 snprintf(name, sizeof(name), "wl%d", unit);
577
578 if (wlc_hw->di[0] == 0) { /* Init FIFOs */
579 uint addrwidth;
580 int dma_attach_err = 0;
581 osl_t *osh = wlc_hw->osh;
582
583 /* Find out the DMA addressing capability and let OS know
584 * All the channels within one DMA core have 'common-minimum' same
585 * capability
586 */
587 addrwidth =
588 dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
589 OSL_DMADDRWIDTH(osh, addrwidth);
590
591 if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
592 WL_ERROR(("wl%d: wlc_attach: alloc_dma_resources failed\n", unit));
593 return FALSE;
594 }
595
596 /*
597 * FIFO 0
598 * TX: TX_AC_BK_FIFO (TX AC Background data packets)
599 * RX: RX_FIFO (RX data packets)
600 */
601 ASSERT(TX_AC_BK_FIFO == 0);
602 ASSERT(RX_FIFO == 0);
603 wlc_hw->di[0] = dma_attach(osh, name, wlc_hw->sih,
604 (wme ? DMAREG(wlc_hw, DMA_TX, 0) :
605 NULL), DMAREG(wlc_hw, DMA_RX, 0),
606 (wme ? tune->ntxd : 0), tune->nrxd,
607 tune->rxbufsz, -1, tune->nrxbufpost,
608 WL_HWRXOFF, &wl_msg_level);
609 dma_attach_err |= (NULL == wlc_hw->di[0]);
610
611 /*
612 * FIFO 1
613 * TX: TX_AC_BE_FIFO (TX AC Best-Effort data packets)
614 * (legacy) TX_DATA_FIFO (TX data packets)
615 * RX: UNUSED
616 */
617 ASSERT(TX_AC_BE_FIFO == 1);
618 ASSERT(TX_DATA_FIFO == 1);
619 wlc_hw->di[1] = dma_attach(osh, name, wlc_hw->sih,
620 DMAREG(wlc_hw, DMA_TX, 1), NULL,
621 tune->ntxd, 0, 0, -1, 0, 0,
622 &wl_msg_level);
623 dma_attach_err |= (NULL == wlc_hw->di[1]);
624
625 /*
626 * FIFO 2
627 * TX: TX_AC_VI_FIFO (TX AC Video data packets)
628 * RX: UNUSED
629 */
630 ASSERT(TX_AC_VI_FIFO == 2);
631 wlc_hw->di[2] = dma_attach(osh, name, wlc_hw->sih,
632 DMAREG(wlc_hw, DMA_TX, 2), NULL,
633 tune->ntxd, 0, 0, -1, 0, 0,
634 &wl_msg_level);
635 dma_attach_err |= (NULL == wlc_hw->di[2]);
636 /*
637 * FIFO 3
638 * TX: TX_AC_VO_FIFO (TX AC Voice data packets)
639 * (legacy) TX_CTL_FIFO (TX control & mgmt packets)
640 * RX: RX_TXSTATUS_FIFO (transmit-status packets)
641 * for corerev < 5 only
642 */
643 ASSERT(TX_AC_VO_FIFO == 3);
644 ASSERT(TX_CTL_FIFO == 3);
645 if (D11REV_IS(wlc_hw->corerev, 4)) {
646 ASSERT(RX_TXSTATUS_FIFO == 3);
647 wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
648 DMAREG(wlc_hw, DMA_TX, 3),
649 DMAREG(wlc_hw, DMA_RX, 3),
650 tune->ntxd, tune->nrxd,
651 sizeof(tx_status_t), -1,
652 tune->nrxbufpost, 0,
653 &wl_msg_level);
654 dma_attach_err |= (NULL == wlc_hw->di[3]);
655 } else {
656 wlc_hw->di[3] = dma_attach(osh, name, wlc_hw->sih,
657 DMAREG(wlc_hw, DMA_TX, 3),
658 NULL, tune->ntxd, 0, 0, -1,
659 0, 0, &wl_msg_level);
660 dma_attach_err |= (NULL == wlc_hw->di[3]);
661 }
662/* Cleaner to leave this as if with AP defined */
663
664 if (dma_attach_err) {
665 WL_ERROR(("wl%d: wlc_attach: dma_attach failed\n",
666 unit));
667 return FALSE;
668 }
669
670 /* get pointer to dma engine tx flow control variable */
671 for (i = 0; i < NFIFO; i++)
672 if (wlc_hw->di[i])
673 wlc_hw->txavail[i] =
674 (uint *) dma_getvar(wlc_hw->di[i],
675 "&txavail");
676 }
677
678 /* initial ucode host flags */
679 wlc_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
680
681 return TRUE;
682}
683
684static void BCMATTACHFN(wlc_bmac_detach_dmapio) (wlc_hw_info_t * wlc_hw) {
685 uint j;
686
687 for (j = 0; j < NFIFO; j++) {
688 if (wlc_hw->di[j]) {
689 dma_detach(wlc_hw->di[j]);
690 wlc_hw->di[j] = NULL;
691 }
692 }
693}
694
695/* low level attach
696 * run backplane attach, init nvram
697 * run phy attach
698 * initialize software state for each core and band
699 * put the whole chip in reset(driver down state), no clock
700 */
701
702int
703BCMATTACHFN(wlc_bmac_attach) (wlc_info_t * wlc, uint16 vendor, uint16 device,
704 uint unit, bool piomode, osl_t * osh,
705 void *regsva, uint bustype, void *btparam) {
706 wlc_hw_info_t *wlc_hw;
707 d11regs_t *regs;
708 char *macaddr = NULL;
709 char *vars;
710 uint err = 0;
711 uint j;
712 bool wme = FALSE;
713 shared_phy_params_t sha_params;
714
715 WL_TRACE(("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n", unit,
716 vendor, device));
717
718 ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
719
720 wme = TRUE;
721
722 wlc_hw = wlc->hw;
723 wlc_hw->wlc = wlc;
724 wlc_hw->unit = unit;
725 wlc_hw->osh = osh;
726 wlc_hw->band = wlc_hw->bandstate[0];
727 wlc_hw->_piomode = piomode;
728
729 /* populate wlc_hw_info_t with default values */
730 wlc_bmac_info_init(wlc_hw);
731
732 /*
733 * Do the hardware portion of the attach.
734 * Also initialize software state that depends on the particular hardware
735 * we are running.
736 */
737 wlc_hw->sih = si_attach((uint) device, osh, regsva, bustype, btparam,
738 &wlc_hw->vars, &wlc_hw->vars_size);
739 if (wlc_hw->sih == NULL) {
740 WL_ERROR(("wl%d: wlc_bmac_attach: si_attach failed\n", unit));
741 err = 11;
742 goto fail;
743 }
744 vars = wlc_hw->vars;
745
746 /*
747 * Get vendid/devid nvram overwrites, which could be different
748 * than those the BIOS recognizes for devices on PCMCIA_BUS,
749 * SDIO_BUS, and SROMless devices on PCI_BUS.
750 */
751#ifdef BCMBUSTYPE
752 bustype = BCMBUSTYPE;
753#endif
754 if (bustype != SI_BUS) {
755 char *var;
756
757 if ((var = getvar(vars, "vendid"))) {
758 vendor = (uint16) bcm_strtoul(var, NULL, 0);
759 WL_ERROR(("Overriding vendor id = 0x%x\n", vendor));
760 }
761 if ((var = getvar(vars, "devid"))) {
762 uint16 devid = (uint16) bcm_strtoul(var, NULL, 0);
763 if (devid != 0xffff) {
764 device = devid;
765 WL_ERROR(("Overriding device id = 0x%x\n",
766 device));
767 }
768 }
769
770 /* verify again the device is supported */
771 if (!wlc_chipmatch(vendor, device)) {
772 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n", unit, vendor, device));
773 err = 12;
774 goto fail;
775 }
776 }
777
778 wlc_hw->vendorid = vendor;
779 wlc_hw->deviceid = device;
780
781 /* set bar0 window to point at D11 core */
782 wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
783 wlc_hw->corerev = si_corerev(wlc_hw->sih);
784
785 regs = wlc_hw->regs;
786
787 wlc->regs = wlc_hw->regs;
788
789 /* validate chip, chiprev and corerev */
790 if (!wlc_isgoodchip(wlc_hw)) {
791 err = 13;
792 goto fail;
793 }
794
795 /* initialize power control registers */
796 si_clkctl_init(wlc_hw->sih);
797
798 /* request fastclock and force fastclock for the rest of attach
799 * bring the d11 core out of reset.
800 * For PMU chips, the first wlc_clkctl_clk is no-op since core-clk is still FALSE;
801 * But it will be called again inside wlc_corereset, after d11 is out of reset.
802 */
803 wlc_clkctl_clk(wlc_hw, CLK_FAST);
804 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
805
806 if (!wlc_bmac_validate_chip_access(wlc_hw)) {
807 WL_ERROR(("wl%d: wlc_bmac_attach: validate_chip_access failed\n", unit));
808 err = 14;
809 goto fail;
810 }
811
812 /* get the board rev, used just below */
813 j = getintvar(vars, "boardrev");
814 /* promote srom boardrev of 0xFF to 1 */
815 if (j == BOARDREV_PROMOTABLE)
816 j = BOARDREV_PROMOTED;
817 wlc_hw->boardrev = (uint16) j;
818 if (!wlc_validboardtype(wlc_hw)) {
819 WL_ERROR(("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n", unit, wlc_hw->sih->boardtype, wlc_hw->boardrev));
820 err = 15;
821 goto fail;
822 }
823 wlc_hw->sromrev = (uint8) getintvar(vars, "sromrev");
824 wlc_hw->boardflags = (uint32) getintvar(vars, "boardflags");
825 wlc_hw->boardflags2 = (uint32) getintvar(vars, "boardflags2");
826
827 if (D11REV_LE(wlc_hw->corerev, 4)
828 || (wlc_hw->boardflags & BFL_NOPLLDOWN))
829 wlc_bmac_pllreq(wlc_hw, TRUE, WLC_PLLREQ_SHARED);
830
831 if ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
832 && (si_pci_war16165(wlc_hw->sih)))
833 wlc->war16165 = TRUE;
834
835 /* check device id(srom, nvram etc.) to set bands */
836 if (wlc_hw->deviceid == BCM43224_D11N_ID) {
837 /* Dualband boards */
838 wlc_hw->_nbands = 2;
839 } else
840 wlc_hw->_nbands = 1;
841
842 if ((CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID))
843 wlc_hw->_nbands = 1;
844
845 /* BMAC_NOTE: remove init of pub values when wlc_attach() unconditionally does the
846 * init of these values
847 */
848 wlc->vendorid = wlc_hw->vendorid;
849 wlc->deviceid = wlc_hw->deviceid;
850 wlc->pub->sih = wlc_hw->sih;
851 wlc->pub->corerev = wlc_hw->corerev;
852 wlc->pub->sromrev = wlc_hw->sromrev;
853 wlc->pub->boardrev = wlc_hw->boardrev;
854 wlc->pub->boardflags = wlc_hw->boardflags;
855 wlc->pub->boardflags2 = wlc_hw->boardflags2;
856 wlc->pub->_nbands = wlc_hw->_nbands;
857
858 wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
859
860 if (wlc_hw->physhim == NULL) {
861 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
862 unit));
863 err = 25;
864 goto fail;
865 }
866
867 /* pass all the parameters to wlc_phy_shared_attach in one struct */
868 sha_params.osh = osh;
869 sha_params.sih = wlc_hw->sih;
870 sha_params.physhim = wlc_hw->physhim;
871 sha_params.unit = unit;
872 sha_params.corerev = wlc_hw->corerev;
873 sha_params.vars = vars;
874 sha_params.vid = wlc_hw->vendorid;
875 sha_params.did = wlc_hw->deviceid;
876 sha_params.chip = wlc_hw->sih->chip;
877 sha_params.chiprev = wlc_hw->sih->chiprev;
878 sha_params.chippkg = wlc_hw->sih->chippkg;
879 sha_params.sromrev = wlc_hw->sromrev;
880 sha_params.boardtype = wlc_hw->sih->boardtype;
881 sha_params.boardrev = wlc_hw->boardrev;
882 sha_params.boardvendor = wlc_hw->sih->boardvendor;
883 sha_params.boardflags = wlc_hw->boardflags;
884 sha_params.boardflags2 = wlc_hw->boardflags2;
885 sha_params.bustype = wlc_hw->sih->bustype;
886 sha_params.buscorerev = wlc_hw->sih->buscorerev;
887
888 /* alloc and save pointer to shared phy state area */
889 wlc_hw->phy_sh = wlc_phy_shared_attach(&sha_params);
890 if (!wlc_hw->phy_sh) {
891 err = 16;
892 goto fail;
893 }
894
895 /* initialize software state for each core and band */
896 for (j = 0; j < NBANDS_HW(wlc_hw); j++) {
897 /*
898 * band0 is always 2.4Ghz
899 * band1, if present, is 5Ghz
900 */
901
902 /* So if this is a single band 11a card, use band 1 */
903 if (IS_SINGLEBAND_5G(wlc_hw->deviceid))
904 j = BAND_5G_INDEX;
905
906 wlc_setxband(wlc_hw, j);
907
908 wlc_hw->band->bandunit = j;
909 wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
910 wlc->band->bandunit = j;
911 wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
912 wlc->core->coreidx = si_coreidx(wlc_hw->sih);
913
914 if (D11REV_GE(wlc_hw->corerev, 13)) {
915 wlc_hw->machwcap = R_REG(wlc_hw->osh, &regs->machwcap);
916 wlc_hw->machwcap_backup = wlc_hw->machwcap;
917 }
918
919 /* init tx fifo size */
920 ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
921 ARRAYSIZE(xmtfifo_sz));
922 wlc_hw->xmtfifo_sz =
923 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
924
925 /* Get a phy for this band */
926 if ((wlc_hw->band->pi =
927 wlc_phy_attach(wlc_hw->phy_sh, (void *)(uintptr) regs,
928 wlc_hw->band->bandtype, vars)) == NULL) {
929 WL_ERROR(("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n", unit));
930 err = 17;
931 goto fail;
932 }
933
934 wlc_phy_machwcap_set(wlc_hw->band->pi, wlc_hw->machwcap);
935
936 wlc_phy_get_phyversion(wlc_hw->band->pi, &wlc_hw->band->phytype,
937 &wlc_hw->band->phyrev,
938 &wlc_hw->band->radioid,
939 &wlc_hw->band->radiorev);
940 wlc_hw->band->abgphy_encore =
941 wlc_phy_get_encore(wlc_hw->band->pi);
942 wlc->band->abgphy_encore = wlc_phy_get_encore(wlc_hw->band->pi);
943 wlc_hw->band->core_flags =
944 wlc_phy_get_coreflags(wlc_hw->band->pi);
945
946 /* verify good phy_type & supported phy revision */
947 if (WLCISNPHY(wlc_hw->band)) {
948 if (NCONF_HAS(wlc_hw->band->phyrev))
949 goto good_phy;
950 else
951 goto bad_phy;
952 } else if (WLCISLCNPHY(wlc_hw->band)) {
953 if (LCNCONF_HAS(wlc_hw->band->phyrev))
954 goto good_phy;
955 else
956 goto bad_phy;
957 } else {
958 bad_phy:
959 WL_ERROR(("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n", unit, wlc_hw->band->phytype, wlc_hw->band->phyrev));
960 err = 18;
961 goto fail;
962 }
963
964 good_phy:
965 /* BMAC_NOTE: wlc->band->pi should not be set below and should be done in the
966 * high level attach. However we can not make that change until all low level access
967 * is changed to wlc_hw->band->pi. Instead do the wlc->band->pi init below, keeping
968 * wlc_hw->band->pi as well for incremental update of low level fns, and cut over
969 * low only init when all fns updated.
970 */
971 wlc->band->pi = wlc_hw->band->pi;
972 wlc->band->phytype = wlc_hw->band->phytype;
973 wlc->band->phyrev = wlc_hw->band->phyrev;
974 wlc->band->radioid = wlc_hw->band->radioid;
975 wlc->band->radiorev = wlc_hw->band->radiorev;
976
977 /* default contention windows size limits */
978 wlc_hw->band->CWmin = APHY_CWMIN;
979 wlc_hw->band->CWmax = PHY_CWMAX;
980
981 if (!wlc_bmac_attach_dmapio(wlc, j, wme)) {
982 err = 19;
983 goto fail;
984 }
985 }
986
987 /* disable core to match driver "down" state */
988 wlc_coredisable(wlc_hw);
989
990 /* Match driver "down" state */
991 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
992 si_pci_down(wlc_hw->sih);
993
994 /* register sb interrupt callback functions */
995 si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
996 (void *)wlc_wlintrsrestore, NULL, wlc);
997
998 /* turn off pll and xtal to match driver "down" state */
999 wlc_bmac_xtal(wlc_hw, OFF);
1000
1001 /* *********************************************************************
1002 * The hardware is in the DOWN state at this point. D11 core
1003 * or cores are in reset with clocks off, and the board PLLs
1004 * are off if possible.
1005 *
1006 * Beyond this point, wlc->sbclk == FALSE and chip registers
1007 * should not be touched.
1008 *********************************************************************
1009 */
1010
1011 /* init etheraddr state variables */
1012 if ((macaddr = wlc_get_macaddr(wlc_hw)) == NULL) {
1013 WL_ERROR(("wl%d: wlc_bmac_attach: macaddr not found\n", unit));
1014 err = 21;
1015 goto fail;
1016 }
1017 bcm_ether_atoe(macaddr, &wlc_hw->etheraddr);
1018 if (ETHER_ISBCAST((char *)&wlc_hw->etheraddr) ||
1019 ETHER_ISNULLADDR((char *)&wlc_hw->etheraddr)) {
1020 WL_ERROR(("wl%d: wlc_bmac_attach: bad macaddr %s\n", unit,
1021 macaddr));
1022 err = 22;
1023 goto fail;
1024 }
1025
1026 WL_ERROR(("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
1027 __func__, wlc_hw->deviceid, wlc_hw->_nbands,
1028 wlc_hw->sih->boardtype, macaddr));
1029
1030 return err;
1031
1032 fail:
1033 WL_ERROR(("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err));
1034 return err;
1035}
1036
1037/*
1038 * Initialize wlc_info default values ...
1039 * may get overrides later in this function
1040 * BMAC_NOTES, move low out and resolve the dangling ones
1041 */
1042void BCMATTACHFN(wlc_bmac_info_init) (wlc_hw_info_t * wlc_hw) {
1043 wlc_info_t *wlc = wlc_hw->wlc;
1044
1045 /* set default sw macintmask value */
1046 wlc->defmacintmask = DEF_MACINTMASK;
1047
1048 /* various 802.11g modes */
1049 wlc_hw->shortslot = FALSE;
1050
1051 wlc_hw->SFBL = RETRY_SHORT_FB;
1052 wlc_hw->LFBL = RETRY_LONG_FB;
1053
1054 /* default mac retry limits */
1055 wlc_hw->SRL = RETRY_SHORT_DEF;
1056 wlc_hw->LRL = RETRY_LONG_DEF;
1057 wlc_hw->chanspec = CH20MHZ_CHSPEC(1);
1058}
1059
1060/*
1061 * low level detach
1062 */
1063int BCMATTACHFN(wlc_bmac_detach) (wlc_info_t * wlc) {
1064 uint i;
1065 wlc_hwband_t *band;
1066 wlc_hw_info_t *wlc_hw = wlc->hw;
1067 int callbacks;
1068
1069 callbacks = 0;
1070
1071 if (wlc_hw->sih) {
1072 /* detach interrupt sync mechanism since interrupt is disabled and per-port
1073 * interrupt object may has been freed. this must be done before sb core switch
1074 */
1075 si_deregister_intr_callback(wlc_hw->sih);
1076
1077 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1078 si_pci_sleep(wlc_hw->sih);
1079 }
1080
1081 wlc_bmac_detach_dmapio(wlc_hw);
1082
1083 band = wlc_hw->band;
1084 for (i = 0; i < NBANDS_HW(wlc_hw); i++) {
1085 if (band->pi) {
1086 /* Detach this band's phy */
1087 wlc_phy_detach(band->pi);
1088 band->pi = NULL;
1089 }
1090 band = wlc_hw->bandstate[OTHERBANDUNIT(wlc)];
1091 }
1092
1093 /* Free shared phy state */
1094 wlc_phy_shared_detach(wlc_hw->phy_sh);
1095
1096 wlc_phy_shim_detach(wlc_hw->physhim);
1097
1098 /* free vars */
1099 if (wlc_hw->vars) {
1100 MFREE(wlc_hw->osh, wlc_hw->vars, wlc_hw->vars_size);
1101 wlc_hw->vars = NULL;
1102 }
1103
1104 if (wlc_hw->sih) {
1105 si_detach(wlc_hw->sih);
1106 wlc_hw->sih = NULL;
1107 }
1108
1109 return callbacks;
1110
1111}
1112
1113void BCMINITFN(wlc_bmac_reset) (wlc_hw_info_t * wlc_hw) {
1114 WL_TRACE(("wl%d: wlc_bmac_reset\n", wlc_hw->unit));
1115
1116 WLCNTINCR(wlc_hw->wlc->pub->_cnt->reset);
1117
1118 /* reset the core */
1119 if (!DEVICEREMOVED(wlc_hw->wlc))
1120 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1121
1122 /* purge the dma rings */
1123 wlc_flushqueues(wlc_hw->wlc);
1124
1125 wlc_reset_bmac_done(wlc_hw->wlc);
1126}
1127
1128void
1129BCMINITFN(wlc_bmac_init) (wlc_hw_info_t * wlc_hw, chanspec_t chanspec,
1130 bool mute) {
1131 uint32 macintmask;
1132 bool fastclk;
1133 wlc_info_t *wlc = wlc_hw->wlc;
1134
1135 WL_TRACE(("wl%d: wlc_bmac_init\n", wlc_hw->unit));
1136
1137 /* request FAST clock if not on */
1138 if (!(fastclk = wlc_hw->forcefastclk))
1139 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1140
1141 /* disable interrupts */
1142 macintmask = wl_intrsoff(wlc->wl);
1143
1144 /* set up the specified band and chanspec */
1145 wlc_setxband(wlc_hw, CHSPEC_WLCBANDUNIT(chanspec));
1146 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
1147
1148 /* do one-time phy inits and calibration */
1149 wlc_phy_cal_init(wlc_hw->band->pi);
1150
1151 /* core-specific initialization */
1152 wlc_coreinit(wlc);
1153
1154 /* suspend the tx fifos and mute the phy for preism cac time */
1155 if (mute)
1156 wlc_bmac_mute(wlc_hw, ON, PHY_MUTE_FOR_PREISM);
1157
1158 /* band-specific inits */
1159 wlc_bmac_bsinit(wlc, chanspec);
1160
1161 /* restore macintmask */
1162 wl_intrsrestore(wlc->wl, macintmask);
1163
1164 /* seed wake_override with WLC_WAKE_OVERRIDE_MACSUSPEND since the mac is suspended
1165 * and wlc_enable_mac() will clear this override bit.
1166 */
1167 mboolset(wlc_hw->wake_override, WLC_WAKE_OVERRIDE_MACSUSPEND);
1168
1169 /*
1170 * initialize mac_suspend_depth to 1 to match ucode initial suspended state
1171 */
1172 wlc_hw->mac_suspend_depth = 1;
1173
1174 /* restore the clk */
1175 if (!fastclk)
1176 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1177}
1178
1179int BCMINITFN(wlc_bmac_up_prep) (wlc_hw_info_t * wlc_hw) {
1180 uint coremask;
1181
1182 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1183
1184 ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
1185
1186 /*
1187 * Enable pll and xtal, initialize the power control registers,
1188 * and force fastclock for the remainder of wlc_up().
1189 */
1190 wlc_bmac_xtal(wlc_hw, ON);
1191 si_clkctl_init(wlc_hw->sih);
1192 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1193
1194 /*
1195 * Configure pci/pcmcia here instead of in wlc_attach()
1196 * to allow mfg hotswap: down, hotswap (chip power cycle), up.
1197 */
1198 coremask = (1 << wlc_hw->wlc->core->coreidx);
1199
1200 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1201 si_pci_setup(wlc_hw->sih, coremask);
1202
1203 ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
1204
1205 /*
1206 * Need to read the hwradio status here to cover the case where the system
1207 * is loaded with the hw radio disabled. We do not want to bring the driver up in this case.
1208 */
1209 if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
1210 /* put SB PCI in down state again */
1211 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1212 si_pci_down(wlc_hw->sih);
1213 wlc_bmac_xtal(wlc_hw, OFF);
1214 return BCME_RADIOOFF;
1215 }
1216
1217 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1218 si_pci_up(wlc_hw->sih);
1219
1220 /* reset the d11 core */
1221 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
1222
1223 return 0;
1224}
1225
1226int BCMINITFN(wlc_bmac_up_finish) (wlc_hw_info_t * wlc_hw) {
1227 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1228
1229 wlc_hw->up = TRUE;
1230 wlc_phy_hw_state_upd(wlc_hw->band->pi, TRUE);
1231
1232 /* FULLY enable dynamic power control and d11 core interrupt */
1233 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1234 ASSERT(wlc_hw->wlc->macintmask == 0);
1235 wl_intrson(wlc_hw->wlc->wl);
1236 return 0;
1237}
1238
1239int BCMUNINITFN(wlc_bmac_down_prep) (wlc_hw_info_t * wlc_hw) {
1240 bool dev_gone;
1241 uint callbacks = 0;
1242
1243 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1244
1245 if (!wlc_hw->up)
1246 return callbacks;
1247
1248 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1249
1250 /* disable interrupts */
1251 if (dev_gone)
1252 wlc_hw->wlc->macintmask = 0;
1253 else {
1254 /* now disable interrupts */
1255 wl_intrsoff(wlc_hw->wlc->wl);
1256
1257 /* ensure we're running on the pll clock again */
1258 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1259 }
1260 /* down phy at the last of this stage */
1261 callbacks += wlc_phy_down(wlc_hw->band->pi);
1262
1263 return callbacks;
1264}
1265
1266int BCMUNINITFN(wlc_bmac_down_finish) (wlc_hw_info_t * wlc_hw) {
1267 uint callbacks = 0;
1268 bool dev_gone;
1269
1270 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
1271
1272 if (!wlc_hw->up)
1273 return callbacks;
1274
1275 wlc_hw->up = FALSE;
1276 wlc_phy_hw_state_upd(wlc_hw->band->pi, FALSE);
1277
1278 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
1279
1280 if (dev_gone) {
1281 wlc_hw->sbclk = FALSE;
1282 wlc_hw->clk = FALSE;
1283 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, FALSE);
1284
1285 /* reclaim any posted packets */
1286 wlc_flushqueues(wlc_hw->wlc);
1287 } else {
1288
1289 /* Reset and disable the core */
1290 if (si_iscoreup(wlc_hw->sih)) {
1291 if (R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) &
1292 MCTL_EN_MAC)
1293 wlc_suspend_mac_and_wait(wlc_hw->wlc);
1294 callbacks += wl_reset(wlc_hw->wlc->wl);
1295 wlc_coredisable(wlc_hw);
1296 }
1297
1298 /* turn off primary xtal and pll */
1299 if (!wlc_hw->noreset) {
1300 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS)
1301 si_pci_down(wlc_hw->sih);
1302 wlc_bmac_xtal(wlc_hw, OFF);
1303 }
1304 }
1305
1306 return callbacks;
1307}
1308
1309void wlc_bmac_wait_for_wake(wlc_hw_info_t * wlc_hw)
1310{
1311 if (D11REV_IS(wlc_hw->corerev, 4)) /* no slowclock */
1312 OSL_DELAY(5);
1313 else {
1314 /* delay before first read of ucode state */
1315 OSL_DELAY(40);
1316
1317 /* wait until ucode is no longer asleep */
1318 SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
1319 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1320 }
1321
1322 ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
1323}
1324
1325void wlc_bmac_hw_etheraddr(wlc_hw_info_t * wlc_hw, struct ether_addr *ea)
1326{
1327 bcopy(&wlc_hw->etheraddr, ea, ETHER_ADDR_LEN);
1328}
1329
1330void wlc_bmac_set_hw_etheraddr(wlc_hw_info_t * wlc_hw, struct ether_addr *ea)
1331{
1332 bcopy(ea, &wlc_hw->etheraddr, ETHER_ADDR_LEN);
1333}
1334
1335int wlc_bmac_bandtype(wlc_hw_info_t * wlc_hw)
1336{
1337 return (wlc_hw->band->bandtype);
1338}
1339
1340void *wlc_cur_phy(wlc_info_t * wlc)
1341{
1342 wlc_hw_info_t *wlc_hw = wlc->hw;
1343 return ((void *)wlc_hw->band->pi);
1344}
1345
1346/* control chip clock to save power, enable dynamic clock or force fast clock */
1347static void wlc_clkctl_clk(wlc_hw_info_t * wlc_hw, uint mode)
1348{
1349 if (PMUCTL_ENAB(wlc_hw->sih)) {
1350 /* new chips with PMU, CCS_FORCEHT will distribute the HT clock on backplane,
1351 * but mac core will still run on ALP(not HT) when it enters powersave mode,
1352 * which means the FCA bit may not be set.
1353 * should wakeup mac if driver wants it to run on HT.
1354 */
1355
1356 if (wlc_hw->clk) {
1357 if (mode == CLK_FAST) {
1358 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1359 CCS_FORCEHT);
1360
1361 OSL_DELAY(64);
1362
1363 SPINWAIT(((R_REG
1364 (wlc_hw->osh,
1365 &wlc_hw->regs->
1366 clk_ctl_st) & CCS_HTAVAIL) == 0),
1367 PMU_MAX_TRANSITION_DLY);
1368 ASSERT(R_REG
1369 (wlc_hw->osh,
1370 &wlc_hw->regs->
1371 clk_ctl_st) & CCS_HTAVAIL);
1372 } else {
1373 if ((wlc_hw->sih->pmurev == 0) &&
1374 (R_REG
1375 (wlc_hw->osh,
1376 &wlc_hw->regs->
1377 clk_ctl_st) & (CCS_FORCEHT | CCS_HTAREQ)))
1378 SPINWAIT(((R_REG
1379 (wlc_hw->osh,
1380 &wlc_hw->regs->
1381 clk_ctl_st) & CCS_HTAVAIL)
1382 == 0),
1383 PMU_MAX_TRANSITION_DLY);
1384 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
1385 ~CCS_FORCEHT);
1386 }
1387 }
1388 wlc_hw->forcefastclk = (mode == CLK_FAST);
1389 } else {
1390 bool wakeup_ucode;
1391
1392 /* old chips w/o PMU, force HT through cc,
1393 * then use FCA to verify mac is running fast clock
1394 */
1395
1396 wakeup_ucode = D11REV_LT(wlc_hw->corerev, 9);
1397
1398 if (wlc_hw->up && wakeup_ucode)
1399 wlc_ucode_wake_override_set(wlc_hw,
1400 WLC_WAKE_OVERRIDE_CLKCTL);
1401
1402 wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
1403
1404 if (D11REV_LT(wlc_hw->corerev, 11)) {
1405 /* ucode WAR for old chips */
1406 if (wlc_hw->forcefastclk)
1407 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK,
1408 MHF1_FORCEFASTCLK, WLC_BAND_ALL);
1409 else
1410 wlc_bmac_mhf(wlc_hw, MHF1, MHF1_FORCEFASTCLK, 0,
1411 WLC_BAND_ALL);
1412 }
1413
1414 /* check fast clock is available (if core is not in reset) */
1415 if (D11REV_GT(wlc_hw->corerev, 4) && wlc_hw->forcefastclk
1416 && wlc_hw->clk)
1417 ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
1418
1419 /* keep the ucode wake bit on if forcefastclk is on
1420 * since we do not want ucode to put us back to slow clock
1421 * when it dozes for PM mode.
1422 * Code below matches the wake override bit with current forcefastclk state
1423 * Only setting bit in wake_override instead of waking ucode immediately
1424 * since old code (wlc.c 1.4499) had this behavior. Older code set
1425 * wlc->forcefastclk but only had the wake happen if the wakup_ucode work
1426 * (protected by an up check) was executed just below.
1427 */
1428 if (wlc_hw->forcefastclk)
1429 mboolset(wlc_hw->wake_override,
1430 WLC_WAKE_OVERRIDE_FORCEFAST);
1431 else
1432 mboolclr(wlc_hw->wake_override,
1433 WLC_WAKE_OVERRIDE_FORCEFAST);
1434
1435 /* ok to clear the wakeup now */
1436 if (wlc_hw->up && wakeup_ucode)
1437 wlc_ucode_wake_override_clear(wlc_hw,
1438 WLC_WAKE_OVERRIDE_CLKCTL);
1439 }
1440}
1441
1442/* set initial host flags value */
1443static void
1444BCMINITFN(wlc_mhfdef) (wlc_info_t * wlc, uint16 * mhfs, uint16 mhf2_init) {
1445 wlc_hw_info_t *wlc_hw = wlc->hw;
1446
1447 bzero(mhfs, sizeof(uint16) * MHFMAX);
1448
1449 mhfs[MHF2] |= mhf2_init;
1450
1451 /* prohibit use of slowclock on multifunction boards */
1452 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1453 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1454
1455 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1456 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1457 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1458 }
1459}
1460
1461/* set or clear ucode host flag bits
1462 * it has an optimization for no-change write
1463 * it only writes through shared memory when the core has clock;
1464 * pre-CLK changes should use wlc_write_mhf to get around the optimization
1465 *
1466 *
1467 * bands values are: WLC_BAND_AUTO <--- Current band only
1468 * WLC_BAND_5G <--- 5G band only
1469 * WLC_BAND_2G <--- 2G band only
1470 * WLC_BAND_ALL <--- All bands
1471 */
1472void
1473wlc_bmac_mhf(wlc_hw_info_t * wlc_hw, uint8 idx, uint16 mask, uint16 val,
1474 int bands)
1475{
1476 uint16 save;
1477 uint16 addr[MHFMAX] =
1478 { M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1479 M_HOST_FLAGS5
1480 };
1481 wlc_hwband_t *band;
1482
1483 ASSERT((val & ~mask) == 0);
1484 ASSERT(idx < MHFMAX);
1485 ASSERT(ARRAYSIZE(addr) == MHFMAX);
1486
1487 switch (bands) {
1488 /* Current band only or all bands,
1489 * then set the band to current band
1490 */
1491 case WLC_BAND_AUTO:
1492 case WLC_BAND_ALL:
1493 band = wlc_hw->band;
1494 break;
1495 case WLC_BAND_5G:
1496 band = wlc_hw->bandstate[BAND_5G_INDEX];
1497 break;
1498 case WLC_BAND_2G:
1499 band = wlc_hw->bandstate[BAND_2G_INDEX];
1500 break;
1501 default:
1502 ASSERT(0);
1503 band = NULL;
1504 }
1505
1506 if (band) {
1507 save = band->mhfs[idx];
1508 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1509
1510 /* optimization: only write through if changed, and
1511 * changed band is the current band
1512 */
1513 if (wlc_hw->clk && (band->mhfs[idx] != save)
1514 && (band == wlc_hw->band))
1515 wlc_bmac_write_shm(wlc_hw, addr[idx],
1516 (uint16) band->mhfs[idx]);
1517 }
1518
1519 if (bands == WLC_BAND_ALL) {
1520 wlc_hw->bandstate[0]->mhfs[idx] =
1521 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1522 wlc_hw->bandstate[1]->mhfs[idx] =
1523 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1524 }
1525}
1526
1527uint16 wlc_bmac_mhf_get(wlc_hw_info_t * wlc_hw, uint8 idx, int bands)
1528{
1529 wlc_hwband_t *band;
1530 ASSERT(idx < MHFMAX);
1531
1532 switch (bands) {
1533 case WLC_BAND_AUTO:
1534 band = wlc_hw->band;
1535 break;
1536 case WLC_BAND_5G:
1537 band = wlc_hw->bandstate[BAND_5G_INDEX];
1538 break;
1539 case WLC_BAND_2G:
1540 band = wlc_hw->bandstate[BAND_2G_INDEX];
1541 break;
1542 default:
1543 ASSERT(0);
1544 band = NULL;
1545 }
1546
1547 if (!band)
1548 return 0;
1549
1550 return band->mhfs[idx];
1551}
1552
1553static void wlc_write_mhf(wlc_hw_info_t * wlc_hw, uint16 * mhfs)
1554{
1555 uint8 idx;
1556 uint16 addr[] =
1557 { M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1558 M_HOST_FLAGS5
1559 };
1560
1561 ASSERT(ARRAYSIZE(addr) == MHFMAX);
1562
1563 for (idx = 0; idx < MHFMAX; idx++) {
1564 wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
1565 }
1566}
1567
1568/* set the maccontrol register to desired reset state and
1569 * initialize the sw cache of the register
1570 */
1571static void wlc_mctrl_reset(wlc_hw_info_t * wlc_hw)
1572{
1573 /* IHR accesses are always enabled, PSM disabled, HPS off and WAKE on */
1574 wlc_hw->maccontrol = 0;
1575 wlc_hw->suspended_fifos = 0;
1576 wlc_hw->wake_override = 0;
1577 wlc_hw->mute_override = 0;
1578 wlc_bmac_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1579}
1580
1581/* set or clear maccontrol bits */
1582void wlc_bmac_mctrl(wlc_hw_info_t * wlc_hw, uint32 mask, uint32 val)
1583{
1584 uint32 maccontrol;
1585 uint32 new_maccontrol;
1586
1587 ASSERT((val & ~mask) == 0);
1588
1589 maccontrol = wlc_hw->maccontrol;
1590 new_maccontrol = (maccontrol & ~mask) | val;
1591
1592 /* if the new maccontrol value is the same as the old, nothing to do */
1593 if (new_maccontrol == maccontrol)
1594 return;
1595
1596 /* something changed, cache the new value */
1597 wlc_hw->maccontrol = new_maccontrol;
1598
1599 /* write the new values with overrides applied */
1600 wlc_mctrl_write(wlc_hw);
1601}
1602
1603/* write the software state of maccontrol and overrides to the maccontrol register */
1604static void wlc_mctrl_write(wlc_hw_info_t * wlc_hw)
1605{
1606 uint32 maccontrol = wlc_hw->maccontrol;
1607
1608 /* OR in the wake bit if overridden */
1609 if (wlc_hw->wake_override)
1610 maccontrol |= MCTL_WAKE;
1611
1612 /* set AP and INFRA bits for mute if needed */
1613 if (wlc_hw->mute_override) {
1614 maccontrol &= ~(MCTL_AP);
1615 maccontrol |= MCTL_INFRA;
1616 }
1617
1618 W_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol, maccontrol);
1619}
1620
1621void wlc_ucode_wake_override_set(wlc_hw_info_t * wlc_hw, uint32 override_bit)
1622{
1623 ASSERT((wlc_hw->wake_override & override_bit) == 0);
1624
1625 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1626 mboolset(wlc_hw->wake_override, override_bit);
1627 return;
1628 }
1629
1630 mboolset(wlc_hw->wake_override, override_bit);
1631
1632 wlc_mctrl_write(wlc_hw);
1633 wlc_bmac_wait_for_wake(wlc_hw);
1634
1635 return;
1636}
1637
1638void wlc_ucode_wake_override_clear(wlc_hw_info_t * wlc_hw, uint32 override_bit)
1639{
1640 ASSERT(wlc_hw->wake_override & override_bit);
1641
1642 mboolclr(wlc_hw->wake_override, override_bit);
1643
1644 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1645 return;
1646
1647 wlc_mctrl_write(wlc_hw);
1648
1649 return;
1650}
1651
1652/* When driver needs ucode to stop beaconing, it has to make sure that
1653 * MCTL_AP is clear and MCTL_INFRA is set
1654 * Mode MCTL_AP MCTL_INFRA
1655 * AP 1 1
1656 * STA 0 1 <--- This will ensure no beacons
1657 * IBSS 0 0
1658 */
1659static void wlc_ucode_mute_override_set(wlc_hw_info_t * wlc_hw)
1660{
1661 wlc_hw->mute_override = 1;
1662
1663 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1664 * override, then there is no change to write
1665 */
1666 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1667 return;
1668
1669 wlc_mctrl_write(wlc_hw);
1670
1671 return;
1672}
1673
1674/* Clear the override on AP and INFRA bits */
1675static void wlc_ucode_mute_override_clear(wlc_hw_info_t * wlc_hw)
1676{
1677 if (wlc_hw->mute_override == 0)
1678 return;
1679
1680 wlc_hw->mute_override = 0;
1681
1682 /* if maccontrol already has AP == 0 and INFRA == 1 without this
1683 * override, then there is no change to write
1684 */
1685 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1686 return;
1687
1688 wlc_mctrl_write(wlc_hw);
1689}
1690
1691/*
1692 * Write a MAC address to the rcmta structure
1693 */
1694void
1695wlc_bmac_set_rcmta(wlc_hw_info_t * wlc_hw, int idx,
1696 const struct ether_addr *addr)
1697{
1698 d11regs_t *regs = wlc_hw->regs;
1699 volatile uint16 *objdata16 =
1700 (volatile uint16 *)(uintptr) & regs->objdata;
1701 uint32 mac_hm;
1702 uint16 mac_l;
1703 osl_t *osh;
1704
1705 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
1706
1707 ASSERT(wlc_hw->corerev > 4);
1708
1709 mac_hm =
1710 (addr->octet[3] << 24) | (addr->octet[2] << 16) | (addr->
1711 octet[1] << 8) |
1712 addr->octet[0];
1713 mac_l = (addr->octet[5] << 8) | addr->octet[4];
1714
1715 osh = wlc_hw->osh;
1716
1717 W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
1718 (void)R_REG(osh, &regs->objaddr);
1719 W_REG(osh, &regs->objdata, mac_hm);
1720 W_REG(osh, &regs->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
1721 (void)R_REG(osh, &regs->objaddr);
1722 W_REG(osh, objdata16, mac_l);
1723}
1724
1725/*
1726 * Write a MAC address to the given match reg offset in the RXE match engine.
1727 */
1728void
1729wlc_bmac_set_addrmatch(wlc_hw_info_t * wlc_hw, int match_reg_offset,
1730 const struct ether_addr *addr)
1731{
1732 d11regs_t *regs;
1733 uint16 mac_l;
1734 uint16 mac_m;
1735 uint16 mac_h;
1736 osl_t *osh;
1737
1738 WL_TRACE(("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit));
1739
1740 ASSERT((match_reg_offset < RCM_SIZE) || (wlc_hw->corerev == 4));
1741
1742 regs = wlc_hw->regs;
1743 mac_l = addr->octet[0] | (addr->octet[1] << 8);
1744 mac_m = addr->octet[2] | (addr->octet[3] << 8);
1745 mac_h = addr->octet[4] | (addr->octet[5] << 8);
1746
1747 osh = wlc_hw->osh;
1748
1749 /* enter the MAC addr into the RXE match registers */
1750 W_REG(osh, &regs->rcm_ctl, RCM_INC_DATA | match_reg_offset);
1751 W_REG(osh, &regs->rcm_mat_data, mac_l);
1752 W_REG(osh, &regs->rcm_mat_data, mac_m);
1753 W_REG(osh, &regs->rcm_mat_data, mac_h);
1754
1755}
1756
1757void
1758wlc_bmac_write_template_ram(wlc_hw_info_t * wlc_hw, int offset, int len,
1759 void *buf)
1760{
1761 d11regs_t *regs;
1762 uint32 word;
1763 bool be_bit;
1764#ifdef IL_BIGENDIAN
1765 volatile uint16 *dptr = NULL;
1766#endif /* IL_BIGENDIAN */
1767 osl_t *osh;
1768
1769 WL_TRACE(("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit));
1770
1771 regs = wlc_hw->regs;
1772 osh = wlc_hw->osh;
1773
1774 ASSERT(ISALIGNED(offset, sizeof(uint32)));
1775 ASSERT(ISALIGNED(len, sizeof(uint32)));
1776 ASSERT((offset & ~0xffff) == 0);
1777
1778 W_REG(osh, &regs->tplatewrptr, offset);
1779
1780 /* if MCTL_BIGEND bit set in mac control register,
1781 * the chip swaps data in fifo, as well as data in
1782 * template ram
1783 */
1784 be_bit = (R_REG(osh, &regs->maccontrol) & MCTL_BIGEND) != 0;
1785
1786 while (len > 0) {
1787 bcopy((uint8 *) buf, &word, sizeof(uint32));
1788
1789 if (be_bit)
1790 word = hton32(word);
1791 else
1792 word = htol32(word);
1793
1794 W_REG(osh, &regs->tplatewrdata, word);
1795
1796 buf = (uint8 *) buf + sizeof(uint32);
1797 len -= sizeof(uint32);
1798 }
1799}
1800
1801void wlc_bmac_set_cwmin(wlc_hw_info_t * wlc_hw, uint16 newmin)
1802{
1803 osl_t *osh;
1804
1805 osh = wlc_hw->osh;
1806 wlc_hw->band->CWmin = newmin;
1807
1808 W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1809 (void)R_REG(osh, &wlc_hw->regs->objaddr);
1810 W_REG(osh, &wlc_hw->regs->objdata, newmin);
1811}
1812
1813void wlc_bmac_set_cwmax(wlc_hw_info_t * wlc_hw, uint16 newmax)
1814{
1815 osl_t *osh;
1816
1817 osh = wlc_hw->osh;
1818 wlc_hw->band->CWmax = newmax;
1819
1820 W_REG(osh, &wlc_hw->regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1821 (void)R_REG(osh, &wlc_hw->regs->objaddr);
1822 W_REG(osh, &wlc_hw->regs->objdata, newmax);
1823}
1824
1825void wlc_bmac_bw_set(wlc_hw_info_t * wlc_hw, uint16 bw)
1826{
1827 bool fastclk;
1828 uint32 tmp;
1829
1830 /* request FAST clock if not on */
1831 if (!(fastclk = wlc_hw->forcefastclk))
1832 wlc_clkctl_clk(wlc_hw, CLK_FAST);
1833
1834 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1835
1836 ASSERT(wlc_hw->clk);
1837 if (D11REV_LT(wlc_hw->corerev, 17))
1838 tmp = R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol);
1839
1840 wlc_bmac_phy_reset(wlc_hw);
1841 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1842
1843 /* restore the clk */
1844 if (!fastclk)
1845 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
1846}
1847
1848static void
1849wlc_write_hw_bcntemplate0(wlc_hw_info_t * wlc_hw, void *bcn, int len)
1850{
1851 d11regs_t *regs = wlc_hw->regs;
1852
1853 wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
1854 bcn);
1855 /* write beacon length to SCR */
1856 ASSERT(len < 65536);
1857 wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (uint16) len);
1858 /* mark beacon0 valid */
1859 OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN0VLD);
1860}
1861
1862static void
1863wlc_write_hw_bcntemplate1(wlc_hw_info_t * wlc_hw, void *bcn, int len)
1864{
1865 d11regs_t *regs = wlc_hw->regs;
1866
1867 wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
1868 bcn);
1869 /* write beacon length to SCR */
1870 ASSERT(len < 65536);
1871 wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (uint16) len);
1872 /* mark beacon1 valid */
1873 OR_REG(wlc_hw->osh, &regs->maccommand, MCMD_BCN1VLD);
1874}
1875
1876/* mac is assumed to be suspended at this point */
1877void
1878wlc_bmac_write_hw_bcntemplates(wlc_hw_info_t * wlc_hw, void *bcn, int len,
1879 bool both)
1880{
1881 d11regs_t *regs = wlc_hw->regs;
1882
1883 if (both) {
1884 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1885 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1886 } else {
1887 /* bcn 0 */
1888 if (!(R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN0VLD))
1889 wlc_write_hw_bcntemplate0(wlc_hw, bcn, len);
1890 /* bcn 1 */
1891 else if (!
1892 (R_REG(wlc_hw->osh, &regs->maccommand) & MCMD_BCN1VLD))
1893 wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
1894 else /* one template should always have been available */
1895 ASSERT(0);
1896 }
1897}
1898
1899static void WLBANDINITFN(wlc_bmac_upd_synthpu) (wlc_hw_info_t * wlc_hw) {
1900 uint16 v;
1901 wlc_info_t *wlc = wlc_hw->wlc;
1902 /* update SYNTHPU_DLY */
1903
1904 if (WLCISLCNPHY(wlc->band)) {
1905 v = SYNTHPU_DLY_LPPHY_US;
1906 } else if (WLCISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3))) {
1907 v = SYNTHPU_DLY_NPHY_US;
1908 } else {
1909 v = SYNTHPU_DLY_BPHY_US;
1910 }
1911
1912 wlc_bmac_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1913}
1914
1915/* band-specific init */
1916static void
1917WLBANDINITFN(wlc_bmac_bsinit) (wlc_info_t * wlc, chanspec_t chanspec) {
1918 wlc_hw_info_t *wlc_hw = wlc->hw;
1919
1920 WL_TRACE(("wl%d: wlc_bmac_bsinit: bandunit %d\n", wlc_hw->unit,
1921 wlc_hw->band->bandunit));
1922
1923 /* sanity check */
1924 if (PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion)) !=
1925 PHY_TYPE_LCNXN)
1926 ASSERT((uint)
1927 PHY_TYPE(R_REG(wlc_hw->osh, &wlc_hw->regs->phyversion))
1928 == wlc_hw->band->phytype);
1929
1930 wlc_ucode_bsinit(wlc_hw);
1931
1932 wlc_phy_init(wlc_hw->band->pi, chanspec);
1933
1934 wlc_ucode_txant_set(wlc_hw);
1935
1936 /* cwmin is band-specific, update hardware with value for current band */
1937 wlc_bmac_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1938 wlc_bmac_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1939
1940 wlc_bmac_update_slot_timing(wlc_hw,
1941 BAND_5G(wlc_hw->band->
1942 bandtype) ? TRUE : wlc_hw->
1943 shortslot);
1944
1945 /* write phytype and phyvers */
1946 wlc_bmac_write_shm(wlc_hw, M_PHYTYPE, (uint16) wlc_hw->band->phytype);
1947 wlc_bmac_write_shm(wlc_hw, M_PHYVER, (uint16) wlc_hw->band->phyrev);
1948
1949 /* initialize the txphyctl1 rate table since shmem is shared between bands */
1950 wlc_upd_ofdm_pctl1_table(wlc_hw);
1951
1952 wlc_bmac_upd_synthpu(wlc_hw);
1953}
1954
1955void wlc_bmac_core_phy_clk(wlc_hw_info_t * wlc_hw, bool clk)
1956{
1957 WL_TRACE(("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk));
1958
1959 wlc_hw->phyclk = clk;
1960
1961 if (OFF == clk) { /* clear gmode bit, put phy into reset */
1962
1963 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
1964 (SICF_PRST | SICF_FGC));
1965 OSL_DELAY(1);
1966 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
1967 OSL_DELAY(1);
1968
1969 } else { /* take phy out of reset */
1970
1971 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
1972 OSL_DELAY(1);
1973 si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
1974 OSL_DELAY(1);
1975
1976 }
1977}
1978
1979/* Perform a soft reset of the PHY PLL */
1980void wlc_bmac_core_phypll_reset(wlc_hw_info_t * wlc_hw)
1981{
1982 WL_TRACE(("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit));
1983
1984 si_corereg(wlc_hw->sih, SI_CC_IDX,
1985 OFFSETOF(chipcregs_t, chipcontrol_addr), ~0, 0);
1986 OSL_DELAY(1);
1987 si_corereg(wlc_hw->sih, SI_CC_IDX,
1988 OFFSETOF(chipcregs_t, chipcontrol_data), 0x4, 0);
1989 OSL_DELAY(1);
1990 si_corereg(wlc_hw->sih, SI_CC_IDX,
1991 OFFSETOF(chipcregs_t, chipcontrol_data), 0x4, 4);
1992 OSL_DELAY(1);
1993 si_corereg(wlc_hw->sih, SI_CC_IDX,
1994 OFFSETOF(chipcregs_t, chipcontrol_data), 0x4, 0);
1995 OSL_DELAY(1);
1996}
1997
1998/* light way to turn on phy clock without reset for NPHY only
1999 * refer to wlc_bmac_core_phy_clk for full version
2000 */
2001void wlc_bmac_phyclk_fgc(wlc_hw_info_t * wlc_hw, bool clk)
2002{
2003 /* support(necessary for NPHY and HYPHY) only */
2004 if (!WLCISNPHY(wlc_hw->band))
2005 return;
2006
2007 if (ON == clk)
2008 si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
2009 else
2010 si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
2011
2012}
2013
2014void wlc_bmac_macphyclk_set(wlc_hw_info_t * wlc_hw, bool clk)
2015{
2016 if (ON == clk)
2017 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
2018 else
2019 si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
2020}
2021
2022void wlc_bmac_phy_reset(wlc_hw_info_t * wlc_hw)
2023{
2024 wlc_phy_t *pih = wlc_hw->band->pi;
2025 uint32 phy_bw_clkbits;
2026 bool phy_in_reset = FALSE;
2027
2028 WL_TRACE(("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit));
2029
2030 if (pih == NULL)
2031 return;
2032
2033 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
2034
2035 /* Specfic reset sequence required for NPHY rev 3 and 4 */
2036 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
2037 NREV_LE(wlc_hw->band->phyrev, 4)) {
2038 /* Set the PHY bandwidth */
2039 si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
2040
2041 OSL_DELAY(1);
2042
2043 /* Perform a soft reset of the PHY PLL */
2044 wlc_bmac_core_phypll_reset(wlc_hw);
2045
2046 /* reset the PHY */
2047 si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
2048 (SICF_PRST | SICF_PCLKE));
2049 phy_in_reset = TRUE;
2050 } else {
2051
2052 si_core_cflags(wlc_hw->sih,
2053 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
2054 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
2055 }
2056
2057 OSL_DELAY(2);
2058 wlc_bmac_core_phy_clk(wlc_hw, ON);
2059
2060 if (pih)
2061 wlc_phy_anacore(pih, ON);
2062}
2063
2064/* switch to and initialize new band */
2065static void
2066WLBANDINITFN(wlc_bmac_setband) (wlc_hw_info_t * wlc_hw, uint bandunit,
2067 chanspec_t chanspec) {
2068 wlc_info_t *wlc = wlc_hw->wlc;
2069 uint32 macintmask;
2070
2071 ASSERT(NBANDS_HW(wlc_hw) > 1);
2072 ASSERT(bandunit != wlc_hw->band->bandunit);
2073
2074 /* Enable the d11 core before accessing it */
2075 if (!si_iscoreup(wlc_hw->sih)) {
2076 si_core_reset(wlc_hw->sih, 0, 0);
2077 ASSERT(si_iscoreup(wlc_hw->sih));
2078 wlc_mctrl_reset(wlc_hw);
2079 }
2080
2081 macintmask = wlc_setband_inact(wlc, bandunit);
2082
2083 if (!wlc_hw->up)
2084 return;
2085
2086 wlc_bmac_core_phy_clk(wlc_hw, ON);
2087
2088 /* band-specific initializations */
2089 wlc_bmac_bsinit(wlc, chanspec);
2090
2091 /*
2092 * If there are any pending software interrupt bits,
2093 * then replace these with a harmless nonzero value
2094 * so wlc_dpc() will re-enable interrupts when done.
2095 */
2096 if (wlc->macintstatus)
2097 wlc->macintstatus = MI_DMAINT;
2098
2099 /* restore macintmask */
2100 wl_intrsrestore(wlc->wl, macintmask);
2101
2102 /* ucode should still be suspended.. */
2103 ASSERT((R_REG(wlc_hw->osh, &wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
2104 0);
2105}
2106
2107/* low-level band switch utility routine */
2108void WLBANDINITFN(wlc_setxband) (wlc_hw_info_t * wlc_hw, uint bandunit) {
2109 WL_TRACE(("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit));
2110
2111 wlc_hw->band = wlc_hw->bandstate[bandunit];
2112
2113 /* BMAC_NOTE: until we eliminate need for wlc->band refs in low level code */
2114 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
2115
2116 /* set gmode core flag */
2117 if (wlc_hw->sbclk && !wlc_hw->noreset) {
2118 si_core_cflags(wlc_hw->sih, SICF_GMODE,
2119 ((bandunit == 0) ? SICF_GMODE : 0));
2120 }
2121}
2122
2123static bool BCMATTACHFN(wlc_isgoodchip) (wlc_hw_info_t * wlc_hw) {
2124
2125 /* reject unsupported corerev */
2126 if (!VALID_COREREV(wlc_hw->corerev)) {
2127 WL_ERROR(("unsupported core rev %d\n", wlc_hw->corerev));
2128 return FALSE;
2129 }
2130
2131 return TRUE;
2132}
2133
2134static bool BCMATTACHFN(wlc_validboardtype) (wlc_hw_info_t * wlc_hw) {
2135 bool goodboard = TRUE;
2136 uint boardrev = wlc_hw->boardrev;
2137
2138 if (boardrev == 0)
2139 goodboard = FALSE;
2140 else if (boardrev > 0xff) {
2141 uint brt = (boardrev & 0xf000) >> 12;
2142 uint b0 = (boardrev & 0xf00) >> 8;
2143 uint b1 = (boardrev & 0xf0) >> 4;
2144 uint b2 = boardrev & 0xf;
2145
2146 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
2147 || (b2 > 9))
2148 goodboard = FALSE;
2149 }
2150
2151 if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
2152 return goodboard;
2153
2154 return goodboard;
2155}
2156
2157static char *BCMINITFN(wlc_get_macaddr) (wlc_hw_info_t * wlc_hw) {
2158 const char *varname = "macaddr";
2159 char *macaddr;
2160
2161 /* If macaddr exists, use it (Sromrev4, CIS, ...). */
2162 if ((macaddr = getvar(wlc_hw->vars, varname)) != NULL)
2163 return macaddr;
2164
2165 if (NBANDS_HW(wlc_hw) > 1)
2166 varname = "et1macaddr";
2167 else
2168 varname = "il0macaddr";
2169
2170 if ((macaddr = getvar(wlc_hw->vars, varname)) == NULL) {
2171 WL_ERROR(("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n", wlc_hw->unit, varname));
2172 }
2173
2174 return macaddr;
2175}
2176
2177/*
2178 * Return TRUE if radio is disabled, otherwise FALSE.
2179 * hw radio disable signal is an external pin, users activate it asynchronously
2180 * this function could be called when driver is down and w/o clock
2181 * it operates on different registers depending on corerev and boardflag.
2182 */
2183bool wlc_bmac_radio_read_hwdisabled(wlc_hw_info_t * wlc_hw)
2184{
2185 bool v, clk, xtal;
2186 uint32 resetbits = 0, flags = 0;
2187
2188 xtal = wlc_hw->sbclk;
2189 if (!xtal)
2190 wlc_bmac_xtal(wlc_hw, ON);
2191
2192 /* may need to take core out of reset first */
2193 clk = wlc_hw->clk;
2194 if (!clk) {
2195 if (D11REV_LE(wlc_hw->corerev, 11))
2196 resetbits |= SICF_PCLKE;
2197
2198 /*
2199 * corerev >= 18, mac no longer enables phyclk automatically when driver accesses
2200 * phyreg throughput mac. This can be skipped since only mac reg is accessed below
2201 */
2202 if (D11REV_GE(wlc_hw->corerev, 18))
2203 flags |= SICF_PCLKE;
2204
2205 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2206 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2207 (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2208 (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2209 wlc_hw->regs =
2210 (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2211 0);
2212 si_core_reset(wlc_hw->sih, flags, resetbits);
2213 wlc_mctrl_reset(wlc_hw);
2214 }
2215
2216 v = ((R_REG(wlc_hw->osh, &wlc_hw->regs->phydebug) & PDBG_RFD) != 0);
2217
2218 /* put core back into reset */
2219 if (!clk)
2220 si_core_disable(wlc_hw->sih, 0);
2221
2222 if (!xtal)
2223 wlc_bmac_xtal(wlc_hw, OFF);
2224
2225 return (v);
2226}
2227
2228/* Initialize just the hardware when coming out of POR or S3/S5 system states */
2229void BCMINITFN(wlc_bmac_hw_up) (wlc_hw_info_t * wlc_hw) {
2230 if (wlc_hw->wlc->pub->hw_up)
2231 return;
2232
2233 WL_TRACE(("wl%d: %s:\n", wlc_hw->unit, __func__));
2234
2235 /*
2236 * Enable pll and xtal, initialize the power control registers,
2237 * and force fastclock for the remainder of wlc_up().
2238 */
2239 wlc_bmac_xtal(wlc_hw, ON);
2240 si_clkctl_init(wlc_hw->sih);
2241 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2242
2243 if (BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) {
2244 si_pci_fixcfg(wlc_hw->sih);
2245
2246 /* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
2247 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2248 (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID) ||
2249 (CHIPID(wlc_hw->sih->chip) == BCM43421_CHIP_ID))
2250 wlc_hw->regs =
2251 (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
2252 0);
2253 }
2254
2255 /* Inform phy that a POR reset has occurred so it does a complete phy init */
2256 wlc_phy_por_inform(wlc_hw->band->pi);
2257
2258 wlc_hw->ucode_loaded = FALSE;
2259 wlc_hw->wlc->pub->hw_up = TRUE;
2260
2261 if ((wlc_hw->boardflags & BFL_FEM)
2262 && (CHIPID(wlc_hw->sih->chip) == BCM4313_CHIP_ID)) {
2263 if (!
2264 (wlc_hw->boardrev >= 0x1250
2265 && (wlc_hw->boardflags & BFL_FEM_BT)))
2266 si_epa_4313war(wlc_hw->sih);
2267 }
2268}
2269
2270static bool wlc_dma_rxreset(wlc_hw_info_t * wlc_hw, uint fifo)
2271{
2272 hnddma_t *di = wlc_hw->di[fifo];
2273 osl_t *osh;
2274
2275 if (D11REV_LT(wlc_hw->corerev, 12)) {
2276 bool rxidle = TRUE;
2277 uint16 rcv_frm_cnt = 0;
2278
2279 osh = wlc_hw->osh;
2280
2281 W_REG(osh, &wlc_hw->regs->rcv_fifo_ctl, fifo << 8);
2282 SPINWAIT((!(rxidle = dma_rxidle(di))) &&
2283 ((rcv_frm_cnt =
2284 R_REG(osh, &wlc_hw->regs->rcv_frm_cnt)) != 0),
2285 50000);
2286
2287 if (!rxidle && (rcv_frm_cnt != 0))
2288 WL_ERROR(("wl%d: %s: rxdma[%d] not idle && rcv_frm_cnt(%d) not zero\n", wlc_hw->unit, __func__, fifo, rcv_frm_cnt));
2289 OSL_DELAY(2000);
2290 }
2291
2292 return (dma_rxreset(di));
2293}
2294
2295/* d11 core reset
2296 * ensure fask clock during reset
2297 * reset dma
2298 * reset d11(out of reset)
2299 * reset phy(out of reset)
2300 * clear software macintstatus for fresh new start
2301 * one testing hack wlc_hw->noreset will bypass the d11/phy reset
2302 */
2303void BCMINITFN(wlc_bmac_corereset) (wlc_hw_info_t * wlc_hw, uint32 flags) {
2304 d11regs_t *regs;
2305 uint i;
2306 bool fastclk;
2307 uint32 resetbits = 0;
2308
2309 if (flags == WLC_USE_COREFLAGS)
2310 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
2311
2312 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
2313
2314 regs = wlc_hw->regs;
2315
2316 /* request FAST clock if not on */
2317 if (!(fastclk = wlc_hw->forcefastclk))
2318 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2319
2320 /* reset the dma engines except first time thru */
2321 if (si_iscoreup(wlc_hw->sih)) {
2322 for (i = 0; i < NFIFO; i++)
2323 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
2324 WL_ERROR(("wl%d: %s: dma_txreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, i));
2325 }
2326
2327 if ((wlc_hw->di[RX_FIFO])
2328 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
2329 WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_FIFO));
2330 }
2331 if (D11REV_IS(wlc_hw->corerev, 4)
2332 && wlc_hw->di[RX_TXSTATUS_FIFO]
2333 && (!wlc_dma_rxreset(wlc_hw, RX_TXSTATUS_FIFO))) {
2334 WL_ERROR(("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n", wlc_hw->unit, __func__, RX_TXSTATUS_FIFO));
2335 }
2336 }
2337 /* if noreset, just stop the psm and return */
2338 if (wlc_hw->noreset) {
2339 wlc_hw->wlc->macintstatus = 0; /* skip wl_dpc after down */
2340 wlc_bmac_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2341 return;
2342 }
2343
2344 if (D11REV_LE(wlc_hw->corerev, 11))
2345 resetbits |= SICF_PCLKE;
2346
2347 /*
2348 * corerev >= 18, mac no longer enables phyclk automatically when driver accesses phyreg
2349 * throughput mac, AND phy_reset is skipped at early stage when band->pi is invalid
2350 * need to enable PHY CLK
2351 */
2352 if (D11REV_GE(wlc_hw->corerev, 18))
2353 flags |= SICF_PCLKE;
2354
2355 /* reset the core
2356 * In chips with PMU, the fastclk request goes through d11 core reg 0x1e0, which
2357 * is cleared by the core_reset. have to re-request it.
2358 * This adds some delay and we can optimize it by also requesting fastclk through
2359 * chipcommon during this period if necessary. But that has to work coordinate
2360 * with other driver like mips/arm since they may touch chipcommon as well.
2361 */
2362 wlc_hw->clk = FALSE;
2363 si_core_reset(wlc_hw->sih, flags, resetbits);
2364 wlc_hw->clk = TRUE;
2365 if (wlc_hw->band && wlc_hw->band->pi)
2366 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, TRUE);
2367
2368 wlc_mctrl_reset(wlc_hw);
2369
2370 if (PMUCTL_ENAB(wlc_hw->sih))
2371 wlc_clkctl_clk(wlc_hw, CLK_FAST);
2372
2373 wlc_bmac_phy_reset(wlc_hw);
2374
2375 /* turn on PHY_PLL */
2376 wlc_bmac_core_phypll_ctl(wlc_hw, TRUE);
2377
2378 /* clear sw intstatus */
2379 wlc_hw->wlc->macintstatus = 0;
2380
2381 /* restore the clk setting */
2382 if (!fastclk)
2383 wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
2384}
2385
2386/* If the ucode that supports corerev 5 is used for corerev 9 and above,
2387 * txfifo sizes needs to be modified(increased) since the newer cores
2388 * have more memory.
2389 */
2390static void BCMINITFN(wlc_corerev_fifofixup) (wlc_hw_info_t * wlc_hw) {
2391 d11regs_t *regs = wlc_hw->regs;
2392 uint16 fifo_nu;
2393 uint16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2394 uint16 txfifo_def, txfifo_def1;
2395 uint16 txfifo_cmd;
2396 osl_t *osh;
2397
2398 if (D11REV_LT(wlc_hw->corerev, 9))
2399 goto exit;
2400
2401 /* tx fifos start at TXFIFO_START_BLK from the Base address */
2402 txfifo_startblk = TXFIFO_START_BLK;
2403
2404 osh = wlc_hw->osh;
2405
2406 /* sequence of operations: reset fifo, set fifo size, reset fifo */
2407 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2408
2409 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2410 txfifo_def = (txfifo_startblk & 0xff) |
2411 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2412 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2413 ((((txfifo_endblk -
2414 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2415 txfifo_cmd =
2416 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2417
2418 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2419 W_REG(osh, &regs->xmtfifodef, txfifo_def);
2420 if (D11REV_GE(wlc_hw->corerev, 16))
2421 W_REG(osh, &regs->xmtfifodef1, txfifo_def1);
2422
2423 W_REG(osh, &regs->xmtfifocmd, txfifo_cmd);
2424
2425 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2426 }
2427 exit:
2428 /* need to propagate to shm location to be in sync since ucode/hw won't do this */
2429 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE0,
2430 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2431 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE1,
2432 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2433 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE2,
2434 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2435 xmtfifo_sz[TX_AC_BK_FIFO]));
2436 wlc_bmac_write_shm(wlc_hw, M_FIFOSIZE3,
2437 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2438 xmtfifo_sz[TX_BCMC_FIFO]));
2439}
2440
2441/* d11 core init
2442 * reset PSM
2443 * download ucode/PCM
2444 * let ucode run to suspended
2445 * download ucode inits
2446 * config other core registers
2447 * init dma
2448 */
2449static void BCMINITFN(wlc_coreinit) (wlc_info_t * wlc) {
2450 wlc_hw_info_t *wlc_hw = wlc->hw;
2451 d11regs_t *regs;
2452 uint32 sflags;
2453 uint bcnint_us;
2454 uint i = 0;
2455 bool fifosz_fixup = FALSE;
2456 osl_t *osh;
2457 int err = 0;
2458 uint16 buf[NFIFO];
2459
2460 regs = wlc_hw->regs;
2461 osh = wlc_hw->osh;
2462
2463 WL_TRACE(("wl%d: wlc_coreinit\n", wlc_hw->unit));
2464
2465 /* reset PSM */
2466 wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
2467
2468 wlc_ucode_download(wlc_hw);
2469 /*
2470 * FIFOSZ fixup
2471 * 1) core5-9 use ucode 5 to save space since the PSM is the same
2472 * 2) newer chips, driver wants to controls the fifo allocation
2473 */
2474 if (D11REV_GE(wlc_hw->corerev, 4))
2475 fifosz_fixup = TRUE;
2476
2477 /* let the PSM run to the suspended state, set mode to BSS STA */
2478 W_REG(osh, &regs->macintstatus, -1);
2479 wlc_bmac_mctrl(wlc_hw, ~0,
2480 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
2481
2482 /* wait for ucode to self-suspend after auto-init */
2483 SPINWAIT(((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0),
2484 1000 * 1000);
2485 if ((R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD) == 0)
2486 WL_ERROR(("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
2487 wlc_hw->unit));
2488
2489 wlc_gpio_init(wlc);
2490
2491 sflags = si_core_sflags(wlc_hw->sih, 0, 0);
2492
2493 if (D11REV_IS(wlc_hw->corerev, 23)) {
2494 if (WLCISNPHY(wlc_hw->band))
2495 wlc_write_inits(wlc_hw, d11n0initvals16);
2496 else
2497 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2498 __func__, wlc_hw->unit, wlc_hw->corerev));
2499 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2500 if (WLCISLCNPHY(wlc_hw->band)) {
2501 wlc_write_inits(wlc_hw, d11lcn0initvals24);
2502 } else {
2503 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2504 __func__, wlc_hw->unit, wlc_hw->corerev));
2505 }
2506 } else {
2507 WL_ERROR(("%s: wl%d: unsupported corerev %d\n",
2508 __func__, wlc_hw->unit, wlc_hw->corerev));
2509 }
2510
2511 /* For old ucode, txfifo sizes needs to be modified(increased) for Corerev >= 9 */
2512 if (fifosz_fixup == TRUE) {
2513 wlc_corerev_fifofixup(wlc_hw);
2514 }
2515
2516 /* check txfifo allocations match between ucode and driver */
2517 buf[TX_AC_BE_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE0);
2518 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
2519 i = TX_AC_BE_FIFO;
2520 err = -1;
2521 }
2522 buf[TX_AC_VI_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE1);
2523 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
2524 i = TX_AC_VI_FIFO;
2525 err = -1;
2526 }
2527 buf[TX_AC_BK_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE2);
2528 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
2529 buf[TX_AC_BK_FIFO] &= 0xff;
2530 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
2531 i = TX_AC_BK_FIFO;
2532 err = -1;
2533 }
2534 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
2535 i = TX_AC_VO_FIFO;
2536 err = -1;
2537 }
2538 buf[TX_BCMC_FIFO] = wlc_bmac_read_shm(wlc_hw, M_FIFOSIZE3);
2539 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
2540 buf[TX_BCMC_FIFO] &= 0xff;
2541 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
2542 i = TX_BCMC_FIFO;
2543 err = -1;
2544 }
2545 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
2546 i = TX_ATIM_FIFO;
2547 err = -1;
2548 }
2549 if (err != 0) {
2550 WL_ERROR(("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n", buf[i], wlc_hw->xmtfifo_sz[i], i));
2551 /* DO NOT ASSERT corerev < 4 even there is a mismatch
2552 * shmem, since driver don't overwrite those chip and
2553 * ucode initialize data will be used.
2554 */
2555 if (D11REV_GE(wlc_hw->corerev, 4))
2556 ASSERT(0);
2557 }
2558
2559 /* make sure we can still talk to the mac */
2560 ASSERT(R_REG(osh, &regs->maccontrol) != 0xffffffff);
2561
2562 /* band-specific inits done by wlc_bsinit() */
2563
2564 /* Set up frame burst size and antenna swap threshold init values */
2565 wlc_bmac_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
2566 wlc_bmac_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
2567
2568 /* enable one rx interrupt per received frame */
2569 W_REG(osh, &regs->intrcvlazy[0], (1 << IRL_FC_SHIFT));
2570 if (D11REV_IS(wlc_hw->corerev, 4))
2571 W_REG(osh, &regs->intrcvlazy[3], (1 << IRL_FC_SHIFT));
2572
2573 /* set the station mode (BSS STA) */
2574 wlc_bmac_mctrl(wlc_hw,
2575 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
2576 (MCTL_INFRA | MCTL_DISCARD_PMQ));
2577
2578 /* set up Beacon interval */
2579 bcnint_us = 0x8000 << 10;
2580 W_REG(osh, &regs->tsf_cfprep, (bcnint_us << CFPREP_CBI_SHIFT));
2581 W_REG(osh, &regs->tsf_cfpstart, bcnint_us);
2582 W_REG(osh, &regs->macintstatus, MI_GP1);
2583
2584 /* write interrupt mask */
2585 W_REG(osh, &regs->intctrlregs[RX_FIFO].intmask, DEF_RXINTMASK);
2586 if (D11REV_IS(wlc_hw->corerev, 4))
2587 W_REG(osh, &regs->intctrlregs[RX_TXSTATUS_FIFO].intmask,
2588 DEF_RXINTMASK);
2589
2590 /* allow the MAC to control the PHY clock (dynamic on/off) */
2591 wlc_bmac_macphyclk_set(wlc_hw, ON);
2592
2593 /* program dynamic clock control fast powerup delay register */
2594 if (D11REV_GT(wlc_hw->corerev, 4)) {
2595 wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
2596 W_REG(osh, &regs->scc_fastpwrup_dly, wlc->fastpwrup_dly);
2597 }
2598
2599 /* tell the ucode the corerev */
2600 wlc_bmac_write_shm(wlc_hw, M_MACHW_VER, (uint16) wlc_hw->corerev);
2601
2602 /* tell the ucode MAC capabilities */
2603 if (D11REV_GE(wlc_hw->corerev, 13)) {
2604 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_L,
2605 (uint16) (wlc_hw->machwcap & 0xffff));
2606 wlc_bmac_write_shm(wlc_hw, M_MACHW_CAP_H,
2607 (uint16) ((wlc_hw->
2608 machwcap >> 16) & 0xffff));
2609 }
2610
2611 /* write retry limits to SCR, this done after PSM init */
2612 W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
2613 (void)R_REG(osh, &regs->objaddr);
2614 W_REG(osh, &regs->objdata, wlc_hw->SRL);
2615 W_REG(osh, &regs->objaddr, OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
2616 (void)R_REG(osh, &regs->objaddr);
2617 W_REG(osh, &regs->objdata, wlc_hw->LRL);
2618
2619 /* write rate fallback retry limits */
2620 wlc_bmac_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
2621 wlc_bmac_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
2622
2623 if (D11REV_GE(wlc_hw->corerev, 16)) {
2624 AND_REG(osh, &regs->ifs_ctl, 0x0FFF);
2625 W_REG(osh, &regs->ifs_aifsn, EDCF_AIFSN_MIN);
2626 }
2627
2628 /* dma initializations */
2629 wlc->txpend16165war = 0;
2630
2631 /* init the tx dma engines */
2632 for (i = 0; i < NFIFO; i++) {
2633 if (wlc_hw->di[i])
2634 dma_txinit(wlc_hw->di[i]);
2635 }
2636
2637 /* init the rx dma engine(s) and post receive buffers */
2638 dma_rxinit(wlc_hw->di[RX_FIFO]);
2639 dma_rxfill(wlc_hw->di[RX_FIFO]);
2640 if (D11REV_IS(wlc_hw->corerev, 4)) {
2641 dma_rxinit(wlc_hw->di[RX_TXSTATUS_FIFO]);
2642 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
2643 }
2644}
2645
2646/* This function is used for changing the tsf frac register
2647 * If spur avoidance mode is off, the mac freq will be 80/120/160Mhz
2648 * If spur avoidance mode is on1, the mac freq will be 82/123/164Mhz
2649 * If spur avoidance mode is on2, the mac freq will be 84/126/168Mhz
2650 * HTPHY Formula is 2^26/freq(MHz) e.g.
2651 * For spuron2 - 126MHz -> 2^26/126 = 532610.0
2652 * - 532610 = 0x82082 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x2082
2653 * For spuron: 123MHz -> 2^26/123 = 545600.5
2654 * - 545601 = 0x85341 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x5341
2655 * For spur off: 120MHz -> 2^26/120 = 559240.5
2656 * - 559241 = 0x88889 => tsf_clk_frac_h = 0x8, tsf_clk_frac_l = 0x8889
2657 */
2658
2659void wlc_bmac_switch_macfreq(wlc_hw_info_t * wlc_hw, uint8 spurmode)
2660{
2661 d11regs_t *regs;
2662 osl_t *osh;
2663 regs = wlc_hw->regs;
2664 osh = wlc_hw->osh;
2665
2666 if ((CHIPID(wlc_hw->sih->chip) == BCM43224_CHIP_ID) ||
2667 (CHIPID(wlc_hw->sih->chip) == BCM43225_CHIP_ID)) {
2668 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
2669 W_REG(osh, &regs->tsf_clk_frac_l, 0x2082);
2670 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2671 } else if (spurmode == WL_SPURAVOID_ON1) { /* 123Mhz */
2672 W_REG(osh, &regs->tsf_clk_frac_l, 0x5341);
2673 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2674 } else { /* 120Mhz */
2675 W_REG(osh, &regs->tsf_clk_frac_l, 0x8889);
2676 W_REG(osh, &regs->tsf_clk_frac_h, 0x8);
2677 }
2678 } else if (WLCISLCNPHY(wlc_hw->band)) {
2679 if (spurmode == WL_SPURAVOID_ON1) { /* 82Mhz */
2680 W_REG(osh, &regs->tsf_clk_frac_l, 0x7CE0);
2681 W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2682 } else { /* 80Mhz */
2683 W_REG(osh, &regs->tsf_clk_frac_l, 0xCCCD);
2684 W_REG(osh, &regs->tsf_clk_frac_h, 0xC);
2685 }
2686 }
2687}
2688
2689/* Initialize GPIOs that are controlled by D11 core */
2690static void BCMINITFN(wlc_gpio_init) (wlc_info_t * wlc) {
2691 wlc_hw_info_t *wlc_hw = wlc->hw;
2692 d11regs_t *regs;
2693 uint32 gc, gm;
2694 osl_t *osh;
2695
2696 regs = wlc_hw->regs;
2697 osh = wlc_hw->osh;
2698
2699 /* use GPIO select 0 to get all gpio signals from the gpio out reg */
2700 wlc_bmac_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2701
2702 /*
2703 * Common GPIO setup:
2704 * G0 = LED 0 = WLAN Activity
2705 * G1 = LED 1 = WLAN 2.4 GHz Radio State
2706 * G2 = LED 2 = WLAN 5 GHz Radio State
2707 * G4 = radio disable input (HI enabled, LO disabled)
2708 */
2709
2710 gc = gm = 0;
2711
2712 /* Allocate GPIOs for mimo antenna diversity feature */
2713 if (WLANTSEL_ENAB(wlc)) {
2714 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2715 /* Enable antenna diversity, use 2x3 mode */
2716 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2717 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2718 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2719 MHF3_ANTSEL_MODE, WLC_BAND_ALL);
2720
2721 /* init superswitch control */
2722 wlc_phy_antsel_init(wlc_hw->band->pi, FALSE);
2723
2724 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2725 ASSERT((gm & BOARD_GPIO_12) == 0);
2726 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2727 /* The board itself is powered by these GPIOs (when not sending pattern)
2728 * So set them high
2729 */
2730 OR_REG(osh, &regs->psm_gpio_oe,
2731 (BOARD_GPIO_12 | BOARD_GPIO_13));
2732 OR_REG(osh, &regs->psm_gpio_out,
2733 (BOARD_GPIO_12 | BOARD_GPIO_13));
2734
2735 /* Enable antenna diversity, use 2x4 mode */
2736 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2737 MHF3_ANTSEL_EN, WLC_BAND_ALL);
2738 wlc_bmac_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2739 WLC_BAND_ALL);
2740
2741 /* Configure the desired clock to be 4Mhz */
2742 wlc_bmac_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2743 ANTSEL_CLKDIV_4MHZ);
2744 }
2745 }
2746 /* gpio 9 controls the PA. ucode is responsible for wiggling out and oe */
2747 if (wlc_hw->boardflags & BFL_PACTRL)
2748 gm |= gc |= BOARD_GPIO_PACTRL;
2749
2750 /* apply to gpiocontrol register */
2751 si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
2752}
2753
2754static void BCMATTACHFN(wlc_ucode_download) (wlc_hw_info_t * wlc_hw) {
2755 wlc_info_t *wlc;
2756 wlc = wlc_hw->wlc;
2757
2758 if (wlc_hw->ucode_loaded)
2759 return;
2760
2761 if (D11REV_IS(wlc_hw->corerev, 23)) {
2762 if (WLCISNPHY(wlc_hw->band)) {
2763 wlc_ucode_write(wlc_hw, bcm43xx_16_mimo,
2764 bcm43xx_16_mimosz);
2765 wlc_hw->ucode_loaded = TRUE;
2766 } else
2767 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2768 __func__, wlc_hw->unit, wlc_hw->corerev));
2769 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2770 if (WLCISLCNPHY(wlc_hw->band)) {
2771 wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
2772 bcm43xx_24_lcnsz);
2773 wlc_hw->ucode_loaded = TRUE;
2774 } else {
2775 WL_ERROR(("%s: wl%d: unsupported phy in corerev %d\n",
2776 __func__, wlc_hw->unit, wlc_hw->corerev));
2777 }
2778 }
2779}
2780
2781static void
2782BCMATTACHFN(wlc_ucode_write) (wlc_hw_info_t * wlc_hw, const uint32 ucode[],
2783 const uint nbytes) {
2784 osl_t *osh;
2785 d11regs_t *regs = wlc_hw->regs;
2786 uint i;
2787 uint count;
2788
2789 osh = wlc_hw->osh;
2790
2791 WL_TRACE(("wl%d: wlc_ucode_write\n", wlc_hw->unit));
2792
2793 ASSERT(ISALIGNED(nbytes, sizeof(uint32)));
2794
2795 count = (nbytes / sizeof(uint32));
2796
2797 W_REG(osh, &regs->objaddr, (OBJADDR_AUTO_INC | OBJADDR_UCM_SEL));
2798 (void)R_REG(osh, &regs->objaddr);
2799 for (i = 0; i < count; i++)
2800 W_REG(osh, &regs->objdata, ucode[i]);
2801}
2802
2803static void wlc_write_inits(wlc_hw_info_t * wlc_hw, const d11init_t * inits)
2804{
2805 int i;
2806 osl_t *osh;
2807 volatile uint8 *base;
2808
2809 WL_TRACE(("wl%d: wlc_write_inits\n", wlc_hw->unit));
2810
2811 osh = wlc_hw->osh;
2812 base = (volatile uint8 *)wlc_hw->regs;
2813
2814 for (i = 0; inits[i].addr != 0xffff; i++) {
2815 ASSERT((inits[i].size == 2) || (inits[i].size == 4));
2816
2817 if (inits[i].size == 2)
2818 W_REG(osh, (uint16 *) (uintptr) (base + inits[i].addr),
2819 inits[i].value);
2820 else if (inits[i].size == 4)
2821 W_REG(osh, (uint32 *) (uintptr) (base + inits[i].addr),
2822 inits[i].value);
2823 }
2824}
2825
2826static void wlc_ucode_txant_set(wlc_hw_info_t * wlc_hw)
2827{
2828 uint16 phyctl;
2829 uint16 phytxant = wlc_hw->bmac_phytxant;
2830 uint16 mask = PHY_TXC_ANT_MASK;
2831
2832 /* set the Probe Response frame phy control word */
2833 phyctl = wlc_bmac_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
2834 phyctl = (phyctl & ~mask) | phytxant;
2835 wlc_bmac_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
2836
2837 /* set the Response (ACK/CTS) frame phy control word */
2838 phyctl = wlc_bmac_read_shm(wlc_hw, M_RSP_PCTLWD);
2839 phyctl = (phyctl & ~mask) | phytxant;
2840 wlc_bmac_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
2841}
2842
2843void wlc_bmac_txant_set(wlc_hw_info_t * wlc_hw, uint16 phytxant)
2844{
2845 /* update sw state */
2846 wlc_hw->bmac_phytxant = phytxant;
2847
2848 /* push to ucode if up */
2849 if (!wlc_hw->up)
2850 return;
2851 wlc_ucode_txant_set(wlc_hw);
2852
2853}
2854
2855uint16 wlc_bmac_get_txant(wlc_hw_info_t * wlc_hw)
2856{
2857 return (uint16) wlc_hw->wlc->stf->txant;
2858}
2859
2860void wlc_bmac_antsel_type_set(wlc_hw_info_t * wlc_hw, uint8 antsel_type)
2861{
2862 wlc_hw->antsel_type = antsel_type;
2863
2864 /* Update the antsel type for phy module to use */
2865 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2866}
2867
2868void wlc_bmac_fifoerrors(wlc_hw_info_t * wlc_hw)
2869{
2870 bool fatal = FALSE;
2871 uint unit;
2872 uint intstatus, idx;
2873 d11regs_t *regs = wlc_hw->regs;
2874
2875 unit = wlc_hw->unit;
2876
2877 for (idx = 0; idx < NFIFO; idx++) {
2878 /* read intstatus register and ignore any non-error bits */
2879 intstatus =
2880 R_REG(wlc_hw->osh,
2881 &regs->intctrlregs[idx].intstatus) & I_ERRORS;
2882 if (!intstatus)
2883 continue;
2884
2885 WL_TRACE(("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n", unit,
2886 idx, intstatus));
2887
2888 if (intstatus & I_RO) {
2889 WL_ERROR(("wl%d: fifo %d: receive fifo overflow\n",
2890 unit, idx));
2891 WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxoflo);
2892 fatal = TRUE;
2893 }
2894
2895 if (intstatus & I_PC) {
2896 WL_ERROR(("wl%d: fifo %d: descriptor error\n", unit,
2897 idx));
2898 WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmade);
2899 fatal = TRUE;
2900 }
2901
2902 if (intstatus & I_PD) {
2903 WL_ERROR(("wl%d: fifo %d: data error\n", unit, idx));
2904 WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmada);
2905 fatal = TRUE;
2906 }
2907
2908 if (intstatus & I_DE) {
2909 WL_ERROR(("wl%d: fifo %d: descriptor protocol error\n",
2910 unit, idx));
2911 WLCNTINCR(wlc_hw->wlc->pub->_cnt->dmape);
2912 fatal = TRUE;
2913 }
2914
2915 if (intstatus & I_RU) {
2916 WL_ERROR(("wl%d: fifo %d: receive descriptor underflow\n", unit, idx));
2917 WLCNTINCR(wlc_hw->wlc->pub->_cnt->rxuflo[idx]);
2918 }
2919
2920 if (intstatus & I_XU) {
2921 WL_ERROR(("wl%d: fifo %d: transmit fifo underflow\n",
2922 idx, unit));
2923 WLCNTINCR(wlc_hw->wlc->pub->_cnt->txuflo);
2924 fatal = TRUE;
2925 }
2926
2927 if (fatal) {
2928 wlc_fatal_error(wlc_hw->wlc); /* big hammer */
2929 break;
2930 } else
2931 W_REG(wlc_hw->osh, &regs->intctrlregs[idx].intstatus,
2932 intstatus);
2933 }
2934}
2935
2936void wlc_intrson(wlc_info_t * wlc)
2937{
2938 wlc_hw_info_t *wlc_hw = wlc->hw;
2939 ASSERT(wlc->defmacintmask);
2940 wlc->macintmask = wlc->defmacintmask;
2941 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2942}
2943
2944/* callback for siutils.c, which has only wlc handler, no wl
2945 * they both check up, not only because there is no need to off/restore d11 interrupt
2946 * but also because per-port code may require sync with valid interrupt.
2947 */
2948
2949static uint32 wlc_wlintrsoff(wlc_info_t * wlc)
2950{
2951 if (!wlc->hw->up)
2952 return 0;
2953
2954 return wl_intrsoff(wlc->wl);
2955}
2956
2957static void wlc_wlintrsrestore(wlc_info_t * wlc, uint32 macintmask)
2958{
2959 if (!wlc->hw->up)
2960 return;
2961
2962 wl_intrsrestore(wlc->wl, macintmask);
2963}
2964
2965uint32 wlc_intrsoff(wlc_info_t * wlc)
2966{
2967 wlc_hw_info_t *wlc_hw = wlc->hw;
2968 uint32 macintmask;
2969
2970 if (!wlc_hw->clk)
2971 return 0;
2972
2973 macintmask = wlc->macintmask; /* isr can still happen */
2974
2975 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, 0);
2976 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->macintmask); /* sync readback */
2977 OSL_DELAY(1); /* ensure int line is no longer driven */
2978 wlc->macintmask = 0;
2979
2980 /* return previous macintmask; resolve race between us and our isr */
2981 return (wlc->macintstatus ? 0 : macintmask);
2982}
2983
2984void wlc_intrsrestore(wlc_info_t * wlc, uint32 macintmask)
2985{
2986 wlc_hw_info_t *wlc_hw = wlc->hw;
2987 if (!wlc_hw->clk)
2988 return;
2989
2990 wlc->macintmask = macintmask;
2991 W_REG(wlc_hw->osh, &wlc_hw->regs->macintmask, wlc->macintmask);
2992}
2993
2994void wlc_bmac_mute(wlc_hw_info_t * wlc_hw, bool on, mbool flags)
2995{
2996 struct ether_addr null_ether_addr = { {0, 0, 0, 0, 0, 0} };
2997
2998 if (on) {
2999 /* suspend tx fifos */
3000 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
3001 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
3002 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
3003 wlc_bmac_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
3004
3005 /* zero the address match register so we do not send ACKs */
3006 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3007 &null_ether_addr);
3008 } else {
3009 /* resume tx fifos */
3010 if (!wlc_hw->wlc->tx_suspended) {
3011 wlc_bmac_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
3012 }
3013 wlc_bmac_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
3014 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
3015 wlc_bmac_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
3016
3017 /* Restore address */
3018 wlc_bmac_set_addrmatch(wlc_hw, RCM_MAC_OFFSET,
3019 &wlc_hw->etheraddr);
3020 }
3021
3022 wlc_phy_mute_upd(wlc_hw->band->pi, on, flags);
3023
3024 if (on)
3025 wlc_ucode_mute_override_set(wlc_hw);
3026 else
3027 wlc_ucode_mute_override_clear(wlc_hw);
3028}
3029
3030void wlc_bmac_set_deaf(wlc_hw_info_t * wlc_hw, bool user_flag)
3031{
3032 wlc_phy_set_deaf(wlc_hw->band->pi, user_flag);
3033}
3034
3035int wlc_bmac_xmtfifo_sz_get(wlc_hw_info_t * wlc_hw, uint fifo, uint * blocks)
3036{
3037 if (fifo >= NFIFO)
3038 return BCME_RANGE;
3039
3040 *blocks = wlc_hw->xmtfifo_sz[fifo];
3041
3042 return 0;
3043}
3044
3045int wlc_bmac_xmtfifo_sz_set(wlc_hw_info_t * wlc_hw, uint fifo, uint blocks)
3046{
3047 if (fifo >= NFIFO || blocks > 299)
3048 return BCME_RANGE;
3049
3050 /* BMAC_NOTE, change blocks to uint16 */
3051 wlc_hw->xmtfifo_sz[fifo] = (uint16) blocks;
3052
3053 return 0;
3054}
3055
3056/* wlc_bmac_tx_fifo_suspended:
3057 * Check the MAC's tx suspend status for a tx fifo.
3058 *
3059 * When the MAC acknowledges a tx suspend, it indicates that no more
3060 * packets will be transmitted out the radio. This is independent of
3061 * DMA channel suspension---the DMA may have finished suspending, or may still
3062 * be pulling data into a tx fifo, by the time the MAC acks the suspend
3063 * request.
3064 */
3065bool wlc_bmac_tx_fifo_suspended(wlc_hw_info_t * wlc_hw, uint tx_fifo)
3066{
3067 /* check that a suspend has been requested and is no longer pending */
3068
3069 /*
3070 * for DMA mode, the suspend request is set in xmtcontrol of the DMA engine,
3071 * and the tx fifo suspend at the lower end of the MAC is acknowledged in the
3072 * chnstatus register.
3073 * The tx fifo suspend completion is independent of the DMA suspend completion and
3074 * may be acked before or after the DMA is suspended.
3075 */
3076 if (dma_txsuspended(wlc_hw->di[tx_fifo]) &&
3077 (R_REG(wlc_hw->osh, &wlc_hw->regs->chnstatus) &
3078 (1 << tx_fifo)) == 0)
3079 return TRUE;
3080
3081 return FALSE;
3082}
3083
3084void wlc_bmac_tx_fifo_suspend(wlc_hw_info_t * wlc_hw, uint tx_fifo)
3085{
3086 uint8 fifo = 1 << tx_fifo;
3087
3088 /* Two clients of this code, 11h Quiet period and scanning. */
3089
3090 /* only suspend if not already suspended */
3091 if ((wlc_hw->suspended_fifos & fifo) == fifo)
3092 return;
3093
3094 /* force the core awake only if not already */
3095 if (wlc_hw->suspended_fifos == 0)
3096 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_TXFIFO);
3097
3098 wlc_hw->suspended_fifos |= fifo;
3099
3100 if (wlc_hw->di[tx_fifo]) {
3101 /* Suspending AMPDU transmissions in the middle can cause underflow
3102 * which may result in mismatch between ucode and driver
3103 * so suspend the mac before suspending the FIFO
3104 */
3105 if (WLC_PHY_11N_CAP(wlc_hw->band))
3106 wlc_suspend_mac_and_wait(wlc_hw->wlc);
3107
3108 dma_txsuspend(wlc_hw->di[tx_fifo]);
3109
3110 if (WLC_PHY_11N_CAP(wlc_hw->band))
3111 wlc_enable_mac(wlc_hw->wlc);
3112 }
3113}
3114
3115void wlc_bmac_tx_fifo_resume(wlc_hw_info_t * wlc_hw, uint tx_fifo)
3116{
3117 /* BMAC_NOTE: WLC_TX_FIFO_ENAB is done in wlc_dpc() for DMA case but need to be done
3118 * here for PIO otherwise the watchdog will catch the inconsistency and fire
3119 */
3120 /* Two clients of this code, 11h Quiet period and scanning. */
3121 if (wlc_hw->di[tx_fifo])
3122 dma_txresume(wlc_hw->di[tx_fifo]);
3123
3124 /* allow core to sleep again */
3125 if (wlc_hw->suspended_fifos == 0)
3126 return;
3127 else {
3128 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
3129 if (wlc_hw->suspended_fifos == 0)
3130 wlc_ucode_wake_override_clear(wlc_hw,
3131 WLC_WAKE_OVERRIDE_TXFIFO);
3132 }
3133}
3134
3135/*
3136 * Read and clear macintmask and macintstatus and intstatus registers.
3137 * This routine should be called with interrupts off
3138 * Return:
3139 * -1 if DEVICEREMOVED(wlc) evaluates to TRUE;
3140 * 0 if the interrupt is not for us, or we are in some special cases;
3141 * device interrupt status bits otherwise.
3142 */
3143static INLINE uint32 wlc_intstatus(wlc_info_t * wlc, bool in_isr)
3144{
3145 wlc_hw_info_t *wlc_hw = wlc->hw;
3146 d11regs_t *regs = wlc_hw->regs;
3147 uint32 macintstatus;
3148 uint32 intstatus_rxfifo, intstatus_txsfifo;
3149 osl_t *osh;
3150
3151 osh = wlc_hw->osh;
3152
3153 /* macintstatus includes a DMA interrupt summary bit */
3154 macintstatus = R_REG(osh, &regs->macintstatus);
3155
3156 WL_TRACE(("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus));
3157
3158 /* detect cardbus removed, in power down(suspend) and in reset */
3159 if (DEVICEREMOVED(wlc))
3160 return -1;
3161
3162 /* DEVICEREMOVED succeeds even when the core is still resetting,
3163 * handle that case here.
3164 */
3165 if (macintstatus == 0xffffffff)
3166 return 0;
3167
3168 /* defer unsolicited interrupts */
3169 macintstatus &= (in_isr ? wlc->macintmask : wlc->defmacintmask);
3170
3171 /* if not for us */
3172 if (macintstatus == 0)
3173 return 0;
3174
3175 /* interrupts are already turned off for CFE build
3176 * Caution: For CFE Turning off the interrupts again has some undesired
3177 * consequences
3178 */
3179 /* turn off the interrupts */
3180 W_REG(osh, &regs->macintmask, 0);
3181#ifndef BCMSDIO
3182 (void)R_REG(osh, &regs->macintmask); /* sync readback */
3183#endif
3184 wlc->macintmask = 0;
3185
3186 /* clear device interrupts */
3187 W_REG(osh, &regs->macintstatus, macintstatus);
3188
3189 /* MI_DMAINT is indication of non-zero intstatus */
3190 if (macintstatus & MI_DMAINT) {
3191 if (D11REV_IS(wlc_hw->corerev, 4)) {
3192 intstatus_rxfifo =
3193 R_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus);
3194 intstatus_txsfifo =
3195 R_REG(osh,
3196 &regs->intctrlregs[RX_TXSTATUS_FIFO].
3197 intstatus);
3198 WL_TRACE(("wl%d: intstatus_rxfifo 0x%x, intstatus_txsfifo 0x%x\n", wlc_hw->unit, intstatus_rxfifo, intstatus_txsfifo));
3199
3200 /* defer unsolicited interrupt hints */
3201 intstatus_rxfifo &= DEF_RXINTMASK;
3202 intstatus_txsfifo &= DEF_RXINTMASK;
3203
3204 /* MI_DMAINT bit in macintstatus is indication of RX_FIFO interrupt */
3205 /* clear interrupt hints */
3206 if (intstatus_rxfifo)
3207 W_REG(osh,
3208 &regs->intctrlregs[RX_FIFO].intstatus,
3209 intstatus_rxfifo);
3210 else
3211 macintstatus &= ~MI_DMAINT;
3212
3213 /* MI_TFS bit in macintstatus is encoding of RX_TXSTATUS_FIFO interrupt */
3214 if (intstatus_txsfifo) {
3215 W_REG(osh,
3216 &regs->intctrlregs[RX_TXSTATUS_FIFO].
3217 intstatus, intstatus_txsfifo);
3218 macintstatus |= MI_TFS;
3219 }
3220 } else {
3221 /*
3222 * For corerevs >= 5, only fifo interrupt enabled is I_RI in RX_FIFO.
3223 * If MI_DMAINT is set, assume it is set and clear the interrupt.
3224 */
3225 W_REG(osh, &regs->intctrlregs[RX_FIFO].intstatus,
3226 DEF_RXINTMASK);
3227 }
3228 }
3229
3230 return macintstatus;
3231}
3232
3233/* Update wlc->macintstatus and wlc->intstatus[]. */
3234/* Return TRUE if they are updated successfully. FALSE otherwise */
3235bool wlc_intrsupd(wlc_info_t * wlc)
3236{
3237 uint32 macintstatus;
3238
3239 ASSERT(wlc->macintstatus != 0);
3240
3241 /* read and clear macintstatus and intstatus registers */
3242 macintstatus = wlc_intstatus(wlc, FALSE);
3243
3244 /* device is removed */
3245 if (macintstatus == 0xffffffff)
3246 return FALSE;
3247
3248 /* update interrupt status in software */
3249 wlc->macintstatus |= macintstatus;
3250
3251 return TRUE;
3252}
3253
3254/*
3255 * First-level interrupt processing.
3256 * Return TRUE if this was our interrupt, FALSE otherwise.
3257 * *wantdpc will be set to TRUE if further wlc_dpc() processing is required,
3258 * FALSE otherwise.
3259 */
3260bool BCMFASTPATH wlc_isr(wlc_info_t * wlc, bool * wantdpc)
3261{
3262 wlc_hw_info_t *wlc_hw = wlc->hw;
3263 uint32 macintstatus;
3264
3265 *wantdpc = FALSE;
3266
3267 if (!wlc_hw->up || !wlc->macintmask)
3268 return (FALSE);
3269
3270 /* read and clear macintstatus and intstatus registers */
3271 macintstatus = wlc_intstatus(wlc, TRUE);
3272
3273 if (macintstatus == 0xffffffff)
3274 WL_ERROR(("DEVICEREMOVED detected in the ISR code path.\n"));
3275
3276 /* it is not for us */
3277 if (macintstatus == 0)
3278 return (FALSE);
3279
3280 *wantdpc = TRUE;
3281
3282 /* save interrupt status bits */
3283 ASSERT(wlc->macintstatus == 0);
3284 wlc->macintstatus = macintstatus;
3285
3286 return (TRUE);
3287
3288}
3289
3290/* process tx completion events for corerev < 5 */
3291static bool wlc_bmac_txstatus_corerev4(wlc_hw_info_t * wlc_hw)
3292{
3293 void *status_p;
3294 tx_status_t *txs;
3295 osl_t *osh;
3296 bool fatal = FALSE;
3297
3298 WL_TRACE(("wl%d: wlc_txstatusrecv\n", wlc_hw->unit));
3299
3300 osh = wlc_hw->osh;
3301
3302 while (!fatal && (status_p = dma_rx(wlc_hw->di[RX_TXSTATUS_FIFO]))) {
3303
3304 txs = (tx_status_t *) PKTDATA(status_p);
3305 /* MAC uses little endian only */
3306 ltoh16_buf((void *)txs, sizeof(tx_status_t));
3307
3308 /* shift low bits for tx_status_t status compatibility */
3309 txs->status = (txs->status & ~TXS_COMPAT_MASK)
3310 | (((txs->status & TXS_COMPAT_MASK) << TXS_COMPAT_SHIFT));
3311
3312 fatal = wlc_bmac_dotxstatus(wlc_hw, txs, 0);
3313
3314 PKTFREE(osh, status_p, FALSE);
3315 }
3316
3317 if (fatal)
3318 return TRUE;
3319
3320 /* post more rbufs */
3321 dma_rxfill(wlc_hw->di[RX_TXSTATUS_FIFO]);
3322
3323 return FALSE;
3324}
3325
3326static bool BCMFASTPATH
3327wlc_bmac_dotxstatus(wlc_hw_info_t * wlc_hw, tx_status_t * txs, uint32 s2)
3328{
3329 /* discard intermediate indications for ucode with one legitimate case:
3330 * e.g. if "useRTS" is set. ucode did a successful rts/cts exchange, but the subsequent
3331 * tx of DATA failed. so it will start rts/cts from the beginning (resetting the rts
3332 * transmission count)
3333 */
3334 if (!(txs->status & TX_STATUS_AMPDU)
3335 && (txs->status & TX_STATUS_INTERMEDIATE)) {
3336 return FALSE;
3337 }
3338
3339 return wlc_dotxstatus(wlc_hw->wlc, txs, s2);
3340}
3341
3342/* process tx completion events in BMAC
3343 * Return TRUE if more tx status need to be processed. FALSE otherwise.
3344 */
3345static bool BCMFASTPATH
3346wlc_bmac_txstatus(wlc_hw_info_t * wlc_hw, bool bound, bool * fatal)
3347{
3348 bool morepending = FALSE;
3349 wlc_info_t *wlc = wlc_hw->wlc;
3350
3351 WL_TRACE(("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit));
3352
3353 if (D11REV_IS(wlc_hw->corerev, 4)) {
3354 /* to retire soon */
3355 *fatal = wlc_bmac_txstatus_corerev4(wlc->hw);
3356
3357 if (*fatal)
3358 return 0;
3359 } else {
3360 /* corerev >= 5 */
3361 d11regs_t *regs;
3362 osl_t *osh;
3363 tx_status_t txstatus, *txs;
3364 uint32 s1, s2;
3365 uint n = 0;
3366 /* Param 'max_tx_num' indicates max. # tx status to process before break out. */
3367 uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
3368
3369 txs = &txstatus;
3370 regs = wlc_hw->regs;
3371 osh = wlc_hw->osh;
3372 while (!(*fatal)
3373 && (s1 = R_REG(osh, &regs->frmtxstatus)) & TXS_V) {
3374
3375 if (s1 == 0xffffffff) {
3376 WL_ERROR(("wl%d: %s: dead chip\n",
3377 wlc_hw->unit, __func__));
3378 ASSERT(s1 != 0xffffffff);
3379 return morepending;
3380 }
3381
3382 s2 = R_REG(osh, &regs->frmtxstatus2);
3383
3384 txs->status = s1 & TXS_STATUS_MASK;
3385 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
3386 txs->sequence = s2 & TXS_SEQ_MASK;
3387 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
3388 txs->lasttxtime = 0;
3389
3390 *fatal = wlc_bmac_dotxstatus(wlc_hw, txs, s2);
3391
3392 /* !give others some time to run! */
3393 if (++n >= max_tx_num)
3394 break;
3395 }
3396
3397 if (*fatal)
3398 return 0;
3399
3400 if (n >= max_tx_num)
3401 morepending = TRUE;
3402 }
3403
3404 if (!pktq_empty(&wlc->active_queue->q))
3405 wlc_send_q(wlc, wlc->active_queue);
3406
3407 return morepending;
3408}
3409
3410void wlc_suspend_mac_and_wait(wlc_info_t * wlc)
3411{
3412 wlc_hw_info_t *wlc_hw = wlc->hw;
3413 d11regs_t *regs = wlc_hw->regs;
3414 uint32 mc, mi;
3415 osl_t *osh;
3416
3417 WL_TRACE(("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n", wlc_hw->unit,
3418 wlc_hw->band->bandunit));
3419
3420 /*
3421 * Track overlapping suspend requests
3422 */
3423 wlc_hw->mac_suspend_depth++;
3424 if (wlc_hw->mac_suspend_depth > 1)
3425 return;
3426
3427 osh = wlc_hw->osh;
3428
3429 /* force the core awake */
3430 wlc_ucode_wake_override_set(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3431
3432 mc = R_REG(osh, &regs->maccontrol);
3433
3434 if (mc == 0xffffffff) {
3435 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3436 wl_down(wlc->wl);
3437 return;
3438 }
3439 ASSERT(!(mc & MCTL_PSM_JMP_0));
3440 ASSERT(mc & MCTL_PSM_RUN);
3441 ASSERT(mc & MCTL_EN_MAC);
3442
3443 mi = R_REG(osh, &regs->macintstatus);
3444 if (mi == 0xffffffff) {
3445 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3446 wl_down(wlc->wl);
3447 return;
3448 }
3449 ASSERT(!(mi & MI_MACSSPNDD));
3450
3451 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
3452
3453 SPINWAIT(!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD),
3454 WLC_MAX_MAC_SUSPEND);
3455
3456 if (!(R_REG(osh, &regs->macintstatus) & MI_MACSSPNDD)) {
3457 WL_ERROR(("wl%d: wlc_suspend_mac_and_wait: waited %d uS and "
3458 "MI_MACSSPNDD is still not on.\n",
3459 wlc_hw->unit, WLC_MAX_MAC_SUSPEND));
3460 WL_ERROR(("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n", wlc_hw->unit, R_REG(osh, &regs->psmdebug), R_REG(osh, &regs->phydebug), R_REG(osh, &regs->psm_brc)));
3461 }
3462
3463 mc = R_REG(osh, &regs->maccontrol);
3464 if (mc == 0xffffffff) {
3465 WL_ERROR(("wl%d: %s: dead chip\n", wlc_hw->unit, __func__));
3466 wl_down(wlc->wl);
3467 return;
3468 }
3469 ASSERT(!(mc & MCTL_PSM_JMP_0));
3470 ASSERT(mc & MCTL_PSM_RUN);
3471 ASSERT(!(mc & MCTL_EN_MAC));
3472}
3473
3474void wlc_enable_mac(wlc_info_t * wlc)
3475{
3476 wlc_hw_info_t *wlc_hw = wlc->hw;
3477 d11regs_t *regs = wlc_hw->regs;
3478 uint32 mc, mi;
3479 osl_t *osh;
3480
3481 WL_TRACE(("wl%d: wlc_enable_mac: bandunit %d\n", wlc_hw->unit,
3482 wlc->band->bandunit));
3483
3484 /*
3485 * Track overlapping suspend requests
3486 */
3487 ASSERT(wlc_hw->mac_suspend_depth > 0);
3488 wlc_hw->mac_suspend_depth--;
3489 if (wlc_hw->mac_suspend_depth > 0)
3490 return;
3491
3492 osh = wlc_hw->osh;
3493
3494 mc = R_REG(osh, &regs->maccontrol);
3495 ASSERT(!(mc & MCTL_PSM_JMP_0));
3496 ASSERT(!(mc & MCTL_EN_MAC));
3497 ASSERT(mc & MCTL_PSM_RUN);
3498
3499 wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
3500 W_REG(osh, &regs->macintstatus, MI_MACSSPNDD);
3501
3502 mc = R_REG(osh, &regs->maccontrol);
3503 ASSERT(!(mc & MCTL_PSM_JMP_0));
3504 ASSERT(mc & MCTL_EN_MAC);
3505 ASSERT(mc & MCTL_PSM_RUN);
3506
3507 mi = R_REG(osh, &regs->macintstatus);
3508 ASSERT(!(mi & MI_MACSSPNDD));
3509
3510 wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
3511}
3512
3513void wlc_bmac_ifsctl_edcrs_set(wlc_hw_info_t * wlc_hw, bool abie, bool isht)
3514{
3515 if (!(WLCISNPHY(wlc_hw->band) && (D11REV_GE(wlc_hw->corerev, 16))))
3516 return;
3517
3518 if (isht) {
3519 if (WLCISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 3)) {
3520 AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3521 ~IFS_CTL1_EDCRS);
3522 }
3523 } else {
3524 /* enable EDCRS for non-11n association */
3525 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1, IFS_CTL1_EDCRS);
3526 }
3527
3528 if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3)) {
3529 if (CHSPEC_IS20(wlc_hw->chanspec)) {
3530 /* 20 mhz, use 20U ED only */
3531 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3532 IFS_CTL1_EDCRS);
3533 AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3534 ~IFS_CTL1_EDCRS_20L);
3535 AND_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3536 ~IFS_CTL1_EDCRS_40);
3537 } else {
3538 /* 40 mhz, use 20U 20L and 40 ED */
3539 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3540 IFS_CTL1_EDCRS);
3541 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3542 IFS_CTL1_EDCRS_20L);
3543 OR_REG(wlc_hw->osh, &wlc_hw->regs->ifs_ctl1,
3544 IFS_CTL1_EDCRS_40);
3545 }
3546 }
3547}
3548
3549static void wlc_upd_ofdm_pctl1_table(wlc_hw_info_t * wlc_hw)
3550{
3551 uint8 rate;
3552 uint8 rates[8] = {
3553 WLC_RATE_6M, WLC_RATE_9M, WLC_RATE_12M, WLC_RATE_18M,
3554 WLC_RATE_24M, WLC_RATE_36M, WLC_RATE_48M, WLC_RATE_54M
3555 };
3556 uint16 entry_ptr;
3557 uint16 pctl1;
3558 uint i;
3559
3560 if (!WLC_PHY_11N_CAP(wlc_hw->band))
3561 return;
3562
3563 /* walk the phy rate table and update the entries */
3564 for (i = 0; i < ARRAYSIZE(rates); i++) {
3565 rate = rates[i];
3566
3567 entry_ptr = wlc_bmac_ofdm_ratetable_offset(wlc_hw, rate);
3568
3569 /* read the SHM Rate Table entry OFDM PCTL1 values */
3570 pctl1 =
3571 wlc_bmac_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
3572
3573 /* modify the value */
3574 pctl1 &= ~PHY_TXC1_MODE_MASK;
3575 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
3576
3577 /* Update the SHM Rate Table entry OFDM PCTL1 values */
3578 wlc_bmac_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
3579 pctl1);
3580 }
3581}
3582
3583static uint16 wlc_bmac_ofdm_ratetable_offset(wlc_hw_info_t * wlc_hw, uint8 rate)
3584{
3585 uint i;
3586 uint8 plcp_rate = 0;
3587 struct plcp_signal_rate_lookup {
3588 uint8 rate;
3589 uint8 signal_rate;
3590 };
3591 /* OFDM RATE sub-field of PLCP SIGNAL field, per 802.11 sec 17.3.4.1 */
3592 const struct plcp_signal_rate_lookup rate_lookup[] = {
3593 {WLC_RATE_6M, 0xB},
3594 {WLC_RATE_9M, 0xF},
3595 {WLC_RATE_12M, 0xA},
3596 {WLC_RATE_18M, 0xE},
3597 {WLC_RATE_24M, 0x9},
3598 {WLC_RATE_36M, 0xD},
3599 {WLC_RATE_48M, 0x8},
3600 {WLC_RATE_54M, 0xC}
3601 };
3602
3603 for (i = 0; i < ARRAYSIZE(rate_lookup); i++) {
3604 if (rate == rate_lookup[i].rate) {
3605 plcp_rate = rate_lookup[i].signal_rate;
3606 break;
3607 }
3608 }
3609
3610 /* Find the SHM pointer to the rate table entry by looking in the
3611 * Direct-map Table
3612 */
3613 return (2 * wlc_bmac_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2)));
3614}
3615
3616void wlc_bmac_band_stf_ss_set(wlc_hw_info_t * wlc_hw, uint8 stf_mode)
3617{
3618 wlc_hw->hw_stf_ss_opmode = stf_mode;
3619
3620 if (wlc_hw->clk)
3621 wlc_upd_ofdm_pctl1_table(wlc_hw);
3622}
3623
3624void BCMFASTPATH
3625wlc_bmac_read_tsf(wlc_hw_info_t * wlc_hw, uint32 * tsf_l_ptr,
3626 uint32 * tsf_h_ptr)
3627{
3628 d11regs_t *regs = wlc_hw->regs;
3629
3630 /* read the tsf timer low, then high to get an atomic read */
3631 *tsf_l_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerlow);
3632 *tsf_h_ptr = R_REG(wlc_hw->osh, &regs->tsf_timerhigh);
3633
3634 return;
3635}
3636
3637bool BCMATTACHFN(wlc_bmac_validate_chip_access) (wlc_hw_info_t * wlc_hw) {
3638 d11regs_t *regs;
3639 uint32 w, val;
3640 volatile uint16 *reg16;
3641 osl_t *osh;
3642
3643 WL_TRACE(("wl%d: validate_chip_access\n", wlc_hw->unit));
3644
3645 regs = wlc_hw->regs;
3646 osh = wlc_hw->osh;
3647
3648 /* Validate dchip register access */
3649
3650 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3651 (void)R_REG(osh, &regs->objaddr);
3652 w = R_REG(osh, &regs->objdata);
3653
3654 /* Can we write and read back a 32bit register? */
3655 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3656 (void)R_REG(osh, &regs->objaddr);
3657 W_REG(osh, &regs->objdata, (uint32) 0xaa5555aa);
3658
3659 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3660 (void)R_REG(osh, &regs->objaddr);
3661 val = R_REG(osh, &regs->objdata);
3662 if (val != (uint32) 0xaa5555aa) {
3663 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n", wlc_hw->unit, val));
3664 return (FALSE);
3665 }
3666
3667 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3668 (void)R_REG(osh, &regs->objaddr);
3669 W_REG(osh, &regs->objdata, (uint32) 0x55aaaa55);
3670
3671 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3672 (void)R_REG(osh, &regs->objaddr);
3673 val = R_REG(osh, &regs->objdata);
3674 if (val != (uint32) 0x55aaaa55) {
3675 WL_ERROR(("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n", wlc_hw->unit, val));
3676 return (FALSE);
3677 }
3678
3679 W_REG(osh, &regs->objaddr, OBJADDR_SHM_SEL | 0);
3680 (void)R_REG(osh, &regs->objaddr);
3681 W_REG(osh, &regs->objdata, w);
3682
3683 if (D11REV_LT(wlc_hw->corerev, 11)) {
3684 /* if 32 bit writes are split into 16 bit writes, are they in the correct order
3685 * for our interface, low to high
3686 */
3687 reg16 = (volatile uint16 *)(uintptr) & regs->tsf_cfpstart;
3688
3689 /* write the CFPStart register low half explicitly, starting a buffered write */
3690 W_REG(osh, reg16, 0xAAAA);
3691
3692 /* Write a 32 bit value to CFPStart to test the 16 bit split order.
3693 * If the low 16 bits are written first, followed by the high 16 bits then the
3694 * 32 bit value 0xCCCCBBBB should end up in the register.
3695 * If the order is reversed, then the write to the high half will trigger a buffered
3696 * write of 0xCCCCAAAA.
3697 * If the bus is 32 bits, then this is not much of a test, and the reg should
3698 * have the correct value 0xCCCCBBBB.
3699 */
3700 W_REG(osh, &regs->tsf_cfpstart, 0xCCCCBBBB);
3701
3702 /* verify with the 16 bit registers that have no side effects */
3703 val = R_REG(osh, &regs->tsf_cfpstrt_l);
3704 if (val != (uint) 0xBBBB) {
3705 WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_l = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xBBBB));
3706 return (FALSE);
3707 }
3708 val = R_REG(osh, &regs->tsf_cfpstrt_h);
3709 if (val != (uint) 0xCCCC) {
3710 WL_ERROR(("wl%d: validate_chip_access: tsf_cfpstrt_h = 0x%x, expected" " 0x%x\n", wlc_hw->unit, val, 0xCCCC));
3711 return (FALSE);
3712 }
3713
3714 }
3715
3716 /* clear CFPStart */
3717 W_REG(osh, &regs->tsf_cfpstart, 0);
3718
3719 w = R_REG(osh, &regs->maccontrol);
3720 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
3721 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
3722 WL_ERROR(("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w, (MCTL_IHR_EN | MCTL_WAKE), (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE)));
3723 return (FALSE);
3724 }
3725
3726 return (TRUE);
3727}
3728
3729#define PHYPLL_WAIT_US 100000
3730
3731void wlc_bmac_core_phypll_ctl(wlc_hw_info_t * wlc_hw, bool on)
3732{
3733 d11regs_t *regs;
3734 osl_t *osh;
3735 uint32 tmp;
3736
3737 WL_TRACE(("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit));
3738
3739 tmp = 0;
3740 regs = wlc_hw->regs;
3741 osh = wlc_hw->osh;
3742
3743 if (D11REV_LE(wlc_hw->corerev, 16) || D11REV_IS(wlc_hw->corerev, 20))
3744 return;
3745
3746 if (on) {
3747 if ((wlc_hw->sih->chip == BCM4313_CHIP_ID)) {
3748 OR_REG(osh, &regs->clk_ctl_st,
3749 (CCS_ERSRC_REQ_HT | CCS_ERSRC_REQ_D11PLL |
3750 CCS_ERSRC_REQ_PHYPLL));
3751 SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3752 (CCS_ERSRC_AVAIL_HT)) != (CCS_ERSRC_AVAIL_HT),
3753 PHYPLL_WAIT_US);
3754
3755 tmp = R_REG(osh, &regs->clk_ctl_st);
3756 if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
3757 (CCS_ERSRC_AVAIL_HT)) {
3758 WL_ERROR(("%s: turn on PHY PLL failed\n",
3759 __func__));
3760 ASSERT(0);
3761 }
3762 } else {
3763 OR_REG(osh, &regs->clk_ctl_st,
3764 (CCS_ERSRC_REQ_D11PLL | CCS_ERSRC_REQ_PHYPLL));
3765 SPINWAIT((R_REG(osh, &regs->clk_ctl_st) &
3766 (CCS_ERSRC_AVAIL_D11PLL |
3767 CCS_ERSRC_AVAIL_PHYPLL)) !=
3768 (CCS_ERSRC_AVAIL_D11PLL |
3769 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
3770
3771 tmp = R_REG(osh, &regs->clk_ctl_st);
3772 if ((tmp &
3773 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
3774 !=
3775 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
3776 WL_ERROR(("%s: turn on PHY PLL failed\n",
3777 __func__));
3778 ASSERT(0);
3779 }
3780 }
3781 } else {
3782 /* Since the PLL may be shared, other cores can still be requesting it;
3783 * so we'll deassert the request but not wait for status to comply.
3784 */
3785 AND_REG(osh, &regs->clk_ctl_st, ~CCS_ERSRC_REQ_PHYPLL);
3786 tmp = R_REG(osh, &regs->clk_ctl_st);
3787 }
3788}
3789
3790void wlc_coredisable(wlc_hw_info_t * wlc_hw)
3791{
3792 bool dev_gone;
3793
3794 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
3795
3796 ASSERT(!wlc_hw->up);
3797
3798 dev_gone = DEVICEREMOVED(wlc_hw->wlc);
3799
3800 if (dev_gone)
3801 return;
3802
3803 if (wlc_hw->noreset)
3804 return;
3805
3806 /* radio off */
3807 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
3808
3809 /* turn off analog core */
3810 wlc_phy_anacore(wlc_hw->band->pi, OFF);
3811
3812 /* turn off PHYPLL to save power */
3813 wlc_bmac_core_phypll_ctl(wlc_hw, FALSE);
3814
3815 /* No need to set wlc->pub->radio_active = OFF
3816 * because this function needs down capability and
3817 * radio_active is designed for BCMNODOWN.
3818 */
3819
3820 /* remove gpio controls */
3821 if (wlc_hw->ucode_dbgsel)
3822 si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
3823
3824 wlc_hw->clk = FALSE;
3825 si_core_disable(wlc_hw->sih, 0);
3826 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, FALSE);
3827}
3828
3829/* power both the pll and external oscillator on/off */
3830void wlc_bmac_xtal(wlc_hw_info_t * wlc_hw, bool want)
3831{
3832 WL_TRACE(("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want));
3833
3834 /* dont power down if plldown is false or we must poll hw radio disable */
3835 if (!want && wlc_hw->pllreq)
3836 return;
3837
3838 if (wlc_hw->sih)
3839 si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
3840
3841 wlc_hw->sbclk = want;
3842 if (!wlc_hw->sbclk) {
3843 wlc_hw->clk = FALSE;
3844 if (wlc_hw->band && wlc_hw->band->pi)
3845 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, FALSE);
3846 }
3847}
3848
3849static void wlc_flushqueues(wlc_info_t * wlc)
3850{
3851 wlc_hw_info_t *wlc_hw = wlc->hw;
3852 uint i;
3853
3854 wlc->txpend16165war = 0;
3855
3856 /* free any posted tx packets */
3857 for (i = 0; i < NFIFO; i++)
3858 if (wlc_hw->di[i]) {
3859 dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
3860 TXPKTPENDCLR(wlc, i);
3861 WL_TRACE(("wlc_flushqueues: pktpend fifo %d cleared\n",
3862 i));
3863 }
3864
3865 /* free any posted rx packets */
3866 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
3867 if (D11REV_IS(wlc_hw->corerev, 4))
3868 dma_rxreclaim(wlc_hw->di[RX_TXSTATUS_FIFO]);
3869}
3870
3871uint16 wlc_bmac_read_shm(wlc_hw_info_t * wlc_hw, uint offset)
3872{
3873 return wlc_bmac_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
3874}
3875
3876void wlc_bmac_write_shm(wlc_hw_info_t * wlc_hw, uint offset, uint16 v)
3877{
3878 wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
3879}
3880
3881/* Set a range of shared memory to a value.
3882 * SHM 'offset' needs to be an even address and
3883 * Buffer length 'len' must be an even number of bytes
3884 */
3885void wlc_bmac_set_shm(wlc_hw_info_t * wlc_hw, uint offset, uint16 v, int len)
3886{
3887 int i;
3888
3889 /* offset and len need to be even */
3890 ASSERT((offset & 1) == 0);
3891 ASSERT((len & 1) == 0);
3892
3893 if (len <= 0)
3894 return;
3895
3896 for (i = 0; i < len; i += 2) {
3897 wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
3898 }
3899}
3900
3901static uint16
3902wlc_bmac_read_objmem(wlc_hw_info_t * wlc_hw, uint offset, uint32 sel)
3903{
3904 d11regs_t *regs = wlc_hw->regs;
3905 volatile uint16 *objdata_lo =
3906 (volatile uint16 *)(uintptr) & regs->objdata;
3907 volatile uint16 *objdata_hi = objdata_lo + 1;
3908 uint16 v;
3909
3910 ASSERT((offset & 1) == 0);
3911
3912 W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3913 (void)R_REG(wlc_hw->osh, &regs->objaddr);
3914 if (offset & 2) {
3915 v = R_REG(wlc_hw->osh, objdata_hi);
3916 } else {
3917 v = R_REG(wlc_hw->osh, objdata_lo);
3918 }
3919
3920 return v;
3921}
3922
3923static void
3924wlc_bmac_write_objmem(wlc_hw_info_t * wlc_hw, uint offset, uint16 v, uint32 sel)
3925{
3926 d11regs_t *regs = wlc_hw->regs;
3927 volatile uint16 *objdata_lo =
3928 (volatile uint16 *)(uintptr) & regs->objdata;
3929 volatile uint16 *objdata_hi = objdata_lo + 1;
3930
3931 ASSERT((offset & 1) == 0);
3932
3933 W_REG(wlc_hw->osh, &regs->objaddr, sel | (offset >> 2));
3934 (void)R_REG(wlc_hw->osh, &regs->objaddr);
3935 if (offset & 2) {
3936 W_REG(wlc_hw->osh, objdata_hi, v);
3937 } else {
3938 W_REG(wlc_hw->osh, objdata_lo, v);
3939 }
3940}
3941
3942/* Copy a buffer to shared memory of specified type .
3943 * SHM 'offset' needs to be an even address and
3944 * Buffer length 'len' must be an even number of bytes
3945 * 'sel' selects the type of memory
3946 */
3947void
3948wlc_bmac_copyto_objmem(wlc_hw_info_t * wlc_hw, uint offset, const void *buf,
3949 int len, uint32 sel)
3950{
3951 uint16 v;
3952 const uint8 *p = (const uint8 *)buf;
3953 int i;
3954
3955 /* offset and len need to be even */
3956 ASSERT((offset & 1) == 0);
3957 ASSERT((len & 1) == 0);
3958
3959 if (len <= 0)
3960 return;
3961
3962 for (i = 0; i < len; i += 2) {
3963 v = p[i] | (p[i + 1] << 8);
3964 wlc_bmac_write_objmem(wlc_hw, offset + i, v, sel);
3965 }
3966}
3967
3968/* Copy a piece of shared memory of specified type to a buffer .
3969 * SHM 'offset' needs to be an even address and
3970 * Buffer length 'len' must be an even number of bytes
3971 * 'sel' selects the type of memory
3972 */
3973void
3974wlc_bmac_copyfrom_objmem(wlc_hw_info_t * wlc_hw, uint offset, void *buf,
3975 int len, uint32 sel)
3976{
3977 uint16 v;
3978 uint8 *p = (uint8 *) buf;
3979 int i;
3980
3981 /* offset and len need to be even */
3982 ASSERT((offset & 1) == 0);
3983 ASSERT((len & 1) == 0);
3984
3985 if (len <= 0)
3986 return;
3987
3988 for (i = 0; i < len; i += 2) {
3989 v = wlc_bmac_read_objmem(wlc_hw, offset + i, sel);
3990 p[i] = v & 0xFF;
3991 p[i + 1] = (v >> 8) & 0xFF;
3992 }
3993}
3994
3995void wlc_bmac_copyfrom_vars(wlc_hw_info_t * wlc_hw, char **buf, uint * len)
3996{
3997 WL_TRACE(("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
3998 wlc_hw->vars_size));
3999
4000 *buf = wlc_hw->vars;
4001 *len = wlc_hw->vars_size;
4002}
4003
4004void wlc_bmac_retrylimit_upd(wlc_hw_info_t * wlc_hw, uint16 SRL, uint16 LRL)
4005{
4006 wlc_hw->SRL = SRL;
4007 wlc_hw->LRL = LRL;
4008
4009 /* write retry limit to SCR, shouldn't need to suspend */
4010 if (wlc_hw->up) {
4011 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4012 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
4013 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4014 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->SRL);
4015 W_REG(wlc_hw->osh, &wlc_hw->regs->objaddr,
4016 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
4017 (void)R_REG(wlc_hw->osh, &wlc_hw->regs->objaddr);
4018 W_REG(wlc_hw->osh, &wlc_hw->regs->objdata, wlc_hw->LRL);
4019 }
4020}
4021
4022void wlc_bmac_set_noreset(wlc_hw_info_t * wlc_hw, bool noreset_flag)
4023{
4024 wlc_hw->noreset = noreset_flag;
4025}
4026
4027void wlc_bmac_set_ucode_loaded(wlc_hw_info_t * wlc_hw, bool ucode_loaded)
4028{
4029 wlc_hw->ucode_loaded = ucode_loaded;
4030}
4031
4032void wlc_bmac_pllreq(wlc_hw_info_t * wlc_hw, bool set, mbool req_bit)
4033{
4034 ASSERT(req_bit);
4035
4036 if (set) {
4037 if (mboolisset(wlc_hw->pllreq, req_bit))
4038 return;
4039
4040 mboolset(wlc_hw->pllreq, req_bit);
4041
4042 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4043 if (!wlc_hw->sbclk) {
4044 wlc_bmac_xtal(wlc_hw, ON);
4045 }
4046 }
4047 } else {
4048 if (!mboolisset(wlc_hw->pllreq, req_bit))
4049 return;
4050
4051 mboolclr(wlc_hw->pllreq, req_bit);
4052
4053 if (mboolisset(wlc_hw->pllreq, WLC_PLLREQ_FLIP)) {
4054 if (wlc_hw->sbclk) {
4055 wlc_bmac_xtal(wlc_hw, OFF);
4056 }
4057 }
4058 }
4059
4060 return;
4061}
4062
4063void wlc_bmac_set_clk(wlc_hw_info_t * wlc_hw, bool on)
4064{
4065 if (on) {
4066 /* power up pll and oscillator */
4067 wlc_bmac_xtal(wlc_hw, ON);
4068
4069 /* enable core(s), ignore bandlocked
4070 * Leave with the same band selected as we entered
4071 */
4072 wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
4073 } else {
4074 /* if already down, must skip the core disable */
4075 if (wlc_hw->clk) {
4076 /* disable core(s), ignore bandlocked */
4077 wlc_coredisable(wlc_hw);
4078 }
4079 /* power down pll and oscillator */
4080 wlc_bmac_xtal(wlc_hw, OFF);
4081 }
4082}
4083
4084/* this will be true for all ai chips */
4085bool wlc_bmac_taclear(wlc_hw_info_t * wlc_hw, bool ta_ok)
4086{
4087 return TRUE;
4088}
4089
4090/* Lower down relevant GPIOs like LED when going down w/o
4091 * doing PCI config cycles or touching interrupts
4092 */
4093void wlc_gpio_fast_deinit(wlc_hw_info_t * wlc_hw)
4094{
4095 if ((wlc_hw == NULL) || (wlc_hw->sih == NULL))
4096 return;
4097
4098 /* Only chips with internal bus or PCIE cores or certain PCI cores
4099 * are able to switch cores w/o disabling interrupts
4100 */
4101 if (!((BUSTYPE(wlc_hw->sih->bustype) == SI_BUS) ||
4102 ((BUSTYPE(wlc_hw->sih->bustype) == PCI_BUS) &&
4103 ((wlc_hw->sih->buscoretype == PCIE_CORE_ID) ||
4104 (wlc_hw->sih->buscorerev >= 13)))))
4105 return;
4106
4107 WL_TRACE(("wl%d: %s\n", wlc_hw->unit, __func__));
4108 return;
4109}
4110
4111bool wlc_bmac_radio_hw(wlc_hw_info_t * wlc_hw, bool enable)
4112{
4113 /* Do not access Phy registers if core is not up */
4114 if (si_iscoreup(wlc_hw->sih) == FALSE)
4115 return FALSE;
4116
4117 if (enable) {
4118 if (PMUCTL_ENAB(wlc_hw->sih)) {
4119 AND_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4120 ~CCS_FORCEHWREQOFF);
4121 si_pmu_radio_enable(wlc_hw->sih, TRUE);
4122 }
4123
4124 wlc_phy_anacore(wlc_hw->band->pi, ON);
4125 wlc_phy_switch_radio(wlc_hw->band->pi, ON);
4126
4127 /* resume d11 core */
4128 wlc_enable_mac(wlc_hw->wlc);
4129 } else {
4130 /* suspend d11 core */
4131 wlc_suspend_mac_and_wait(wlc_hw->wlc);
4132
4133 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
4134 wlc_phy_anacore(wlc_hw->band->pi, OFF);
4135
4136 if (PMUCTL_ENAB(wlc_hw->sih)) {
4137 si_pmu_radio_enable(wlc_hw->sih, FALSE);
4138 OR_REG(wlc_hw->osh, &wlc_hw->regs->clk_ctl_st,
4139 CCS_FORCEHWREQOFF);
4140 }
4141 }
4142
4143 return TRUE;
4144}
4145
4146uint16 wlc_bmac_rate_shm_offset(wlc_hw_info_t * wlc_hw, uint8 rate)
4147{
4148 uint16 table_ptr;
4149 uint8 phy_rate, index;
4150
4151 /* get the phy specific rate encoding for the PLCP SIGNAL field */
4152 /* XXX4321 fixup needed ? */
4153 if (IS_OFDM(rate))
4154 table_ptr = M_RT_DIRMAP_A;
4155 else
4156 table_ptr = M_RT_DIRMAP_B;
4157
4158 /* for a given rate, the LS-nibble of the PLCP SIGNAL field is
4159 * the index into the rate table.
4160 */
4161 phy_rate = rate_info[rate] & RATE_MASK;
4162 index = phy_rate & 0xf;
4163
4164 /* Find the SHM pointer to the rate table entry by looking in the
4165 * Direct-map Table
4166 */
4167 return (2 * wlc_bmac_read_shm(wlc_hw, table_ptr + (index * 2)));
4168}
4169
4170void wlc_bmac_set_txpwr_percent(wlc_hw_info_t * wlc_hw, uint8 val)
4171{
4172 wlc_phy_txpwr_percent_set(wlc_hw->band->pi, val);
4173}
4174
4175void wlc_bmac_antsel_set(wlc_hw_info_t * wlc_hw, uint32 antsel_avail)
4176{
4177 wlc_hw->antsel_avail = antsel_avail;
4178}
Linux kernel - Deliverables
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