[deliverable/linux.git] / drivers / staging / comedi / drivers / addi_apci_1032.c

/*
 * addi_apci_1032.c
 * Copyright (C) 2004,2005  ADDI-DATA GmbH for the source code of this module.
 * Project manager: Eric Stolz
 *
 *	ADDI-DATA GmbH
 *	Dieselstrasse 3
 *	D-77833 Ottersweier
 *	Tel: +19(0)7223/9493-0
 *	Fax: +49(0)7223/9493-92
 *	http://www.addi-data.com
 *	info@addi-data.com
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 */

#include <linux/pci.h>
#include <linux/interrupt.h>

#include "../comedidev.h"
#include "comedi_fc.h"
#include "amcc_s5933.h"

/*
 * I/O Register Map
 */
#define APCI1032_DI_REG			0x00
#define APCI1032_MODE1_REG		0x04
#define APCI1032_MODE2_REG		0x08
#define APCI1032_STATUS_REG		0x0c
#define APCI1032_CTRL_REG		0x10
#define APCI1032_CTRL_INT_OR		(0 << 1)
#define APCI1032_CTRL_INT_AND		(1 << 1)
#define APCI1032_CTRL_INT_ENA		(1 << 2)

struct apci1032_private {
	unsigned long amcc_iobase;	/* base of AMCC I/O registers */
	unsigned int mode1;	/* rising-edge/high level channels */
	unsigned int mode2;	/* falling-edge/low level channels */
	unsigned int ctrl;	/* interrupt mode OR (edge) . AND (level) */
};

static int apci1032_reset(struct comedi_device *dev)
{
	/* disable the interrupts */
	outl(0x0, dev->iobase + APCI1032_CTRL_REG);
	/* Reset the interrupt status register */
	inl(dev->iobase + APCI1032_STATUS_REG);
	/* Disable the and/or interrupt */
	outl(0x0, dev->iobase + APCI1032_MODE1_REG);
	outl(0x0, dev->iobase + APCI1032_MODE2_REG);

	return 0;
}

/*
 * Change-Of-State (COS) interrupt configuration
 *
 * Channels 0 to 15 are interruptible. These channels can be configured
 * to generate interrupts based on AND/OR logic for the desired channels.
 *
 *	OR logic
 *		- reacts to rising or falling edges
 *		- interrupt is generated when any enabled channel
 *		  meet the desired interrupt condition
 *
 *	AND logic
 *		- reacts to changes in level of the selected inputs
 *		- interrupt is generated when all enabled channels
 *		  meet the desired interrupt condition
 *		- after an interrupt, a change in level must occur on
 *		  the selected inputs to release the IRQ logic
 *
 * The COS interrupt must be configured before it can be enabled.
 *
 *	data[0] : INSN_CONFIG_DIGITAL_TRIG
 *	data[1] : trigger number (= 0)
 *	data[2] : configuration operation:
 *	          COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
 *	          COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
 *	          COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
 *	data[3] : left-shift for data[4] and data[5]
 *	data[4] : rising-edge/high level channels
 *	data[5] : falling-edge/low level channels
 */
static int apci1032_cos_insn_config(struct comedi_device *dev,
				    struct comedi_subdevice *s,
				    struct comedi_insn *insn,
				    unsigned int *data)
{
	struct apci1032_private *devpriv = dev->private;
	unsigned int shift, oldmask;

	switch (data[0]) {
	case INSN_CONFIG_DIGITAL_TRIG:
		if (data[1] != 0)
			return -EINVAL;
		shift = data[3];
		oldmask = (1U << shift) - 1;
		switch (data[2]) {
		case COMEDI_DIGITAL_TRIG_DISABLE:
			devpriv->ctrl = 0;
			devpriv->mode1 = 0;
			devpriv->mode2 = 0;
			apci1032_reset(dev);
			break;
		case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
			if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA |
					      APCI1032_CTRL_INT_OR)) {
				/* switching to 'OR' mode */
				devpriv->ctrl = APCI1032_CTRL_INT_ENA |
						APCI1032_CTRL_INT_OR;
				/* wipe old channels */
				devpriv->mode1 = 0;
				devpriv->mode2 = 0;
			} else {
				/* preserve unspecified channels */
				devpriv->mode1 &= oldmask;
				devpriv->mode2 &= oldmask;
			}
			/* configure specified channels */
			devpriv->mode1 |= data[4] << shift;
			devpriv->mode2 |= data[5] << shift;
			break;
		case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
			if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA |
					      APCI1032_CTRL_INT_AND)) {
				/* switching to 'AND' mode */
				devpriv->ctrl = APCI1032_CTRL_INT_ENA |
						APCI1032_CTRL_INT_AND;
				/* wipe old channels */
				devpriv->mode1 = 0;
				devpriv->mode2 = 0;
			} else {
				/* preserve unspecified channels */
				devpriv->mode1 &= oldmask;
				devpriv->mode2 &= oldmask;
			}
			/* configure specified channels */
			devpriv->mode1 |= data[4] << shift;
			devpriv->mode2 |= data[5] << shift;
			break;
		default:
			return -EINVAL;
		}
		break;
	default:
		return -EINVAL;
	}

	return insn->n;
}

static int apci1032_cos_insn_bits(struct comedi_device *dev,
				  struct comedi_subdevice *s,
				  struct comedi_insn *insn,
				  unsigned int *data)
{
	data[1] = s->state;

	return 0;
}

static int apci1032_cos_cmdtest(struct comedi_device *dev,
				struct comedi_subdevice *s,
				struct comedi_cmd *cmd)
{
	int err = 0;

	/* Step 1 : check if triggers are trivially valid */

	err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
	err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
	err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);

	if (err)
		return 1;

	/* Step 2a : make sure trigger sources are unique */
	/* Step 2b : and mutually compatible */

	if (err)
		return 2;

	/* Step 3: check if arguments are trivially valid */

	err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
	err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
	err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);

	if (err)
		return 3;

	/* step 4: ignored */

	if (err)
		return 4;

	return 0;
}

/*
 * Change-Of-State (COS) 'do_cmd' operation
 *
 * Enable the COS interrupt as configured by apci1032_cos_insn_config().
 */
static int apci1032_cos_cmd(struct comedi_device *dev,
			    struct comedi_subdevice *s)
{
	struct apci1032_private *devpriv = dev->private;

	if (!devpriv->ctrl) {
		dev_warn(dev->class_dev,
			"Interrupts disabled due to mode configuration!\n");
		return -EINVAL;
	}

	outl(devpriv->mode1, dev->iobase + APCI1032_MODE1_REG);
	outl(devpriv->mode2, dev->iobase + APCI1032_MODE2_REG);
	outl(devpriv->ctrl, dev->iobase + APCI1032_CTRL_REG);

	return 0;
}

static int apci1032_cos_cancel(struct comedi_device *dev,
			       struct comedi_subdevice *s)
{
	return apci1032_reset(dev);
}

static irqreturn_t apci1032_interrupt(int irq, void *d)
{
	struct comedi_device *dev = d;
	struct apci1032_private *devpriv = dev->private;
	struct comedi_subdevice *s = dev->read_subdev;
	unsigned int ctrl;

	/* check interrupt is from this device */
	if ((inl(devpriv->amcc_iobase + AMCC_OP_REG_INTCSR) &
	     INTCSR_INTR_ASSERTED) == 0)
		return IRQ_NONE;

	/* check interrupt is enabled */
	ctrl = inl(dev->iobase + APCI1032_CTRL_REG);
	if ((ctrl & APCI1032_CTRL_INT_ENA) == 0)
		return IRQ_HANDLED;

	/* disable the interrupt */
	outl(ctrl & ~APCI1032_CTRL_INT_ENA, dev->iobase + APCI1032_CTRL_REG);

	s->state = inl(dev->iobase + APCI1032_STATUS_REG) & 0xffff;
	comedi_buf_put(s->async, s->state);
	s->async->events |= COMEDI_CB_BLOCK | COMEDI_CB_EOS;
	comedi_event(dev, s);

	/* enable the interrupt */
	outl(ctrl, dev->iobase + APCI1032_CTRL_REG);

	return IRQ_HANDLED;
}

static int apci1032_di_insn_bits(struct comedi_device *dev,
				 struct comedi_subdevice *s,
				 struct comedi_insn *insn,
				 unsigned int *data)
{
	data[1] = inl(dev->iobase + APCI1032_DI_REG);

	return insn->n;
}

static int apci1032_auto_attach(struct comedi_device *dev,
					  unsigned long context_unused)
{
	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
	struct apci1032_private *devpriv;
	struct comedi_subdevice *s;
	int ret;

	devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
	if (!devpriv)
		return -ENOMEM;
	dev->private = devpriv;

	ret = comedi_pci_enable(dev);
	if (ret)
		return ret;

	devpriv->amcc_iobase = pci_resource_start(pcidev, 0);
	dev->iobase = pci_resource_start(pcidev, 1);
	apci1032_reset(dev);
	if (pcidev->irq > 0) {
		ret = request_irq(pcidev->irq, apci1032_interrupt, IRQF_SHARED,
				  dev->board_name, dev);
		if (ret == 0)
			dev->irq = pcidev->irq;
	}

	ret = comedi_alloc_subdevices(dev, 2);
	if (ret)
		return ret;

	/*  Allocate and Initialise DI Subdevice Structures */
	s = &dev->subdevices[0];
	s->type		= COMEDI_SUBD_DI;
	s->subdev_flags	= SDF_READABLE;
	s->n_chan	= 32;
	s->maxdata	= 1;
	s->range_table	= &range_digital;
	s->insn_bits	= apci1032_di_insn_bits;

	/* Change-Of-State (COS) interrupt subdevice */
	s = &dev->subdevices[1];
	if (dev->irq) {
		dev->read_subdev = s;
		s->type		= COMEDI_SUBD_DI | SDF_CMD_READ;
		s->subdev_flags	= SDF_READABLE;
		s->n_chan	= 1;
		s->maxdata	= 1;
		s->range_table	= &range_digital;
		s->insn_config	= apci1032_cos_insn_config;
		s->insn_bits	= apci1032_cos_insn_bits;
		s->do_cmdtest	= apci1032_cos_cmdtest;
		s->do_cmd	= apci1032_cos_cmd;
		s->cancel	= apci1032_cos_cancel;
	} else {
		s->type		= COMEDI_SUBD_UNUSED;
	}

	return 0;
}

static void apci1032_detach(struct comedi_device *dev)
{
	if (dev->iobase)
		apci1032_reset(dev);
	if (dev->irq)
		free_irq(dev->irq, dev);
	comedi_pci_disable(dev);
}

static struct comedi_driver apci1032_driver = {
	.driver_name	= "addi_apci_1032",
	.module		= THIS_MODULE,
	.auto_attach	= apci1032_auto_attach,
	.detach		= apci1032_detach,
};

static int apci1032_pci_probe(struct pci_dev *dev,
			      const struct pci_device_id *id)
{
	return comedi_pci_auto_config(dev, &apci1032_driver, id->driver_data);
}

static DEFINE_PCI_DEVICE_TABLE(apci1032_pci_table) = {
	{ PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1003) },
	{ 0 }
};
MODULE_DEVICE_TABLE(pci, apci1032_pci_table);

static struct pci_driver apci1032_pci_driver = {
	.name		= "addi_apci_1032",
	.id_table	= apci1032_pci_table,
	.probe		= apci1032_pci_probe,
	.remove		= comedi_pci_auto_unconfig,
};
module_comedi_pci_driver(apci1032_driver, apci1032_pci_driver);

MODULE_AUTHOR("Comedi http://www.comedi.org");
MODULE_DESCRIPTION("Comedi low-level driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
6a3734af HS	1	/*
	2	* addi_apci_1032.c
	3	* Copyright (C) 2004,2005 ADDI-DATA GmbH for the source code of this module.
	4	* Project manager: Eric Stolz
	5	*
	6	* ADDI-DATA GmbH
	7	* Dieselstrasse 3
	8	* D-77833 Ottersweier
	9	* Tel: +19(0)7223/9493-0
	10	* Fax: +49(0)7223/9493-92
	11	* http://www.addi-data.com
	12	* info@addi-data.com
	13	*
	14	* This program is free software; you can redistribute it and/or modify it
	15	* under the terms of the GNU General Public License as published by the
	16	* Free Software Foundation; either version 2 of the License, or (at your
	17	* option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful, but WITHOUT
	20	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	21	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	22	* more details.
6a3734af HS	23	*/
6a3734af HS	24
33782dd5	25	#include <linux/pci.h>
abac8b54 HS	26	#include <linux/interrupt.h>
abac8b54 HS	27
3d41c443 HS	28	#include "../comedidev.h"
3d41c443 HS	29	#include "comedi_fc.h"
792660d5	30	#include "amcc_s5933.h"
3d41c443	31
6a3734af HS	32	/*
	33	* I/O Register Map
	34	*/
	35	#define APCI1032_DI_REG 0x00
	36	#define APCI1032_MODE1_REG 0x04
	37	#define APCI1032_MODE2_REG 0x08
	38	#define APCI1032_STATUS_REG 0x0c
	39	#define APCI1032_CTRL_REG 0x10
	40	#define APCI1032_CTRL_INT_OR (0 << 1)
	41	#define APCI1032_CTRL_INT_AND (1 << 1)
	42	#define APCI1032_CTRL_INT_ENA (1 << 2)
	43
4cde0a6d	44	struct apci1032_private {
792660d5	45	unsigned long amcc_iobase; /* base of AMCC I/O registers */
4cde0a6d HS	46	unsigned int mode1; /* rising-edge/high level channels */
	47	unsigned int mode2; /* falling-edge/low level channels */
	48	unsigned int ctrl; /* interrupt mode OR (edge) . AND (level) */
	49	};
6a3734af	50
4cde0a6d HS	51	static int apci1032_reset(struct comedi_device *dev)
	52	{
	53	/* disable the interrupts */
	54	outl(0x0, dev->iobase + APCI1032_CTRL_REG);
	55	/* Reset the interrupt status register */
	56	inl(dev->iobase + APCI1032_STATUS_REG);
	57	/* Disable the and/or interrupt */
	58	outl(0x0, dev->iobase + APCI1032_MODE1_REG);
	59	outl(0x0, dev->iobase + APCI1032_MODE2_REG);
	60
	61	return 0;
	62	}
6a3734af HS	63
6a3734af HS	64	/*
4cde0a6d HS	65	* Change-Of-State (COS) interrupt configuration
	66	*
	67	* Channels 0 to 15 are interruptible. These channels can be configured
	68	* to generate interrupts based on AND/OR logic for the desired channels.
	69	*
	70	* OR logic
	71	* - reacts to rising or falling edges
	72	* - interrupt is generated when any enabled channel
	73	* meet the desired interrupt condition
	74	*
	75	* AND logic
	76	* - reacts to changes in level of the selected inputs
	77	* - interrupt is generated when all enabled channels
	78	* meet the desired interrupt condition
	79	* - after an interrupt, a change in level must occur on
	80	* the selected inputs to release the IRQ logic
	81	*
	82	* The COS interrupt must be configured before it can be enabled.
	83	*
	84	* data[0] : INSN_CONFIG_DIGITAL_TRIG
33cdce62 IA	85	* data[1] : trigger number (= 0)
	86	* data[2] : configuration operation:
	87	* COMEDI_DIGITAL_TRIG_DISABLE = no interrupts
	88	* COMEDI_DIGITAL_TRIG_ENABLE_EDGES = OR (edge) interrupts
	89	* COMEDI_DIGITAL_TRIG_ENABLE_LEVELS = AND (level) interrupts
	90	* data[3] : left-shift for data[4] and data[5]
	91	* data[4] : rising-edge/high level channels
	92	* data[5] : falling-edge/low level channels
6a3734af	93	*/
4cde0a6d HS	94	static int apci1032_cos_insn_config(struct comedi_device *dev,
	95	struct comedi_subdevice *s,
	96	struct comedi_insn *insn,
	97	unsigned int *data)
6a3734af	98	{
4cde0a6d	99	struct apci1032_private *devpriv = dev->private;
33cdce62	100	unsigned int shift, oldmask;
4cde0a6d HS	101
	102	switch (data[0]) {
	103	case INSN_CONFIG_DIGITAL_TRIG:
33cdce62 IA	104	if (data[1] != 0)
	105	return -EINVAL;
	106	shift = data[3];
	107	oldmask = (1U << shift) - 1;
	108	switch (data[2]) {
	109	case COMEDI_DIGITAL_TRIG_DISABLE:
4cde0a6d	110	devpriv->ctrl = 0;
33cdce62 IA	111	devpriv->mode1 = 0;
33cdce62 IA	112	devpriv->mode2 = 0;
4cde0a6d	113	apci1032_reset(dev);
33cdce62 IA	114	break;
	115	case COMEDI_DIGITAL_TRIG_ENABLE_EDGES:
	116	if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA \|
	117	APCI1032_CTRL_INT_OR)) {
	118	/* switching to 'OR' mode */
	119	devpriv->ctrl = APCI1032_CTRL_INT_ENA \|
	120	APCI1032_CTRL_INT_OR;
	121	/* wipe old channels */
	122	devpriv->mode1 = 0;
	123	devpriv->mode2 = 0;
	124	} else {
	125	/* preserve unspecified channels */
	126	devpriv->mode1 &= oldmask;
	127	devpriv->mode2 &= oldmask;
	128	}
	129	/* configure specified channels */
	130	devpriv->mode1 \|= data[4] << shift;
	131	devpriv->mode2 \|= data[5] << shift;
	132	break;
	133	case COMEDI_DIGITAL_TRIG_ENABLE_LEVELS:
	134	if (devpriv->ctrl != (APCI1032_CTRL_INT_ENA \|
	135	APCI1032_CTRL_INT_AND)) {
	136	/* switching to 'AND' mode */
	137	devpriv->ctrl = APCI1032_CTRL_INT_ENA \|
	138	APCI1032_CTRL_INT_AND;
	139	/* wipe old channels */
	140	devpriv->mode1 = 0;
	141	devpriv->mode2 = 0;
	142	} else {
	143	/* preserve unspecified channels */
	144	devpriv->mode1 &= oldmask;
	145	devpriv->mode2 &= oldmask;
	146	}
	147	/* configure specified channels */
	148	devpriv->mode1 \|= data[4] << shift;
	149	devpriv->mode2 \|= data[5] << shift;
	150	break;
	151	default:
	152	return -EINVAL;
4cde0a6d HS	153	}
	154	break;
	155	default:
	156	return -EINVAL;
	157	}
6a3734af HS	158
	159	return insn->n;
	160	}
2bb8b1df	161
4cde0a6d HS	162	static int apci1032_cos_insn_bits(struct comedi_device *dev,
	163	struct comedi_subdevice *s,
	164	struct comedi_insn *insn,
	165	unsigned int *data)
	166	{
	167	data[1] = s->state;
	168
	169	return 0;
	170	}
	171
	172	static int apci1032_cos_cmdtest(struct comedi_device *dev,
	173	struct comedi_subdevice *s,
	174	struct comedi_cmd *cmd)
	175	{
	176	int err = 0;
	177
	178	/* Step 1 : check if triggers are trivially valid */
	179
	180	err \|= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW);
	181	err \|= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_EXT);
	182	err \|= cfc_check_trigger_src(&cmd->convert_src, TRIG_FOLLOW);
	183	err \|= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
	184	err \|= cfc_check_trigger_src(&cmd->stop_src, TRIG_NONE);
	185
	186	if (err)
	187	return 1;
	188
	189	/* Step 2a : make sure trigger sources are unique */
	190	/* Step 2b : and mutually compatible */
	191
	192	if (err)
	193	return 2;
	194
58bed93e	195	/* Step 3: check if arguments are trivially valid */
4cde0a6d	196
58bed93e HS	197	err \|= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
	198	err \|= cfc_check_trigger_arg_is(&cmd->scan_begin_arg, 0);
	199	err \|= cfc_check_trigger_arg_is(&cmd->convert_arg, 0);
	200	err \|= cfc_check_trigger_arg_is(&cmd->scan_end_arg, 1);
	201	err \|= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
4cde0a6d HS	202
	203	if (err)
	204	return 3;
	205
	206	/* step 4: ignored */
	207
	208	if (err)
	209	return 4;
	210
	211	return 0;
	212	}
	213
	214	/*
	215	* Change-Of-State (COS) 'do_cmd' operation
	216	*
	217	* Enable the COS interrupt as configured by apci1032_cos_insn_config().
	218	*/
	219	static int apci1032_cos_cmd(struct comedi_device *dev,
	220	struct comedi_subdevice *s)
	221	{
	222	struct apci1032_private *devpriv = dev->private;
	223
	224	if (!devpriv->ctrl) {
	225	dev_warn(dev->class_dev,
	226	"Interrupts disabled due to mode configuration!\n");
	227	return -EINVAL;
	228	}
	229
	230	outl(devpriv->mode1, dev->iobase + APCI1032_MODE1_REG);
	231	outl(devpriv->mode2, dev->iobase + APCI1032_MODE2_REG);
	232	outl(devpriv->ctrl, dev->iobase + APCI1032_CTRL_REG);
	233
	234	return 0;
	235	}
	236
	237	static int apci1032_cos_cancel(struct comedi_device *dev,
	238	struct comedi_subdevice *s)
	239	{
	240	return apci1032_reset(dev);
	241	}
	242
12d606f7	243	static irqreturn_t apci1032_interrupt(int irq, void *d)
2bb8b1df	244	{
12d606f7	245	struct comedi_device *dev = d;
792660d5	246	struct apci1032_private *devpriv = dev->private;
4cde0a6d	247	struct comedi_subdevice *s = dev->read_subdev;
12d606f7 HS	248	unsigned int ctrl;
12d606f7 HS	249
792660d5 IA	250	/* check interrupt is from this device */
	251	if ((inl(devpriv->amcc_iobase + AMCC_OP_REG_INTCSR) &
	252	INTCSR_INTR_ASSERTED) == 0)
	253	return IRQ_NONE;
	254
	255	/* check interrupt is enabled */
12d606f7	256	ctrl = inl(dev->iobase + APCI1032_CTRL_REG);
792660d5 IA	257	if ((ctrl & APCI1032_CTRL_INT_ENA) == 0)
	258	return IRQ_HANDLED;
	259
	260	/* disable the interrupt */
12d606f7 HS	261	outl(ctrl & ~APCI1032_CTRL_INT_ENA, dev->iobase + APCI1032_CTRL_REG);
12d606f7 HS	262
4cde0a6d HS	263	s->state = inl(dev->iobase + APCI1032_STATUS_REG) & 0xffff;
	264	comedi_buf_put(s->async, s->state);
	265	s->async->events \|= COMEDI_CB_BLOCK \| COMEDI_CB_EOS;
	266	comedi_event(dev, s);
12d606f7 HS	267
	268	/* enable the interrupt */
	269	outl(ctrl, dev->iobase + APCI1032_CTRL_REG);
	270
	271	return IRQ_HANDLED;
2bb8b1df HS	272	}
2bb8b1df HS	273
a3de4cd3 HS	274	static int apci1032_di_insn_bits(struct comedi_device *dev,
	275	struct comedi_subdevice *s,
	276	struct comedi_insn *insn,
	277	unsigned int *data)
	278	{
	279	data[1] = inl(dev->iobase + APCI1032_DI_REG);
	280
	281	return insn->n;
	282	}
	283
a690b7e5	284	static int apci1032_auto_attach(struct comedi_device *dev,
891e62c3	285	unsigned long context_unused)
2bb8b1df	286	{
891e62c3	287	struct pci_dev *pcidev = comedi_to_pci_dev(dev);
4cde0a6d	288	struct apci1032_private *devpriv;
2bb8b1df	289	struct comedi_subdevice *s;
b37f84d5	290	int ret;
2bb8b1df	291
4cde0a6d HS	292	devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
	293	if (!devpriv)
	294	return -ENOMEM;
	295	dev->private = devpriv;
	296
818f569f	297	ret = comedi_pci_enable(dev);
2bb8b1df HS	298	if (ret)
	299	return ret;
	300
792660d5	301	devpriv->amcc_iobase = pci_resource_start(pcidev, 0);
c965c8b7	302	dev->iobase = pci_resource_start(pcidev, 1);
792660d5	303	apci1032_reset(dev);
2bb8b1df	304	if (pcidev->irq > 0) {
12d606f7	305	ret = request_irq(pcidev->irq, apci1032_interrupt, IRQF_SHARED,
2bb8b1df HS	306	dev->board_name, dev);
	307	if (ret == 0)
	308	dev->irq = pcidev->irq;
	309	}
	310
6835a17a	311	ret = comedi_alloc_subdevices(dev, 2);
2bb8b1df HS	312	if (ret)
	313	return ret;
	314
2bb8b1df	315	/* Allocate and Initialise DI Subdevice Structures */
b37f84d5	316	s = &dev->subdevices[0];
4c2c1488 HS	317	s->type = COMEDI_SUBD_DI;
	318	s->subdev_flags = SDF_READABLE;
	319	s->n_chan = 32;
	320	s->maxdata = 1;
4c2c1488	321	s->range_table = &range_digital;
a3de4cd3	322	s->insn_bits = apci1032_di_insn_bits;
5dbdbf67	323
4cde0a6d HS	324	/* Change-Of-State (COS) interrupt subdevice */
4cde0a6d HS	325	s = &dev->subdevices[1];
6835a17a	326	if (dev->irq) {
4cde0a6d HS	327	dev->read_subdev = s;
4cde0a6d HS	328	s->type = COMEDI_SUBD_DI \| SDF_CMD_READ;
6835a17a HS	329	s->subdev_flags = SDF_READABLE;
	330	s->n_chan = 1;
	331	s->maxdata = 1;
	332	s->range_table = &range_digital;
4cde0a6d HS	333	s->insn_config = apci1032_cos_insn_config;
	334	s->insn_bits = apci1032_cos_insn_bits;
	335	s->do_cmdtest = apci1032_cos_cmdtest;
	336	s->do_cmd = apci1032_cos_cmd;
	337	s->cancel = apci1032_cos_cancel;
	338	} else {
	339	s->type = COMEDI_SUBD_UNUSED;
6835a17a HS	340	}
6835a17a HS	341
2bb8b1df HS	342	return 0;
	343	}
	344
	345	static void apci1032_detach(struct comedi_device *dev)
	346	{
14696bbe HS	347	if (dev->iobase)
	348	apci1032_reset(dev);
	349	if (dev->irq)
	350	free_irq(dev->irq, dev);
7f072f54	351	comedi_pci_disable(dev);
2bb8b1df HS	352	}
2bb8b1df HS	353
20a22b70 HS	354	static struct comedi_driver apci1032_driver = {
	355	.driver_name = "addi_apci_1032",
	356	.module = THIS_MODULE,
891e62c3	357	.auto_attach = apci1032_auto_attach,
2bb8b1df	358	.detach = apci1032_detach,
20a22b70 HS	359	};
20a22b70 HS	360
a690b7e5	361	static int apci1032_pci_probe(struct pci_dev *dev,
b8f4ac23	362	const struct pci_device_id *id)
20a22b70	363	{
b8f4ac23	364	return comedi_pci_auto_config(dev, &apci1032_driver, id->driver_data);
20a22b70 HS	365	}
20a22b70 HS	366
20a22b70	367	static DEFINE_PCI_DEVICE_TABLE(apci1032_pci_table) = {
317285d7 HS	368	{ PCI_DEVICE(PCI_VENDOR_ID_ADDIDATA, 0x1003) },
	369	{ 0 }
	370	};
20a22b70	371	MODULE_DEVICE_TABLE(pci, apci1032_pci_table);
317285d7	372
20a22b70 HS	373	static struct pci_driver apci1032_pci_driver = {
	374	.name = "addi_apci_1032",
	375	.id_table = apci1032_pci_table,
	376	.probe = apci1032_pci_probe,
9901a4d7	377	.remove = comedi_pci_auto_unconfig,
20a22b70 HS	378	};
20a22b70 HS	379	module_comedi_pci_driver(apci1032_driver, apci1032_pci_driver);
90f703d3 AT	380
	381	MODULE_AUTHOR("Comedi http://www.comedi.org");
	382	MODULE_DESCRIPTION("Comedi low-level driver");
	383	MODULE_LICENSE("GPL");