[deliverable/linux.git] / drivers / staging / comedi / drivers / amplc_dio200.c

/*
 * comedi/drivers/amplc_dio200.c
 *
 * Driver for Amplicon PC212E, PC214E, PC215E, PC218E, PC272E.
 *
 * Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
 *
 * COMEDI - Linux Control and Measurement Device Interface
 * Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/*
 * Driver: amplc_dio200
 * Description: Amplicon 200 Series ISA Digital I/O
 * Author: Ian Abbott <abbotti@mev.co.uk>
 * Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e),
 *   PC218E (pc218e), PC272E (pc272e)
 * Updated: Mon, 18 Mar 2013 14:40:41 +0000
 *
 * Status: works
 *
 * Configuration options:
 *   [0] - I/O port base address
 *   [1] - IRQ (optional, but commands won't work without it)
 *
 * Passing a zero for an option is the same as leaving it unspecified.
 *
 * SUBDEVICES
 *
 *                     PC212E         PC214E         PC215E
 *                  -------------  -------------  -------------
 *   Subdevices           6              4              5
 *    0                 PPI-X          PPI-X          PPI-X
 *    1                 CTR-Y1         PPI-Y          PPI-Y
 *    2                 CTR-Y2         CTR-Z1*        CTR-Z1
 *    3                 CTR-Z1       INTERRUPT*       CTR-Z2
 *    4                 CTR-Z2                      INTERRUPT
 *    5               INTERRUPT
 *
 *                     PC218E         PC272E
 *                  -------------  -------------
 *   Subdevices           7              4
 *    0                 CTR-X1         PPI-X
 *    1                 CTR-X2         PPI-Y
 *    2                 CTR-Y1         PPI-Z
 *    3                 CTR-Y2       INTERRUPT
 *    4                 CTR-Z1
 *    5                 CTR-Z2
 *    6               INTERRUPT
 *
 * Each PPI is a 8255 chip providing 24 DIO channels.  The DIO channels
 * are configurable as inputs or outputs in four groups:
 *
 *   Port A  - channels  0 to  7
 *   Port B  - channels  8 to 15
 *   Port CL - channels 16 to 19
 *   Port CH - channels 20 to 23
 *
 * Only mode 0 of the 8255 chips is supported.
 *
 * Each CTR is a 8254 chip providing 3 16-bit counter channels.  Each
 * channel is configured individually with INSN_CONFIG instructions.  The
 * specific type of configuration instruction is specified in data[0].
 * Some configuration instructions expect an additional parameter in
 * data[1]; others return a value in data[1].  The following configuration
 * instructions are supported:
 *
 *   INSN_CONFIG_SET_COUNTER_MODE.  Sets the counter channel's mode and
 *     BCD/binary setting specified in data[1].
 *
 *   INSN_CONFIG_8254_READ_STATUS.  Reads the status register value for the
 *     counter channel into data[1].
 *
 *   INSN_CONFIG_SET_CLOCK_SRC.  Sets the counter channel's clock source as
 *     specified in data[1] (this is a hardware-specific value).  Not
 *     supported on PC214E.  For the other boards, valid clock sources are
 *     0 to 7 as follows:
 *
 *       0.  CLK n, the counter channel's dedicated CLK input from the SK1
 *         connector.  (N.B. for other values, the counter channel's CLKn
 *         pin on the SK1 connector is an output!)
 *       1.  Internal 10 MHz clock.
 *       2.  Internal 1 MHz clock.
 *       3.  Internal 100 kHz clock.
 *       4.  Internal 10 kHz clock.
 *       5.  Internal 1 kHz clock.
 *       6.  OUT n-1, the output of counter channel n-1 (see note 1 below).
 *       7.  Ext Clock, the counter chip's dedicated Ext Clock input from
 *         the SK1 connector.  This pin is shared by all three counter
 *         channels on the chip.
 *
 *   INSN_CONFIG_GET_CLOCK_SRC.  Returns the counter channel's current
 *     clock source in data[1].  For internal clock sources, data[2] is set
 *     to the period in ns.
 *
 *   INSN_CONFIG_SET_GATE_SRC.  Sets the counter channel's gate source as
 *     specified in data[2] (this is a hardware-specific value).  Not
 *     supported on PC214E.  For the other boards, valid gate sources are 0
 *     to 7 as follows:
 *
 *       0.  VCC (internal +5V d.c.), i.e. gate permanently enabled.
 *       1.  GND (internal 0V d.c.), i.e. gate permanently disabled.
 *       2.  GAT n, the counter channel's dedicated GAT input from the SK1
 *         connector.  (N.B. for other values, the counter channel's GATn
 *         pin on the SK1 connector is an output!)
 *       3.  /OUT n-2, the inverted output of counter channel n-2 (see note
 *         2 below).
 *       4.  Reserved.
 *       5.  Reserved.
 *       6.  Reserved.
 *       7.  Reserved.
 *
 *   INSN_CONFIG_GET_GATE_SRC.  Returns the counter channel's current gate
 *     source in data[2].
 *
 * Clock and gate interconnection notes:
 *
 *   1.  Clock source OUT n-1 is the output of the preceding channel on the
 *   same counter subdevice if n > 0, or the output of channel 2 on the
 *   preceding counter subdevice (see note 3) if n = 0.
 *
 *   2.  Gate source /OUT n-2 is the inverted output of channel 0 on the
 *   same counter subdevice if n = 2, or the inverted output of channel n+1
 *   on the preceding counter subdevice (see note 3) if n < 2.
 *
 *   3.  The counter subdevices are connected in a ring, so the highest
 *   counter subdevice precedes the lowest.
 *
 * The 'INTERRUPT' subdevice pretends to be a digital input subdevice.  The
 * digital inputs come from the interrupt status register.  The number of
 * channels matches the number of interrupt sources.  The PC214E does not
 * have an interrupt status register; see notes on 'INTERRUPT SOURCES'
 * below.
 *
 * INTERRUPT SOURCES
 *
 *                     PC212E         PC214E         PC215E
 *                  -------------  -------------  -------------
 *   Sources              6              1              6
 *    0               PPI-X-C0       JUMPER-J5      PPI-X-C0
 *    1               PPI-X-C3                      PPI-X-C3
 *    2              CTR-Y1-OUT1                    PPI-Y-C0
 *    3              CTR-Y2-OUT1                    PPI-Y-C3
 *    4              CTR-Z1-OUT1                   CTR-Z1-OUT1
 *    5              CTR-Z2-OUT1                   CTR-Z2-OUT1
 *
 *                     PC218E         PC272E
 *                  -------------  -------------
 *   Sources              6              6
 *    0              CTR-X1-OUT1     PPI-X-C0
 *    1              CTR-X2-OUT1     PPI-X-C3
 *    2              CTR-Y1-OUT1     PPI-Y-C0
 *    3              CTR-Y2-OUT1     PPI-Y-C3
 *    4              CTR-Z1-OUT1     PPI-Z-C0
 *    5              CTR-Z2-OUT1     PPI-Z-C3
 *
 * When an interrupt source is enabled in the interrupt source enable
 * register, a rising edge on the source signal latches the corresponding
 * bit to 1 in the interrupt status register.
 *
 * When the interrupt status register value as a whole (actually, just the
 * 6 least significant bits) goes from zero to non-zero, the board will
 * generate an interrupt.  No further interrupts will occur until the
 * interrupt status register is cleared to zero.  To clear a bit to zero in
 * the interrupt status register, the corresponding interrupt source must
 * be disabled in the interrupt source enable register (there is no
 * separate interrupt clear register).
 *
 * The PC214E does not have an interrupt source enable register or an
 * interrupt status register; its 'INTERRUPT' subdevice has a single
 * channel and its interrupt source is selected by the position of jumper
 * J5.
 *
 * COMMANDS
 *
 * The driver supports a read streaming acquisition command on the
 * 'INTERRUPT' subdevice.  The channel list selects the interrupt sources
 * to be enabled.  All channels will be sampled together (convert_src ==
 * TRIG_NOW).  The scan begins a short time after the hardware interrupt
 * occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
 * scan_begin_arg == 0).  The value read from the interrupt status register
 * is packed into a short value, one bit per requested channel, in the
 * order they appear in the channel list.
 */

#include <linux/module.h>
#include "../comedidev.h"

#include "amplc_dio200.h"

/*
 * Board descriptions.
 */
static const struct dio200_board dio200_isa_boards[] = {
	{
		.name		= "pc212e",
		.n_subdevs	= 6,
		.sdtype		= {
			sd_8255, sd_8254, sd_8254, sd_8254, sd_8254, sd_intr
		},
		.sdinfo		= { 0x00, 0x08, 0x0c, 0x10, 0x14, 0x3f },
		.has_int_sce	= true,
		.has_clk_gat_sce = true,
	}, {
		.name		= "pc214e",
		.n_subdevs	= 4,
		.sdtype		= {
			sd_8255, sd_8255, sd_8254, sd_intr
		},
		.sdinfo		= { 0x00, 0x08, 0x10, 0x01 },
	}, {
		.name		= "pc215e",
		.n_subdevs	= 5,
		.sdtype		= {
			sd_8255, sd_8255, sd_8254, sd_8254, sd_intr
		},
		.sdinfo		= { 0x00, 0x08, 0x10, 0x14, 0x3f },
		.has_int_sce	= true,
		.has_clk_gat_sce = true,
	}, {
		.name		= "pc218e",
		.n_subdevs	= 7,
		.sdtype		= {
			sd_8254, sd_8254, sd_8255, sd_8254, sd_8254, sd_intr
		},
		.sdinfo		= { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x3f },
		.has_int_sce	= true,
		.has_clk_gat_sce = true,
	}, {
		.name		= "pc272e",
		.n_subdevs	= 4,
		.sdtype		= {
			sd_8255, sd_8255, sd_8255, sd_intr
		},
		.sdinfo		= { 0x00, 0x08, 0x10, 0x3f },
		.has_int_sce = true,
	},
};

static int dio200_attach(struct comedi_device *dev, struct comedi_devconfig *it)
{
	int ret;

	ret = comedi_request_region(dev, it->options[0], 0x20);
	if (ret)
		return ret;

	return amplc_dio200_common_attach(dev, it->options[1], 0);
}

static struct comedi_driver amplc_dio200_driver = {
	.driver_name	= "amplc_dio200",
	.module		= THIS_MODULE,
	.attach		= dio200_attach,
	.detach		= comedi_legacy_detach,
	.board_name	= &dio200_isa_boards[0].name,
	.offset		= sizeof(struct dio200_board),
	.num_names	= ARRAY_SIZE(dio200_isa_boards),
};
module_comedi_driver(amplc_dio200_driver);

MODULE_AUTHOR("Comedi http://www.comedi.org");
MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series ISA DIO boards");
MODULE_LICENSE("GPL");
Commit	Line	Data
e948cb52	1	/*
158bb728 IA	2	* comedi/drivers/amplc_dio200.c
	3	*
	4	* Driver for Amplicon PC212E, PC214E, PC215E, PC218E, PC272E.
	5	*
	6	* Copyright (C) 2005-2013 MEV Ltd. <http://www.mev.co.uk/>
	7	*
	8	* COMEDI - Linux Control and Measurement Device Interface
	9	* Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
	10	*
	11	* This program is free software; you can redistribute it and/or modify
	12	* it under the terms of the GNU General Public License as published by
	13	* the Free Software Foundation; either version 2 of the License, or
	14	* (at your option) any later version.
	15	*
	16	* This program is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*/
e948cb52	21
e948cb52	22	/*
41b25f87	23	* Driver: amplc_dio200
7ff7e4c2	24	* Description: Amplicon 200 Series ISA Digital I/O
41b25f87 IA	25	* Author: Ian Abbott <abbotti@mev.co.uk>
41b25f87 IA	26	* Devices: [Amplicon] PC212E (pc212e), PC214E (pc214e), PC215E (pc215e),
7ff7e4c2 IA	27	* PC218E (pc218e), PC272E (pc272e)
	28	* Updated: Mon, 18 Mar 2013 14:40:41 +0000
	29	*
41b25f87 IA	30	* Status: works
41b25f87 IA	31	*
7ff7e4c2	32	* Configuration options:
41b25f87 IA	33	* [0] - I/O port base address
	34	* [1] - IRQ (optional, but commands won't work without it)
	35	*
41b25f87 IA	36	* Passing a zero for an option is the same as leaving it unspecified.
	37	*
	38	* SUBDEVICES
	39	*
7ff7e4c2	40	* PC212E PC214E PC215E
41b25f87	41	* ------------- ------------- -------------
2421a024 IA	42	* Subdevices 6 4 5
	43	* 0 PPI-X PPI-X PPI-X
	44	* 1 CTR-Y1 PPI-Y PPI-Y
	45	* 2 CTR-Y2 CTR-Z1* CTR-Z1
	46	* 3 CTR-Z1 INTERRUPT* CTR-Z2
	47	* 4 CTR-Z2 INTERRUPT
	48	* 5 INTERRUPT
41b25f87	49	*
7ff7e4c2	50	* PC218E PC272E
41b25f87	51	* ------------- -------------
7ff7e4c2 IA	52	* Subdevices 7 4
	53	* 0 CTR-X1 PPI-X
	54	* 1 CTR-X2 PPI-Y
	55	* 2 CTR-Y1 PPI-Z
	56	* 3 CTR-Y2 INTERRUPT
	57	* 4 CTR-Z1
	58	* 5 CTR-Z2
	59	* 6 INTERRUPT
41b25f87 IA	60	*
	61	* Each PPI is a 8255 chip providing 24 DIO channels. The DIO channels
	62	* are configurable as inputs or outputs in four groups:
	63	*
	64	* Port A - channels 0 to 7
	65	* Port B - channels 8 to 15
	66	* Port CL - channels 16 to 19
	67	* Port CH - channels 20 to 23
	68	*
	69	* Only mode 0 of the 8255 chips is supported.
	70	*
	71	* Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
	72	* channel is configured individually with INSN_CONFIG instructions. The
	73	* specific type of configuration instruction is specified in data[0].
	74	* Some configuration instructions expect an additional parameter in
	75	* data[1]; others return a value in data[1]. The following configuration
	76	* instructions are supported:
	77	*
	78	* INSN_CONFIG_SET_COUNTER_MODE. Sets the counter channel's mode and
	79	* BCD/binary setting specified in data[1].
	80	*
	81	* INSN_CONFIG_8254_READ_STATUS. Reads the status register value for the
	82	* counter channel into data[1].
	83	*
	84	* INSN_CONFIG_SET_CLOCK_SRC. Sets the counter channel's clock source as
	85	* specified in data[1] (this is a hardware-specific value). Not
	86	* supported on PC214E. For the other boards, valid clock sources are
	87	* 0 to 7 as follows:
	88	*
	89	* 0. CLK n, the counter channel's dedicated CLK input from the SK1
	90	* connector. (N.B. for other values, the counter channel's CLKn
	91	* pin on the SK1 connector is an output!)
	92	* 1. Internal 10 MHz clock.
	93	* 2. Internal 1 MHz clock.
	94	* 3. Internal 100 kHz clock.
	95	* 4. Internal 10 kHz clock.
	96	* 5. Internal 1 kHz clock.
	97	* 6. OUT n-1, the output of counter channel n-1 (see note 1 below).
	98	* 7. Ext Clock, the counter chip's dedicated Ext Clock input from
	99	* the SK1 connector. This pin is shared by all three counter
	100	* channels on the chip.
	101	*
	102	* INSN_CONFIG_GET_CLOCK_SRC. Returns the counter channel's current
	103	* clock source in data[1]. For internal clock sources, data[2] is set
	104	* to the period in ns.
	105	*
	106	* INSN_CONFIG_SET_GATE_SRC. Sets the counter channel's gate source as
	107	* specified in data[2] (this is a hardware-specific value). Not
	108	* supported on PC214E. For the other boards, valid gate sources are 0
	109	* to 7 as follows:
	110	*
	111	* 0. VCC (internal +5V d.c.), i.e. gate permanently enabled.
	112	* 1. GND (internal 0V d.c.), i.e. gate permanently disabled.
	113	* 2. GAT n, the counter channel's dedicated GAT input from the SK1
	114	* connector. (N.B. for other values, the counter channel's GATn
	115	* pin on the SK1 connector is an output!)
	116	* 3. /OUT n-2, the inverted output of counter channel n-2 (see note
	117	* 2 below).
	118	* 4. Reserved.
	119	* 5. Reserved.
	120	* 6. Reserved.
	121	* 7. Reserved.
	122	*
	123	* INSN_CONFIG_GET_GATE_SRC. Returns the counter channel's current gate
124	* source in data[2].
125	*
126	* Clock and gate interconnection notes:
127	*
128	* 1. Clock source OUT n-1 is the output of the preceding channel on the
129	* same counter subdevice if n > 0, or the output of channel 2 on the
130	* preceding counter subdevice (see note 3) if n = 0.
131	*
132	* 2. Gate source /OUT n-2 is the inverted output of channel 0 on the
133	* same counter subdevice if n = 2, or the inverted output of channel n+1
134	* on the preceding counter subdevice (see note 3) if n < 2.
135	*
136	* 3. The counter subdevices are connected in a ring, so the highest
137	* counter subdevice precedes the lowest.
138	*
139	* The 'INTERRUPT' subdevice pretends to be a digital input subdevice. The
140	* digital inputs come from the interrupt status register. The number of
141	* channels matches the number of interrupt sources. The PC214E does not
142	* have an interrupt status register; see notes on 'INTERRUPT SOURCES'
143	* below.
144	*
145	* INTERRUPT SOURCES
146	*
7ff7e4c2	147	* PC212E PC214E PC215E
2421a024 IA	148	* ------------- ------------- -------------
	149	* Sources 6 1 6
	150	* 0 PPI-X-C0 JUMPER-J5 PPI-X-C0
	151	* 1 PPI-X-C3 PPI-X-C3
	152	* 2 CTR-Y1-OUT1 PPI-Y-C0
	153	* 3 CTR-Y2-OUT1 PPI-Y-C3
	154	* 4 CTR-Z1-OUT1 CTR-Z1-OUT1
	155	* 5 CTR-Z2-OUT1 CTR-Z2-OUT1
	156	*
7ff7e4c2	157	* PC218E PC272E
41b25f87	158	* ------------- -------------
2421a024	159	* Sources 6 6
7ff7e4c2 IA	160	* 0 CTR-X1-OUT1 PPI-X-C0
	161	* 1 CTR-X2-OUT1 PPI-X-C3
	162	* 2 CTR-Y1-OUT1 PPI-Y-C0
	163	* 3 CTR-Y2-OUT1 PPI-Y-C3
	164	* 4 CTR-Z1-OUT1 PPI-Z-C0
	165	* 5 CTR-Z2-OUT1 PPI-Z-C3
41b25f87 IA	166	*
	167	* When an interrupt source is enabled in the interrupt source enable
	168	* register, a rising edge on the source signal latches the corresponding
	169	* bit to 1 in the interrupt status register.
	170	*
	171	* When the interrupt status register value as a whole (actually, just the
	172	* 6 least significant bits) goes from zero to non-zero, the board will
7ff7e4c2 IA	173	* generate an interrupt. No further interrupts will occur until the
	174	* interrupt status register is cleared to zero. To clear a bit to zero in
	175	* the interrupt status register, the corresponding interrupt source must
	176	* be disabled in the interrupt source enable register (there is no
	177	* separate interrupt clear register).
41b25f87 IA	178	*
	179	* The PC214E does not have an interrupt source enable register or an
	180	* interrupt status register; its 'INTERRUPT' subdevice has a single
	181	* channel and its interrupt source is selected by the position of jumper
	182	* J5.
	183	*
	184	* COMMANDS
	185	*
	186	* The driver supports a read streaming acquisition command on the
	187	* 'INTERRUPT' subdevice. The channel list selects the interrupt sources
	188	* to be enabled. All channels will be sampled together (convert_src ==
	189	* TRIG_NOW). The scan begins a short time after the hardware interrupt
	190	* occurs, subject to interrupt latencies (scan_begin_src == TRIG_EXT,
	191	* scan_begin_arg == 0). The value read from the interrupt status register
	192	* is packed into a short value, one bit per requested channel, in the
	193	* order they appear in the channel list.
	194	*/
e948cb52	195
ce157f80	196	#include <linux/module.h>
e948cb52 IA	197	#include "../comedidev.h"
e948cb52 IA	198
7ff7e4c2	199	#include "amplc_dio200.h"
f7282f05	200
e948cb52 IA	201	/*
	202	* Board descriptions.
	203	*/
3d9bfccd	204	static const struct dio200_board dio200_isa_boards[] = {
e948cb52	205	{
f6ce0950 HS	206	.name = "pc212e",
	207	.n_subdevs = 6,
	208	.sdtype = {
	209	sd_8255, sd_8254, sd_8254, sd_8254, sd_8254, sd_intr
f7282f05	210	},
f6ce0950 HS	211	.sdinfo = { 0x00, 0x08, 0x0c, 0x10, 0x14, 0x3f },
	212	.has_int_sce = true,
	213	.has_clk_gat_sce = true,
	214	}, {
	215	.name = "pc214e",
	216	.n_subdevs = 4,
	217	.sdtype = {
	218	sd_8255, sd_8255, sd_8254, sd_intr
f7282f05	219	},
f6ce0950 HS	220	.sdinfo = { 0x00, 0x08, 0x10, 0x01 },
	221	}, {
	222	.name = "pc215e",
	223	.n_subdevs = 5,
	224	.sdtype = {
	225	sd_8255, sd_8255, sd_8254, sd_8254, sd_intr
f7282f05	226	},
f6ce0950 HS	227	.sdinfo = { 0x00, 0x08, 0x10, 0x14, 0x3f },
	228	.has_int_sce = true,
	229	.has_clk_gat_sce = true,
	230	}, {
	231	.name = "pc218e",
	232	.n_subdevs = 7,
	233	.sdtype = {
	234	sd_8254, sd_8254, sd_8255, sd_8254, sd_8254, sd_intr
f7282f05	235	},
f6ce0950 HS	236	.sdinfo = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, 0x3f },
	237	.has_int_sce = true,
	238	.has_clk_gat_sce = true,
	239	}, {
	240	.name = "pc272e",
	241	.n_subdevs = 4,
	242	.sdtype = {
	243	sd_8255, sd_8255, sd_8255, sd_intr
f7282f05	244	},
f6ce0950 HS	245	.sdinfo = { 0x00, 0x08, 0x10, 0x3f },
f6ce0950 HS	246	.has_int_sce = true,
3d9bfccd IA	247	},
3d9bfccd IA	248	};
87276012	249
7ff7e4c2	250	static int dio200_attach(struct comedi_device dev, struct comedi_devconfig it)
e948cb52	251	{
7ff7e4c2	252	int ret;
e948cb52	253
cf200de9	254	ret = comedi_request_region(dev, it->options[0], 0x20);
71827d43	255	if (ret)
7ff7e4c2	256	return ret;
0c3dfdc2	257
acb16513	258	return amplc_dio200_common_attach(dev, it->options[1], 0);
e948cb52 IA	259	}
e948cb52 IA	260
fd97962b	261	static struct comedi_driver amplc_dio200_driver = {
849db1aa HS	262	.driver_name = "amplc_dio200",
	263	.module = THIS_MODULE,
	264	.attach = dio200_attach,
bb83abed	265	.detach = comedi_legacy_detach,
849db1aa HS	266	.board_name = &dio200_isa_boards[0].name,
	267	.offset = sizeof(struct dio200_board),
	268	.num_names = ARRAY_SIZE(dio200_isa_boards),
fd97962b	269	};
fd97962b	270	module_comedi_driver(amplc_dio200_driver);
fd97962b	271
90f703d3	272	MODULE_AUTHOR("Comedi http://www.comedi.org");
7ff7e4c2	273	MODULE_DESCRIPTION("Comedi driver for Amplicon 200 Series ISA DIO boards");
90f703d3	274	MODULE_LICENSE("GPL");