staging: comedi: amplc_pci224: __devinit pci224_attach_pci()
[deliverable/linux.git] / drivers / staging / comedi / drivers / amplc_pci224.c
CommitLineData
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1/*
2 comedi/drivers/amplc_pci224.c
3 Driver for Amplicon PCI224 and PCI234 AO boards.
4
5 Copyright (C) 2005 MEV Ltd. <http://www.mev.co.uk/>
6
7 COMEDI - Linux Control and Measurement Device Interface
8 Copyright (C) 1998,2000 David A. Schleef <ds@schleef.org>
9
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2 of the License, or
13 (at your option) any later version.
14
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
19
20 You should have received a copy of the GNU General Public License
21 along with this program; if not, write to the Free Software
22 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23
24*/
25/*
26Driver: amplc_pci224
27Description: Amplicon PCI224, PCI234
28Author: Ian Abbott <abbotti@mev.co.uk>
29Devices: [Amplicon] PCI224 (amplc_pci224 or pci224),
30 PCI234 (amplc_pci224 or pci234)
31Updated: Wed, 22 Oct 2008 12:25:08 +0100
32Status: works, but see caveats
33
34Supports:
35
36 - ao_insn read/write
37 - ao_do_cmd mode with the following sources:
38
39 - start_src TRIG_INT TRIG_EXT
40 - scan_begin_src TRIG_TIMER TRIG_EXT
41 - convert_src TRIG_NOW
42 - scan_end_src TRIG_COUNT
43 - stop_src TRIG_COUNT TRIG_EXT TRIG_NONE
44
45 The channel list must contain at least one channel with no repeated
46 channels. The scan end count must equal the number of channels in
47 the channel list.
48
49 There is only one external trigger source so only one of start_src,
50 scan_begin_src or stop_src may use TRIG_EXT.
51
52Configuration options - PCI224:
53 [0] - PCI bus of device (optional).
54 [1] - PCI slot of device (optional).
55 If bus/slot is not specified, the first available PCI device
56 will be used.
57 [2] - Select available ranges according to jumper LK1. All channels
58 are set to the same range:
59 0=Jumper position 1-2 (factory default), 4 software-selectable
60 internal voltage references, giving 4 bipolar and 4 unipolar
61 ranges:
62 [-10V,+10V], [-5V,+5V], [-2.5V,+2.5V], [-1.25V,+1.25V],
63 [0,+10V], [0,+5V], [0,+2.5V], [0,1.25V].
64 1=Jumper position 2-3, 1 external voltage reference, giving
65 1 bipolar and 1 unipolar range:
66 [-Vext,+Vext], [0,+Vext].
67
68Configuration options - PCI234:
69 [0] - PCI bus of device (optional).
70 [1] - PCI slot of device (optional).
71 If bus/slot is not specified, the first available PCI device
72 will be used.
73 [2] - Select internal or external voltage reference according to
74 jumper LK1. This affects all channels:
75 0=Jumper position 1-2 (factory default), Vref=5V internal.
76 1=Jumper position 2-3, Vref=Vext external.
77 [3] - Select channel 0 range according to jumper LK2:
78 0=Jumper position 2-3 (factory default), range [-2*Vref,+2*Vref]
79 (10V bipolar when options[2]=0).
80 1=Jumper position 1-2, range [-Vref,+Vref]
81 (5V bipolar when options[2]=0).
82 [4] - Select channel 1 range according to jumper LK3: cf. options[3].
83 [5] - Select channel 2 range according to jumper LK4: cf. options[3].
84 [6] - Select channel 3 range according to jumper LK5: cf. options[3].
85
86Passing a zero for an option is the same as leaving it unspecified.
87
88Caveats:
89
90 1) All channels on the PCI224 share the same range. Any change to the
91 range as a result of insn_write or a streaming command will affect
92 the output voltages of all channels, including those not specified
93 by the instruction or command.
94
95 2) For the analog output command, the first scan may be triggered
96 falsely at the start of acquisition. This occurs when the DAC scan
97 trigger source is switched from 'none' to 'timer' (scan_begin_src =
98 TRIG_TIMER) or 'external' (scan_begin_src == TRIG_EXT) at the start
99 of acquisition and the trigger source is at logic level 1 at the
100 time of the switch. This is very likely for TRIG_TIMER. For
101 TRIG_EXT, it depends on the state of the external line and whether
102 the CR_INVERT flag has been set. The remaining scans are triggered
103 correctly.
104*/
105
70265d24 106#include <linux/interrupt.h>
5a0e3ad6 107#include <linux/slab.h>
70265d24 108
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109#include "../comedidev.h"
110
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111#include "comedi_fc.h"
112#include "8253.h"
113
114#define DRIVER_NAME "amplc_pci224"
115
116/*
117 * PCI IDs.
118 */
6608224c 119#define PCI_VENDOR_ID_AMPLICON 0x14dc
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120#define PCI_DEVICE_ID_AMPLICON_PCI224 0x0007
121#define PCI_DEVICE_ID_AMPLICON_PCI234 0x0008
122#define PCI_DEVICE_ID_INVALID 0xffff
123
124/*
125 * PCI224/234 i/o space 1 (PCIBAR2) registers.
126 */
127#define PCI224_IO1_SIZE 0x20 /* Size of i/o space 1 (8-bit registers) */
128#define PCI224_Z2_CT0 0x14 /* 82C54 counter/timer 0 */
129#define PCI224_Z2_CT1 0x15 /* 82C54 counter/timer 1 */
130#define PCI224_Z2_CT2 0x16 /* 82C54 counter/timer 2 */
131#define PCI224_Z2_CTC 0x17 /* 82C54 counter/timer control word */
132#define PCI224_ZCLK_SCE 0x1A /* Group Z Clock Configuration Register */
133#define PCI224_ZGAT_SCE 0x1D /* Group Z Gate Configuration Register */
134#define PCI224_INT_SCE 0x1E /* ISR Interrupt source mask register */
135 /* /Interrupt status */
136
137/*
138 * PCI224/234 i/o space 2 (PCIBAR3) 16-bit registers.
139 */
140#define PCI224_IO2_SIZE 0x10 /* Size of i/o space 2 (16-bit registers). */
141#define PCI224_DACDATA 0x00 /* (w-o) DAC FIFO data. */
142#define PCI224_SOFTTRIG 0x00 /* (r-o) DAC software scan trigger. */
143#define PCI224_DACCON 0x02 /* (r/w) DAC status/configuration. */
144#define PCI224_FIFOSIZ 0x04 /* (w-o) FIFO size for wraparound mode. */
145#define PCI224_DACCEN 0x06 /* (w-o) DAC channel enable register. */
146
147/*
148 * DACCON values.
149 */
150/* (r/w) Scan trigger. */
151#define PCI224_DACCON_TRIG_MASK (7 << 0)
152#define PCI224_DACCON_TRIG_NONE (0 << 0) /* none */
153#define PCI224_DACCON_TRIG_SW (1 << 0) /* software trig */
154#define PCI224_DACCON_TRIG_EXTP (2 << 0) /* ext +ve edge */
155#define PCI224_DACCON_TRIG_EXTN (3 << 0) /* ext -ve edge */
156#define PCI224_DACCON_TRIG_Z2CT0 (4 << 0) /* Z2 CT0 out */
157#define PCI224_DACCON_TRIG_Z2CT1 (5 << 0) /* Z2 CT1 out */
158#define PCI224_DACCON_TRIG_Z2CT2 (6 << 0) /* Z2 CT2 out */
159/* (r/w) Polarity (PCI224 only, PCI234 always bipolar!). */
160#define PCI224_DACCON_POLAR_MASK (1 << 3)
161#define PCI224_DACCON_POLAR_UNI (0 << 3) /* range [0,Vref] */
162#define PCI224_DACCON_POLAR_BI (1 << 3) /* range [-Vref,Vref] */
163/* (r/w) Internal Vref (PCI224 only, when LK1 in position 1-2). */
164#define PCI224_DACCON_VREF_MASK (3 << 4)
165#define PCI224_DACCON_VREF_1_25 (0 << 4) /* Vref = 1.25V */
166#define PCI224_DACCON_VREF_2_5 (1 << 4) /* Vref = 2.5V */
167#define PCI224_DACCON_VREF_5 (2 << 4) /* Vref = 5V */
168#define PCI224_DACCON_VREF_10 (3 << 4) /* Vref = 10V */
169/* (r/w) Wraparound mode enable (to play back stored waveform). */
170#define PCI224_DACCON_FIFOWRAP (1 << 7)
171/* (r/w) FIFO enable. It MUST be set! */
172#define PCI224_DACCON_FIFOENAB (1 << 8)
173/* (r/w) FIFO interrupt trigger level (most values are not very useful). */
174#define PCI224_DACCON_FIFOINTR_MASK (7 << 9)
175#define PCI224_DACCON_FIFOINTR_EMPTY (0 << 9) /* when empty */
176#define PCI224_DACCON_FIFOINTR_NEMPTY (1 << 9) /* when not empty */
177#define PCI224_DACCON_FIFOINTR_NHALF (2 << 9) /* when not half full */
178#define PCI224_DACCON_FIFOINTR_HALF (3 << 9) /* when half full */
179#define PCI224_DACCON_FIFOINTR_NFULL (4 << 9) /* when not full */
180#define PCI224_DACCON_FIFOINTR_FULL (5 << 9) /* when full */
181/* (r-o) FIFO fill level. */
182#define PCI224_DACCON_FIFOFL_MASK (7 << 12)
183#define PCI224_DACCON_FIFOFL_EMPTY (1 << 12) /* 0 */
184#define PCI224_DACCON_FIFOFL_ONETOHALF (0 << 12) /* [1,2048] */
185#define PCI224_DACCON_FIFOFL_HALFTOFULL (4 << 12) /* [2049,4095] */
186#define PCI224_DACCON_FIFOFL_FULL (6 << 12) /* 4096 */
187/* (r-o) DAC busy flag. */
188#define PCI224_DACCON_BUSY (1 << 15)
189/* (w-o) FIFO reset. */
190#define PCI224_DACCON_FIFORESET (1 << 12)
191/* (w-o) Global reset (not sure what it does). */
192#define PCI224_DACCON_GLOBALRESET (1 << 13)
193
194/*
195 * DAC FIFO size.
196 */
197#define PCI224_FIFO_SIZE 4096
198
199/*
200 * DAC FIFO guaranteed minimum room available, depending on reported fill level.
201 * The maximum room available depends on the reported fill level and how much
202 * has been written!
203 */
204#define PCI224_FIFO_ROOM_EMPTY PCI224_FIFO_SIZE
205#define PCI224_FIFO_ROOM_ONETOHALF (PCI224_FIFO_SIZE / 2)
206#define PCI224_FIFO_ROOM_HALFTOFULL 1
207#define PCI224_FIFO_ROOM_FULL 0
208
209/*
210 * Counter/timer clock input configuration sources.
211 */
212#define CLK_CLK 0 /* reserved (channel-specific clock) */
213#define CLK_10MHZ 1 /* internal 10 MHz clock */
214#define CLK_1MHZ 2 /* internal 1 MHz clock */
215#define CLK_100KHZ 3 /* internal 100 kHz clock */
216#define CLK_10KHZ 4 /* internal 10 kHz clock */
217#define CLK_1KHZ 5 /* internal 1 kHz clock */
218#define CLK_OUTNM1 6 /* output of channel-1 modulo total */
219#define CLK_EXT 7 /* external clock */
220/* Macro to construct clock input configuration register value. */
221#define CLK_CONFIG(chan, src) ((((chan) & 3) << 3) | ((src) & 7))
222/* Timebases in ns. */
223#define TIMEBASE_10MHZ 100
224#define TIMEBASE_1MHZ 1000
225#define TIMEBASE_100KHZ 10000
226#define TIMEBASE_10KHZ 100000
227#define TIMEBASE_1KHZ 1000000
228
229/*
230 * Counter/timer gate input configuration sources.
231 */
232#define GAT_VCC 0 /* VCC (i.e. enabled) */
233#define GAT_GND 1 /* GND (i.e. disabled) */
234#define GAT_EXT 2 /* reserved (external gate input) */
235#define GAT_NOUTNM2 3 /* inverted output of channel-2 modulo total */
236/* Macro to construct gate input configuration register value. */
237#define GAT_CONFIG(chan, src) ((((chan) & 3) << 3) | ((src) & 7))
238
239/*
240 * Summary of CLK_OUTNM1 and GAT_NOUTNM2 connections for PCI224 and PCI234:
241 *
242 * Channel's Channel's
243 * clock input gate input
244 * Channel CLK_OUTNM1 GAT_NOUTNM2
245 * ------- ---------- -----------
246 * Z2-CT0 Z2-CT2-OUT /Z2-CT1-OUT
247 * Z2-CT1 Z2-CT0-OUT /Z2-CT2-OUT
248 * Z2-CT2 Z2-CT1-OUT /Z2-CT0-OUT
249 */
250
251/*
252 * Interrupt enable/status bits
253 */
254#define PCI224_INTR_EXT 0x01 /* rising edge on external input */
255#define PCI224_INTR_DAC 0x04 /* DAC (FIFO) interrupt */
256#define PCI224_INTR_Z2CT1 0x20 /* rising edge on Z2-CT1 output */
257
258#define PCI224_INTR_EDGE_BITS (PCI224_INTR_EXT | PCI224_INTR_Z2CT1)
259#define PCI224_INTR_LEVEL_BITS PCI224_INTR_DACFIFO
260
261/*
262 * Handy macros.
263 */
264
265/* Combine old and new bits. */
266#define COMBINE(old, new, mask) (((old) & ~(mask)) | ((new) & (mask)))
267
268/* A generic null function pointer value. */
269#define NULLFUNC 0
270
271/* Current CPU. XXX should this be hard_smp_processor_id()? */
272#define THISCPU smp_processor_id()
273
274/* State bits for use with atomic bit operations. */
275#define AO_CMD_STARTED 0
276
277/*
278 * Range tables.
279 */
280
281/* The software selectable internal ranges for PCI224 (option[2] == 0). */
9ced1de6 282static const struct comedi_lrange range_pci224_internal = {
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283 8,
284 {
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285 BIP_RANGE(10),
286 BIP_RANGE(5),
287 BIP_RANGE(2.5),
288 BIP_RANGE(1.25),
289 UNI_RANGE(10),
290 UNI_RANGE(5),
291 UNI_RANGE(2.5),
292 UNI_RANGE(1.25),
293 }
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294};
295
296static const unsigned short hwrange_pci224_internal[8] = {
297 PCI224_DACCON_POLAR_BI | PCI224_DACCON_VREF_10,
298 PCI224_DACCON_POLAR_BI | PCI224_DACCON_VREF_5,
299 PCI224_DACCON_POLAR_BI | PCI224_DACCON_VREF_2_5,
300 PCI224_DACCON_POLAR_BI | PCI224_DACCON_VREF_1_25,
301 PCI224_DACCON_POLAR_UNI | PCI224_DACCON_VREF_10,
302 PCI224_DACCON_POLAR_UNI | PCI224_DACCON_VREF_5,
303 PCI224_DACCON_POLAR_UNI | PCI224_DACCON_VREF_2_5,
304 PCI224_DACCON_POLAR_UNI | PCI224_DACCON_VREF_1_25,
305};
306
307/* The software selectable external ranges for PCI224 (option[2] == 1). */
9ced1de6 308static const struct comedi_lrange range_pci224_external = {
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309 2,
310 {
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311 RANGE_ext(-1, 1), /* bipolar [-Vref,+Vref] */
312 RANGE_ext(0, 1), /* unipolar [0,+Vref] */
313 }
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314};
315
316static const unsigned short hwrange_pci224_external[2] = {
317 PCI224_DACCON_POLAR_BI,
318 PCI224_DACCON_POLAR_UNI,
319};
320
321/* The hardware selectable Vref*2 external range for PCI234
322 * (option[2] == 1, option[3+n] == 0). */
9ced1de6 323static const struct comedi_lrange range_pci234_ext2 = {
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324 1,
325 {
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326 RANGE_ext(-2, 2),
327 }
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328};
329
330/* The hardware selectable Vref external range for PCI234
331 * (option[2] == 1, option[3+n] == 1). */
9ced1de6 332static const struct comedi_lrange range_pci234_ext = {
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333 1,
334 {
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335 RANGE_ext(-1, 1),
336 }
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337};
338
339/* This serves for all the PCI234 ranges. */
340static const unsigned short hwrange_pci234[1] = {
341 PCI224_DACCON_POLAR_BI, /* bipolar - hardware ignores it! */
342};
343
344/*
345 * Board descriptions.
346 */
347
348enum pci224_model { any_model, pci224_model, pci234_model };
349
5a676a21 350struct pci224_board {
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351 const char *name;
352 unsigned short devid;
353 enum pci224_model model;
354 unsigned int ao_chans;
355 unsigned int ao_bits;
5a676a21 356};
ea1aeae4 357
5a676a21 358static const struct pci224_board pci224_boards[] = {
ea1aeae4 359 {
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360 .name = "pci224",
361 .devid = PCI_DEVICE_ID_AMPLICON_PCI224,
362 .model = pci224_model,
363 .ao_chans = 16,
364 .ao_bits = 12,
365 },
ea1aeae4 366 {
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367 .name = "pci234",
368 .devid = PCI_DEVICE_ID_AMPLICON_PCI234,
369 .model = pci234_model,
370 .ao_chans = 4,
371 .ao_bits = 16,
372 },
ea1aeae4 373 {
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374 .name = DRIVER_NAME,
375 .devid = PCI_DEVICE_ID_INVALID,
376 .model = any_model, /* wildcard */
377 },
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378};
379
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380/*
381 * Useful for shorthand access to the particular board structure
382 */
5a676a21 383#define thisboard ((struct pci224_board *)dev->board_ptr)
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384
385/* this structure is for data unique to this hardware driver. If
386 several hardware drivers keep similar information in this structure,
71b5f4f1 387 feel free to suggest moving the variable to the struct comedi_device struct. */
a27872bf 388struct pci224_private {
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389 struct pci_dev *pci_dev; /* PCI device */
390 const unsigned short *hwrange;
391 unsigned long iobase1;
392 unsigned long state;
393 spinlock_t ao_spinlock;
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394 unsigned int *ao_readback;
395 short *ao_scan_vals;
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396 unsigned char *ao_scan_order;
397 int intr_cpuid;
398 short intr_running;
399 unsigned short daccon;
400 unsigned int cached_div1;
401 unsigned int cached_div2;
402 unsigned int ao_stop_count;
403 short ao_stop_continuous;
404 unsigned short ao_enab; /* max 16 channels so 'short' will do */
405 unsigned char intsce;
a27872bf 406};
ea1aeae4 407
a27872bf 408#define devpriv ((struct pci224_private *)dev->private)
ea1aeae4 409
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410/*
411 * Called from the 'insn_write' function to perform a single write.
412 */
413static void
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414pci224_ao_set_data(struct comedi_device *dev, int chan, int range,
415 unsigned int data)
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416{
417 unsigned short mangled;
418
419 /* Store unmangled data for readback. */
420 devpriv->ao_readback[chan] = data;
421 /* Enable the channel. */
422 outw(1 << chan, dev->iobase + PCI224_DACCEN);
423 /* Set range and reset FIFO. */
424 devpriv->daccon = COMBINE(devpriv->daccon, devpriv->hwrange[range],
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425 (PCI224_DACCON_POLAR_MASK |
426 PCI224_DACCON_VREF_MASK));
ea1aeae4 427 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
0a85b6f0 428 dev->iobase + PCI224_DACCON);
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429 /*
430 * Mangle the data. The hardware expects:
431 * - bipolar: 16-bit 2's complement
432 * - unipolar: 16-bit unsigned
433 */
434 mangled = (unsigned short)data << (16 - thisboard->ao_bits);
435 if ((devpriv->daccon & PCI224_DACCON_POLAR_MASK) ==
0a85b6f0 436 PCI224_DACCON_POLAR_BI) {
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437 mangled ^= 0x8000;
438 }
439 /* Write mangled data to the FIFO. */
440 outw(mangled, dev->iobase + PCI224_DACDATA);
441 /* Trigger the conversion. */
442 inw(dev->iobase + PCI224_SOFTTRIG);
443}
444
445/*
446 * 'insn_write' function for AO subdevice.
447 */
448static int
da91b269 449pci224_ao_insn_write(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 450 struct comedi_insn *insn, unsigned int *data)
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451{
452 int i;
453 int chan, range;
454
455 /* Unpack channel and range. */
456 chan = CR_CHAN(insn->chanspec);
457 range = CR_RANGE(insn->chanspec);
458
459 /* Writing a list of values to an AO channel is probably not
460 * very useful, but that's how the interface is defined. */
767700c4 461 for (i = 0; i < insn->n; i++)
ea1aeae4 462 pci224_ao_set_data(dev, chan, range, data[i]);
767700c4 463
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464 return i;
465}
466
467/*
468 * 'insn_read' function for AO subdevice.
469 *
470 * N.B. The value read will not be valid if the DAC channel has
471 * never been written successfully since the device was attached
472 * or since the channel has been used by an AO streaming write
473 * command.
474 */
475static int
da91b269 476pci224_ao_insn_read(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 477 struct comedi_insn *insn, unsigned int *data)
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478{
479 int i;
480 int chan;
481
482 chan = CR_CHAN(insn->chanspec);
483
767700c4 484 for (i = 0; i < insn->n; i++)
ea1aeae4 485 data[i] = devpriv->ao_readback[chan];
767700c4 486
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487
488 return i;
489}
490
491/*
492 * Just a wrapper for the inline function 'i8253_cascade_ns_to_timer'.
493 */
494static void
495pci224_cascade_ns_to_timer(int osc_base, unsigned int *d1, unsigned int *d2,
0a85b6f0 496 unsigned int *nanosec, int round_mode)
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497{
498 i8253_cascade_ns_to_timer(osc_base, d1, d2, nanosec, round_mode);
499}
500
501/*
502 * Kills a command running on the AO subdevice.
503 */
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504static void pci224_ao_stop(struct comedi_device *dev,
505 struct comedi_subdevice *s)
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506{
507 unsigned long flags;
508
767700c4 509 if (!test_and_clear_bit(AO_CMD_STARTED, &devpriv->state))
ea1aeae4 510 return;
767700c4 511
ea1aeae4 512
5f74ea14 513 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
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514 /* Kill the interrupts. */
515 devpriv->intsce = 0;
516 outb(0, devpriv->iobase1 + PCI224_INT_SCE);
517 /*
518 * Interrupt routine may or may not be running. We may or may not
519 * have been called from the interrupt routine (directly or
520 * indirectly via a comedi_events() callback routine). It's highly
521 * unlikely that we've been called from some other interrupt routine
522 * but who knows what strange things coders get up to!
523 *
524 * If the interrupt routine is currently running, wait for it to
525 * finish, unless we appear to have been called via the interrupt
526 * routine.
527 */
528 while (devpriv->intr_running && devpriv->intr_cpuid != THISCPU) {
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529 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
530 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4 531 }
5f74ea14 532 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
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533 /* Reconfigure DAC for insn_write usage. */
534 outw(0, dev->iobase + PCI224_DACCEN); /* Disable channels. */
535 devpriv->daccon = COMBINE(devpriv->daccon,
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536 PCI224_DACCON_TRIG_SW |
537 PCI224_DACCON_FIFOINTR_EMPTY,
538 PCI224_DACCON_TRIG_MASK |
539 PCI224_DACCON_FIFOINTR_MASK);
ea1aeae4 540 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
0a85b6f0 541 dev->iobase + PCI224_DACCON);
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542}
543
544/*
545 * Handles start of acquisition for the AO subdevice.
546 */
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547static void pci224_ao_start(struct comedi_device *dev,
548 struct comedi_subdevice *s)
ea1aeae4 549{
ea6d0d4c 550 struct comedi_cmd *cmd = &s->async->cmd;
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551 unsigned long flags;
552
553 set_bit(AO_CMD_STARTED, &devpriv->state);
554 if (!devpriv->ao_stop_continuous && devpriv->ao_stop_count == 0) {
555 /* An empty acquisition! */
556 pci224_ao_stop(dev, s);
557 s->async->events |= COMEDI_CB_EOA;
558 comedi_event(dev, s);
559 } else {
560 /* Enable interrupts. */
5f74ea14 561 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
767700c4 562 if (cmd->stop_src == TRIG_EXT)
ea1aeae4 563 devpriv->intsce = PCI224_INTR_EXT | PCI224_INTR_DAC;
767700c4 564 else
ea1aeae4 565 devpriv->intsce = PCI224_INTR_DAC;
767700c4 566
ea1aeae4 567 outb(devpriv->intsce, devpriv->iobase1 + PCI224_INT_SCE);
5f74ea14 568 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
569 }
570}
571
572/*
573 * Handles interrupts from the DAC FIFO.
574 */
0a85b6f0
MT
575static void pci224_ao_handle_fifo(struct comedi_device *dev,
576 struct comedi_subdevice *s)
ea1aeae4 577{
ea6d0d4c 578 struct comedi_cmd *cmd = &s->async->cmd;
ea1aeae4
IA
579 unsigned int num_scans;
580 unsigned int room;
581 unsigned short dacstat;
582 unsigned int i, n;
583 unsigned int bytes_per_scan;
584
585 if (cmd->chanlist_len) {
790c5541 586 bytes_per_scan = cmd->chanlist_len * sizeof(short);
ea1aeae4
IA
587 } else {
588 /* Shouldn't get here! */
790c5541 589 bytes_per_scan = sizeof(short);
ea1aeae4
IA
590 }
591 /* Determine number of scans available in buffer. */
592 num_scans = comedi_buf_read_n_available(s->async) / bytes_per_scan;
593 if (!devpriv->ao_stop_continuous) {
594 /* Fixed number of scans. */
767700c4 595 if (num_scans > devpriv->ao_stop_count)
ea1aeae4 596 num_scans = devpriv->ao_stop_count;
767700c4 597
ea1aeae4
IA
598 }
599
600 /* Determine how much room is in the FIFO (in samples). */
601 dacstat = inw(dev->iobase + PCI224_DACCON);
602 switch (dacstat & PCI224_DACCON_FIFOFL_MASK) {
603 case PCI224_DACCON_FIFOFL_EMPTY:
604 room = PCI224_FIFO_ROOM_EMPTY;
0a85b6f0 605 if (!devpriv->ao_stop_continuous && devpriv->ao_stop_count == 0) {
ea1aeae4
IA
606 /* FIFO empty at end of counted acquisition. */
607 pci224_ao_stop(dev, s);
608 s->async->events |= COMEDI_CB_EOA;
609 comedi_event(dev, s);
610 return;
611 }
612 break;
613 case PCI224_DACCON_FIFOFL_ONETOHALF:
614 room = PCI224_FIFO_ROOM_ONETOHALF;
615 break;
616 case PCI224_DACCON_FIFOFL_HALFTOFULL:
617 room = PCI224_FIFO_ROOM_HALFTOFULL;
618 break;
619 default:
620 room = PCI224_FIFO_ROOM_FULL;
621 break;
622 }
623 if (room >= PCI224_FIFO_ROOM_ONETOHALF) {
624 /* FIFO is less than half-full. */
625 if (num_scans == 0) {
626 /* Nothing left to put in the FIFO. */
627 pci224_ao_stop(dev, s);
628 s->async->events |= COMEDI_CB_OVERFLOW;
5f74ea14 629 printk(KERN_ERR "comedi%d: "
0a85b6f0 630 "AO buffer underrun\n", dev->minor);
ea1aeae4
IA
631 }
632 }
633 /* Determine how many new scans can be put in the FIFO. */
767700c4 634 if (cmd->chanlist_len)
ea1aeae4 635 room /= cmd->chanlist_len;
767700c4 636
ea1aeae4 637 /* Determine how many scans to process. */
767700c4 638 if (num_scans > room)
ea1aeae4 639 num_scans = room;
767700c4 640
ea1aeae4
IA
641 /* Process scans. */
642 for (n = 0; n < num_scans; n++) {
643 cfc_read_array_from_buffer(s, &devpriv->ao_scan_vals[0],
0a85b6f0 644 bytes_per_scan);
ea1aeae4 645 for (i = 0; i < cmd->chanlist_len; i++) {
0a85b6f0
MT
646 outw(devpriv->ao_scan_vals[devpriv->ao_scan_order[i]],
647 dev->iobase + PCI224_DACDATA);
ea1aeae4
IA
648 }
649 }
650 if (!devpriv->ao_stop_continuous) {
651 devpriv->ao_stop_count -= num_scans;
652 if (devpriv->ao_stop_count == 0) {
653 /*
654 * Change FIFO interrupt trigger level to wait
655 * until FIFO is empty.
656 */
657 devpriv->daccon = COMBINE(devpriv->daccon,
0a85b6f0
MT
658 PCI224_DACCON_FIFOINTR_EMPTY,
659 PCI224_DACCON_FIFOINTR_MASK);
660 outw(devpriv->daccon, dev->iobase + PCI224_DACCON);
ea1aeae4
IA
661 }
662 }
663 if ((devpriv->daccon & PCI224_DACCON_TRIG_MASK) ==
0a85b6f0 664 PCI224_DACCON_TRIG_NONE) {
ea1aeae4
IA
665 unsigned short trig;
666
667 /*
668 * This is the initial DAC FIFO interrupt at the
669 * start of the acquisition. The DAC's scan trigger
670 * has been set to 'none' up until now.
671 *
672 * Now that data has been written to the FIFO, the
673 * DAC's scan trigger source can be set to the
674 * correct value.
675 *
676 * BUG: The first scan will be triggered immediately
677 * if the scan trigger source is at logic level 1.
678 */
679 if (cmd->scan_begin_src == TRIG_TIMER) {
680 trig = PCI224_DACCON_TRIG_Z2CT0;
681 } else {
682 /* cmd->scan_begin_src == TRIG_EXT */
767700c4 683 if (cmd->scan_begin_arg & CR_INVERT)
ea1aeae4 684 trig = PCI224_DACCON_TRIG_EXTN;
767700c4 685 else
ea1aeae4 686 trig = PCI224_DACCON_TRIG_EXTP;
767700c4 687
ea1aeae4
IA
688 }
689 devpriv->daccon = COMBINE(devpriv->daccon, trig,
0a85b6f0 690 PCI224_DACCON_TRIG_MASK);
ea1aeae4
IA
691 outw(devpriv->daccon, dev->iobase + PCI224_DACCON);
692 }
767700c4 693 if (s->async->events)
ea1aeae4 694 comedi_event(dev, s);
767700c4 695
ea1aeae4
IA
696}
697
698/*
699 * Internal trigger function to start acquisition on AO subdevice.
700 */
701static int
da91b269 702pci224_ao_inttrig_start(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 703 unsigned int trignum)
ea1aeae4
IA
704{
705 if (trignum != 0)
706 return -EINVAL;
707
708 s->async->inttrig = NULLFUNC;
709 pci224_ao_start(dev, s);
710
711 return 1;
712}
713
714#define MAX_SCAN_PERIOD 0xFFFFFFFFU
715#define MIN_SCAN_PERIOD 2500
716#define CONVERT_PERIOD 625
717
718/*
719 * 'do_cmdtest' function for AO subdevice.
720 */
721static int
0a85b6f0
MT
722pci224_ao_cmdtest(struct comedi_device *dev, struct comedi_subdevice *s,
723 struct comedi_cmd *cmd)
ea1aeae4
IA
724{
725 int err = 0;
726 unsigned int tmp;
727
728 /* Step 1: make sure trigger sources are trivially valid. */
729
730 tmp = cmd->start_src;
731 cmd->start_src &= TRIG_INT | TRIG_EXT;
732 if (!cmd->start_src || tmp != cmd->start_src)
733 err++;
734
735 tmp = cmd->scan_begin_src;
736 cmd->scan_begin_src &= TRIG_EXT | TRIG_TIMER;
737 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
738 err++;
739
740 tmp = cmd->convert_src;
741 cmd->convert_src &= TRIG_NOW;
742 if (!cmd->convert_src || tmp != cmd->convert_src)
743 err++;
744
745 tmp = cmd->scan_end_src;
746 cmd->scan_end_src &= TRIG_COUNT;
747 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
748 err++;
749
750 tmp = cmd->stop_src;
751 cmd->stop_src &= TRIG_COUNT | TRIG_EXT | TRIG_NONE;
752 if (!cmd->stop_src || tmp != cmd->stop_src)
753 err++;
754
755 if (err)
756 return 1;
757
758 /* Step 2: make sure trigger sources are unique and mutually
759 * compatible. */
760
761 /* these tests are true if more than one _src bit is set */
762 if ((cmd->start_src & (cmd->start_src - 1)) != 0)
763 err++;
764 if ((cmd->scan_begin_src & (cmd->scan_begin_src - 1)) != 0)
765 err++;
766 if ((cmd->convert_src & (cmd->convert_src - 1)) != 0)
767 err++;
768 if ((cmd->scan_end_src & (cmd->scan_end_src - 1)) != 0)
769 err++;
770 if ((cmd->stop_src & (cmd->stop_src - 1)) != 0)
771 err++;
772
773 /* There's only one external trigger signal (which makes these
774 * tests easier). Only one thing can use it. */
775 tmp = 0;
776 if (cmd->start_src & TRIG_EXT)
777 tmp++;
778 if (cmd->scan_begin_src & TRIG_EXT)
779 tmp++;
780 if (cmd->stop_src & TRIG_EXT)
781 tmp++;
782 if (tmp > 1)
783 err++;
784
785 if (err)
786 return 2;
787
788 /* Step 3: make sure arguments are trivially compatible. */
789
790 switch (cmd->start_src) {
791 case TRIG_INT:
792 if (cmd->start_arg != 0) {
793 cmd->start_arg = 0;
794 err++;
795 }
796 break;
797 case TRIG_EXT:
798 /* Force to external trigger 0. */
799 if ((cmd->start_arg & ~CR_FLAGS_MASK) != 0) {
800 cmd->start_arg = COMBINE(cmd->start_arg, 0,
0a85b6f0 801 ~CR_FLAGS_MASK);
ea1aeae4
IA
802 err++;
803 }
804 /* The only flag allowed is CR_EDGE, which is ignored. */
805 if ((cmd->start_arg & CR_FLAGS_MASK & ~CR_EDGE) != 0) {
806 cmd->start_arg = COMBINE(cmd->start_arg, 0,
0a85b6f0 807 CR_FLAGS_MASK & ~CR_EDGE);
ea1aeae4
IA
808 err++;
809 }
810 break;
811 }
812
813 switch (cmd->scan_begin_src) {
814 case TRIG_TIMER:
815 if (cmd->scan_begin_arg > MAX_SCAN_PERIOD) {
816 cmd->scan_begin_arg = MAX_SCAN_PERIOD;
817 err++;
818 }
819 tmp = cmd->chanlist_len * CONVERT_PERIOD;
767700c4 820 if (tmp < MIN_SCAN_PERIOD)
ea1aeae4 821 tmp = MIN_SCAN_PERIOD;
767700c4 822
ea1aeae4
IA
823 if (cmd->scan_begin_arg < tmp) {
824 cmd->scan_begin_arg = tmp;
825 err++;
826 }
827 break;
828 case TRIG_EXT:
829 /* Force to external trigger 0. */
830 if ((cmd->scan_begin_arg & ~CR_FLAGS_MASK) != 0) {
831 cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
0a85b6f0 832 ~CR_FLAGS_MASK);
ea1aeae4
IA
833 err++;
834 }
835 /* Only allow flags CR_EDGE and CR_INVERT. Ignore CR_EDGE. */
836 if ((cmd->scan_begin_arg & CR_FLAGS_MASK &
0a85b6f0 837 ~(CR_EDGE | CR_INVERT)) != 0) {
ea1aeae4 838 cmd->scan_begin_arg = COMBINE(cmd->scan_begin_arg, 0,
0a85b6f0
MT
839 CR_FLAGS_MASK & ~(CR_EDGE
840 |
841 CR_INVERT));
ea1aeae4
IA
842 err++;
843 }
844 break;
845 }
846
847 /* cmd->convert_src == TRIG_NOW */
848 if (cmd->convert_arg != 0) {
849 cmd->convert_arg = 0;
850 err++;
851 }
852
853 /* cmd->scan_end_arg == TRIG_COUNT */
854 if (cmd->scan_end_arg != cmd->chanlist_len) {
855 cmd->scan_end_arg = cmd->chanlist_len;
856 err++;
857 }
858
859 switch (cmd->stop_src) {
860 case TRIG_COUNT:
861 /* Any count allowed. */
862 break;
863 case TRIG_EXT:
864 /* Force to external trigger 0. */
865 if ((cmd->stop_arg & ~CR_FLAGS_MASK) != 0) {
866 cmd->stop_arg = COMBINE(cmd->stop_arg, 0,
0a85b6f0 867 ~CR_FLAGS_MASK);
ea1aeae4
IA
868 err++;
869 }
870 /* The only flag allowed is CR_EDGE, which is ignored. */
871 if ((cmd->stop_arg & CR_FLAGS_MASK & ~CR_EDGE) != 0) {
872 cmd->stop_arg = COMBINE(cmd->stop_arg, 0,
0a85b6f0 873 CR_FLAGS_MASK & ~CR_EDGE);
ea1aeae4
IA
874 }
875 break;
876 case TRIG_NONE:
877 if (cmd->stop_arg != 0) {
878 cmd->stop_arg = 0;
879 err++;
880 }
881 break;
882 }
883
884 if (err)
885 return 3;
886
887 /* Step 4: fix up any arguments. */
888
889 if (cmd->scan_begin_src == TRIG_TIMER) {
890 unsigned int div1, div2, round;
891 int round_mode = cmd->flags & TRIG_ROUND_MASK;
892
893 tmp = cmd->scan_begin_arg;
894 /* Check whether to use a single timer. */
895 switch (round_mode) {
896 case TRIG_ROUND_NEAREST:
897 default:
898 round = TIMEBASE_10MHZ / 2;
899 break;
900 case TRIG_ROUND_DOWN:
901 round = 0;
902 break;
903 case TRIG_ROUND_UP:
904 round = TIMEBASE_10MHZ - 1;
905 break;
906 }
907 /* Be careful to avoid overflow! */
908 div2 = cmd->scan_begin_arg / TIMEBASE_10MHZ;
909 div2 += (round + cmd->scan_begin_arg % TIMEBASE_10MHZ) /
0a85b6f0 910 TIMEBASE_10MHZ;
ea1aeae4
IA
911 if (div2 <= 0x10000) {
912 /* A single timer will suffice. */
913 if (div2 < 2)
914 div2 = 2;
915 cmd->scan_begin_arg = div2 * TIMEBASE_10MHZ;
916 if (cmd->scan_begin_arg < div2 ||
0a85b6f0 917 cmd->scan_begin_arg < TIMEBASE_10MHZ) {
ea1aeae4
IA
918 /* Overflow! */
919 cmd->scan_begin_arg = MAX_SCAN_PERIOD;
920 }
921 } else {
922 /* Use two timers. */
923 div1 = devpriv->cached_div1;
924 div2 = devpriv->cached_div2;
925 pci224_cascade_ns_to_timer(TIMEBASE_10MHZ, &div1, &div2,
0a85b6f0
MT
926 &cmd->scan_begin_arg,
927 round_mode);
ea1aeae4
IA
928 devpriv->cached_div1 = div1;
929 devpriv->cached_div2 = div2;
930 }
767700c4 931 if (tmp != cmd->scan_begin_arg)
ea1aeae4 932 err++;
767700c4 933
ea1aeae4
IA
934 }
935
936 if (err)
937 return 4;
938
939 /* Step 5: check channel list. */
940
941 if (cmd->chanlist && (cmd->chanlist_len > 0)) {
942 unsigned int range;
943 enum { range_err = 1, dupchan_err = 2, };
944 unsigned errors;
945 unsigned int n;
946 unsigned int ch;
947
948 /*
949 * Check all channels have the same range index. Don't care
950 * about analogue reference, as we can't configure it.
951 *
952 * Check the list has no duplicate channels.
953 */
954 range = CR_RANGE(cmd->chanlist[0]);
955 errors = 0;
956 tmp = 0;
957 for (n = 0; n < cmd->chanlist_len; n++) {
958 ch = CR_CHAN(cmd->chanlist[n]);
767700c4 959 if (tmp & (1U << ch))
ea1aeae4 960 errors |= dupchan_err;
767700c4 961
ea1aeae4 962 tmp |= (1U << ch);
767700c4 963 if (CR_RANGE(cmd->chanlist[n]) != range)
ea1aeae4 964 errors |= range_err;
767700c4 965
ea1aeae4
IA
966 }
967 if (errors) {
968 if (errors & dupchan_err) {
969 DPRINTK("comedi%d: " DRIVER_NAME
970 ": ao_cmdtest: "
971 "entries in chanlist must contain no "
972 "duplicate channels\n", dev->minor);
973 }
974 if (errors & range_err) {
975 DPRINTK("comedi%d: " DRIVER_NAME
976 ": ao_cmdtest: "
977 "entries in chanlist must all have "
978 "the same range index\n", dev->minor);
979 }
980 err++;
981 }
982 }
983
984 if (err)
985 return 5;
986
987 return 0;
988}
989
990/*
991 * 'do_cmd' function for AO subdevice.
992 */
da91b269 993static int pci224_ao_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
ea1aeae4 994{
ea6d0d4c 995 struct comedi_cmd *cmd = &s->async->cmd;
ea1aeae4
IA
996 int range;
997 unsigned int i, j;
998 unsigned int ch;
999 unsigned int rank;
1000 unsigned long flags;
1001
1002 /* Cannot handle null/empty chanlist. */
767700c4 1003 if (cmd->chanlist == NULL || cmd->chanlist_len == 0)
ea1aeae4 1004 return -EINVAL;
767700c4 1005
ea1aeae4
IA
1006
1007 /* Determine which channels are enabled and their load order. */
1008 devpriv->ao_enab = 0;
1009
1010 for (i = 0; i < cmd->chanlist_len; i++) {
1011 ch = CR_CHAN(cmd->chanlist[i]);
1012 devpriv->ao_enab |= 1U << ch;
1013 rank = 0;
1014 for (j = 0; j < cmd->chanlist_len; j++) {
767700c4 1015 if (CR_CHAN(cmd->chanlist[j]) < ch)
ea1aeae4 1016 rank++;
767700c4 1017
ea1aeae4
IA
1018 }
1019 devpriv->ao_scan_order[rank] = i;
1020 }
1021
1022 /* Set enabled channels. */
1023 outw(devpriv->ao_enab, dev->iobase + PCI224_DACCEN);
1024
1025 /* Determine range and polarity. All channels the same. */
1026 range = CR_RANGE(cmd->chanlist[0]);
1027
1028 /*
1029 * Set DAC range and polarity.
1030 * Set DAC scan trigger source to 'none'.
1031 * Set DAC FIFO interrupt trigger level to 'not half full'.
1032 * Reset DAC FIFO.
1033 *
1034 * N.B. DAC FIFO interrupts are currently disabled.
1035 */
1036 devpriv->daccon = COMBINE(devpriv->daccon,
0a85b6f0
MT
1037 (devpriv->
1038 hwrange[range] | PCI224_DACCON_TRIG_NONE |
1039 PCI224_DACCON_FIFOINTR_NHALF),
1040 (PCI224_DACCON_POLAR_MASK |
1041 PCI224_DACCON_VREF_MASK |
1042 PCI224_DACCON_TRIG_MASK |
1043 PCI224_DACCON_FIFOINTR_MASK));
ea1aeae4 1044 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
0a85b6f0 1045 dev->iobase + PCI224_DACCON);
ea1aeae4
IA
1046
1047 if (cmd->scan_begin_src == TRIG_TIMER) {
1048 unsigned int div1, div2, round;
1049 unsigned int ns = cmd->scan_begin_arg;
1050 int round_mode = cmd->flags & TRIG_ROUND_MASK;
1051
1052 /* Check whether to use a single timer. */
1053 switch (round_mode) {
1054 case TRIG_ROUND_NEAREST:
1055 default:
1056 round = TIMEBASE_10MHZ / 2;
1057 break;
1058 case TRIG_ROUND_DOWN:
1059 round = 0;
1060 break;
1061 case TRIG_ROUND_UP:
1062 round = TIMEBASE_10MHZ - 1;
1063 break;
1064 }
1065 /* Be careful to avoid overflow! */
1066 div2 = cmd->scan_begin_arg / TIMEBASE_10MHZ;
1067 div2 += (round + cmd->scan_begin_arg % TIMEBASE_10MHZ) /
0a85b6f0 1068 TIMEBASE_10MHZ;
ea1aeae4
IA
1069 if (div2 <= 0x10000) {
1070 /* A single timer will suffice. */
1071 if (div2 < 2)
1072 div2 = 2;
1073 div2 &= 0xffff;
1074 div1 = 1; /* Flag that single timer to be used. */
1075 } else {
1076 /* Use two timers. */
1077 div1 = devpriv->cached_div1;
1078 div2 = devpriv->cached_div2;
1079 pci224_cascade_ns_to_timer(TIMEBASE_10MHZ, &div1, &div2,
0a85b6f0 1080 &ns, round_mode);
ea1aeae4
IA
1081 }
1082
1083 /*
1084 * The output of timer Z2-0 will be used as the scan trigger
1085 * source.
1086 */
1087 /* Make sure Z2-0 is gated on. */
1088 outb(GAT_CONFIG(0, GAT_VCC),
0a85b6f0 1089 devpriv->iobase1 + PCI224_ZGAT_SCE);
ea1aeae4
IA
1090 if (div1 == 1) {
1091 /* Not cascading. Z2-0 needs 10 MHz clock. */
1092 outb(CLK_CONFIG(0, CLK_10MHZ),
0a85b6f0 1093 devpriv->iobase1 + PCI224_ZCLK_SCE);
ea1aeae4
IA
1094 } else {
1095 /* Cascading with Z2-2. */
1096 /* Make sure Z2-2 is gated on. */
1097 outb(GAT_CONFIG(2, GAT_VCC),
0a85b6f0 1098 devpriv->iobase1 + PCI224_ZGAT_SCE);
ea1aeae4
IA
1099 /* Z2-2 needs 10 MHz clock. */
1100 outb(CLK_CONFIG(2, CLK_10MHZ),
0a85b6f0 1101 devpriv->iobase1 + PCI224_ZCLK_SCE);
ea1aeae4
IA
1102 /* Load Z2-2 mode (2) and counter (div1). */
1103 i8254_load(devpriv->iobase1 + PCI224_Z2_CT0, 0,
0a85b6f0 1104 2, div1, 2);
ea1aeae4
IA
1105 /* Z2-0 is clocked from Z2-2's output. */
1106 outb(CLK_CONFIG(0, CLK_OUTNM1),
0a85b6f0 1107 devpriv->iobase1 + PCI224_ZCLK_SCE);
ea1aeae4
IA
1108 }
1109 /* Load Z2-0 mode (2) and counter (div2). */
1110 i8254_load(devpriv->iobase1 + PCI224_Z2_CT0, 0, 0, div2, 2);
1111 }
1112
1113 /*
1114 * Sort out end of acquisition.
1115 */
1116 switch (cmd->stop_src) {
1117 case TRIG_COUNT:
1118 /* Fixed number of scans. */
1119 devpriv->ao_stop_continuous = 0;
1120 devpriv->ao_stop_count = cmd->stop_arg;
1121 break;
1122 default:
1123 /* Continuous scans. */
1124 devpriv->ao_stop_continuous = 1;
1125 devpriv->ao_stop_count = 0;
1126 break;
1127 }
1128
1129 /*
1130 * Sort out start of acquisition.
1131 */
1132 switch (cmd->start_src) {
1133 case TRIG_INT:
5f74ea14 1134 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4 1135 s->async->inttrig = &pci224_ao_inttrig_start;
5f74ea14 1136 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1137 break;
1138 case TRIG_EXT:
1139 /* Enable external interrupt trigger to start acquisition. */
5f74ea14 1140 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1141 devpriv->intsce |= PCI224_INTR_EXT;
1142 outb(devpriv->intsce, devpriv->iobase1 + PCI224_INT_SCE);
5f74ea14 1143 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1144 break;
1145 }
1146
1147 return 0;
1148}
1149
1150/*
1151 * 'cancel' function for AO subdevice.
1152 */
0a85b6f0
MT
1153static int pci224_ao_cancel(struct comedi_device *dev,
1154 struct comedi_subdevice *s)
ea1aeae4
IA
1155{
1156 pci224_ao_stop(dev, s);
1157 return 0;
1158}
1159
1160/*
1161 * 'munge' data for AO command.
1162 */
1163static void
0a85b6f0
MT
1164pci224_ao_munge(struct comedi_device *dev, struct comedi_subdevice *s,
1165 void *data, unsigned int num_bytes, unsigned int chan_index)
ea1aeae4 1166{
d163679c 1167 struct comedi_async *async = s->async;
790c5541 1168 short *array = data;
ea1aeae4
IA
1169 unsigned int length = num_bytes / sizeof(*array);
1170 unsigned int offset;
1171 unsigned int shift;
1172 unsigned int i;
1173
1174 /* The hardware expects 16-bit numbers. */
1175 shift = 16 - thisboard->ao_bits;
1176 /* Channels will be all bipolar or all unipolar. */
1177 if ((devpriv->hwrange[CR_RANGE(async->cmd.chanlist[0])] &
0a85b6f0 1178 PCI224_DACCON_POLAR_MASK) == PCI224_DACCON_POLAR_UNI) {
ea1aeae4
IA
1179 /* Unipolar */
1180 offset = 0;
1181 } else {
1182 /* Bipolar */
1183 offset = 32768;
1184 }
1185 /* Munge the data. */
767700c4 1186 for (i = 0; i < length; i++)
ea1aeae4 1187 array[i] = (array[i] << shift) - offset;
767700c4 1188
ea1aeae4
IA
1189}
1190
1191/*
1192 * Interrupt handler.
1193 */
70265d24 1194static irqreturn_t pci224_interrupt(int irq, void *d)
ea1aeae4 1195{
71b5f4f1 1196 struct comedi_device *dev = d;
34c43922 1197 struct comedi_subdevice *s = &dev->subdevices[0];
ea6d0d4c 1198 struct comedi_cmd *cmd;
ea1aeae4
IA
1199 unsigned char intstat, valid_intstat;
1200 unsigned char curenab;
1201 int retval = 0;
1202 unsigned long flags;
1203
1204 intstat = inb(devpriv->iobase1 + PCI224_INT_SCE) & 0x3F;
1205 if (intstat) {
1206 retval = 1;
5f74ea14 1207 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1208 valid_intstat = devpriv->intsce & intstat;
1209 /* Temporarily disable interrupt sources. */
1210 curenab = devpriv->intsce & ~intstat;
1211 outb(curenab, devpriv->iobase1 + PCI224_INT_SCE);
1212 devpriv->intr_running = 1;
1213 devpriv->intr_cpuid = THISCPU;
5f74ea14 1214 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1215 if (valid_intstat != 0) {
1216 cmd = &s->async->cmd;
1217 if (valid_intstat & PCI224_INTR_EXT) {
1218 devpriv->intsce &= ~PCI224_INTR_EXT;
767700c4 1219 if (cmd->start_src == TRIG_EXT)
ea1aeae4 1220 pci224_ao_start(dev, s);
767700c4 1221 else if (cmd->stop_src == TRIG_EXT)
ea1aeae4 1222 pci224_ao_stop(dev, s);
767700c4 1223
ea1aeae4 1224 }
767700c4 1225 if (valid_intstat & PCI224_INTR_DAC)
ea1aeae4 1226 pci224_ao_handle_fifo(dev, s);
767700c4 1227
ea1aeae4
IA
1228 }
1229 /* Reenable interrupt sources. */
5f74ea14 1230 spin_lock_irqsave(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1231 if (curenab != devpriv->intsce) {
1232 outb(devpriv->intsce,
0a85b6f0 1233 devpriv->iobase1 + PCI224_INT_SCE);
ea1aeae4
IA
1234 }
1235 devpriv->intr_running = 0;
5f74ea14 1236 spin_unlock_irqrestore(&devpriv->ao_spinlock, flags);
ea1aeae4
IA
1237 }
1238 return IRQ_RETVAL(retval);
1239}
1240
5e9d922f
IA
1241/*
1242 * This function looks for a board matching the supplied PCI device.
1243 */
1244static const struct pci224_board
1245*pci224_find_pci_board(struct pci_dev *pci_dev)
1246{
1247 int i;
1248
1249 for (i = 0; i < ARRAY_SIZE(pci224_boards); i++)
1250 if (pci_dev->device == pci224_boards[i].devid)
1251 return &pci224_boards[i];
1252 return NULL;
1253}
1254
ea1aeae4
IA
1255/*
1256 * This function looks for a PCI device matching the requested board name,
1257 * bus and slot.
1258 */
1259static int
da91b269 1260pci224_find_pci(struct comedi_device *dev, int bus, int slot,
0a85b6f0 1261 struct pci_dev **pci_dev_p)
ea1aeae4
IA
1262{
1263 struct pci_dev *pci_dev = NULL;
1264
1265 *pci_dev_p = NULL;
1266
1267 /* Look for matching PCI device. */
1268 for (pci_dev = pci_get_device(PCI_VENDOR_ID_AMPLICON, PCI_ANY_ID, NULL);
0a85b6f0
MT
1269 pci_dev != NULL;
1270 pci_dev = pci_get_device(PCI_VENDOR_ID_AMPLICON, PCI_ANY_ID,
1271 pci_dev)) {
ea1aeae4
IA
1272 /* If bus/slot specified, check them. */
1273 if (bus || slot) {
1274 if (bus != pci_dev->bus->number
0a85b6f0 1275 || slot != PCI_SLOT(pci_dev->devfn))
ea1aeae4
IA
1276 continue;
1277 }
1278 if (thisboard->model == any_model) {
1279 /* Match any supported model. */
5e9d922f
IA
1280 const struct pci224_board *board_ptr;
1281 board_ptr = pci224_find_pci_board(pci_dev);
1282 if (board_ptr == NULL)
ea1aeae4 1283 continue;
5e9d922f
IA
1284 /* Change board_ptr to matched board. */
1285 dev->board_ptr = board_ptr;
ea1aeae4
IA
1286 } else {
1287 /* Match specific model name. */
1288 if (thisboard->devid != pci_dev->device)
1289 continue;
1290 }
1291
1292 /* Found a match. */
1293 *pci_dev_p = pci_dev;
1294 return 0;
1295 }
1296 /* No match found. */
1297 if (bus || slot) {
1298 printk(KERN_ERR "comedi%d: error! "
0a85b6f0
MT
1299 "no %s found at pci %02x:%02x!\n",
1300 dev->minor, thisboard->name, bus, slot);
ea1aeae4
IA
1301 } else {
1302 printk(KERN_ERR "comedi%d: error! no %s found!\n",
0a85b6f0 1303 dev->minor, thisboard->name);
ea1aeae4
IA
1304 }
1305 return -EIO;
1306}
1307
1308/*
5e9d922f 1309 * Common part of attach and attach_pci.
ea1aeae4 1310 */
5e9d922f
IA
1311static int pci224_attach_common(struct comedi_device *dev,
1312 struct pci_dev *pci_dev, int *options)
ea1aeae4 1313{
34c43922 1314 struct comedi_subdevice *s;
ea1aeae4 1315 unsigned int irq;
ea1aeae4
IA
1316 unsigned n;
1317 int ret;
1318
c3744138
BP
1319 devpriv->pci_dev = pci_dev;
1320 ret = comedi_pci_enable(pci_dev, DRIVER_NAME);
1321 if (ret < 0) {
ea1aeae4 1322 printk(KERN_ERR
0a85b6f0
MT
1323 "comedi%d: error! cannot enable PCI device "
1324 "and request regions!\n", dev->minor);
ea1aeae4
IA
1325 return ret;
1326 }
1327 spin_lock_init(&devpriv->ao_spinlock);
1328
1329 devpriv->iobase1 = pci_resource_start(pci_dev, 2);
1330 dev->iobase = pci_resource_start(pci_dev, 3);
1331 irq = pci_dev->irq;
1332
1333 /* Allocate readback buffer for AO channels. */
1334 devpriv->ao_readback = kmalloc(sizeof(devpriv->ao_readback[0]) *
0a85b6f0 1335 thisboard->ao_chans, GFP_KERNEL);
767700c4 1336 if (!devpriv->ao_readback)
ea1aeae4 1337 return -ENOMEM;
767700c4 1338
ea1aeae4
IA
1339
1340 /* Allocate buffer to hold values for AO channel scan. */
1341 devpriv->ao_scan_vals = kmalloc(sizeof(devpriv->ao_scan_vals[0]) *
0a85b6f0 1342 thisboard->ao_chans, GFP_KERNEL);
767700c4 1343 if (!devpriv->ao_scan_vals)
ea1aeae4 1344 return -ENOMEM;
767700c4 1345
ea1aeae4
IA
1346
1347 /* Allocate buffer to hold AO channel scan order. */
1348 devpriv->ao_scan_order = kmalloc(sizeof(devpriv->ao_scan_order[0]) *
0a85b6f0 1349 thisboard->ao_chans, GFP_KERNEL);
767700c4 1350 if (!devpriv->ao_scan_order)
ea1aeae4 1351 return -ENOMEM;
767700c4 1352
ea1aeae4
IA
1353
1354 /* Disable interrupt sources. */
1355 devpriv->intsce = 0;
1356 outb(0, devpriv->iobase1 + PCI224_INT_SCE);
1357
1358 /* Initialize the DAC hardware. */
1359 outw(PCI224_DACCON_GLOBALRESET, dev->iobase + PCI224_DACCON);
1360 outw(0, dev->iobase + PCI224_DACCEN);
1361 outw(0, dev->iobase + PCI224_FIFOSIZ);
1362 devpriv->daccon = (PCI224_DACCON_TRIG_SW | PCI224_DACCON_POLAR_BI |
0a85b6f0
MT
1363 PCI224_DACCON_FIFOENAB |
1364 PCI224_DACCON_FIFOINTR_EMPTY);
ea1aeae4 1365 outw(devpriv->daccon | PCI224_DACCON_FIFORESET,
0a85b6f0 1366 dev->iobase + PCI224_DACCON);
ea1aeae4
IA
1367
1368 /* Allocate subdevices. There is only one! */
c3744138
BP
1369 ret = alloc_subdevices(dev, 1);
1370 if (ret < 0) {
ea1aeae4 1371 printk(KERN_ERR "comedi%d: error! out of memory!\n",
0a85b6f0 1372 dev->minor);
ea1aeae4
IA
1373 return ret;
1374 }
1375
1376 s = dev->subdevices + 0;
1377 /* Analog output subdevice. */
1378 s->type = COMEDI_SUBD_AO;
1379 s->subdev_flags = SDF_WRITABLE | SDF_GROUND | SDF_CMD_WRITE;
1380 s->n_chan = thisboard->ao_chans;
1381 s->maxdata = (1 << thisboard->ao_bits) - 1;
1382 s->insn_write = &pci224_ao_insn_write;
1383 s->insn_read = &pci224_ao_insn_read;
1384 s->len_chanlist = s->n_chan;
1385
1386 dev->write_subdev = s;
1387 s->do_cmd = &pci224_ao_cmd;
1388 s->do_cmdtest = &pci224_ao_cmdtest;
1389 s->cancel = &pci224_ao_cancel;
1390 s->munge = &pci224_ao_munge;
1391
1392 /* Sort out channel range options. */
1393 if (thisboard->model == pci234_model) {
1394 /* PCI234 range options. */
9ced1de6 1395 const struct comedi_lrange **range_table_list;
ea1aeae4
IA
1396
1397 s->range_table_list = range_table_list =
0a85b6f0
MT
1398 kmalloc(sizeof(struct comedi_lrange *) * s->n_chan,
1399 GFP_KERNEL);
767700c4 1400 if (!s->range_table_list)
ea1aeae4 1401 return -ENOMEM;
767700c4 1402
5e9d922f
IA
1403 if (options) {
1404 for (n = 2; n < 3 + s->n_chan; n++) {
1405 if (options[n] < 0 || options[n] > 1) {
1406 printk(KERN_WARNING
1407 "comedi%d: %s: warning! bad options[%u]=%d\n",
1408 dev->minor, DRIVER_NAME, n,
1409 options[n]);
1410 }
ea1aeae4
IA
1411 }
1412 }
1413 for (n = 0; n < s->n_chan; n++) {
5e9d922f
IA
1414 if (n < COMEDI_NDEVCONFOPTS - 3 && options &&
1415 options[3 + n] == 1) {
1416 if (options[2] == 1)
ea1aeae4 1417 range_table_list[n] = &range_pci234_ext;
767700c4 1418 else
ea1aeae4 1419 range_table_list[n] = &range_bipolar5;
767700c4 1420
ea1aeae4 1421 } else {
5e9d922f 1422 if (options && options[2] == 1) {
ea1aeae4 1423 range_table_list[n] =
0a85b6f0 1424 &range_pci234_ext2;
ea1aeae4
IA
1425 } else {
1426 range_table_list[n] = &range_bipolar10;
1427 }
1428 }
1429 }
1430 devpriv->hwrange = hwrange_pci234;
1431 } else {
1432 /* PCI224 range options. */
5e9d922f 1433 if (options && options[2] == 1) {
ea1aeae4
IA
1434 s->range_table = &range_pci224_external;
1435 devpriv->hwrange = hwrange_pci224_external;
1436 } else {
5e9d922f 1437 if (options && options[2] != 0) {
ea1aeae4 1438 printk(KERN_WARNING "comedi%d: %s: warning! "
0a85b6f0 1439 "bad options[2]=%d\n",
5e9d922f 1440 dev->minor, DRIVER_NAME, options[2]);
ea1aeae4
IA
1441 }
1442 s->range_table = &range_pci224_internal;
1443 devpriv->hwrange = hwrange_pci224_internal;
1444 }
1445 }
1446
1447 dev->board_name = thisboard->name;
1448
1449 if (irq) {
5f74ea14
GKH
1450 ret = request_irq(irq, pci224_interrupt, IRQF_SHARED,
1451 DRIVER_NAME, dev);
ea1aeae4
IA
1452 if (ret < 0) {
1453 printk(KERN_ERR "comedi%d: error! "
0a85b6f0 1454 "unable to allocate irq %u\n", dev->minor, irq);
ea1aeae4
IA
1455 return ret;
1456 } else {
1457 dev->irq = irq;
1458 }
1459 }
1460
1461 printk(KERN_INFO "comedi%d: %s ", dev->minor, dev->board_name);
1462 printk("(pci %s) ", pci_name(pci_dev));
767700c4 1463 if (irq)
ea1aeae4 1464 printk("(irq %u%s) ", irq, (dev->irq ? "" : " UNAVAILABLE"));
767700c4 1465 else
ea1aeae4 1466 printk("(no irq) ");
767700c4 1467
ea1aeae4
IA
1468
1469 printk("attached\n");
1470
1471 return 1;
1472}
1473
5e9d922f
IA
1474static int pci224_attach(struct comedi_device *dev, struct comedi_devconfig *it)
1475{
1476 struct pci_dev *pci_dev;
1477 int bus, slot;
1478 int ret;
1479
1480 printk(KERN_DEBUG "comedi%d: %s: attach\n", dev->minor, DRIVER_NAME);
1481
1482 bus = it->options[0];
1483 slot = it->options[1];
1484 ret = alloc_private(dev, sizeof(struct pci224_private));
1485 if (ret < 0) {
1486 printk(KERN_ERR "comedi%d: error! out of memory!\n",
1487 dev->minor);
1488 return ret;
1489 }
1490
1491 ret = pci224_find_pci(dev, bus, slot, &pci_dev);
1492 if (ret < 0)
1493 return ret;
1494
1495 return pci224_attach_common(dev, pci_dev, it->options);
1496}
1497
52954abc 1498static int __devinit
5e9d922f
IA
1499pci224_attach_pci(struct comedi_device *dev, struct pci_dev *pci_dev)
1500{
1501 int ret;
1502
1503 printk(KERN_DEBUG "comedi%d: %s: attach_pci %s\n", dev->minor,
1504 DRIVER_NAME, pci_name(pci_dev));
1505
1506 ret = alloc_private(dev, sizeof(struct pci224_private));
1507 if (ret < 0) {
1508 printk(KERN_ERR "comedi%d: error! out of memory!\n",
1509 dev->minor);
1510 return ret;
1511 }
1512
1513 dev->board_ptr = pci224_find_pci_board(pci_dev);
1514 if (dev->board_ptr == NULL) {
1515 printk(KERN_ERR
1516 "comedi%d: %s: BUG! cannot determine board type!\n",
1517 dev->minor, DRIVER_NAME);
1518 return -EINVAL;
1519 }
1520 return pci224_attach_common(dev, pci_dev, NULL);
1521}
1522
484ecc95 1523static void pci224_detach(struct comedi_device *dev)
ea1aeae4 1524{
767700c4 1525 if (dev->irq)
5f74ea14 1526 free_irq(dev->irq, dev);
ea1aeae4 1527 if (dev->subdevices) {
34c43922 1528 struct comedi_subdevice *s;
ea1aeae4
IA
1529
1530 s = dev->subdevices + 0;
1531 /* AO subdevice */
48d07f2b 1532 kfree(s->range_table_list);
ea1aeae4
IA
1533 }
1534 if (devpriv) {
48d07f2b 1535 kfree(devpriv->ao_readback);
1536 kfree(devpriv->ao_scan_vals);
1537 kfree(devpriv->ao_scan_order);
ea1aeae4 1538 if (devpriv->pci_dev) {
767700c4 1539 if (dev->iobase)
ea1aeae4 1540 comedi_pci_disable(devpriv->pci_dev);
ea1aeae4
IA
1541 pci_dev_put(devpriv->pci_dev);
1542 }
1543 }
ea1aeae4 1544}
90f703d3 1545
0d09df00
HS
1546static struct comedi_driver amplc_pci224_driver = {
1547 .driver_name = "amplc_pci224",
1548 .module = THIS_MODULE,
1549 .attach = pci224_attach,
1550 .detach = pci224_detach,
1551 .attach_pci = pci224_attach_pci,
1552 .board_name = &pci224_boards[0].name,
1553 .offset = sizeof(struct pci224_board),
1554 .num_names = ARRAY_SIZE(pci224_boards),
1555};
1556
1557static int __devinit amplc_pci224_pci_probe(struct pci_dev *dev,
1558 const struct pci_device_id
1559 *ent)
1560{
1561 return comedi_pci_auto_config(dev, &amplc_pci224_driver);
1562}
1563
1564static void __devexit amplc_pci224_pci_remove(struct pci_dev *dev)
1565{
1566 comedi_pci_auto_unconfig(dev);
1567}
1568
1569static DEFINE_PCI_DEVICE_TABLE(amplc_pci224_pci_table) = {
1570 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI224) },
1571 { PCI_DEVICE(PCI_VENDOR_ID_AMPLICON, PCI_DEVICE_ID_AMPLICON_PCI234) },
1572 { 0 }
1573};
1574MODULE_DEVICE_TABLE(pci, amplc_pci224_pci_table);
1575
1576static struct pci_driver amplc_pci224_pci_driver = {
1577 .name = "amplc_pci224",
1578 .id_table = amplc_pci224_pci_table,
1579 .probe = amplc_pci224_pci_probe,
1580 .remove = __devexit_p(amplc_pci224_pci_remove),
1581};
1582module_comedi_pci_driver(amplc_pci224_driver, amplc_pci224_pci_driver);
1583
90f703d3
AT
1584MODULE_AUTHOR("Comedi http://www.comedi.org");
1585MODULE_DESCRIPTION("Comedi low-level driver");
1586MODULE_LICENSE("GPL");
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