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staging: comedi: dmm32at: remove unneeded boardinfo variables
[deliverable/linux.git] / drivers / staging / comedi / drivers / dmm32at.c
CommitLineData
3c501880
PP		 1/*
2 comedi/drivers/dmm32at.c
3 Diamond Systems mm32at code for a Comedi driver
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21
22*/
23/*
24Driver: dmm32at
25Description: Diamond Systems mm32at driver.
26Devices:
27Author: Perry J. Piplani <perry.j.piplani@nasa.gov>
28Updated: Fri Jun 4 09:13:24 CDT 2004
29Status: experimental
30
31This driver is for the Diamond Systems MM-32-AT board
32http://www.diamondsystems.com/products/diamondmm32at It is being used
33on serveral projects inside NASA, without problems so far. For analog
34input commands, TRIG_EXT is not yet supported at all..
35
36Configuration Options:
37 comedi_config /dev/comedi0 dmm32at baseaddr,irq
38*/
39
25436dc9 40#include <linux/interrupt.h>
3c501880
PP		 41#include "../comedidev.h"
42#include <linux/ioport.h>
43
44/* Board register addresses */
45
46#define DMM32AT_MEMSIZE 0x10
47
48#define DMM32AT_CONV 0x00
49#define DMM32AT_AILSB 0x00
50#define DMM32AT_AUXDOUT 0x01
51#define DMM32AT_AIMSB 0x01
52#define DMM32AT_AILOW 0x02
53#define DMM32AT_AIHIGH 0x03
54
55#define DMM32AT_DACLSB 0x04
56#define DMM32AT_DACSTAT 0x04
57#define DMM32AT_DACMSB 0x05
58
59#define DMM32AT_FIFOCNTRL 0x07
60#define DMM32AT_FIFOSTAT 0x07
61
62#define DMM32AT_CNTRL 0x08
63#define DMM32AT_AISTAT 0x08
64
65#define DMM32AT_INTCLOCK 0x09
66
67#define DMM32AT_CNTRDIO 0x0a
68
69#define DMM32AT_AICONF 0x0b
70#define DMM32AT_AIRBACK 0x0b
71
72#define DMM32AT_CLK1 0x0d
73#define DMM32AT_CLK2 0x0e
74#define DMM32AT_CLKCT 0x0f
75
76#define DMM32AT_DIOA 0x0c
77#define DMM32AT_DIOB 0x0d
78#define DMM32AT_DIOC 0x0e
79#define DMM32AT_DIOCONF 0x0f
80
3c501880
PP		 81/* Board register values. */
82
83/* DMM32AT_DACSTAT 0x04 */
84#define DMM32AT_DACBUSY 0x80
85
86/* DMM32AT_FIFOCNTRL 0x07 */
87#define DMM32AT_FIFORESET 0x02
88#define DMM32AT_SCANENABLE 0x04
89
90/* DMM32AT_CNTRL 0x08 */
91#define DMM32AT_RESET 0x20
92#define DMM32AT_INTRESET 0x08
93#define DMM32AT_CLKACC 0x00
94#define DMM32AT_DIOACC 0x01
95
96/* DMM32AT_AISTAT 0x08 */
97#define DMM32AT_STATUS 0x80
98
99/* DMM32AT_INTCLOCK 0x09 */
100#define DMM32AT_ADINT 0x80
101#define DMM32AT_CLKSEL 0x03
102
103/* DMM32AT_CNTRDIO 0x0a */
104#define DMM32AT_FREQ12 0x80
105
106/* DMM32AT_AICONF 0x0b */
107#define DMM32AT_RANGE_U10 0x0c
108#define DMM32AT_RANGE_U5 0x0d
109#define DMM32AT_RANGE_B10 0x08
110#define DMM32AT_RANGE_B5 0x00
111#define DMM32AT_SCINT_20 0x00
112#define DMM32AT_SCINT_15 0x10
113#define DMM32AT_SCINT_10 0x20
114#define DMM32AT_SCINT_5 0x30
115
116/* DMM32AT_CLKCT 0x0f */
117#define DMM32AT_CLKCT1 0x56 /* mode3 counter 1 - write low byte only */
118#define DMM32AT_CLKCT2 0xb6 /* mode3 counter 2 - write high and low byte */
119
120/* DMM32AT_DIOCONF 0x0f */
121#define DMM32AT_DIENABLE 0x80
122#define DMM32AT_DIRA 0x10
123#define DMM32AT_DIRB 0x02
124#define DMM32AT_DIRCL 0x01
125#define DMM32AT_DIRCH 0x08
126
127/* board AI ranges in comedi structure */
9ced1de6 128static const struct comedi_lrange dmm32at_airanges = {
3c501880
PP		 129 4,
130 {
0a85b6f0
MT		 131 UNI_RANGE(10),
132 UNI_RANGE(5),
133 BIP_RANGE(10),
134 BIP_RANGE(5),
135 }
3c501880
PP		 136};
137
138/* register values for above ranges */
139static const unsigned char dmm32at_rangebits[] = {
140 DMM32AT_RANGE_U10,
141 DMM32AT_RANGE_U5,
142 DMM32AT_RANGE_B10,
143 DMM32AT_RANGE_B5,
144};
145
146/* only one of these ranges is valid, as set by a jumper on the
147 * board. The application should only use the range set by the jumper
148 */
9ced1de6 149static const struct comedi_lrange dmm32at_aoranges = {
3c501880
PP		 150 4,
151 {
0a85b6f0
MT		 152 UNI_RANGE(10),
153 UNI_RANGE(5),
154 BIP_RANGE(10),
155 BIP_RANGE(5),
156 }
3c501880
PP		 157};
158
38baea3a 159struct dmm32at_board {
3c501880 160 const char *name;
38baea3a 161};
3c501880 162
3c501880
PP		 163/* this structure is for data unique to this hardware driver. If
164 * several hardware drivers keep similar information in this structure,
71b5f4f1 165 * feel free to suggest moving the variable to the struct comedi_device struct.
3c501880 166 */
39d31e09 167struct dmm32at_private {
3c501880
PP		 168
169 int data;
170 int ai_inuse;
171 unsigned int ai_scans_left;
172
173 /* Used for AO readback */
790c5541 174 unsigned int ao_readback[4];
3c501880
PP		 175 unsigned char dio_config;
176
39d31e09 177};
3c501880
PP		 178
179/*
180 * most drivers define the following macro to make it easy to
181 * access the private structure.
182 */
39d31e09 183#define devpriv ((struct dmm32at_private *)dev->private)
3c501880 184
3c501880
PP		 185/*
186 * "instructions" read/write data in "one-shot" or "software-triggered"
187 * mode.
188 */
189
0a85b6f0
MT		 190static int dmm32at_ai_rinsn(struct comedi_device *dev,
191 struct comedi_subdevice *s,
192 struct comedi_insn *insn, unsigned int *data)
3c501880
PP		 193{
194 int n, i;
195 unsigned int d;
196 unsigned char status;
197 unsigned short msb, lsb;
198 unsigned char chan;
199 int range;
200
201 /* get the channel and range number */
202
203 chan = CR_CHAN(insn->chanspec) & (s->n_chan - 1);
204 range = CR_RANGE(insn->chanspec);
205
2696fb57 206 /* printk("channel=0x%02x, range=%d\n",chan,range); */
3c501880
PP		 207
208 /* zero scan and fifo control and reset fifo */
29f747c2 209 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL);
3c501880
PP		 210
211 /* write the ai channel range regs */
29f747c2
HS		 212 outb(chan, dev->iobase + DMM32AT_AILOW);
213 outb(chan, dev->iobase + DMM32AT_AIHIGH);
3c501880 214 /* set the range bits */
29f747c2 215 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF);
3c501880
PP		 216
217 /* wait for circuit to settle */
218 for (i = 0; i < 40000; i++) {
99953ea1 219 status = inb(dev->iobase + DMM32AT_AIRBACK);
3c501880
PP		 220 if ((status & DMM32AT_STATUS) == 0)
221 break;
222 }
223 if (i == 40000) {
27bf0bc9 224 printk(KERN_WARNING "dmm32at: timeout\n");
3c501880
PP		 225 return -ETIMEDOUT;
226 }
227
228 /* convert n samples */
229 for (n = 0; n < insn->n; n++) {
230 /* trigger conversion */
29f747c2 231 outb(0xff, dev->iobase + DMM32AT_CONV);
3c501880
PP		 232 /* wait for conversion to end */
233 for (i = 0; i < 40000; i++) {
99953ea1 234 status = inb(dev->iobase + DMM32AT_AISTAT);
3c501880
PP		 235 if ((status & DMM32AT_STATUS) == 0)
236 break;
237 }
238 if (i == 40000) {
27bf0bc9 239 printk(KERN_WARNING "dmm32at: timeout\n");
3c501880
PP		 240 return -ETIMEDOUT;
241 }
242
243 /* read data */
99953ea1
HS		 244 lsb = inb(dev->iobase + DMM32AT_AILSB);
245 msb = inb(dev->iobase + DMM32AT_AIMSB);
3c501880
PP		 246
247 /* invert sign bit to make range unsigned, this is an
25985edc 248 idiosyncrasy of the diamond board, it return
3c501880
PP		 249 conversions as a signed value, i.e. -32768 to
250 32767, flipping the bit and interpreting it as
251 signed gives you a range of 0 to 65535 which is
252 used by comedi */
253 d = ((msb ^ 0x0080) << 8) + lsb;
254
255 data[n] = d;
256 }
257
258 /* return the number of samples read/written */
259 return n;
260}
261
47ae6a72
HS		 262/* This function doesn't require a particular form, this is just
263 * what happens to be used in some of the drivers. It should
264 * convert ns nanoseconds to a counter value suitable for programming
265 * the device. Also, it should adjust ns so that it cooresponds to
266 * the actual time that the device will use. */
267static int dmm32at_ns_to_timer(unsigned int *ns, int round)
268{
269 /* trivial timer */
270 /* if your timing is done through two cascaded timers, the
271 * i8253_cascade_ns_to_timer() function in 8253.h can be
272 * very helpful. There are also i8254_load() and i8254_mm_load()
273 * which can be used to load values into the ubiquitous 8254 counters
274 */
275
276 return *ns;
277}
278
0a85b6f0
MT		 279static int dmm32at_ai_cmdtest(struct comedi_device *dev,
280 struct comedi_subdevice *s,
281 struct comedi_cmd *cmd)
3c501880
PP		 282{
283 int err = 0;
284 int tmp;
285 int start_chan, gain, i;
286
2696fb57 287 /* printk("dmmat32 in command test\n"); */
3c501880
PP		 288
289 /* cmdtest tests a particular command to see if it is valid.
290 * Using the cmdtest ioctl, a user can create a valid cmd
291 * and then have it executes by the cmd ioctl.
292 *
293 * cmdtest returns 1,2,3,4 or 0, depending on which tests
294 * the command passes. */
295
296 /* step 1: make sure trigger sources are trivially valid */
297
298 tmp = cmd->start_src;
299 cmd->start_src &= TRIG_NOW;
300 if (!cmd->start_src || tmp != cmd->start_src)
301 err++;
302
303 tmp = cmd->scan_begin_src;
304 cmd->scan_begin_src &= TRIG_TIMER /*| TRIG_EXT */ ;
305 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
306 err++;
307
308 tmp = cmd->convert_src;
309 cmd->convert_src &= TRIG_TIMER /*| TRIG_EXT */ ;
310 if (!cmd->convert_src || tmp != cmd->convert_src)
311 err++;
312
313 tmp = cmd->scan_end_src;
314 cmd->scan_end_src &= TRIG_COUNT;
315 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
316 err++;
317
318 tmp = cmd->stop_src;
319 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
320 if (!cmd->stop_src || tmp != cmd->stop_src)
321 err++;
322
323 if (err)
324 return 1;
325
27bf0bc9
M		 326 /* step 2: make sure trigger sources are unique and mutually
327 * compatible */
3c501880 328
828684f9 329 /* note that mutual compatibility is not an issue here */
3c501880 330 if (cmd->scan_begin_src != TRIG_TIMER &&
0a85b6f0 331 cmd->scan_begin_src != TRIG_EXT)
3c501880
PP		 332 err++;
333 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
334 err++;
335 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
336 err++;
337
338 if (err)
339 return 2;
340
341 /* step 3: make sure arguments are trivially compatible */
342
343 if (cmd->start_arg != 0) {
344 cmd->start_arg = 0;
345 err++;
346 }
347#define MAX_SCAN_SPEED 1000000 /* in nanoseconds */
348#define MIN_SCAN_SPEED 1000000000 /* in nanoseconds */
349
350 if (cmd->scan_begin_src == TRIG_TIMER) {
351 if (cmd->scan_begin_arg < MAX_SCAN_SPEED) {
352 cmd->scan_begin_arg = MAX_SCAN_SPEED;
353 err++;
354 }
355 if (cmd->scan_begin_arg > MIN_SCAN_SPEED) {
356 cmd->scan_begin_arg = MIN_SCAN_SPEED;
357 err++;
358 }
359 } else {
360 /* external trigger */
361 /* should be level/edge, hi/lo specification here */
362 /* should specify multiple external triggers */
363 if (cmd->scan_begin_arg > 9) {
364 cmd->scan_begin_arg = 9;
365 err++;
366 }
367 }
368 if (cmd->convert_src == TRIG_TIMER) {
369 if (cmd->convert_arg >= 17500)
370 cmd->convert_arg = 20000;
371 else if (cmd->convert_arg >= 12500)
372 cmd->convert_arg = 15000;
373 else if (cmd->convert_arg >= 7500)
374 cmd->convert_arg = 10000;
375 else
376 cmd->convert_arg = 5000;
377
378 } else {
379 /* external trigger */
380 /* see above */
381 if (cmd->convert_arg > 9) {
382 cmd->convert_arg = 9;
383 err++;
384 }
385 }
386
387 if (cmd->scan_end_arg != cmd->chanlist_len) {
388 cmd->scan_end_arg = cmd->chanlist_len;
389 err++;
390 }
391 if (cmd->stop_src == TRIG_COUNT) {
392 if (cmd->stop_arg > 0xfffffff0) {
393 cmd->stop_arg = 0xfffffff0;
394 err++;
395 }
396 if (cmd->stop_arg == 0) {
397 cmd->stop_arg = 1;
398 err++;
399 }
400 } else {
401 /* TRIG_NONE */
402 if (cmd->stop_arg != 0) {
403 cmd->stop_arg = 0;
404 err++;
405 }
406 }
407
408 if (err)
409 return 3;
410
411 /* step 4: fix up any arguments */
412
413 if (cmd->scan_begin_src == TRIG_TIMER) {
414 tmp = cmd->scan_begin_arg;
415 dmm32at_ns_to_timer(&cmd->scan_begin_arg,
0a85b6f0 416 cmd->flags & TRIG_ROUND_MASK);
3c501880
PP		 417 if (tmp != cmd->scan_begin_arg)
418 err++;
419 }
420 if (cmd->convert_src == TRIG_TIMER) {
421 tmp = cmd->convert_arg;
422 dmm32at_ns_to_timer(&cmd->convert_arg,
0a85b6f0 423 cmd->flags & TRIG_ROUND_MASK);
3c501880
PP		 424 if (tmp != cmd->convert_arg)
425 err++;
426 if (cmd->scan_begin_src == TRIG_TIMER &&
0a85b6f0
MT		 427 cmd->scan_begin_arg <
428 cmd->convert_arg * cmd->scan_end_arg) {
3c501880 429 cmd->scan_begin_arg =
0a85b6f0 430 cmd->convert_arg * cmd->scan_end_arg;
3c501880
PP		 431 err++;
432 }
433 }
434
435 if (err)
436 return 4;
437
438 /* step 5 check the channel list, the channel list for this
439 board must be consecutive and gains must be the same */
440
441 if (cmd->chanlist) {
442 gain = CR_RANGE(cmd->chanlist[0]);
443 start_chan = CR_CHAN(cmd->chanlist[0]);
444 for (i = 1; i < cmd->chanlist_len; i++) {
445 if (CR_CHAN(cmd->chanlist[i]) !=
0a85b6f0 446 (start_chan + i) % s->n_chan) {
3c501880 447 comedi_error(dev,
0a85b6f0 448 "entries in chanlist must be consecutive channels, counting upwards\n");
3c501880
PP		 449 err++;
450 }
451 if (CR_RANGE(cmd->chanlist[i]) != gain) {
452 comedi_error(dev,
0a85b6f0 453 "entries in chanlist must all have the same gain\n");
3c501880
PP		 454 err++;
455 }
456 }
457 }
458
459 if (err)
460 return 5;
461
462 return 0;
463}
464
47ae6a72
HS		 465static void dmm32at_setaitimer(struct comedi_device *dev, unsigned int nansec)
466{
467 unsigned char lo1, lo2, hi2;
468 unsigned short both2;
469
470 /* based on 10mhz clock */
471 lo1 = 200;
472 both2 = nansec / 20000;
473 hi2 = (both2 & 0xff00) >> 8;
474 lo2 = both2 & 0x00ff;
475
476 /* set the counter frequency to 10mhz */
29f747c2 477 outb(0, dev->iobase + DMM32AT_CNTRDIO);
47ae6a72
HS		 478
479 /* get access to the clock regs */
29f747c2 480 outb(DMM32AT_CLKACC, dev->iobase + DMM32AT_CNTRL);
47ae6a72
HS		 481
482 /* write the counter 1 control word and low byte to counter */
29f747c2
HS		 483 outb(DMM32AT_CLKCT1, dev->iobase + DMM32AT_CLKCT);
484 outb(lo1, dev->iobase + DMM32AT_CLK1);
47ae6a72
HS		 485
486 /* write the counter 2 control word and low byte then to counter */
29f747c2
HS		 487 outb(DMM32AT_CLKCT2, dev->iobase + DMM32AT_CLKCT);
488 outb(lo2, dev->iobase + DMM32AT_CLK2);
489 outb(hi2, dev->iobase + DMM32AT_CLK2);
47ae6a72
HS		 490
491 /* enable the ai conversion interrupt and the clock to start scans */
29f747c2 492 outb(DMM32AT_ADINT | DMM32AT_CLKSEL, dev->iobase + DMM32AT_INTCLOCK);
47ae6a72
HS		 493}
494
da91b269 495static int dmm32at_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
3c501880 496{
ea6d0d4c 497 struct comedi_cmd *cmd = &s->async->cmd;
3c501880
PP		 498 int i, range;
499 unsigned char chanlo, chanhi, status;
500
501 if (!cmd->chanlist)
502 return -EINVAL;
503
504 /* get the channel list and range */
505 chanlo = CR_CHAN(cmd->chanlist[0]) & (s->n_chan - 1);
506 chanhi = chanlo + cmd->chanlist_len - 1;
507 if (chanhi >= s->n_chan)
508 return -EINVAL;
509 range = CR_RANGE(cmd->chanlist[0]);
510
511 /* reset fifo */
29f747c2 512 outb(DMM32AT_FIFORESET, dev->iobase + DMM32AT_FIFOCNTRL);
3c501880
PP		 513
514 /* set scan enable */
29f747c2 515 outb(DMM32AT_SCANENABLE, dev->iobase + DMM32AT_FIFOCNTRL);
3c501880
PP		 516
517 /* write the ai channel range regs */
29f747c2
HS		 518 outb(chanlo, dev->iobase + DMM32AT_AILOW);
519 outb(chanhi, dev->iobase + DMM32AT_AIHIGH);
3c501880
PP		 520
521 /* set the range bits */
29f747c2 522 outb(dmm32at_rangebits[range], dev->iobase + DMM32AT_AICONF);
3c501880
PP		 523
524 /* reset the interrupt just in case */
29f747c2 525 outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL);
3c501880
PP		 526
527 if (cmd->stop_src == TRIG_COUNT)
528 devpriv->ai_scans_left = cmd->stop_arg;
529 else { /* TRIG_NONE */
27bf0bc9
M		 530 devpriv->ai_scans_left = 0xffffffff; /* indicates TRIG_NONE to
531 * isr */
3c501880
PP		 532 }
533
534 /* wait for circuit to settle */
535 for (i = 0; i < 40000; i++) {
99953ea1 536 status = inb(dev->iobase + DMM32AT_AIRBACK);
3c501880
PP		 537 if ((status & DMM32AT_STATUS) == 0)
538 break;
539 }
540 if (i == 40000) {
27bf0bc9 541 printk(KERN_WARNING "dmm32at: timeout\n");
3c501880
PP		 542 return -ETIMEDOUT;
543 }
544
545 if (devpriv->ai_scans_left > 1) {
546 /* start the clock and enable the interrupts */
547 dmm32at_setaitimer(dev, cmd->scan_begin_arg);
548 } else {
549 /* start the interrups and initiate a single scan */
29f747c2
HS		 550 outb(DMM32AT_ADINT, dev->iobase + DMM32AT_INTCLOCK);
551 outb(0xff, dev->iobase + DMM32AT_CONV);
3c501880
PP		 552 }
553
27bf0bc9 554/* printk("dmmat32 in command\n"); */
3c501880 555
27bf0bc9
M		 556/* for(i=0;i<cmd->chanlist_len;i++) */
557/* comedi_buf_put(s->async,i*100); */
3c501880 558
27bf0bc9
M		 559/* s->async->events |= COMEDI_CB_EOA; */
560/* comedi_event(dev, s); */
3c501880
PP		 561
562 return 0;
563
564}
565
0a85b6f0
MT		 566static int dmm32at_ai_cancel(struct comedi_device *dev,
567 struct comedi_subdevice *s)
3c501880
PP		 568{
569 devpriv->ai_scans_left = 1;
570 return 0;
571}
572
70265d24 573static irqreturn_t dmm32at_isr(int irq, void *d)
3c501880
PP		 574{
575 unsigned char intstat;
576 unsigned int samp;
577 unsigned short msb, lsb;
578 int i;
71b5f4f1 579 struct comedi_device *dev = d;
3c501880
PP		 580
581 if (!dev->attached) {
582 comedi_error(dev, "spurious interrupt");
583 return IRQ_HANDLED;
584 }
585
99953ea1 586 intstat = inb(dev->iobase + DMM32AT_INTCLOCK);
3c501880
PP		 587
588 if (intstat & DMM32AT_ADINT) {
34c43922 589 struct comedi_subdevice *s = dev->read_subdev;
ea6d0d4c 590 struct comedi_cmd *cmd = &s->async->cmd;
3c501880
PP		 591
592 for (i = 0; i < cmd->chanlist_len; i++) {
593 /* read data */
99953ea1
HS		 594 lsb = inb(dev->iobase + DMM32AT_AILSB);
595 msb = inb(dev->iobase + DMM32AT_AIMSB);
3c501880
PP		 596
597 /* invert sign bit to make range unsigned */
598 samp = ((msb ^ 0x0080) << 8) + lsb;
599 comedi_buf_put(s->async, samp);
600 }
601
602 if (devpriv->ai_scans_left != 0xffffffff) { /* TRIG_COUNT */
603 devpriv->ai_scans_left--;
604 if (devpriv->ai_scans_left == 0) {
605 /* disable further interrupts and clocks */
29f747c2 606 outb(0x0, dev->iobase + DMM32AT_INTCLOCK);
3c501880
PP		 607 /* set the buffer to be flushed with an EOF */
608 s->async->events |= COMEDI_CB_EOA;
609 }
610
611 }
612 /* flush the buffer */
613 comedi_event(dev, s);
614 }
615
616 /* reset the interrupt */
29f747c2 617 outb(DMM32AT_INTRESET, dev->iobase + DMM32AT_CNTRL);
3c501880
PP		 618 return IRQ_HANDLED;
619}
620
0a85b6f0
MT		 621static int dmm32at_ao_winsn(struct comedi_device *dev,
622 struct comedi_subdevice *s,
623 struct comedi_insn *insn, unsigned int *data)
3c501880
PP		 624{
625 int i;
626 int chan = CR_CHAN(insn->chanspec);
627 unsigned char hi, lo, status;
628
629 /* Writing a list of values to an AO channel is probably not
630 * very useful, but that's how the interface is defined. */
631 for (i = 0; i < insn->n; i++) {
632
633 devpriv->ao_readback[chan] = data[i];
634
635 /* get the low byte */
636 lo = data[i] & 0x00ff;
637 /* high byte also contains channel number */
638 hi = (data[i] >> 8) + chan * (1 << 6);
2696fb57 639 /* printk("writing 0x%02x 0x%02x\n",hi,lo); */
3c501880 640 /* write the low and high values to the board */
29f747c2
HS		 641 outb(lo, dev->iobase + DMM32AT_DACLSB);
642 outb(hi, dev->iobase + DMM32AT_DACMSB);
3c501880
PP		 643
644 /* wait for circuit to settle */
645 for (i = 0; i < 40000; i++) {
99953ea1 646 status = inb(dev->iobase + DMM32AT_DACSTAT);
3c501880
PP		 647 if ((status & DMM32AT_DACBUSY) == 0)
648 break;
649 }
650 if (i == 40000) {
27bf0bc9 651 printk(KERN_WARNING "dmm32at: timeout\n");
3c501880
PP		 652 return -ETIMEDOUT;
653 }
654 /* dummy read to update trigger the output */
99953ea1 655 status = inb(dev->iobase + DMM32AT_DACMSB);
3c501880
PP		 656
657 }
658
659 /* return the number of samples read/written */
660 return i;
661}
662
663/* AO subdevices should have a read insn as well as a write insn.
664 * Usually this means copying a value stored in devpriv. */
0a85b6f0
MT		 665static int dmm32at_ao_rinsn(struct comedi_device *dev,
666 struct comedi_subdevice *s,
667 struct comedi_insn *insn, unsigned int *data)
3c501880
PP		 668{
669 int i;
670 int chan = CR_CHAN(insn->chanspec);
671
672 for (i = 0; i < insn->n; i++)
673 data[i] = devpriv->ao_readback[chan];
674
675 return i;
676}
677
678/* DIO devices are slightly special. Although it is possible to
679 * implement the insn_read/insn_write interface, it is much more
680 * useful to applications if you implement the insn_bits interface.
681 * This allows packed reading/writing of the DIO channels. The
682 * comedi core can convert between insn_bits and insn_read/write */
0a85b6f0
MT		 683static int dmm32at_dio_insn_bits(struct comedi_device *dev,
684 struct comedi_subdevice *s,
685 struct comedi_insn *insn, unsigned int *data)
3c501880
PP		 686{
687 unsigned char diobits;
688
3c501880
PP		 689 /* The insn data is a mask in data[0] and the new data
690 * in data[1], each channel cooresponding to a bit. */
691 if (data[0]) {
692 s->state &= ~data[0];
693 s->state |= data[0] & data[1];
694 /* Write out the new digital output lines */
2696fb57 695 /* outw(s->state,dev->iobase + DMM32AT_DIO); */
3c501880
PP		 696 }
697
698 /* get access to the DIO regs */
29f747c2 699 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
3c501880
PP		 700
701 /* if either part of dio is set for output */
702 if (((devpriv->dio_config & DMM32AT_DIRCL) == 0) ||
0a85b6f0 703 ((devpriv->dio_config & DMM32AT_DIRCH) == 0)) {
3c501880 704 diobits = (s->state & 0x00ff0000) >> 16;
29f747c2 705 outb(diobits, dev->iobase + DMM32AT_DIOC);
3c501880
PP		 706 }
707 if ((devpriv->dio_config & DMM32AT_DIRB) == 0) {
708 diobits = (s->state & 0x0000ff00) >> 8;
29f747c2 709 outb(diobits, dev->iobase + DMM32AT_DIOB);
3c501880
PP		 710 }
711 if ((devpriv->dio_config & DMM32AT_DIRA) == 0) {
712 diobits = (s->state & 0x000000ff);
29f747c2 713 outb(diobits, dev->iobase + DMM32AT_DIOA);
3c501880
PP		 714 }
715
716 /* now read the state back in */
99953ea1 717 s->state = inb(dev->iobase + DMM32AT_DIOC);
3c501880 718 s->state <<= 8;
99953ea1 719 s->state |= inb(dev->iobase + DMM32AT_DIOB);
3c501880 720 s->state <<= 8;
99953ea1 721 s->state |= inb(dev->iobase + DMM32AT_DIOA);
3c501880
PP		 722 data[1] = s->state;
723
724 /* on return, data[1] contains the value of the digital
725 * input and output lines. */
2696fb57 726 /* data[1]=inw(dev->iobase + DMM32AT_DIO); */
3c501880
PP		 727 /* or we could just return the software copy of the output values if
728 * it was a purely digital output subdevice */
2696fb57 729 /* data[1]=s->state; */
3c501880 730
a2714e3e 731 return insn->n;
3c501880
PP		 732}
733
0a85b6f0
MT		 734static int dmm32at_dio_insn_config(struct comedi_device *dev,
735 struct comedi_subdevice *s,
736 struct comedi_insn *insn, unsigned int *data)
3c501880
PP		 737{
738 unsigned char chanbit;
739 int chan = CR_CHAN(insn->chanspec);
740
741 if (insn->n != 1)
742 return -EINVAL;
743
744 if (chan < 8)
745 chanbit = DMM32AT_DIRA;
746 else if (chan < 16)
747 chanbit = DMM32AT_DIRB;
748 else if (chan < 20)
749 chanbit = DMM32AT_DIRCL;
750 else
751 chanbit = DMM32AT_DIRCH;
752
753 /* The input or output configuration of each digital line is
754 * configured by a special insn_config instruction. chanspec
755 * contains the channel to be changed, and data[0] contains the
756 * value COMEDI_INPUT or COMEDI_OUTPUT. */
757
758 /* if output clear the bit, otherwise set it */
20962c10 759 if (data[0] == COMEDI_OUTPUT)
3c501880 760 devpriv->dio_config &= ~chanbit;
20962c10 761 else
3c501880 762 devpriv->dio_config |= chanbit;
3c501880 763 /* get access to the DIO regs */
29f747c2 764 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
3c501880 765 /* set the DIO's to the new configuration setting */
29f747c2 766 outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF);
3c501880
PP		 767
768 return 1;
769}
770
4f793db3
HS		 771static int dmm32at_attach(struct comedi_device *dev,
772 struct comedi_devconfig *it)
773{
774 const struct dmm32at_board *board = comedi_board(dev);
775 int ret;
776 struct comedi_subdevice *s;
777 unsigned char aihi, ailo, fifostat, aistat, intstat, airback;
778 unsigned long iobase;
779 unsigned int irq;
780
781 iobase = it->options[0];
782 irq = it->options[1];
783
784 printk(KERN_INFO "comedi%d: dmm32at: attaching\n", dev->minor);
785 printk(KERN_DEBUG "dmm32at: probing at address 0x%04lx, irq %u\n",
786 iobase, irq);
787
788 /* register address space */
789 if (!request_region(iobase, DMM32AT_MEMSIZE, board->name)) {
790 printk(KERN_ERR "comedi%d: dmm32at: I/O port conflict\n",
791 dev->minor);
792 return -EIO;
793 }
794 dev->iobase = iobase;
795
796 /* the following just makes sure the board is there and gets
797 it to a known state */
798
799 /* reset the board */
29f747c2 800 outb(DMM32AT_RESET, dev->iobase + DMM32AT_CNTRL);
4f793db3
HS		 801
802 /* allow a millisecond to reset */
803 udelay(1000);
804
805 /* zero scan and fifo control */
29f747c2 806 outb(0x0, dev->iobase + DMM32AT_FIFOCNTRL);
4f793db3
HS		 807
808 /* zero interrupt and clock control */
29f747c2 809 outb(0x0, dev->iobase + DMM32AT_INTCLOCK);
4f793db3
HS		 810
811 /* write a test channel range, the high 3 bits should drop */
29f747c2
HS		 812 outb(0x80, dev->iobase + DMM32AT_AILOW);
813 outb(0xff, dev->iobase + DMM32AT_AIHIGH);
4f793db3
HS		 814
815 /* set the range at 10v unipolar */
29f747c2 816 outb(DMM32AT_RANGE_U10, dev->iobase + DMM32AT_AICONF);
4f793db3
HS		 817
818 /* should take 10 us to settle, here's a hundred */
819 udelay(100);
820
821 /* read back the values */
99953ea1
HS		 822 ailo = inb(dev->iobase + DMM32AT_AILOW);
823 aihi = inb(dev->iobase + DMM32AT_AIHIGH);
824 fifostat = inb(dev->iobase + DMM32AT_FIFOSTAT);
825 aistat = inb(dev->iobase + DMM32AT_AISTAT);
826 intstat = inb(dev->iobase + DMM32AT_INTCLOCK);
827 airback = inb(dev->iobase + DMM32AT_AIRBACK);
4f793db3
HS		 828
829 printk(KERN_DEBUG "dmm32at: lo=0x%02x hi=0x%02x fifostat=0x%02x\n",
830 ailo, aihi, fifostat);
831 printk(KERN_DEBUG
832 "dmm32at: aistat=0x%02x intstat=0x%02x airback=0x%02x\n",
833 aistat, intstat, airback);
834
835 if ((ailo != 0x00) || (aihi != 0x1f) || (fifostat != 0x80) ||
836 (aistat != 0x60 || (intstat != 0x00) || airback != 0x0c)) {
837 printk(KERN_ERR "dmmat32: board detection failed\n");
838 return -EIO;
839 }
840
841 /* board is there, register interrupt */
842 if (irq) {
843 ret = request_irq(irq, dmm32at_isr, 0, board->name, dev);
844 if (ret < 0) {
845 printk(KERN_ERR "dmm32at: irq conflict\n");
846 return ret;
847 }
848 dev->irq = irq;
849 }
850
851 dev->board_name = board->name;
852
853/*
854 * Allocate the private structure area. alloc_private() is a
855 * convenient macro defined in comedidev.h.
856 */
857 if (alloc_private(dev, sizeof(struct dmm32at_private)) < 0)
858 return -ENOMEM;
859
860 ret = comedi_alloc_subdevices(dev, 3);
861 if (ret)
862 return ret;
863
864 s = dev->subdevices + 0;
865 dev->read_subdev = s;
866 /* analog input subdevice */
867 s->type = COMEDI_SUBD_AI;
868 /* we support single-ended (ground) and differential */
869 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_DIFF | SDF_CMD_READ;
27921828
HS		 870 s->n_chan = 32;
871 s->maxdata = 0xffff;
872 s->range_table = &dmm32at_airanges;
4f793db3
HS		 873 s->len_chanlist = 32; /* This is the maximum chanlist length that
874 the board can handle */
875 s->insn_read = dmm32at_ai_rinsn;
876 s->do_cmd = dmm32at_ai_cmd;
877 s->do_cmdtest = dmm32at_ai_cmdtest;
878 s->cancel = dmm32at_ai_cancel;
879
880 s = dev->subdevices + 1;
881 /* analog output subdevice */
882 s->type = COMEDI_SUBD_AO;
883 s->subdev_flags = SDF_WRITABLE;
27921828
HS		 884 s->n_chan = 4;
885 s->maxdata = 0x0fff;
886 s->range_table = &dmm32at_aoranges;
4f793db3
HS		 887 s->insn_write = dmm32at_ao_winsn;
888 s->insn_read = dmm32at_ao_rinsn;
889
890 s = dev->subdevices + 2;
891 /* digital i/o subdevice */
27921828
HS		 892
893 /* get access to the DIO regs */
894 outb(DMM32AT_DIOACC, dev->iobase + DMM32AT_CNTRL);
895 /* set the DIO's to the defualt input setting */
896 devpriv->dio_config = DMM32AT_DIRA | DMM32AT_DIRB |
897 DMM32AT_DIRCL | DMM32AT_DIRCH | DMM32AT_DIENABLE;
898 outb(devpriv->dio_config, dev->iobase + DMM32AT_DIOCONF);
899
900 /* set up the subdevice */
901 s->type = COMEDI_SUBD_DIO;
902 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
903 s->n_chan = 24;
904 s->maxdata = 1;
905 s->state = 0;
906 s->range_table = &range_digital;
907 s->insn_bits = dmm32at_dio_insn_bits;
908 s->insn_config = dmm32at_dio_insn_config;
4f793db3
HS		 909
910 /* success */
911 printk(KERN_INFO "comedi%d: dmm32at: attached\n", dev->minor);
912
913 return 1;
914
915}
916
917static void dmm32at_detach(struct comedi_device *dev)
918{
919 if (dev->irq)
920 free_irq(dev->irq, dev);
921 if (dev->iobase)
922 release_region(dev->iobase, DMM32AT_MEMSIZE);
923}
924
925static const struct dmm32at_board dmm32at_boards[] = {
926 {
927 .name = "dmm32at",
4f793db3
HS		 928 },
929};
930
17f49dd4
HS		 931static struct comedi_driver dmm32at_driver = {
932 .driver_name = "dmm32at",
933 .module = THIS_MODULE,
934 .attach = dmm32at_attach,
935 .detach = dmm32at_detach,
936 .board_name = &dmm32at_boards[0].name,
937 .offset = sizeof(struct dmm32at_board),
938 .num_names = ARRAY_SIZE(dmm32at_boards),
939};
940module_comedi_driver(dmm32at_driver);
90f703d3
AT		 941
942MODULE_AUTHOR("Comedi http://www.comedi.org");
943MODULE_DESCRIPTION("Comedi low-level driver");
944MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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