Commit | Line | Data |
---|---|---|
e55c95a3 GG |
1 | /* |
2 | comedi/drivers/me4000.c | |
3 | Source code for the Meilhaus ME-4000 board family. | |
4 | ||
5 | COMEDI - Linux Control and Measurement Device Interface | |
6 | Copyright (C) 2000 David A. Schleef <ds@schleef.org> | |
7 | ||
8 | This program is free software; you can redistribute it and/or modify | |
9 | it under the terms of the GNU General Public License as published by | |
10 | the Free Software Foundation; either version 2 of the License, or | |
11 | (at your option) any later version. | |
12 | ||
13 | This program is distributed in the hope that it will be useful, | |
14 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | GNU General Public License for more details. | |
e55c95a3 GG |
17 | */ |
18 | /* | |
19 | Driver: me4000 | |
20 | Description: Meilhaus ME-4000 series boards | |
21 | Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is | |
22 | Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>) | |
23 | Updated: Mon, 18 Mar 2002 15:34:01 -0800 | |
24 | Status: broken (no support for loading firmware) | |
25 | ||
26 | Supports: | |
27 | ||
28 | - Analog Input | |
29 | - Analog Output | |
30 | - Digital I/O | |
31 | - Counter | |
32 | ||
5f8f8d43 | 33 | Configuration Options: not applicable, uses PCI auto config |
e55c95a3 GG |
34 | |
35 | The firmware required by these boards is available in the | |
36 | comedi_nonfree_firmware tarball available from | |
37 | http://www.comedi.org. However, the driver's support for | |
38 | loading the firmware through comedi_config is currently | |
39 | broken. | |
40 | ||
41 | */ | |
42 | ||
ce157f80 | 43 | #include <linux/module.h> |
e55c95a3 | 44 | #include <linux/delay.h> |
33782dd5 | 45 | #include <linux/interrupt.h> |
e55c95a3 | 46 | |
f2e8e285 | 47 | #include "../comedi_pci.h" |
33782dd5 | 48 | |
d92d39d9 | 49 | #include "comedi_8254.h" |
58af6b92 | 50 | #include "plx9052.h" |
81dd1811 | 51 | |
ac584af5 | 52 | #define ME4000_FIRMWARE "me4000_firmware.bin" |
e55c95a3 | 53 | |
81dd1811 HS |
54 | /* |
55 | * ME4000 Register map and bit defines | |
56 | */ | |
57 | #define ME4000_AO_CHAN(x) ((x) * 0x18) | |
58 | ||
59 | #define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x)) | |
7e92a5eb HS |
60 | #define ME4000_AO_CTRL_MODE_0 BIT(0) |
61 | #define ME4000_AO_CTRL_MODE_1 BIT(1) | |
62 | #define ME4000_AO_CTRL_STOP BIT(2) | |
63 | #define ME4000_AO_CTRL_ENABLE_FIFO BIT(3) | |
64 | #define ME4000_AO_CTRL_ENABLE_EX_TRIG BIT(4) | |
65 | #define ME4000_AO_CTRL_EX_TRIG_EDGE BIT(5) | |
66 | #define ME4000_AO_CTRL_IMMEDIATE_STOP BIT(7) | |
67 | #define ME4000_AO_CTRL_ENABLE_DO BIT(8) | |
68 | #define ME4000_AO_CTRL_ENABLE_IRQ BIT(9) | |
69 | #define ME4000_AO_CTRL_RESET_IRQ BIT(10) | |
81dd1811 | 70 | #define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x)) |
4831748e HS |
71 | #define ME4000_AO_STATUS_FSM BIT(0) |
72 | #define ME4000_AO_STATUS_FF BIT(1) | |
73 | #define ME4000_AO_STATUS_HF BIT(2) | |
74 | #define ME4000_AO_STATUS_EF BIT(3) | |
81dd1811 HS |
75 | #define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x)) |
76 | #define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x)) | |
77 | #define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x)) | |
78 | #define ME4000_AI_CTRL_REG 0x74 | |
79 | #define ME4000_AI_STATUS_REG 0x74 | |
da772ad9 HS |
80 | #define ME4000_AI_CTRL_MODE_0 BIT(0) |
81 | #define ME4000_AI_CTRL_MODE_1 BIT(1) | |
82 | #define ME4000_AI_CTRL_MODE_2 BIT(2) | |
83 | #define ME4000_AI_CTRL_SAMPLE_HOLD BIT(3) | |
84 | #define ME4000_AI_CTRL_IMMEDIATE_STOP BIT(4) | |
85 | #define ME4000_AI_CTRL_STOP BIT(5) | |
86 | #define ME4000_AI_CTRL_CHANNEL_FIFO BIT(6) | |
87 | #define ME4000_AI_CTRL_DATA_FIFO BIT(7) | |
88 | #define ME4000_AI_CTRL_FULLSCALE BIT(8) | |
89 | #define ME4000_AI_CTRL_OFFSET BIT(9) | |
90 | #define ME4000_AI_CTRL_EX_TRIG_ANALOG BIT(10) | |
91 | #define ME4000_AI_CTRL_EX_TRIG BIT(11) | |
92 | #define ME4000_AI_CTRL_EX_TRIG_FALLING BIT(12) | |
93 | #define ME4000_AI_CTRL_EX_IRQ BIT(13) | |
94 | #define ME4000_AI_CTRL_EX_IRQ_RESET BIT(14) | |
95 | #define ME4000_AI_CTRL_LE_IRQ BIT(15) | |
96 | #define ME4000_AI_CTRL_LE_IRQ_RESET BIT(16) | |
97 | #define ME4000_AI_CTRL_HF_IRQ BIT(17) | |
98 | #define ME4000_AI_CTRL_HF_IRQ_RESET BIT(18) | |
99 | #define ME4000_AI_CTRL_SC_IRQ BIT(19) | |
100 | #define ME4000_AI_CTRL_SC_IRQ_RESET BIT(20) | |
101 | #define ME4000_AI_CTRL_SC_RELOAD BIT(21) | |
a9b586a5 HS |
102 | #define ME4000_AI_STATUS_EF_CHANNEL BIT(22) |
103 | #define ME4000_AI_STATUS_HF_CHANNEL BIT(23) | |
104 | #define ME4000_AI_STATUS_FF_CHANNEL BIT(24) | |
105 | #define ME4000_AI_STATUS_EF_DATA BIT(25) | |
106 | #define ME4000_AI_STATUS_HF_DATA BIT(26) | |
107 | #define ME4000_AI_STATUS_FF_DATA BIT(27) | |
108 | #define ME4000_AI_STATUS_LE BIT(28) | |
109 | #define ME4000_AI_STATUS_FSM BIT(29) | |
da772ad9 | 110 | #define ME4000_AI_CTRL_EX_TRIG_BOTH BIT(31) |
81dd1811 | 111 | #define ME4000_AI_CHANNEL_LIST_REG 0x78 |
a0861f87 | 112 | #define ME4000_AI_LIST_INPUT_DIFFERENTIAL BIT(5) |
245bd462 | 113 | #define ME4000_AI_LIST_RANGE(x) ((3 - ((x) & 3)) << 6) |
a0861f87 | 114 | #define ME4000_AI_LIST_LAST_ENTRY BIT(8) |
81dd1811 HS |
115 | #define ME4000_AI_DATA_REG 0x7c |
116 | #define ME4000_AI_CHAN_TIMER_REG 0x80 | |
117 | #define ME4000_AI_CHAN_PRE_TIMER_REG 0x84 | |
118 | #define ME4000_AI_SCAN_TIMER_LOW_REG 0x88 | |
119 | #define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c | |
120 | #define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90 | |
121 | #define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94 | |
122 | #define ME4000_AI_START_REG 0x98 | |
123 | #define ME4000_IRQ_STATUS_REG 0x9c | |
2ec0019a HS |
124 | #define ME4000_IRQ_STATUS_EX BIT(0) |
125 | #define ME4000_IRQ_STATUS_LE BIT(1) | |
126 | #define ME4000_IRQ_STATUS_AI_HF BIT(2) | |
127 | #define ME4000_IRQ_STATUS_AO_0_HF BIT(3) | |
128 | #define ME4000_IRQ_STATUS_AO_1_HF BIT(4) | |
129 | #define ME4000_IRQ_STATUS_AO_2_HF BIT(5) | |
130 | #define ME4000_IRQ_STATUS_AO_3_HF BIT(6) | |
131 | #define ME4000_IRQ_STATUS_SC BIT(7) | |
81dd1811 HS |
132 | #define ME4000_DIO_PORT_0_REG 0xa0 |
133 | #define ME4000_DIO_PORT_1_REG 0xa4 | |
134 | #define ME4000_DIO_PORT_2_REG 0xa8 | |
135 | #define ME4000_DIO_PORT_3_REG 0xac | |
136 | #define ME4000_DIO_DIR_REG 0xb0 | |
137 | #define ME4000_AO_LOADSETREG_XX 0xb4 | |
138 | #define ME4000_DIO_CTRL_REG 0xb8 | |
55fb972e HS |
139 | #define ME4000_DIO_CTRL_MODE_0 BIT(0) |
140 | #define ME4000_DIO_CTRL_MODE_1 BIT(1) | |
141 | #define ME4000_DIO_CTRL_MODE_2 BIT(2) | |
142 | #define ME4000_DIO_CTRL_MODE_3 BIT(3) | |
143 | #define ME4000_DIO_CTRL_MODE_4 BIT(4) | |
144 | #define ME4000_DIO_CTRL_MODE_5 BIT(5) | |
145 | #define ME4000_DIO_CTRL_MODE_6 BIT(6) | |
146 | #define ME4000_DIO_CTRL_MODE_7 BIT(7) | |
147 | #define ME4000_DIO_CTRL_FUNCTION_0 BIT(8) | |
148 | #define ME4000_DIO_CTRL_FUNCTION_1 BIT(9) | |
149 | #define ME4000_DIO_CTRL_FIFO_HIGH_0 BIT(10) | |
150 | #define ME4000_DIO_CTRL_FIFO_HIGH_1 BIT(11) | |
151 | #define ME4000_DIO_CTRL_FIFO_HIGH_2 BIT(12) | |
152 | #define ME4000_DIO_CTRL_FIFO_HIGH_3 BIT(13) | |
81dd1811 HS |
153 | #define ME4000_AO_DEMUX_ADJUST_REG 0xbc |
154 | #define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c | |
155 | #define ME4000_AI_SAMPLE_COUNTER_REG 0xc0 | |
156 | ||
81dd1811 HS |
157 | #define ME4000_AI_FIFO_COUNT 2048 |
158 | ||
159 | #define ME4000_AI_MIN_TICKS 66 | |
160 | #define ME4000_AI_MIN_SAMPLE_TIME 2000 | |
81dd1811 HS |
161 | |
162 | #define ME4000_AI_CHANNEL_LIST_COUNT 1024 | |
163 | ||
3674a87e | 164 | struct me4000_private { |
cc6f3336 | 165 | unsigned long plx_regbase; |
272e426e | 166 | unsigned int ai_ctrl_mode; |
0f97f5c9 HS |
167 | unsigned int ai_init_ticks; |
168 | unsigned int ai_scan_ticks; | |
169 | unsigned int ai_chan_ticks; | |
cc6f3336 HS |
170 | }; |
171 | ||
8c355509 HS |
172 | enum me4000_boardid { |
173 | BOARD_ME4650, | |
174 | BOARD_ME4660, | |
175 | BOARD_ME4660I, | |
176 | BOARD_ME4660S, | |
177 | BOARD_ME4660IS, | |
178 | BOARD_ME4670, | |
179 | BOARD_ME4670I, | |
180 | BOARD_ME4670S, | |
181 | BOARD_ME4670IS, | |
182 | BOARD_ME4680, | |
183 | BOARD_ME4680I, | |
184 | BOARD_ME4680S, | |
185 | BOARD_ME4680IS, | |
186 | }; | |
187 | ||
06b60981 HS |
188 | struct me4000_board { |
189 | const char *name; | |
06b60981 | 190 | int ai_nchan; |
56f71de6 | 191 | unsigned int can_do_diff_ai:1; |
e5f66350 | 192 | unsigned int can_do_sh_ai:1; /* sample & hold (8 channels) */ |
13a463ae | 193 | unsigned int ex_trig_analog:1; |
aed9b663 | 194 | unsigned int has_ao:1; |
77714d31 | 195 | unsigned int has_ao_fifo:1; |
13a463ae | 196 | unsigned int has_counter:1; |
06b60981 HS |
197 | }; |
198 | ||
27f4caaa | 199 | static const struct me4000_board me4000_boards[] = { |
8c355509 | 200 | [BOARD_ME4650] = { |
035d432a | 201 | .name = "ME-4650", |
6ba8dfef | 202 | .ai_nchan = 16, |
8c355509 HS |
203 | }, |
204 | [BOARD_ME4660] = { | |
035d432a | 205 | .name = "ME-4660", |
6ba8dfef | 206 | .ai_nchan = 32, |
56f71de6 | 207 | .can_do_diff_ai = 1, |
eedf4299 | 208 | .has_counter = 1, |
8c355509 HS |
209 | }, |
210 | [BOARD_ME4660I] = { | |
035d432a | 211 | .name = "ME-4660i", |
6ba8dfef | 212 | .ai_nchan = 32, |
56f71de6 | 213 | .can_do_diff_ai = 1, |
eedf4299 | 214 | .has_counter = 1, |
8c355509 HS |
215 | }, |
216 | [BOARD_ME4660S] = { | |
035d432a | 217 | .name = "ME-4660s", |
6ba8dfef | 218 | .ai_nchan = 32, |
56f71de6 | 219 | .can_do_diff_ai = 1, |
e5f66350 | 220 | .can_do_sh_ai = 1, |
eedf4299 | 221 | .has_counter = 1, |
8c355509 HS |
222 | }, |
223 | [BOARD_ME4660IS] = { | |
035d432a | 224 | .name = "ME-4660is", |
6ba8dfef | 225 | .ai_nchan = 32, |
56f71de6 | 226 | .can_do_diff_ai = 1, |
e5f66350 | 227 | .can_do_sh_ai = 1, |
eedf4299 | 228 | .has_counter = 1, |
8c355509 HS |
229 | }, |
230 | [BOARD_ME4670] = { | |
035d432a | 231 | .name = "ME-4670", |
6ba8dfef | 232 | .ai_nchan = 32, |
56f71de6 | 233 | .can_do_diff_ai = 1, |
6ba8dfef | 234 | .ex_trig_analog = 1, |
aed9b663 | 235 | .has_ao = 1, |
eedf4299 | 236 | .has_counter = 1, |
8c355509 HS |
237 | }, |
238 | [BOARD_ME4670I] = { | |
035d432a | 239 | .name = "ME-4670i", |
6ba8dfef | 240 | .ai_nchan = 32, |
56f71de6 | 241 | .can_do_diff_ai = 1, |
6ba8dfef | 242 | .ex_trig_analog = 1, |
aed9b663 | 243 | .has_ao = 1, |
eedf4299 | 244 | .has_counter = 1, |
8c355509 HS |
245 | }, |
246 | [BOARD_ME4670S] = { | |
035d432a | 247 | .name = "ME-4670s", |
6ba8dfef | 248 | .ai_nchan = 32, |
56f71de6 | 249 | .can_do_diff_ai = 1, |
e5f66350 | 250 | .can_do_sh_ai = 1, |
6ba8dfef | 251 | .ex_trig_analog = 1, |
aed9b663 | 252 | .has_ao = 1, |
eedf4299 | 253 | .has_counter = 1, |
8c355509 HS |
254 | }, |
255 | [BOARD_ME4670IS] = { | |
035d432a | 256 | .name = "ME-4670is", |
6ba8dfef | 257 | .ai_nchan = 32, |
56f71de6 | 258 | .can_do_diff_ai = 1, |
e5f66350 | 259 | .can_do_sh_ai = 1, |
6ba8dfef | 260 | .ex_trig_analog = 1, |
aed9b663 | 261 | .has_ao = 1, |
eedf4299 | 262 | .has_counter = 1, |
8c355509 HS |
263 | }, |
264 | [BOARD_ME4680] = { | |
035d432a | 265 | .name = "ME-4680", |
6ba8dfef | 266 | .ai_nchan = 32, |
56f71de6 | 267 | .can_do_diff_ai = 1, |
6ba8dfef | 268 | .ex_trig_analog = 1, |
aed9b663 | 269 | .has_ao = 1, |
77714d31 | 270 | .has_ao_fifo = 1, |
eedf4299 | 271 | .has_counter = 1, |
8c355509 HS |
272 | }, |
273 | [BOARD_ME4680I] = { | |
035d432a | 274 | .name = "ME-4680i", |
6ba8dfef | 275 | .ai_nchan = 32, |
56f71de6 | 276 | .can_do_diff_ai = 1, |
6ba8dfef | 277 | .ex_trig_analog = 1, |
aed9b663 | 278 | .has_ao = 1, |
77714d31 | 279 | .has_ao_fifo = 1, |
eedf4299 | 280 | .has_counter = 1, |
8c355509 HS |
281 | }, |
282 | [BOARD_ME4680S] = { | |
035d432a | 283 | .name = "ME-4680s", |
6ba8dfef | 284 | .ai_nchan = 32, |
56f71de6 | 285 | .can_do_diff_ai = 1, |
e5f66350 | 286 | .can_do_sh_ai = 1, |
6ba8dfef | 287 | .ex_trig_analog = 1, |
aed9b663 | 288 | .has_ao = 1, |
77714d31 | 289 | .has_ao_fifo = 1, |
eedf4299 | 290 | .has_counter = 1, |
8c355509 HS |
291 | }, |
292 | [BOARD_ME4680IS] = { | |
035d432a | 293 | .name = "ME-4680is", |
6ba8dfef | 294 | .ai_nchan = 32, |
56f71de6 | 295 | .can_do_diff_ai = 1, |
e5f66350 | 296 | .can_do_sh_ai = 1, |
6ba8dfef | 297 | .ex_trig_analog = 1, |
aed9b663 | 298 | .has_ao = 1, |
77714d31 | 299 | .has_ao_fifo = 1, |
eedf4299 | 300 | .has_counter = 1, |
035d432a | 301 | }, |
e55c95a3 GG |
302 | }; |
303 | ||
245bd462 HS |
304 | /* |
305 | * NOTE: the ranges here are inverted compared to the values | |
306 | * written to the ME4000_AI_CHANNEL_LIST_REG, | |
307 | * | |
308 | * The ME4000_AI_LIST_RANGE() macro handles the inversion. | |
309 | */ | |
9ced1de6 | 310 | static const struct comedi_lrange me4000_ai_range = { |
93626a45 HS |
311 | 4, { |
312 | UNI_RANGE(2.5), | |
313 | UNI_RANGE(10), | |
314 | BIP_RANGE(2.5), | |
315 | BIP_RANGE(10) | |
316 | } | |
e55c95a3 GG |
317 | }; |
318 | ||
ac584af5 HS |
319 | static int me4000_xilinx_download(struct comedi_device *dev, |
320 | const u8 *data, size_t size, | |
321 | unsigned long context) | |
e55c95a3 | 322 | { |
fe531d12 | 323 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
3674a87e | 324 | struct me4000_private *devpriv = dev->private; |
fe531d12 | 325 | unsigned long xilinx_iobase = pci_resource_start(pcidev, 5); |
ac584af5 HS |
326 | unsigned int file_length; |
327 | unsigned int val; | |
328 | unsigned int i; | |
e55c95a3 | 329 | |
fe531d12 HS |
330 | if (!xilinx_iobase) |
331 | return -ENODEV; | |
332 | ||
e55c95a3 GG |
333 | /* |
334 | * Set PLX local interrupt 2 polarity to high. | |
335 | * Interrupt is thrown by init pin of xilinx. | |
336 | */ | |
3674a87e | 337 | outl(PLX9052_INTCSR_LI2POL, devpriv->plx_regbase + PLX9052_INTCSR); |
e55c95a3 GG |
338 | |
339 | /* Set /CS and /WRITE of the Xilinx */ | |
3674a87e | 340 | val = inl(devpriv->plx_regbase + PLX9052_CNTRL); |
ac584af5 | 341 | val |= PLX9052_CNTRL_UIO2_DATA; |
3674a87e | 342 | outl(val, devpriv->plx_regbase + PLX9052_CNTRL); |
e55c95a3 GG |
343 | |
344 | /* Init Xilinx with CS1 */ | |
fe531d12 | 345 | inb(xilinx_iobase + 0xC8); |
e55c95a3 GG |
346 | |
347 | /* Wait until /INIT pin is set */ | |
348 | udelay(20); | |
3674a87e | 349 | val = inl(devpriv->plx_regbase + PLX9052_INTCSR); |
ac584af5 | 350 | if (!(val & PLX9052_INTCSR_LI2STAT)) { |
5da80ee8 | 351 | dev_err(dev->class_dev, "Can't init Xilinx\n"); |
e55c95a3 GG |
352 | return -EIO; |
353 | } | |
354 | ||
355 | /* Reset /CS and /WRITE of the Xilinx */ | |
3674a87e | 356 | val = inl(devpriv->plx_regbase + PLX9052_CNTRL); |
ac584af5 | 357 | val &= ~PLX9052_CNTRL_UIO2_DATA; |
3674a87e | 358 | outl(val, devpriv->plx_regbase + PLX9052_CNTRL); |
e55c95a3 | 359 | |
ac584af5 HS |
360 | /* Download Xilinx firmware */ |
361 | file_length = (((unsigned int)data[0] & 0xff) << 24) + | |
362 | (((unsigned int)data[1] & 0xff) << 16) + | |
363 | (((unsigned int)data[2] & 0xff) << 8) + | |
364 | ((unsigned int)data[3] & 0xff); | |
365 | udelay(10); | |
e55c95a3 | 366 | |
ac584af5 HS |
367 | for (i = 0; i < file_length; i++) { |
368 | outb(data[16 + i], xilinx_iobase); | |
369 | udelay(10); | |
370 | ||
371 | /* Check if BUSY flag is low */ | |
3674a87e | 372 | val = inl(devpriv->plx_regbase + PLX9052_CNTRL); |
ac584af5 HS |
373 | if (val & PLX9052_CNTRL_UIO1_DATA) { |
374 | dev_err(dev->class_dev, | |
375 | "Xilinx is still busy (i = %d)\n", i); | |
376 | return -EIO; | |
e55c95a3 GG |
377 | } |
378 | } | |
379 | ||
380 | /* If done flag is high download was successful */ | |
3674a87e | 381 | val = inl(devpriv->plx_regbase + PLX9052_CNTRL); |
ac584af5 | 382 | if (!(val & PLX9052_CNTRL_UIO0_DATA)) { |
5da80ee8 HS |
383 | dev_err(dev->class_dev, "DONE flag is not set\n"); |
384 | dev_err(dev->class_dev, "Download not successful\n"); | |
e55c95a3 GG |
385 | return -EIO; |
386 | } | |
387 | ||
388 | /* Set /CS and /WRITE */ | |
3674a87e | 389 | val = inl(devpriv->plx_regbase + PLX9052_CNTRL); |
ac584af5 | 390 | val |= PLX9052_CNTRL_UIO2_DATA; |
3674a87e | 391 | outl(val, devpriv->plx_regbase + PLX9052_CNTRL); |
e55c95a3 GG |
392 | |
393 | return 0; | |
394 | } | |
395 | ||
b047d9cc HS |
396 | static void me4000_ai_reset(struct comedi_device *dev) |
397 | { | |
398 | unsigned int ctrl; | |
399 | ||
400 | /* Stop any running conversion */ | |
401 | ctrl = inl(dev->iobase + ME4000_AI_CTRL_REG); | |
402 | ctrl |= ME4000_AI_CTRL_STOP | ME4000_AI_CTRL_IMMEDIATE_STOP; | |
403 | outl(ctrl, dev->iobase + ME4000_AI_CTRL_REG); | |
404 | ||
405 | /* Clear the control register */ | |
406 | outl(0x0, dev->iobase + ME4000_AI_CTRL_REG); | |
407 | } | |
408 | ||
2f348ecd | 409 | static void me4000_reset(struct comedi_device *dev) |
e55c95a3 | 410 | { |
3674a87e | 411 | struct me4000_private *devpriv = dev->private; |
ac2832f8 | 412 | unsigned int val; |
e1d7ccb7 | 413 | int chan; |
e55c95a3 | 414 | |
8f3f3eb7 HS |
415 | /* Disable interrupts on the PLX */ |
416 | outl(0, devpriv->plx_regbase + PLX9052_INTCSR); | |
417 | ||
418 | /* Software reset the PLX */ | |
3674a87e | 419 | val = inl(devpriv->plx_regbase + PLX9052_CNTRL); |
4564cfd0 | 420 | val |= PLX9052_CNTRL_PCI_RESET; |
3674a87e | 421 | outl(val, devpriv->plx_regbase + PLX9052_CNTRL); |
4564cfd0 | 422 | val &= ~PLX9052_CNTRL_PCI_RESET; |
3674a87e | 423 | outl(val, devpriv->plx_regbase + PLX9052_CNTRL); |
e55c95a3 GG |
424 | |
425 | /* 0x8000 to the DACs means an output voltage of 0V */ | |
e1d7ccb7 HS |
426 | for (chan = 0; chan < 4; chan++) |
427 | outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan)); | |
e55c95a3 | 428 | |
b047d9cc | 429 | me4000_ai_reset(dev); |
a31b50ed | 430 | |
e55c95a3 | 431 | /* Set both stop bits in the analog output control register */ |
7e92a5eb | 432 | val = ME4000_AO_CTRL_IMMEDIATE_STOP | ME4000_AO_CTRL_STOP; |
e1d7ccb7 HS |
433 | for (chan = 0; chan < 4; chan++) |
434 | outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan)); | |
e55c95a3 | 435 | |
e55c95a3 | 436 | /* Set the adustment register for AO demux */ |
d6cbe537 | 437 | outl(ME4000_AO_DEMUX_ADJUST_VALUE, |
6c7d2c8b | 438 | dev->iobase + ME4000_AO_DEMUX_ADJUST_REG); |
e55c95a3 | 439 | |
b6241fda GS |
440 | /* |
441 | * Set digital I/O direction for port 0 | |
442 | * to output on isolated versions | |
443 | */ | |
362bcbde HS |
444 | if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1)) |
445 | outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG); | |
e55c95a3 GG |
446 | } |
447 | ||
023c129f HS |
448 | static int me4000_ai_eoc(struct comedi_device *dev, |
449 | struct comedi_subdevice *s, | |
450 | struct comedi_insn *insn, | |
451 | unsigned long context) | |
452 | { | |
453 | unsigned int status; | |
454 | ||
455 | status = inl(dev->iobase + ME4000_AI_STATUS_REG); | |
a9b586a5 | 456 | if (status & ME4000_AI_STATUS_EF_DATA) |
023c129f HS |
457 | return 0; |
458 | return -EBUSY; | |
459 | } | |
e55c95a3 | 460 | |
71b5f4f1 | 461 | static int me4000_ai_insn_read(struct comedi_device *dev, |
1a023870 HS |
462 | struct comedi_subdevice *s, |
463 | struct comedi_insn *insn, | |
464 | unsigned int *data) | |
e55c95a3 | 465 | { |
959717a3 | 466 | unsigned int chan = CR_CHAN(insn->chanspec); |
e9784261 | 467 | unsigned int range = CR_RANGE(insn->chanspec); |
959717a3 | 468 | unsigned int aref = CR_AREF(insn->chanspec); |
e9784261 | 469 | unsigned int entry; |
b047d9cc | 470 | int ret = 0; |
fb7891e4 | 471 | int i; |
e55c95a3 | 472 | |
e9784261 | 473 | entry = chan | ME4000_AI_LIST_RANGE(range); |
271f5aa0 | 474 | if (aref == AREF_DIFF) { |
1a023870 HS |
475 | if (!(s->subdev_flags && SDF_DIFF)) { |
476 | dev_err(dev->class_dev, | |
477 | "Differential inputs are not available\n"); | |
478 | return -EINVAL; | |
479 | } | |
480 | ||
e9784261 | 481 | if (!comedi_range_is_bipolar(s, range)) { |
5da80ee8 HS |
482 | dev_err(dev->class_dev, |
483 | "Range must be bipolar when aref = diff\n"); | |
e55c95a3 GG |
484 | return -EINVAL; |
485 | } | |
486 | ||
1a023870 | 487 | if (chan >= (s->n_chan / 2)) { |
5da80ee8 HS |
488 | dev_err(dev->class_dev, |
489 | "Analog input is not available\n"); | |
e55c95a3 GG |
490 | return -EINVAL; |
491 | } | |
271f5aa0 | 492 | entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL; |
e55c95a3 GG |
493 | } |
494 | ||
495 | entry |= ME4000_AI_LIST_LAST_ENTRY; | |
496 | ||
b047d9cc HS |
497 | /* Enable channel list and data fifo for single acquisition mode */ |
498 | outl(ME4000_AI_CTRL_CHANNEL_FIFO | ME4000_AI_CTRL_DATA_FIFO, | |
499 | dev->iobase + ME4000_AI_CTRL_REG); | |
e55c95a3 GG |
500 | |
501 | /* Generate channel list entry */ | |
b08bfa38 | 502 | outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG); |
e55c95a3 GG |
503 | |
504 | /* Set the timer to maximum sample rate */ | |
b08bfa38 HS |
505 | outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG); |
506 | outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG); | |
e55c95a3 | 507 | |
fb7891e4 HS |
508 | for (i = 0; i < insn->n; i++) { |
509 | unsigned int val; | |
e55c95a3 | 510 | |
fb7891e4 HS |
511 | /* start conversion by dummy read */ |
512 | inl(dev->iobase + ME4000_AI_START_REG); | |
e55c95a3 | 513 | |
fb7891e4 HS |
514 | ret = comedi_timeout(dev, s, insn, me4000_ai_eoc, 0); |
515 | if (ret) | |
b047d9cc | 516 | break; |
fb7891e4 HS |
517 | |
518 | /* read two's complement value and munge to offset binary */ | |
519 | val = inl(dev->iobase + ME4000_AI_DATA_REG); | |
520 | data[i] = comedi_offset_munge(s, val); | |
521 | } | |
e55c95a3 | 522 | |
b047d9cc HS |
523 | me4000_ai_reset(dev); |
524 | ||
525 | return ret ? ret : insn->n; | |
e55c95a3 GG |
526 | } |
527 | ||
0a85b6f0 MT |
528 | static int me4000_ai_cancel(struct comedi_device *dev, |
529 | struct comedi_subdevice *s) | |
e55c95a3 | 530 | { |
b047d9cc | 531 | me4000_ai_reset(dev); |
e55c95a3 GG |
532 | |
533 | return 0; | |
534 | } | |
535 | ||
926e5073 HS |
536 | static int me4000_ai_check_chanlist(struct comedi_device *dev, |
537 | struct comedi_subdevice *s, | |
538 | struct comedi_cmd *cmd) | |
e55c95a3 | 539 | { |
926e5073 | 540 | unsigned int aref0 = CR_AREF(cmd->chanlist[0]); |
e55c95a3 GG |
541 | int i; |
542 | ||
e55c95a3 | 543 | for (i = 0; i < cmd->chanlist_len; i++) { |
926e5073 HS |
544 | unsigned int chan = CR_CHAN(cmd->chanlist[i]); |
545 | unsigned int range = CR_RANGE(cmd->chanlist[i]); | |
546 | unsigned int aref = CR_AREF(cmd->chanlist[i]); | |
547 | ||
548 | if (aref != aref0) { | |
549 | dev_dbg(dev->class_dev, | |
5da80ee8 | 550 | "Mode is not equal for all entries\n"); |
e55c95a3 GG |
551 | return -EINVAL; |
552 | } | |
e55c95a3 | 553 | |
a7dab198 | 554 | if (aref == AREF_DIFF) { |
4ec85dad HS |
555 | if (!(s->subdev_flags && SDF_DIFF)) { |
556 | dev_err(dev->class_dev, | |
557 | "Differential inputs are not available\n"); | |
558 | return -EINVAL; | |
559 | } | |
560 | ||
561 | if (chan >= (s->n_chan / 2)) { | |
926e5073 | 562 | dev_dbg(dev->class_dev, |
5da80ee8 | 563 | "Channel number to high\n"); |
e55c95a3 GG |
564 | return -EINVAL; |
565 | } | |
e55c95a3 | 566 | |
926e5073 HS |
567 | if (!comedi_range_is_bipolar(s, range)) { |
568 | dev_dbg(dev->class_dev, | |
6c7d2c8b | 569 | "Bipolar is not selected in differential mode\n"); |
e55c95a3 GG |
570 | return -EINVAL; |
571 | } | |
572 | } | |
573 | } | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
c72c4c6e HS |
578 | static void me4000_ai_round_cmd_args(struct comedi_device *dev, |
579 | struct comedi_subdevice *s, | |
0f97f5c9 | 580 | struct comedi_cmd *cmd) |
e55c95a3 | 581 | { |
0f97f5c9 | 582 | struct me4000_private *devpriv = dev->private; |
e55c95a3 GG |
583 | int rest; |
584 | ||
0f97f5c9 HS |
585 | devpriv->ai_init_ticks = 0; |
586 | devpriv->ai_scan_ticks = 0; | |
587 | devpriv->ai_chan_ticks = 0; | |
e55c95a3 | 588 | |
e55c95a3 | 589 | if (cmd->start_arg) { |
0f97f5c9 | 590 | devpriv->ai_init_ticks = (cmd->start_arg * 33) / 1000; |
e55c95a3 GG |
591 | rest = (cmd->start_arg * 33) % 1000; |
592 | ||
1e00dedc | 593 | if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) { |
82675f35 | 594 | if (rest > 33) |
0f97f5c9 | 595 | devpriv->ai_init_ticks++; |
1e00dedc | 596 | } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) { |
e55c95a3 | 597 | if (rest) |
0f97f5c9 | 598 | devpriv->ai_init_ticks++; |
e55c95a3 GG |
599 | } |
600 | } | |
601 | ||
602 | if (cmd->scan_begin_arg) { | |
0f97f5c9 | 603 | devpriv->ai_scan_ticks = (cmd->scan_begin_arg * 33) / 1000; |
e55c95a3 GG |
604 | rest = (cmd->scan_begin_arg * 33) % 1000; |
605 | ||
1e00dedc | 606 | if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) { |
82675f35 | 607 | if (rest > 33) |
0f97f5c9 | 608 | devpriv->ai_scan_ticks++; |
1e00dedc | 609 | } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) { |
e55c95a3 | 610 | if (rest) |
0f97f5c9 | 611 | devpriv->ai_scan_ticks++; |
e55c95a3 GG |
612 | } |
613 | } | |
614 | ||
615 | if (cmd->convert_arg) { | |
0f97f5c9 | 616 | devpriv->ai_chan_ticks = (cmd->convert_arg * 33) / 1000; |
e55c95a3 GG |
617 | rest = (cmd->convert_arg * 33) % 1000; |
618 | ||
1e00dedc | 619 | if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) { |
82675f35 | 620 | if (rest > 33) |
0f97f5c9 | 621 | devpriv->ai_chan_ticks++; |
1e00dedc | 622 | } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) { |
e55c95a3 | 623 | if (rest) |
0f97f5c9 | 624 | devpriv->ai_chan_ticks++; |
e55c95a3 GG |
625 | } |
626 | } | |
e55c95a3 GG |
627 | } |
628 | ||
ffaeab34 HS |
629 | static void me4000_ai_write_chanlist(struct comedi_device *dev, |
630 | struct comedi_subdevice *s, | |
631 | struct comedi_cmd *cmd) | |
4b2f15f1 | 632 | { |
4b2f15f1 HS |
633 | int i; |
634 | ||
635 | for (i = 0; i < cmd->chanlist_len; i++) { | |
518c5b64 HS |
636 | unsigned int chan = CR_CHAN(cmd->chanlist[i]); |
637 | unsigned int range = CR_RANGE(cmd->chanlist[i]); | |
638 | unsigned int aref = CR_AREF(cmd->chanlist[i]); | |
639 | unsigned int entry; | |
4b2f15f1 | 640 | |
518c5b64 | 641 | entry = chan | ME4000_AI_LIST_RANGE(range); |
4b2f15f1 | 642 | |
8d44945d | 643 | if (aref == AREF_DIFF) |
4b2f15f1 | 644 | entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL; |
4b2f15f1 | 645 | |
518c5b64 HS |
646 | if (i == (cmd->chanlist_len - 1)) |
647 | entry |= ME4000_AI_LIST_LAST_ENTRY; | |
648 | ||
4b2f15f1 HS |
649 | outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG); |
650 | } | |
4b2f15f1 HS |
651 | } |
652 | ||
11e480c3 HS |
653 | static int me4000_ai_do_cmd(struct comedi_device *dev, |
654 | struct comedi_subdevice *s) | |
e55c95a3 | 655 | { |
272e426e | 656 | struct me4000_private *devpriv = dev->private; |
11e480c3 | 657 | struct comedi_cmd *cmd = &s->async->cmd; |
272e426e | 658 | unsigned int ctrl; |
e55c95a3 | 659 | |
e55c95a3 | 660 | /* Write timer arguments */ |
576694d8 HS |
661 | outl(devpriv->ai_init_ticks - 1, |
662 | dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG); | |
663 | outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG); | |
664 | ||
665 | if (devpriv->ai_scan_ticks) { | |
666 | outl(devpriv->ai_scan_ticks - 1, | |
667 | dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG); | |
668 | outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG); | |
669 | } | |
670 | ||
671 | outl(devpriv->ai_chan_ticks - 1, | |
672 | dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG); | |
673 | outl(devpriv->ai_chan_ticks - 1, | |
674 | dev->iobase + ME4000_AI_CHAN_TIMER_REG); | |
e55c95a3 | 675 | |
e55c95a3 | 676 | /* Start sources */ |
272e426e HS |
677 | ctrl = devpriv->ai_ctrl_mode | |
678 | ME4000_AI_CTRL_CHANNEL_FIFO | | |
679 | ME4000_AI_CTRL_DATA_FIFO; | |
e55c95a3 GG |
680 | |
681 | /* Stop triggers */ | |
682 | if (cmd->stop_src == TRIG_COUNT) { | |
d6cbe537 | 683 | outl(cmd->chanlist_len * cmd->stop_arg, |
6c7d2c8b | 684 | dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG); |
272e426e | 685 | ctrl |= ME4000_AI_CTRL_SC_IRQ; |
e55c95a3 | 686 | } else if (cmd->stop_src == TRIG_NONE && |
0a85b6f0 | 687 | cmd->scan_end_src == TRIG_COUNT) { |
d6cbe537 | 688 | outl(cmd->scan_end_arg, |
6c7d2c8b | 689 | dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG); |
272e426e | 690 | ctrl |= ME4000_AI_CTRL_SC_IRQ; |
e55c95a3 | 691 | } |
272e426e | 692 | ctrl |= ME4000_AI_CTRL_HF_IRQ; |
e55c95a3 GG |
693 | |
694 | /* Write the setup to the control register */ | |
272e426e | 695 | outl(ctrl, dev->iobase + ME4000_AI_CTRL_REG); |
e55c95a3 GG |
696 | |
697 | /* Write the channel list */ | |
518c5b64 | 698 | me4000_ai_write_chanlist(dev, s, cmd); |
e55c95a3 | 699 | |
e55c95a3 | 700 | /* Start acquistion by dummy read */ |
b08bfa38 | 701 | inl(dev->iobase + ME4000_AI_START_REG); |
e55c95a3 GG |
702 | |
703 | return 0; | |
704 | } | |
705 | ||
71b5f4f1 | 706 | static int me4000_ai_do_cmd_test(struct comedi_device *dev, |
0a85b6f0 MT |
707 | struct comedi_subdevice *s, |
708 | struct comedi_cmd *cmd) | |
e55c95a3 | 709 | { |
0f97f5c9 | 710 | struct me4000_private *devpriv = dev->private; |
e55c95a3 GG |
711 | int err = 0; |
712 | ||
27020ffe HS |
713 | /* Step 1 : check if triggers are trivially valid */ |
714 | ||
51ec1db9 IA |
715 | err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); |
716 | err |= comedi_check_trigger_src(&cmd->scan_begin_src, | |
27020ffe | 717 | TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT); |
51ec1db9 IA |
718 | err |= comedi_check_trigger_src(&cmd->convert_src, |
719 | TRIG_TIMER | TRIG_EXT); | |
720 | err |= comedi_check_trigger_src(&cmd->scan_end_src, | |
27020ffe | 721 | TRIG_NONE | TRIG_COUNT); |
51ec1db9 | 722 | err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT); |
27020ffe | 723 | |
82675f35 | 724 | if (err) |
e55c95a3 | 725 | return 1; |
e55c95a3 | 726 | |
27020ffe HS |
727 | /* Step 2a : make sure trigger sources are unique */ |
728 | ||
51ec1db9 IA |
729 | err |= comedi_check_trigger_is_unique(cmd->start_src); |
730 | err |= comedi_check_trigger_is_unique(cmd->scan_begin_src); | |
731 | err |= comedi_check_trigger_is_unique(cmd->convert_src); | |
732 | err |= comedi_check_trigger_is_unique(cmd->scan_end_src); | |
733 | err |= comedi_check_trigger_is_unique(cmd->stop_src); | |
27020ffe HS |
734 | |
735 | /* Step 2b : and mutually compatible */ | |
736 | ||
e55c95a3 | 737 | if (cmd->start_src == TRIG_NOW && |
0a85b6f0 MT |
738 | cmd->scan_begin_src == TRIG_TIMER && |
739 | cmd->convert_src == TRIG_TIMER) { | |
272e426e | 740 | devpriv->ai_ctrl_mode = ME4000_AI_CTRL_MODE_0; |
e55c95a3 | 741 | } else if (cmd->start_src == TRIG_NOW && |
0a85b6f0 MT |
742 | cmd->scan_begin_src == TRIG_FOLLOW && |
743 | cmd->convert_src == TRIG_TIMER) { | |
272e426e | 744 | devpriv->ai_ctrl_mode = ME4000_AI_CTRL_MODE_0; |
e55c95a3 | 745 | } else if (cmd->start_src == TRIG_EXT && |
0a85b6f0 MT |
746 | cmd->scan_begin_src == TRIG_TIMER && |
747 | cmd->convert_src == TRIG_TIMER) { | |
272e426e | 748 | devpriv->ai_ctrl_mode = ME4000_AI_CTRL_MODE_1; |
e55c95a3 | 749 | } else if (cmd->start_src == TRIG_EXT && |
0a85b6f0 MT |
750 | cmd->scan_begin_src == TRIG_FOLLOW && |
751 | cmd->convert_src == TRIG_TIMER) { | |
272e426e | 752 | devpriv->ai_ctrl_mode = ME4000_AI_CTRL_MODE_1; |
e55c95a3 | 753 | } else if (cmd->start_src == TRIG_EXT && |
0a85b6f0 MT |
754 | cmd->scan_begin_src == TRIG_EXT && |
755 | cmd->convert_src == TRIG_TIMER) { | |
272e426e | 756 | devpriv->ai_ctrl_mode = ME4000_AI_CTRL_MODE_2; |
e55c95a3 | 757 | } else if (cmd->start_src == TRIG_EXT && |
0a85b6f0 MT |
758 | cmd->scan_begin_src == TRIG_EXT && |
759 | cmd->convert_src == TRIG_EXT) { | |
272e426e HS |
760 | devpriv->ai_ctrl_mode = ME4000_AI_CTRL_MODE_0 | |
761 | ME4000_AI_CTRL_MODE_1; | |
e55c95a3 | 762 | } else { |
27020ffe | 763 | err |= -EINVAL; |
e55c95a3 GG |
764 | } |
765 | ||
82675f35 | 766 | if (err) |
e55c95a3 | 767 | return 2; |
e55c95a3 | 768 | |
8c6c5a69 HS |
769 | /* Step 3: check if arguments are trivially valid */ |
770 | ||
51ec1db9 | 771 | err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0); |
025b9187 | 772 | |
e55c95a3 | 773 | if (cmd->chanlist_len < 1) { |
e55c95a3 | 774 | cmd->chanlist_len = 1; |
8c6c5a69 | 775 | err |= -EINVAL; |
e55c95a3 | 776 | } |
c72c4c6e HS |
777 | |
778 | /* Round the timer arguments */ | |
0f97f5c9 | 779 | me4000_ai_round_cmd_args(dev, s, cmd); |
c72c4c6e | 780 | |
0f97f5c9 | 781 | if (devpriv->ai_init_ticks < 66) { |
e55c95a3 | 782 | cmd->start_arg = 2000; |
8c6c5a69 | 783 | err |= -EINVAL; |
e55c95a3 | 784 | } |
0f97f5c9 | 785 | if (devpriv->ai_scan_ticks && devpriv->ai_scan_ticks < 67) { |
e55c95a3 | 786 | cmd->scan_begin_arg = 2031; |
8c6c5a69 | 787 | err |= -EINVAL; |
e55c95a3 | 788 | } |
0f97f5c9 | 789 | if (devpriv->ai_chan_ticks < 66) { |
e55c95a3 | 790 | cmd->convert_arg = 2000; |
8c6c5a69 | 791 | err |= -EINVAL; |
e55c95a3 | 792 | } |
82675f35 | 793 | |
76af50dd | 794 | if (cmd->stop_src == TRIG_COUNT) |
51ec1db9 | 795 | err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1); |
76af50dd | 796 | else /* TRIG_NONE */ |
51ec1db9 | 797 | err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0); |
76af50dd | 798 | |
82675f35 | 799 | if (err) |
e55c95a3 | 800 | return 3; |
e55c95a3 GG |
801 | |
802 | /* | |
803 | * Stage 4. Check for argument conflicts. | |
804 | */ | |
805 | if (cmd->start_src == TRIG_NOW && | |
0a85b6f0 MT |
806 | cmd->scan_begin_src == TRIG_TIMER && |
807 | cmd->convert_src == TRIG_TIMER) { | |
e55c95a3 | 808 | /* Check timer arguments */ |
0f97f5c9 | 809 | if (devpriv->ai_init_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 810 | dev_err(dev->class_dev, "Invalid start arg\n"); |
b6c77757 | 811 | cmd->start_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
812 | err++; |
813 | } | |
0f97f5c9 | 814 | if (devpriv->ai_chan_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 815 | dev_err(dev->class_dev, "Invalid convert arg\n"); |
b6c77757 | 816 | cmd->convert_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
817 | err++; |
818 | } | |
0f97f5c9 HS |
819 | if (devpriv->ai_scan_ticks <= |
820 | cmd->chanlist_len * devpriv->ai_chan_ticks) { | |
5da80ee8 | 821 | dev_err(dev->class_dev, "Invalid scan end arg\n"); |
b6241fda GS |
822 | |
823 | /* At least one tick more */ | |
824 | cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31; | |
e55c95a3 GG |
825 | err++; |
826 | } | |
827 | } else if (cmd->start_src == TRIG_NOW && | |
0a85b6f0 MT |
828 | cmd->scan_begin_src == TRIG_FOLLOW && |
829 | cmd->convert_src == TRIG_TIMER) { | |
e55c95a3 | 830 | /* Check timer arguments */ |
0f97f5c9 | 831 | if (devpriv->ai_init_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 832 | dev_err(dev->class_dev, "Invalid start arg\n"); |
b6c77757 | 833 | cmd->start_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
834 | err++; |
835 | } | |
0f97f5c9 | 836 | if (devpriv->ai_chan_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 837 | dev_err(dev->class_dev, "Invalid convert arg\n"); |
b6c77757 | 838 | cmd->convert_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
839 | err++; |
840 | } | |
841 | } else if (cmd->start_src == TRIG_EXT && | |
0a85b6f0 MT |
842 | cmd->scan_begin_src == TRIG_TIMER && |
843 | cmd->convert_src == TRIG_TIMER) { | |
e55c95a3 | 844 | /* Check timer arguments */ |
0f97f5c9 | 845 | if (devpriv->ai_init_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 846 | dev_err(dev->class_dev, "Invalid start arg\n"); |
b6c77757 | 847 | cmd->start_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
848 | err++; |
849 | } | |
0f97f5c9 | 850 | if (devpriv->ai_chan_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 851 | dev_err(dev->class_dev, "Invalid convert arg\n"); |
b6c77757 | 852 | cmd->convert_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
853 | err++; |
854 | } | |
0f97f5c9 HS |
855 | if (devpriv->ai_scan_ticks <= |
856 | cmd->chanlist_len * devpriv->ai_chan_ticks) { | |
5da80ee8 | 857 | dev_err(dev->class_dev, "Invalid scan end arg\n"); |
b6241fda GS |
858 | |
859 | /* At least one tick more */ | |
860 | cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31; | |
e55c95a3 GG |
861 | err++; |
862 | } | |
863 | } else if (cmd->start_src == TRIG_EXT && | |
0a85b6f0 MT |
864 | cmd->scan_begin_src == TRIG_FOLLOW && |
865 | cmd->convert_src == TRIG_TIMER) { | |
e55c95a3 | 866 | /* Check timer arguments */ |
0f97f5c9 | 867 | if (devpriv->ai_init_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 868 | dev_err(dev->class_dev, "Invalid start arg\n"); |
b6c77757 | 869 | cmd->start_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
870 | err++; |
871 | } | |
0f97f5c9 | 872 | if (devpriv->ai_chan_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 873 | dev_err(dev->class_dev, "Invalid convert arg\n"); |
b6c77757 | 874 | cmd->convert_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
875 | err++; |
876 | } | |
877 | } else if (cmd->start_src == TRIG_EXT && | |
0a85b6f0 MT |
878 | cmd->scan_begin_src == TRIG_EXT && |
879 | cmd->convert_src == TRIG_TIMER) { | |
e55c95a3 | 880 | /* Check timer arguments */ |
0f97f5c9 | 881 | if (devpriv->ai_init_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 882 | dev_err(dev->class_dev, "Invalid start arg\n"); |
b6c77757 | 883 | cmd->start_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
884 | err++; |
885 | } | |
0f97f5c9 | 886 | if (devpriv->ai_chan_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 887 | dev_err(dev->class_dev, "Invalid convert arg\n"); |
b6c77757 | 888 | cmd->convert_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
889 | err++; |
890 | } | |
891 | } else if (cmd->start_src == TRIG_EXT && | |
0a85b6f0 MT |
892 | cmd->scan_begin_src == TRIG_EXT && |
893 | cmd->convert_src == TRIG_EXT) { | |
e55c95a3 | 894 | /* Check timer arguments */ |
0f97f5c9 | 895 | if (devpriv->ai_init_ticks < ME4000_AI_MIN_TICKS) { |
5da80ee8 | 896 | dev_err(dev->class_dev, "Invalid start arg\n"); |
b6c77757 | 897 | cmd->start_arg = 2000; /* 66 ticks at least */ |
e55c95a3 GG |
898 | err++; |
899 | } | |
900 | } | |
e55c95a3 GG |
901 | if (cmd->scan_end_src == TRIG_COUNT) { |
902 | if (cmd->scan_end_arg == 0) { | |
5da80ee8 | 903 | dev_err(dev->class_dev, "Invalid scan end arg\n"); |
e55c95a3 GG |
904 | cmd->scan_end_arg = 1; |
905 | err++; | |
906 | } | |
907 | } | |
82675f35 BP |
908 | |
909 | if (err) | |
e55c95a3 | 910 | return 4; |
e55c95a3 | 911 | |
926e5073 HS |
912 | /* Step 5: check channel list if it exists */ |
913 | if (cmd->chanlist && cmd->chanlist_len > 0) | |
914 | err |= me4000_ai_check_chanlist(dev, s, cmd); | |
915 | ||
916 | if (err) | |
e55c95a3 GG |
917 | return 5; |
918 | ||
919 | return 0; | |
920 | } | |
921 | ||
70265d24 | 922 | static irqreturn_t me4000_ai_isr(int irq, void *dev_id) |
e55c95a3 GG |
923 | { |
924 | unsigned int tmp; | |
71b5f4f1 | 925 | struct comedi_device *dev = dev_id; |
b3403f2e | 926 | struct comedi_subdevice *s = dev->read_subdev; |
e55c95a3 GG |
927 | int i; |
928 | int c = 0; | |
ac2832f8 | 929 | unsigned int lval; |
e55c95a3 | 930 | |
ef5bbfcb | 931 | if (!dev->attached) |
e55c95a3 | 932 | return IRQ_NONE; |
e55c95a3 | 933 | |
b08bfa38 | 934 | if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) & |
2ec0019a | 935 | ME4000_IRQ_STATUS_AI_HF) { |
e55c95a3 | 936 | /* Read status register to find out what happened */ |
a9b586a5 | 937 | tmp = inl(dev->iobase + ME4000_AI_STATUS_REG); |
e55c95a3 | 938 | |
a9b586a5 HS |
939 | if (!(tmp & ME4000_AI_STATUS_FF_DATA) && |
940 | !(tmp & ME4000_AI_STATUS_HF_DATA) && | |
941 | (tmp & ME4000_AI_STATUS_EF_DATA)) { | |
e55c95a3 GG |
942 | c = ME4000_AI_FIFO_COUNT; |
943 | ||
b6241fda GS |
944 | /* |
945 | * FIFO overflow, so stop conversion | |
946 | * and disable all interrupts | |
947 | */ | |
da772ad9 HS |
948 | tmp |= ME4000_AI_CTRL_IMMEDIATE_STOP; |
949 | tmp &= ~(ME4000_AI_CTRL_HF_IRQ | | |
950 | ME4000_AI_CTRL_SC_IRQ); | |
b08bfa38 | 951 | outl(tmp, dev->iobase + ME4000_AI_CTRL_REG); |
e55c95a3 | 952 | |
3e6cb74f | 953 | s->async->events |= COMEDI_CB_ERROR; |
e55c95a3 | 954 | |
5da80ee8 | 955 | dev_err(dev->class_dev, "FIFO overflow\n"); |
a9b586a5 HS |
956 | } else if ((tmp & ME4000_AI_STATUS_FF_DATA) && |
957 | !(tmp & ME4000_AI_STATUS_HF_DATA) && | |
958 | (tmp & ME4000_AI_STATUS_EF_DATA)) { | |
e55c95a3 GG |
959 | c = ME4000_AI_FIFO_COUNT / 2; |
960 | } else { | |
5da80ee8 HS |
961 | dev_err(dev->class_dev, |
962 | "Can't determine state of fifo\n"); | |
e55c95a3 GG |
963 | c = 0; |
964 | ||
b6241fda GS |
965 | /* |
966 | * Undefined state, so stop conversion | |
967 | * and disable all interrupts | |
968 | */ | |
da772ad9 HS |
969 | tmp |= ME4000_AI_CTRL_IMMEDIATE_STOP; |
970 | tmp &= ~(ME4000_AI_CTRL_HF_IRQ | | |
971 | ME4000_AI_CTRL_SC_IRQ); | |
b08bfa38 | 972 | outl(tmp, dev->iobase + ME4000_AI_CTRL_REG); |
e55c95a3 | 973 | |
3e6cb74f | 974 | s->async->events |= COMEDI_CB_ERROR; |
e55c95a3 | 975 | |
5da80ee8 | 976 | dev_err(dev->class_dev, "Undefined FIFO state\n"); |
e55c95a3 GG |
977 | } |
978 | ||
e55c95a3 GG |
979 | for (i = 0; i < c; i++) { |
980 | /* Read value from data fifo */ | |
b08bfa38 | 981 | lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF; |
e55c95a3 GG |
982 | lval ^= 0x8000; |
983 | ||
de88924f | 984 | if (!comedi_buf_write_samples(s, &lval, 1)) { |
b6241fda GS |
985 | /* |
986 | * Buffer overflow, so stop conversion | |
987 | * and disable all interrupts | |
988 | */ | |
da772ad9 HS |
989 | tmp |= ME4000_AI_CTRL_IMMEDIATE_STOP; |
990 | tmp &= ~(ME4000_AI_CTRL_HF_IRQ | | |
991 | ME4000_AI_CTRL_SC_IRQ); | |
b08bfa38 | 992 | outl(tmp, dev->iobase + ME4000_AI_CTRL_REG); |
e55c95a3 GG |
993 | break; |
994 | } | |
995 | } | |
996 | ||
997 | /* Work is done, so reset the interrupt */ | |
da772ad9 | 998 | tmp |= ME4000_AI_CTRL_HF_IRQ_RESET; |
b08bfa38 | 999 | outl(tmp, dev->iobase + ME4000_AI_CTRL_REG); |
da772ad9 | 1000 | tmp &= ~ME4000_AI_CTRL_HF_IRQ_RESET; |
b08bfa38 | 1001 | outl(tmp, dev->iobase + ME4000_AI_CTRL_REG); |
e55c95a3 GG |
1002 | } |
1003 | ||
b08bfa38 | 1004 | if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) & |
2ec0019a | 1005 | ME4000_IRQ_STATUS_SC) { |
de88924f | 1006 | s->async->events |= COMEDI_CB_EOA; |
e55c95a3 | 1007 | |
b6241fda GS |
1008 | /* |
1009 | * Acquisition is complete, so stop | |
1010 | * conversion and disable all interrupts | |
1011 | */ | |
b08bfa38 | 1012 | tmp = inl(dev->iobase + ME4000_AI_CTRL_REG); |
da772ad9 HS |
1013 | tmp |= ME4000_AI_CTRL_IMMEDIATE_STOP; |
1014 | tmp &= ~(ME4000_AI_CTRL_HF_IRQ | ME4000_AI_CTRL_SC_IRQ); | |
b08bfa38 | 1015 | outl(tmp, dev->iobase + ME4000_AI_CTRL_REG); |
e55c95a3 GG |
1016 | |
1017 | /* Poll data until fifo empty */ | |
a9b586a5 HS |
1018 | while (inl(dev->iobase + ME4000_AI_STATUS_REG) & |
1019 | ME4000_AI_STATUS_EF_DATA) { | |
e55c95a3 | 1020 | /* Read value from data fifo */ |
b08bfa38 | 1021 | lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF; |
e55c95a3 GG |
1022 | lval ^= 0x8000; |
1023 | ||
de88924f | 1024 | if (!comedi_buf_write_samples(s, &lval, 1)) |
e55c95a3 | 1025 | break; |
e55c95a3 GG |
1026 | } |
1027 | ||
1028 | /* Work is done, so reset the interrupt */ | |
da772ad9 | 1029 | tmp |= ME4000_AI_CTRL_SC_IRQ_RESET; |
b08bfa38 | 1030 | outl(tmp, dev->iobase + ME4000_AI_CTRL_REG); |
da772ad9 | 1031 | tmp &= ~ME4000_AI_CTRL_SC_IRQ_RESET; |
b08bfa38 | 1032 | outl(tmp, dev->iobase + ME4000_AI_CTRL_REG); |
e55c95a3 GG |
1033 | } |
1034 | ||
3fa1eb64 | 1035 | comedi_handle_events(dev, s); |
e55c95a3 GG |
1036 | |
1037 | return IRQ_HANDLED; | |
1038 | } | |
1039 | ||
71b5f4f1 | 1040 | static int me4000_ao_insn_write(struct comedi_device *dev, |
0a85b6f0 | 1041 | struct comedi_subdevice *s, |
97e658d1 HS |
1042 | struct comedi_insn *insn, |
1043 | unsigned int *data) | |
e55c95a3 | 1044 | { |
959717a3 | 1045 | unsigned int chan = CR_CHAN(insn->chanspec); |
ac2832f8 | 1046 | unsigned int tmp; |
e55c95a3 | 1047 | |
e55c95a3 | 1048 | /* Stop any running conversion */ |
e1d7ccb7 | 1049 | tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan)); |
7e92a5eb | 1050 | tmp |= ME4000_AO_CTRL_IMMEDIATE_STOP; |
e1d7ccb7 | 1051 | outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan)); |
e55c95a3 GG |
1052 | |
1053 | /* Clear control register and set to single mode */ | |
e1d7ccb7 | 1054 | outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan)); |
e55c95a3 GG |
1055 | |
1056 | /* Write data value */ | |
e1d7ccb7 | 1057 | outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan)); |
e55c95a3 GG |
1058 | |
1059 | /* Store in the mirror */ | |
081b6ee6 | 1060 | s->readback[chan] = data[0]; |
e55c95a3 GG |
1061 | |
1062 | return 1; | |
1063 | } | |
1064 | ||
71b5f4f1 | 1065 | static int me4000_dio_insn_bits(struct comedi_device *dev, |
0a85b6f0 | 1066 | struct comedi_subdevice *s, |
b523c2b2 HS |
1067 | struct comedi_insn *insn, |
1068 | unsigned int *data) | |
e55c95a3 | 1069 | { |
b523c2b2 | 1070 | if (comedi_dio_update_state(s, data)) { |
d6cbe537 | 1071 | outl((s->state >> 0) & 0xFF, |
6c7d2c8b | 1072 | dev->iobase + ME4000_DIO_PORT_0_REG); |
d6cbe537 | 1073 | outl((s->state >> 8) & 0xFF, |
6c7d2c8b | 1074 | dev->iobase + ME4000_DIO_PORT_1_REG); |
d6cbe537 | 1075 | outl((s->state >> 16) & 0xFF, |
6c7d2c8b | 1076 | dev->iobase + ME4000_DIO_PORT_2_REG); |
d6cbe537 | 1077 | outl((s->state >> 24) & 0xFF, |
6c7d2c8b | 1078 | dev->iobase + ME4000_DIO_PORT_3_REG); |
e55c95a3 GG |
1079 | } |
1080 | ||
da755d15 HS |
1081 | data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) | |
1082 | ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) | | |
1083 | ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) | | |
1084 | ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24); | |
e55c95a3 | 1085 | |
a2714e3e | 1086 | return insn->n; |
e55c95a3 GG |
1087 | } |
1088 | ||
71b5f4f1 | 1089 | static int me4000_dio_insn_config(struct comedi_device *dev, |
0a85b6f0 | 1090 | struct comedi_subdevice *s, |
5dacadcc HS |
1091 | struct comedi_insn *insn, |
1092 | unsigned int *data) | |
e55c95a3 | 1093 | { |
5dacadcc HS |
1094 | unsigned int chan = CR_CHAN(insn->chanspec); |
1095 | unsigned int mask; | |
1096 | unsigned int tmp; | |
1097 | int ret; | |
e55c95a3 | 1098 | |
5dacadcc HS |
1099 | if (chan < 8) |
1100 | mask = 0x000000ff; | |
1101 | else if (chan < 16) | |
1102 | mask = 0x0000ff00; | |
1103 | else if (chan < 24) | |
1104 | mask = 0x00ff0000; | |
1105 | else | |
1106 | mask = 0xff000000; | |
e55c95a3 | 1107 | |
5dacadcc HS |
1108 | ret = comedi_dio_insn_config(dev, s, insn, data, mask); |
1109 | if (ret) | |
1110 | return ret; | |
e55c95a3 | 1111 | |
da755d15 | 1112 | tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG); |
55fb972e HS |
1113 | tmp &= ~(ME4000_DIO_CTRL_MODE_0 | ME4000_DIO_CTRL_MODE_1 | |
1114 | ME4000_DIO_CTRL_MODE_2 | ME4000_DIO_CTRL_MODE_3 | | |
1115 | ME4000_DIO_CTRL_MODE_4 | ME4000_DIO_CTRL_MODE_5 | | |
1116 | ME4000_DIO_CTRL_MODE_6 | ME4000_DIO_CTRL_MODE_7); | |
5dacadcc | 1117 | if (s->io_bits & 0x000000ff) |
55fb972e | 1118 | tmp |= ME4000_DIO_CTRL_MODE_0; |
5dacadcc | 1119 | if (s->io_bits & 0x0000ff00) |
55fb972e | 1120 | tmp |= ME4000_DIO_CTRL_MODE_2; |
5dacadcc | 1121 | if (s->io_bits & 0x00ff0000) |
55fb972e | 1122 | tmp |= ME4000_DIO_CTRL_MODE_4; |
5dacadcc | 1123 | if (s->io_bits & 0xff000000) |
55fb972e | 1124 | tmp |= ME4000_DIO_CTRL_MODE_6; |
e55c95a3 | 1125 | |
5dacadcc HS |
1126 | /* |
1127 | * Check for optoisolated ME-4000 version. | |
1128 | * If one the first port is a fixed output | |
1129 | * port and the second is a fixed input port. | |
1130 | */ | |
1131 | if (inl(dev->iobase + ME4000_DIO_DIR_REG)) { | |
1132 | s->io_bits |= 0x000000ff; | |
1133 | s->io_bits &= ~0x0000ff00; | |
55fb972e HS |
1134 | tmp |= ME4000_DIO_CTRL_MODE_0; |
1135 | tmp &= ~(ME4000_DIO_CTRL_MODE_2 | ME4000_DIO_CTRL_MODE_3); | |
e55c95a3 GG |
1136 | } |
1137 | ||
da755d15 | 1138 | outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG); |
e55c95a3 | 1139 | |
5dacadcc | 1140 | return insn->n; |
e55c95a3 GG |
1141 | } |
1142 | ||
a690b7e5 | 1143 | static int me4000_auto_attach(struct comedi_device *dev, |
8c355509 | 1144 | unsigned long context) |
ba5cb4ba | 1145 | { |
750af5e5 | 1146 | struct pci_dev *pcidev = comedi_to_pci_dev(dev); |
49ef9c85 | 1147 | const struct me4000_board *board = NULL; |
3674a87e | 1148 | struct me4000_private *devpriv; |
ba5cb4ba HS |
1149 | struct comedi_subdevice *s; |
1150 | int result; | |
4b2f15f1 | 1151 | |
8c355509 | 1152 | if (context < ARRAY_SIZE(me4000_boards)) |
49ef9c85 HS |
1153 | board = &me4000_boards[context]; |
1154 | if (!board) | |
5f8f8d43 | 1155 | return -ENODEV; |
49ef9c85 HS |
1156 | dev->board_ptr = board; |
1157 | dev->board_name = board->name; | |
4b2f15f1 | 1158 | |
3674a87e HS |
1159 | devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv)); |
1160 | if (!devpriv) | |
c34fa261 | 1161 | return -ENOMEM; |
4b2f15f1 | 1162 | |
818f569f | 1163 | result = comedi_pci_enable(dev); |
ba5cb4ba HS |
1164 | if (result) |
1165 | return result; | |
1166 | ||
3674a87e | 1167 | devpriv->plx_regbase = pci_resource_start(pcidev, 1); |
ba5cb4ba | 1168 | dev->iobase = pci_resource_start(pcidev, 2); |
3674a87e | 1169 | if (!devpriv->plx_regbase || !dev->iobase) |
4b2f15f1 HS |
1170 | return -ENODEV; |
1171 | ||
ac584af5 HS |
1172 | result = comedi_load_firmware(dev, &pcidev->dev, ME4000_FIRMWARE, |
1173 | me4000_xilinx_download, 0); | |
1174 | if (result < 0) | |
4b2f15f1 HS |
1175 | return result; |
1176 | ||
2f348ecd | 1177 | me4000_reset(dev); |
4b2f15f1 | 1178 | |
a9b7ff93 HS |
1179 | if (pcidev->irq > 0) { |
1180 | result = request_irq(pcidev->irq, me4000_ai_isr, IRQF_SHARED, | |
6c7d2c8b | 1181 | dev->board_name, dev); |
8f3f3eb7 | 1182 | if (result == 0) { |
a9b7ff93 | 1183 | dev->irq = pcidev->irq; |
8f3f3eb7 HS |
1184 | |
1185 | /* Enable interrupts on the PLX */ | |
1186 | outl(PLX9052_INTCSR_LI1ENAB | PLX9052_INTCSR_LI1POL | | |
1187 | PLX9052_INTCSR_PCIENAB, | |
1188 | devpriv->plx_regbase + PLX9052_INTCSR); | |
1189 | } | |
a9b7ff93 HS |
1190 | } |
1191 | ||
8b6c5694 HS |
1192 | result = comedi_alloc_subdevices(dev, 4); |
1193 | if (result) | |
1194 | return result; | |
3af09830 | 1195 | |
14aa4789 | 1196 | /* Analog Input subdevice */ |
8aaf2717 | 1197 | s = &dev->subdevices[0]; |
14aa4789 | 1198 | s->type = COMEDI_SUBD_AI; |
31bebc03 | 1199 | s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND; |
56f71de6 | 1200 | if (board->can_do_diff_ai) |
31bebc03 | 1201 | s->subdev_flags |= SDF_DIFF; |
14aa4789 HS |
1202 | s->n_chan = board->ai_nchan; |
1203 | s->maxdata = 0xffff; | |
1204 | s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT; | |
1205 | s->range_table = &me4000_ai_range; | |
1206 | s->insn_read = me4000_ai_insn_read; | |
1207 | ||
1208 | if (dev->irq) { | |
1209 | dev->read_subdev = s; | |
1210 | s->subdev_flags |= SDF_CMD_READ; | |
1211 | s->cancel = me4000_ai_cancel; | |
1212 | s->do_cmdtest = me4000_ai_do_cmd_test; | |
1213 | s->do_cmd = me4000_ai_do_cmd; | |
3af09830 HS |
1214 | } |
1215 | ||
1216 | /*========================================================================= | |
1217 | Analog output subdevice | |
1218 | ========================================================================*/ | |
1219 | ||
8aaf2717 | 1220 | s = &dev->subdevices[1]; |
3af09830 | 1221 | |
aed9b663 | 1222 | if (board->has_ao) { |
3af09830 | 1223 | s->type = COMEDI_SUBD_AO; |
ef49d832 | 1224 | s->subdev_flags = SDF_WRITABLE | SDF_COMMON | SDF_GROUND; |
aed9b663 | 1225 | s->n_chan = 4; |
3af09830 | 1226 | s->maxdata = 0xFFFF; /* 16 bit DAC */ |
4683f9f8 | 1227 | s->range_table = &range_bipolar10; |
3af09830 | 1228 | s->insn_write = me4000_ao_insn_write; |
081b6ee6 HS |
1229 | |
1230 | result = comedi_alloc_subdev_readback(s); | |
1231 | if (result) | |
1232 | return result; | |
3af09830 HS |
1233 | } else { |
1234 | s->type = COMEDI_SUBD_UNUSED; | |
1235 | } | |
1236 | ||
d8553701 | 1237 | /* Digital I/O subdevice */ |
8aaf2717 | 1238 | s = &dev->subdevices[2]; |
d8553701 HS |
1239 | s->type = COMEDI_SUBD_DIO; |
1240 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE; | |
1241 | s->n_chan = 32; | |
1242 | s->maxdata = 1; | |
1243 | s->range_table = &range_digital; | |
1244 | s->insn_bits = me4000_dio_insn_bits; | |
1245 | s->insn_config = me4000_dio_insn_config; | |
3af09830 HS |
1246 | |
1247 | /* | |
1248 | * Check for optoisolated ME-4000 version. If one the first | |
1249 | * port is a fixed output port and the second is a fixed input port. | |
1250 | */ | |
da755d15 | 1251 | if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) { |
3af09830 | 1252 | s->io_bits |= 0xFF; |
55fb972e | 1253 | outl(ME4000_DIO_CTRL_MODE_0, |
6c7d2c8b | 1254 | dev->iobase + ME4000_DIO_DIR_REG); |
3af09830 HS |
1255 | } |
1256 | ||
d92d39d9 | 1257 | /* Counter subdevice (8254) */ |
8aaf2717 | 1258 | s = &dev->subdevices[3]; |
49ef9c85 | 1259 | if (board->has_counter) { |
d92d39d9 HS |
1260 | unsigned long timer_base = pci_resource_start(pcidev, 3); |
1261 | ||
1262 | if (!timer_base) | |
1263 | return -ENODEV; | |
1264 | ||
1265 | dev->pacer = comedi_8254_init(timer_base, 0, I8254_IO8, 0); | |
1266 | if (!dev->pacer) | |
1267 | return -ENOMEM; | |
1268 | ||
1269 | comedi_8254_subdevice_init(s, dev->pacer); | |
3af09830 HS |
1270 | } else { |
1271 | s->type = COMEDI_SUBD_UNUSED; | |
1272 | } | |
1273 | ||
1274 | return 0; | |
1275 | } | |
1276 | ||
484ecc95 | 1277 | static void me4000_detach(struct comedi_device *dev) |
3af09830 | 1278 | { |
7f072f54 HS |
1279 | if (dev->iobase) |
1280 | me4000_reset(dev); | |
aac307f9 | 1281 | comedi_pci_detach(dev); |
3af09830 HS |
1282 | } |
1283 | ||
75e6301b | 1284 | static struct comedi_driver me4000_driver = { |
3af09830 HS |
1285 | .driver_name = "me4000", |
1286 | .module = THIS_MODULE, | |
750af5e5 | 1287 | .auto_attach = me4000_auto_attach, |
3af09830 HS |
1288 | .detach = me4000_detach, |
1289 | }; | |
1290 | ||
a690b7e5 | 1291 | static int me4000_pci_probe(struct pci_dev *dev, |
b8f4ac23 | 1292 | const struct pci_device_id *id) |
727b286b | 1293 | { |
b8f4ac23 | 1294 | return comedi_pci_auto_config(dev, &me4000_driver, id->driver_data); |
727b286b AT |
1295 | } |
1296 | ||
41e043fc | 1297 | static const struct pci_device_id me4000_pci_table[] = { |
8c355509 HS |
1298 | { PCI_VDEVICE(MEILHAUS, 0x4650), BOARD_ME4650 }, |
1299 | { PCI_VDEVICE(MEILHAUS, 0x4660), BOARD_ME4660 }, | |
1300 | { PCI_VDEVICE(MEILHAUS, 0x4661), BOARD_ME4660I }, | |
1301 | { PCI_VDEVICE(MEILHAUS, 0x4662), BOARD_ME4660S }, | |
1302 | { PCI_VDEVICE(MEILHAUS, 0x4663), BOARD_ME4660IS }, | |
1303 | { PCI_VDEVICE(MEILHAUS, 0x4670), BOARD_ME4670 }, | |
1304 | { PCI_VDEVICE(MEILHAUS, 0x4671), BOARD_ME4670I }, | |
1305 | { PCI_VDEVICE(MEILHAUS, 0x4672), BOARD_ME4670S }, | |
1306 | { PCI_VDEVICE(MEILHAUS, 0x4673), BOARD_ME4670IS }, | |
1307 | { PCI_VDEVICE(MEILHAUS, 0x4680), BOARD_ME4680 }, | |
1308 | { PCI_VDEVICE(MEILHAUS, 0x4681), BOARD_ME4680I }, | |
1309 | { PCI_VDEVICE(MEILHAUS, 0x4682), BOARD_ME4680S }, | |
1310 | { PCI_VDEVICE(MEILHAUS, 0x4683), BOARD_ME4680IS }, | |
1311 | { 0 } | |
3af09830 HS |
1312 | }; |
1313 | MODULE_DEVICE_TABLE(pci, me4000_pci_table); | |
1314 | ||
75e6301b HS |
1315 | static struct pci_driver me4000_pci_driver = { |
1316 | .name = "me4000", | |
3af09830 | 1317 | .id_table = me4000_pci_table, |
75e6301b | 1318 | .probe = me4000_pci_probe, |
9901a4d7 | 1319 | .remove = comedi_pci_auto_unconfig, |
727b286b | 1320 | }; |
75e6301b | 1321 | module_comedi_pci_driver(me4000_driver, me4000_pci_driver); |
90f703d3 AT |
1322 | |
1323 | MODULE_AUTHOR("Comedi http://www.comedi.org"); | |
1324 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
1325 | MODULE_LICENSE("GPL"); | |
ac584af5 | 1326 | MODULE_FIRMWARE(ME4000_FIRMWARE); |