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staging: comedi: me4000: fix me4000_ai_insn_read()
[deliverable/linux.git] / drivers / staging / comedi / drivers / me4000.c
CommitLineData
e55c95a3
GG		 1/*
2 comedi/drivers/me4000.c
3 Source code for the Meilhaus ME-4000 board family.
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
e55c95a3
GG		 17 */
18/*
19Driver: me4000
20Description: Meilhaus ME-4000 series boards
21Devices: [Meilhaus] ME-4650 (me4000), ME-4670i, ME-4680, ME-4680i, ME-4680is
22Author: gg (Guenter Gebhardt <g.gebhardt@meilhaus.com>)
23Updated: Mon, 18 Mar 2002 15:34:01 -0800
24Status: broken (no support for loading firmware)
25
26Supports:
27
28 - Analog Input
29 - Analog Output
30 - Digital I/O
31 - Counter
32
5f8f8d43 33Configuration Options: not applicable, uses PCI auto config
e55c95a3
GG		 34
35The firmware required by these boards is available in the
36comedi_nonfree_firmware tarball available from
37http://www.comedi.org. However, the driver's support for
38loading the firmware through comedi_config is currently
39broken.
40
41 */
42
ce157f80 43#include <linux/module.h>
e55c95a3 44#include <linux/delay.h>
33782dd5 45#include <linux/interrupt.h>
e55c95a3 46
f2e8e285 47#include "../comedi_pci.h"
33782dd5 48
d92d39d9 49#include "comedi_8254.h"
58af6b92 50#include "plx9052.h"
81dd1811 51
ac584af5 52#define ME4000_FIRMWARE "me4000_firmware.bin"
e55c95a3 53
81dd1811
HS		 54/*
55 * ME4000 Register map and bit defines
56 */
57#define ME4000_AO_CHAN(x) ((x) * 0x18)
58
59#define ME4000_AO_CTRL_REG(x) (0x00 + ME4000_AO_CHAN(x))
60#define ME4000_AO_CTRL_BIT_MODE_0 (1 << 0)
61#define ME4000_AO_CTRL_BIT_MODE_1 (1 << 1)
62#define ME4000_AO_CTRL_MASK_MODE (3 << 0)
63#define ME4000_AO_CTRL_BIT_STOP (1 << 2)
64#define ME4000_AO_CTRL_BIT_ENABLE_FIFO (1 << 3)
65#define ME4000_AO_CTRL_BIT_ENABLE_EX_TRIG (1 << 4)
66#define ME4000_AO_CTRL_BIT_EX_TRIG_EDGE (1 << 5)
67#define ME4000_AO_CTRL_BIT_IMMEDIATE_STOP (1 << 7)
68#define ME4000_AO_CTRL_BIT_ENABLE_DO (1 << 8)
69#define ME4000_AO_CTRL_BIT_ENABLE_IRQ (1 << 9)
70#define ME4000_AO_CTRL_BIT_RESET_IRQ (1 << 10)
71#define ME4000_AO_STATUS_REG(x) (0x04 + ME4000_AO_CHAN(x))
72#define ME4000_AO_STATUS_BIT_FSM (1 << 0)
73#define ME4000_AO_STATUS_BIT_FF (1 << 1)
74#define ME4000_AO_STATUS_BIT_HF (1 << 2)
75#define ME4000_AO_STATUS_BIT_EF (1 << 3)
76#define ME4000_AO_FIFO_REG(x) (0x08 + ME4000_AO_CHAN(x))
77#define ME4000_AO_SINGLE_REG(x) (0x0c + ME4000_AO_CHAN(x))
78#define ME4000_AO_TIMER_REG(x) (0x10 + ME4000_AO_CHAN(x))
79#define ME4000_AI_CTRL_REG 0x74
80#define ME4000_AI_STATUS_REG 0x74
81#define ME4000_AI_CTRL_BIT_MODE_0 (1 << 0)
82#define ME4000_AI_CTRL_BIT_MODE_1 (1 << 1)
83#define ME4000_AI_CTRL_BIT_MODE_2 (1 << 2)
84#define ME4000_AI_CTRL_BIT_SAMPLE_HOLD (1 << 3)
85#define ME4000_AI_CTRL_BIT_IMMEDIATE_STOP (1 << 4)
86#define ME4000_AI_CTRL_BIT_STOP (1 << 5)
87#define ME4000_AI_CTRL_BIT_CHANNEL_FIFO (1 << 6)
88#define ME4000_AI_CTRL_BIT_DATA_FIFO (1 << 7)
89#define ME4000_AI_CTRL_BIT_FULLSCALE (1 << 8)
90#define ME4000_AI_CTRL_BIT_OFFSET (1 << 9)
91#define ME4000_AI_CTRL_BIT_EX_TRIG_ANALOG (1 << 10)
92#define ME4000_AI_CTRL_BIT_EX_TRIG (1 << 11)
93#define ME4000_AI_CTRL_BIT_EX_TRIG_FALLING (1 << 12)
94#define ME4000_AI_CTRL_BIT_EX_IRQ (1 << 13)
95#define ME4000_AI_CTRL_BIT_EX_IRQ_RESET (1 << 14)
96#define ME4000_AI_CTRL_BIT_LE_IRQ (1 << 15)
97#define ME4000_AI_CTRL_BIT_LE_IRQ_RESET (1 << 16)
98#define ME4000_AI_CTRL_BIT_HF_IRQ (1 << 17)
99#define ME4000_AI_CTRL_BIT_HF_IRQ_RESET (1 << 18)
100#define ME4000_AI_CTRL_BIT_SC_IRQ (1 << 19)
101#define ME4000_AI_CTRL_BIT_SC_IRQ_RESET (1 << 20)
102#define ME4000_AI_CTRL_BIT_SC_RELOAD (1 << 21)
103#define ME4000_AI_STATUS_BIT_EF_CHANNEL (1 << 22)
104#define ME4000_AI_STATUS_BIT_HF_CHANNEL (1 << 23)
105#define ME4000_AI_STATUS_BIT_FF_CHANNEL (1 << 24)
106#define ME4000_AI_STATUS_BIT_EF_DATA (1 << 25)
107#define ME4000_AI_STATUS_BIT_HF_DATA (1 << 26)
108#define ME4000_AI_STATUS_BIT_FF_DATA (1 << 27)
109#define ME4000_AI_STATUS_BIT_LE (1 << 28)
110#define ME4000_AI_STATUS_BIT_FSM (1 << 29)
111#define ME4000_AI_CTRL_BIT_EX_TRIG_BOTH (1 << 31)
112#define ME4000_AI_CHANNEL_LIST_REG 0x78
a0861f87 113#define ME4000_AI_LIST_INPUT_DIFFERENTIAL BIT(5)
245bd462 114#define ME4000_AI_LIST_RANGE(x) ((3 - ((x) & 3)) << 6)
a0861f87 115#define ME4000_AI_LIST_LAST_ENTRY BIT(8)
81dd1811
HS		 116#define ME4000_AI_DATA_REG 0x7c
117#define ME4000_AI_CHAN_TIMER_REG 0x80
118#define ME4000_AI_CHAN_PRE_TIMER_REG 0x84
119#define ME4000_AI_SCAN_TIMER_LOW_REG 0x88
120#define ME4000_AI_SCAN_TIMER_HIGH_REG 0x8c
121#define ME4000_AI_SCAN_PRE_TIMER_LOW_REG 0x90
122#define ME4000_AI_SCAN_PRE_TIMER_HIGH_REG 0x94
123#define ME4000_AI_START_REG 0x98
124#define ME4000_IRQ_STATUS_REG 0x9c
125#define ME4000_IRQ_STATUS_BIT_EX (1 << 0)
126#define ME4000_IRQ_STATUS_BIT_LE (1 << 1)
127#define ME4000_IRQ_STATUS_BIT_AI_HF (1 << 2)
128#define ME4000_IRQ_STATUS_BIT_AO_0_HF (1 << 3)
129#define ME4000_IRQ_STATUS_BIT_AO_1_HF (1 << 4)
130#define ME4000_IRQ_STATUS_BIT_AO_2_HF (1 << 5)
131#define ME4000_IRQ_STATUS_BIT_AO_3_HF (1 << 6)
132#define ME4000_IRQ_STATUS_BIT_SC (1 << 7)
133#define ME4000_DIO_PORT_0_REG 0xa0
134#define ME4000_DIO_PORT_1_REG 0xa4
135#define ME4000_DIO_PORT_2_REG 0xa8
136#define ME4000_DIO_PORT_3_REG 0xac
137#define ME4000_DIO_DIR_REG 0xb0
138#define ME4000_AO_LOADSETREG_XX 0xb4
139#define ME4000_DIO_CTRL_REG 0xb8
140#define ME4000_DIO_CTRL_BIT_MODE_0 (1 << 0)
141#define ME4000_DIO_CTRL_BIT_MODE_1 (1 << 1)
142#define ME4000_DIO_CTRL_BIT_MODE_2 (1 << 2)
143#define ME4000_DIO_CTRL_BIT_MODE_3 (1 << 3)
144#define ME4000_DIO_CTRL_BIT_MODE_4 (1 << 4)
145#define ME4000_DIO_CTRL_BIT_MODE_5 (1 << 5)
146#define ME4000_DIO_CTRL_BIT_MODE_6 (1 << 6)
147#define ME4000_DIO_CTRL_BIT_MODE_7 (1 << 7)
148#define ME4000_DIO_CTRL_BIT_FUNCTION_0 (1 << 8)
149#define ME4000_DIO_CTRL_BIT_FUNCTION_1 (1 << 9)
150#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_0 (1 << 10)
151#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_1 (1 << 11)
152#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_2 (1 << 12)
153#define ME4000_DIO_CTRL_BIT_FIFO_HIGH_3 (1 << 13)
154#define ME4000_AO_DEMUX_ADJUST_REG 0xbc
155#define ME4000_AO_DEMUX_ADJUST_VALUE 0x4c
156#define ME4000_AI_SAMPLE_COUNTER_REG 0xc0
157
81dd1811
HS		 158#define ME4000_AI_FIFO_COUNT 2048
159
160#define ME4000_AI_MIN_TICKS 66
161#define ME4000_AI_MIN_SAMPLE_TIME 2000
81dd1811
HS		 162
163#define ME4000_AI_CHANNEL_LIST_COUNT 1024
164
3674a87e 165struct me4000_private {
cc6f3336 166 unsigned long plx_regbase;
cc6f3336
HS		 167};
168
8c355509
HS		 169enum me4000_boardid {
170 BOARD_ME4650,
171 BOARD_ME4660,
172 BOARD_ME4660I,
173 BOARD_ME4660S,
174 BOARD_ME4660IS,
175 BOARD_ME4670,
176 BOARD_ME4670I,
177 BOARD_ME4670S,
178 BOARD_ME4670IS,
179 BOARD_ME4680,
180 BOARD_ME4680I,
181 BOARD_ME4680S,
182 BOARD_ME4680IS,
183};
184
06b60981
HS		 185struct me4000_board {
186 const char *name;
06b60981 187 int ai_nchan;
56f71de6 188 unsigned int can_do_diff_ai:1;
e5f66350 189 unsigned int can_do_sh_ai:1; /* sample & hold (8 channels) */
13a463ae 190 unsigned int ex_trig_analog:1;
aed9b663 191 unsigned int has_ao:1;
77714d31 192 unsigned int has_ao_fifo:1;
13a463ae 193 unsigned int has_counter:1;
06b60981
HS		 194};
195
27f4caaa 196static const struct me4000_board me4000_boards[] = {
8c355509 197 [BOARD_ME4650] = {
035d432a 198 .name = "ME-4650",
6ba8dfef 199 .ai_nchan = 16,
8c355509
HS		 200 },
201 [BOARD_ME4660] = {
035d432a 202 .name = "ME-4660",
6ba8dfef 203 .ai_nchan = 32,
56f71de6 204 .can_do_diff_ai = 1,
eedf4299 205 .has_counter = 1,
8c355509
HS		 206 },
207 [BOARD_ME4660I] = {
035d432a 208 .name = "ME-4660i",
6ba8dfef 209 .ai_nchan = 32,
56f71de6 210 .can_do_diff_ai = 1,
eedf4299 211 .has_counter = 1,
8c355509
HS		 212 },
213 [BOARD_ME4660S] = {
035d432a 214 .name = "ME-4660s",
6ba8dfef 215 .ai_nchan = 32,
56f71de6 216 .can_do_diff_ai = 1,
e5f66350 217 .can_do_sh_ai = 1,
eedf4299 218 .has_counter = 1,
8c355509
HS		 219 },
220 [BOARD_ME4660IS] = {
035d432a 221 .name = "ME-4660is",
6ba8dfef 222 .ai_nchan = 32,
56f71de6 223 .can_do_diff_ai = 1,
e5f66350 224 .can_do_sh_ai = 1,
eedf4299 225 .has_counter = 1,
8c355509
HS		 226 },
227 [BOARD_ME4670] = {
035d432a 228 .name = "ME-4670",
6ba8dfef 229 .ai_nchan = 32,
56f71de6 230 .can_do_diff_ai = 1,
6ba8dfef 231 .ex_trig_analog = 1,
aed9b663 232 .has_ao = 1,
eedf4299 233 .has_counter = 1,
8c355509
HS		 234 },
235 [BOARD_ME4670I] = {
035d432a 236 .name = "ME-4670i",
6ba8dfef 237 .ai_nchan = 32,
56f71de6 238 .can_do_diff_ai = 1,
6ba8dfef 239 .ex_trig_analog = 1,
aed9b663 240 .has_ao = 1,
eedf4299 241 .has_counter = 1,
8c355509
HS		 242 },
243 [BOARD_ME4670S] = {
035d432a 244 .name = "ME-4670s",
6ba8dfef 245 .ai_nchan = 32,
56f71de6 246 .can_do_diff_ai = 1,
e5f66350 247 .can_do_sh_ai = 1,
6ba8dfef 248 .ex_trig_analog = 1,
aed9b663 249 .has_ao = 1,
eedf4299 250 .has_counter = 1,
8c355509
HS		 251 },
252 [BOARD_ME4670IS] = {
035d432a 253 .name = "ME-4670is",
6ba8dfef 254 .ai_nchan = 32,
56f71de6 255 .can_do_diff_ai = 1,
e5f66350 256 .can_do_sh_ai = 1,
6ba8dfef 257 .ex_trig_analog = 1,
aed9b663 258 .has_ao = 1,
eedf4299 259 .has_counter = 1,
8c355509
HS		 260 },
261 [BOARD_ME4680] = {
035d432a 262 .name = "ME-4680",
6ba8dfef 263 .ai_nchan = 32,
56f71de6 264 .can_do_diff_ai = 1,
6ba8dfef 265 .ex_trig_analog = 1,
aed9b663 266 .has_ao = 1,
77714d31 267 .has_ao_fifo = 1,
eedf4299 268 .has_counter = 1,
8c355509
HS		 269 },
270 [BOARD_ME4680I] = {
035d432a 271 .name = "ME-4680i",
6ba8dfef 272 .ai_nchan = 32,
56f71de6 273 .can_do_diff_ai = 1,
6ba8dfef 274 .ex_trig_analog = 1,
aed9b663 275 .has_ao = 1,
77714d31 276 .has_ao_fifo = 1,
eedf4299 277 .has_counter = 1,
8c355509
HS		 278 },
279 [BOARD_ME4680S] = {
035d432a 280 .name = "ME-4680s",
6ba8dfef 281 .ai_nchan = 32,
56f71de6 282 .can_do_diff_ai = 1,
e5f66350 283 .can_do_sh_ai = 1,
6ba8dfef 284 .ex_trig_analog = 1,
aed9b663 285 .has_ao = 1,
77714d31 286 .has_ao_fifo = 1,
eedf4299 287 .has_counter = 1,
8c355509
HS		 288 },
289 [BOARD_ME4680IS] = {
035d432a 290 .name = "ME-4680is",
6ba8dfef 291 .ai_nchan = 32,
56f71de6 292 .can_do_diff_ai = 1,
e5f66350 293 .can_do_sh_ai = 1,
6ba8dfef 294 .ex_trig_analog = 1,
aed9b663 295 .has_ao = 1,
77714d31 296 .has_ao_fifo = 1,
eedf4299 297 .has_counter = 1,
035d432a 298 },
e55c95a3
GG		 299};
300
245bd462
HS		 301/*
302 * NOTE: the ranges here are inverted compared to the values
303 * written to the ME4000_AI_CHANNEL_LIST_REG,
304 *
305 * The ME4000_AI_LIST_RANGE() macro handles the inversion.
306 */
9ced1de6 307static const struct comedi_lrange me4000_ai_range = {
93626a45
HS		 308 4, {
309 UNI_RANGE(2.5),
310 UNI_RANGE(10),
311 BIP_RANGE(2.5),
312 BIP_RANGE(10)
313 }
e55c95a3
GG		 314};
315
ac584af5
HS		 316static int me4000_xilinx_download(struct comedi_device *dev,
317 const u8 *data, size_t size,
318 unsigned long context)
e55c95a3 319{
fe531d12 320 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
3674a87e 321 struct me4000_private *devpriv = dev->private;
fe531d12 322 unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
ac584af5
HS		 323 unsigned int file_length;
324 unsigned int val;
325 unsigned int i;
e55c95a3 326
fe531d12
HS		 327 if (!xilinx_iobase)
328 return -ENODEV;
329
e55c95a3
GG		 330 /*
331 * Set PLX local interrupt 2 polarity to high.
332 * Interrupt is thrown by init pin of xilinx.
333 */
3674a87e 334 outl(PLX9052_INTCSR_LI2POL, devpriv->plx_regbase + PLX9052_INTCSR);
e55c95a3
GG		 335
336 /* Set /CS and /WRITE of the Xilinx */
3674a87e 337 val = inl(devpriv->plx_regbase + PLX9052_CNTRL);
ac584af5 338 val |= PLX9052_CNTRL_UIO2_DATA;
3674a87e 339 outl(val, devpriv->plx_regbase + PLX9052_CNTRL);
e55c95a3
GG		 340
341 /* Init Xilinx with CS1 */
fe531d12 342 inb(xilinx_iobase + 0xC8);
e55c95a3
GG		 343
344 /* Wait until /INIT pin is set */
345 udelay(20);
3674a87e 346 val = inl(devpriv->plx_regbase + PLX9052_INTCSR);
ac584af5 347 if (!(val & PLX9052_INTCSR_LI2STAT)) {
5da80ee8 348 dev_err(dev->class_dev, "Can't init Xilinx\n");
e55c95a3
GG		 349 return -EIO;
350 }
351
352 /* Reset /CS and /WRITE of the Xilinx */
3674a87e 353 val = inl(devpriv->plx_regbase + PLX9052_CNTRL);
ac584af5 354 val &= ~PLX9052_CNTRL_UIO2_DATA;
3674a87e 355 outl(val, devpriv->plx_regbase + PLX9052_CNTRL);
e55c95a3 356
ac584af5
HS		 357 /* Download Xilinx firmware */
358 file_length = (((unsigned int)data[0] & 0xff) << 24) +
359 (((unsigned int)data[1] & 0xff) << 16) +
360 (((unsigned int)data[2] & 0xff) << 8) +
361 ((unsigned int)data[3] & 0xff);
362 udelay(10);
e55c95a3 363
ac584af5
HS		 364 for (i = 0; i < file_length; i++) {
365 outb(data[16 + i], xilinx_iobase);
366 udelay(10);
367
368 /* Check if BUSY flag is low */
3674a87e 369 val = inl(devpriv->plx_regbase + PLX9052_CNTRL);
ac584af5
HS		 370 if (val & PLX9052_CNTRL_UIO1_DATA) {
371 dev_err(dev->class_dev,
372 "Xilinx is still busy (i = %d)\n", i);
373 return -EIO;
e55c95a3
GG		 374 }
375 }
376
377 /* If done flag is high download was successful */
3674a87e 378 val = inl(devpriv->plx_regbase + PLX9052_CNTRL);
ac584af5 379 if (!(val & PLX9052_CNTRL_UIO0_DATA)) {
5da80ee8
HS		 380 dev_err(dev->class_dev, "DONE flag is not set\n");
381 dev_err(dev->class_dev, "Download not successful\n");
e55c95a3
GG		 382 return -EIO;
383 }
384
385 /* Set /CS and /WRITE */
3674a87e 386 val = inl(devpriv->plx_regbase + PLX9052_CNTRL);
ac584af5 387 val |= PLX9052_CNTRL_UIO2_DATA;
3674a87e 388 outl(val, devpriv->plx_regbase + PLX9052_CNTRL);
e55c95a3
GG		 389
390 return 0;
391}
392
2f348ecd 393static void me4000_reset(struct comedi_device *dev)
e55c95a3 394{
3674a87e 395 struct me4000_private *devpriv = dev->private;
ac2832f8 396 unsigned int val;
e1d7ccb7 397 int chan;
e55c95a3 398
e55c95a3 399 /* Make a hardware reset */
3674a87e 400 val = inl(devpriv->plx_regbase + PLX9052_CNTRL);
4564cfd0 401 val |= PLX9052_CNTRL_PCI_RESET;
3674a87e 402 outl(val, devpriv->plx_regbase + PLX9052_CNTRL);
4564cfd0 403 val &= ~PLX9052_CNTRL_PCI_RESET;
3674a87e 404 outl(val, devpriv->plx_regbase + PLX9052_CNTRL);
e55c95a3
GG		 405
406 /* 0x8000 to the DACs means an output voltage of 0V */
e1d7ccb7
HS		 407 for (chan = 0; chan < 4; chan++)
408 outl(0x8000, dev->iobase + ME4000_AO_SINGLE_REG(chan));
e55c95a3
GG		 409
410 /* Set both stop bits in the analog input control register */
d6cbe537 411 outl(ME4000_AI_CTRL_BIT_IMMEDIATE_STOP | ME4000_AI_CTRL_BIT_STOP,
6c7d2c8b 412 dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 413
414 /* Set both stop bits in the analog output control register */
e1d7ccb7
HS		 415 val = ME4000_AO_CTRL_BIT_IMMEDIATE_STOP | ME4000_AO_CTRL_BIT_STOP;
416 for (chan = 0; chan < 4; chan++)
417 outl(val, dev->iobase + ME4000_AO_CTRL_REG(chan));
e55c95a3
GG		 418
419 /* Enable interrupts on the PLX */
58af6b92
HS		 420 outl(PLX9052_INTCSR_LI1ENAB |
421 PLX9052_INTCSR_LI1POL |
3674a87e 422 PLX9052_INTCSR_PCIENAB, devpriv->plx_regbase + PLX9052_INTCSR);
e55c95a3
GG		 423
424 /* Set the adustment register for AO demux */
d6cbe537 425 outl(ME4000_AO_DEMUX_ADJUST_VALUE,
6c7d2c8b 426 dev->iobase + ME4000_AO_DEMUX_ADJUST_REG);
e55c95a3 427
b6241fda
GS		 428 /*
429 * Set digital I/O direction for port 0
430 * to output on isolated versions
431 */
362bcbde
HS		 432 if (!(inl(dev->iobase + ME4000_DIO_DIR_REG) & 0x1))
433 outl(0x1, dev->iobase + ME4000_DIO_CTRL_REG);
e55c95a3
GG		 434}
435
023c129f
HS		 436static int me4000_ai_eoc(struct comedi_device *dev,
437 struct comedi_subdevice *s,
438 struct comedi_insn *insn,
439 unsigned long context)
440{
441 unsigned int status;
442
443 status = inl(dev->iobase + ME4000_AI_STATUS_REG);
444 if (status & ME4000_AI_STATUS_BIT_EF_DATA)
445 return 0;
446 return -EBUSY;
447}
e55c95a3 448
71b5f4f1 449static int me4000_ai_insn_read(struct comedi_device *dev,
1a023870
HS		 450 struct comedi_subdevice *s,
451 struct comedi_insn *insn,
452 unsigned int *data)
e55c95a3 453{
e55c95a3
GG		 454 int chan = CR_CHAN(insn->chanspec);
455 int rang = CR_RANGE(insn->chanspec);
456 int aref = CR_AREF(insn->chanspec);
ac2832f8
IA		 457 unsigned int entry = 0;
458 unsigned int tmp;
023c129f 459 int ret;
fb7891e4 460 int i;
e55c95a3 461
245bd462 462 entry |= ME4000_AI_LIST_RANGE(rang);
271f5aa0
HS		 463 entry |= chan;
464 if (aref == AREF_DIFF) {
1a023870
HS		 465 if (!(s->subdev_flags && SDF_DIFF)) {
466 dev_err(dev->class_dev,
467 "Differential inputs are not available\n");
468 return -EINVAL;
469 }
470
e55c95a3 471 if (rang == 0 || rang == 1) {
5da80ee8
HS		 472 dev_err(dev->class_dev,
473 "Range must be bipolar when aref = diff\n");
e55c95a3
GG		 474 return -EINVAL;
475 }
476
1a023870 477 if (chan >= (s->n_chan / 2)) {
5da80ee8
HS		 478 dev_err(dev->class_dev,
479 "Analog input is not available\n");
e55c95a3
GG		 480 return -EINVAL;
481 }
271f5aa0 482 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
e55c95a3
GG		 483 }
484
485 entry |= ME4000_AI_LIST_LAST_ENTRY;
486
487 /* Clear channel list, data fifo and both stop bits */
b08bfa38 488 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3 489 tmp &= ~(ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
0a85b6f0
MT		 490 ME4000_AI_CTRL_BIT_DATA_FIFO |
491 ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
b08bfa38 492 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 493
494 /* Set the acquisition mode to single */
495 tmp &= ~(ME4000_AI_CTRL_BIT_MODE_0 | ME4000_AI_CTRL_BIT_MODE_1 |
0a85b6f0 496 ME4000_AI_CTRL_BIT_MODE_2);
b08bfa38 497 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 498
499 /* Enable channel list and data fifo */
500 tmp |= ME4000_AI_CTRL_BIT_CHANNEL_FIFO | ME4000_AI_CTRL_BIT_DATA_FIFO;
b08bfa38 501 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 502
503 /* Generate channel list entry */
b08bfa38 504 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
e55c95a3
GG		 505
506 /* Set the timer to maximum sample rate */
b08bfa38
HS		 507 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
508 outl(ME4000_AI_MIN_TICKS, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
e55c95a3 509
fb7891e4
HS		 510 for (i = 0; i < insn->n; i++) {
511 unsigned int val;
e55c95a3 512
fb7891e4
HS		 513 /* start conversion by dummy read */
514 inl(dev->iobase + ME4000_AI_START_REG);
e55c95a3 515
fb7891e4
HS		 516 ret = comedi_timeout(dev, s, insn, me4000_ai_eoc, 0);
517 if (ret)
518 return ret;
519
520 /* read two's complement value and munge to offset binary */
521 val = inl(dev->iobase + ME4000_AI_DATA_REG);
522 data[i] = comedi_offset_munge(s, val);
523 }
e55c95a3 524
fb7891e4 525 return insn->n;
e55c95a3
GG		 526}
527
0a85b6f0
MT		 528static int me4000_ai_cancel(struct comedi_device *dev,
529 struct comedi_subdevice *s)
e55c95a3 530{
ac2832f8 531 unsigned int tmp;
e55c95a3 532
e55c95a3 533 /* Stop any running conversion */
b08bfa38 534 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3 535 tmp &= ~(ME4000_AI_CTRL_BIT_STOP | ME4000_AI_CTRL_BIT_IMMEDIATE_STOP);
b08bfa38 536 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 537
538 /* Clear the control register */
b08bfa38 539 outl(0x0, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 540
541 return 0;
542}
543
926e5073
HS		 544static int me4000_ai_check_chanlist(struct comedi_device *dev,
545 struct comedi_subdevice *s,
546 struct comedi_cmd *cmd)
e55c95a3 547{
926e5073 548 unsigned int aref0 = CR_AREF(cmd->chanlist[0]);
e55c95a3
GG		 549 int i;
550
e55c95a3 551 for (i = 0; i < cmd->chanlist_len; i++) {
926e5073
HS		 552 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
553 unsigned int range = CR_RANGE(cmd->chanlist[i]);
554 unsigned int aref = CR_AREF(cmd->chanlist[i]);
555
556 if (aref != aref0) {
557 dev_dbg(dev->class_dev,
5da80ee8 558 "Mode is not equal for all entries\n");
e55c95a3
GG		 559 return -EINVAL;
560 }
e55c95a3 561
a7dab198 562 if (aref == AREF_DIFF) {
4ec85dad
HS		 563 if (!(s->subdev_flags && SDF_DIFF)) {
564 dev_err(dev->class_dev,
565 "Differential inputs are not available\n");
566 return -EINVAL;
567 }
568
569 if (chan >= (s->n_chan / 2)) {
926e5073 570 dev_dbg(dev->class_dev,
5da80ee8 571 "Channel number to high\n");
e55c95a3
GG		 572 return -EINVAL;
573 }
e55c95a3 574
926e5073
HS		 575 if (!comedi_range_is_bipolar(s, range)) {
576 dev_dbg(dev->class_dev,
6c7d2c8b 577 "Bipolar is not selected in differential mode\n");
e55c95a3
GG		 578 return -EINVAL;
579 }
580 }
581 }
582
583 return 0;
584}
585
71b5f4f1 586static int ai_round_cmd_args(struct comedi_device *dev,
0a85b6f0
MT		 587 struct comedi_subdevice *s,
588 struct comedi_cmd *cmd,
589 unsigned int *init_ticks,
590 unsigned int *scan_ticks, unsigned int *chan_ticks)
e55c95a3 591{
e55c95a3
GG		 592 int rest;
593
e55c95a3
GG		 594 *init_ticks = 0;
595 *scan_ticks = 0;
596 *chan_ticks = 0;
597
e55c95a3
GG		 598 if (cmd->start_arg) {
599 *init_ticks = (cmd->start_arg * 33) / 1000;
600 rest = (cmd->start_arg * 33) % 1000;
601
1e00dedc 602 if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) {
82675f35 603 if (rest > 33)
e55c95a3 604 (*init_ticks)++;
1e00dedc 605 } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) {
e55c95a3
GG		 606 if (rest)
607 (*init_ticks)++;
608 }
609 }
610
611 if (cmd->scan_begin_arg) {
612 *scan_ticks = (cmd->scan_begin_arg * 33) / 1000;
613 rest = (cmd->scan_begin_arg * 33) % 1000;
614
1e00dedc 615 if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) {
82675f35 616 if (rest > 33)
e55c95a3 617 (*scan_ticks)++;
1e00dedc 618 } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) {
e55c95a3
GG		 619 if (rest)
620 (*scan_ticks)++;
621 }
622 }
623
624 if (cmd->convert_arg) {
625 *chan_ticks = (cmd->convert_arg * 33) / 1000;
626 rest = (cmd->convert_arg * 33) % 1000;
627
1e00dedc 628 if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_NEAREST) {
82675f35 629 if (rest > 33)
e55c95a3 630 (*chan_ticks)++;
1e00dedc 631 } else if ((cmd->flags & CMDF_ROUND_MASK) == CMDF_ROUND_UP) {
e55c95a3
GG		 632 if (rest)
633 (*chan_ticks)++;
634 }
635 }
636
e55c95a3
GG		 637 return 0;
638}
639
71b5f4f1 640static void ai_write_timer(struct comedi_device *dev,
0a85b6f0
MT		 641 unsigned int init_ticks,
642 unsigned int scan_ticks, unsigned int chan_ticks)
e55c95a3 643{
b08bfa38
HS		 644 outl(init_ticks - 1, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_LOW_REG);
645 outl(0x0, dev->iobase + ME4000_AI_SCAN_PRE_TIMER_HIGH_REG);
e55c95a3
GG		 646
647 if (scan_ticks) {
b08bfa38
HS		 648 outl(scan_ticks - 1, dev->iobase + ME4000_AI_SCAN_TIMER_LOW_REG);
649 outl(0x0, dev->iobase + ME4000_AI_SCAN_TIMER_HIGH_REG);
e55c95a3
GG		 650 }
651
b08bfa38
HS		 652 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_PRE_TIMER_REG);
653 outl(chan_ticks - 1, dev->iobase + ME4000_AI_CHAN_TIMER_REG);
e55c95a3
GG		 654}
655
518c5b64
HS		 656static int me4000_ai_write_chanlist(struct comedi_device *dev,
657 struct comedi_subdevice *s,
658 struct comedi_cmd *cmd)
4b2f15f1 659{
4b2f15f1
HS		 660 int i;
661
662 for (i = 0; i < cmd->chanlist_len; i++) {
518c5b64
HS		 663 unsigned int chan = CR_CHAN(cmd->chanlist[i]);
664 unsigned int range = CR_RANGE(cmd->chanlist[i]);
665 unsigned int aref = CR_AREF(cmd->chanlist[i]);
666 unsigned int entry;
4b2f15f1 667
518c5b64 668 entry = chan | ME4000_AI_LIST_RANGE(range);
4b2f15f1 669
8d44945d 670 if (aref == AREF_DIFF)
4b2f15f1 671 entry |= ME4000_AI_LIST_INPUT_DIFFERENTIAL;
4b2f15f1 672
518c5b64
HS		 673 if (i == (cmd->chanlist_len - 1))
674 entry |= ME4000_AI_LIST_LAST_ENTRY;
675
4b2f15f1
HS		 676 outl(entry, dev->iobase + ME4000_AI_CHANNEL_LIST_REG);
677 }
678
679 return 0;
680}
681
71b5f4f1 682static int ai_prepare(struct comedi_device *dev,
0a85b6f0
MT		 683 struct comedi_subdevice *s,
684 struct comedi_cmd *cmd,
685 unsigned int init_ticks,
686 unsigned int scan_ticks, unsigned int chan_ticks)
e55c95a3 687{
ac2832f8 688 unsigned int tmp = 0;
e55c95a3 689
e55c95a3
GG		 690 /* Write timer arguments */
691 ai_write_timer(dev, init_ticks, scan_ticks, chan_ticks);
692
693 /* Reset control register */
b08bfa38 694 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 695
696 /* Start sources */
697 if ((cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 698 cmd->scan_begin_src == TRIG_TIMER &&
699 cmd->convert_src == TRIG_TIMER) ||
700 (cmd->start_src == TRIG_EXT &&
701 cmd->scan_begin_src == TRIG_FOLLOW &&
702 cmd->convert_src == TRIG_TIMER)) {
e55c95a3 703 tmp = ME4000_AI_CTRL_BIT_MODE_1 |
0a85b6f0
MT		 704 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
705 ME4000_AI_CTRL_BIT_DATA_FIFO;
e55c95a3 706 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 707 cmd->scan_begin_src == TRIG_EXT &&
708 cmd->convert_src == TRIG_TIMER) {
e55c95a3 709 tmp = ME4000_AI_CTRL_BIT_MODE_2 |
0a85b6f0
MT		 710 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
711 ME4000_AI_CTRL_BIT_DATA_FIFO;
e55c95a3 712 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 713 cmd->scan_begin_src == TRIG_EXT &&
714 cmd->convert_src == TRIG_EXT) {
e55c95a3 715 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
0a85b6f0
MT		 716 ME4000_AI_CTRL_BIT_MODE_1 |
717 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
718 ME4000_AI_CTRL_BIT_DATA_FIFO;
e55c95a3
GG		 719 } else {
720 tmp = ME4000_AI_CTRL_BIT_MODE_0 |
0a85b6f0
MT		 721 ME4000_AI_CTRL_BIT_CHANNEL_FIFO |
722 ME4000_AI_CTRL_BIT_DATA_FIFO;
e55c95a3
GG		 723 }
724
725 /* Stop triggers */
726 if (cmd->stop_src == TRIG_COUNT) {
d6cbe537 727 outl(cmd->chanlist_len * cmd->stop_arg,
6c7d2c8b 728 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
e55c95a3
GG		 729 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
730 } else if (cmd->stop_src == TRIG_NONE &&
0a85b6f0 731 cmd->scan_end_src == TRIG_COUNT) {
d6cbe537 732 outl(cmd->scan_end_arg,
6c7d2c8b 733 dev->iobase + ME4000_AI_SAMPLE_COUNTER_REG);
e55c95a3
GG		 734 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ;
735 } else {
736 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ;
737 }
738
739 /* Write the setup to the control register */
b08bfa38 740 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 741
742 /* Write the channel list */
518c5b64 743 me4000_ai_write_chanlist(dev, s, cmd);
e55c95a3
GG		 744
745 return 0;
746}
747
0a85b6f0
MT		 748static int me4000_ai_do_cmd(struct comedi_device *dev,
749 struct comedi_subdevice *s)
e55c95a3
GG		 750{
751 int err;
752 unsigned int init_ticks = 0;
753 unsigned int scan_ticks = 0;
754 unsigned int chan_ticks = 0;
ea6d0d4c 755 struct comedi_cmd *cmd = &s->async->cmd;
e55c95a3 756
e55c95a3
GG		 757 /* Reset the analog input */
758 err = me4000_ai_cancel(dev, s);
759 if (err)
760 return err;
761
762 /* Round the timer arguments */
763 err = ai_round_cmd_args(dev,
0a85b6f0 764 s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
e55c95a3
GG		 765 if (err)
766 return err;
767
768 /* Prepare the AI for acquisition */
769 err = ai_prepare(dev, s, cmd, init_ticks, scan_ticks, chan_ticks);
770 if (err)
771 return err;
772
773 /* Start acquistion by dummy read */
b08bfa38 774 inl(dev->iobase + ME4000_AI_START_REG);
e55c95a3
GG		 775
776 return 0;
777}
778
71b5f4f1 779static int me4000_ai_do_cmd_test(struct comedi_device *dev,
0a85b6f0
MT		 780 struct comedi_subdevice *s,
781 struct comedi_cmd *cmd)
e55c95a3 782{
e55c95a3
GG		 783 unsigned int init_ticks;
784 unsigned int chan_ticks;
785 unsigned int scan_ticks;
786 int err = 0;
787
e55c95a3
GG		 788 /* Round the timer arguments */
789 ai_round_cmd_args(dev, s, cmd, &init_ticks, &scan_ticks, &chan_ticks);
790
27020ffe
HS		 791 /* Step 1 : check if triggers are trivially valid */
792
51ec1db9
IA		 793 err |= comedi_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
794 err |= comedi_check_trigger_src(&cmd->scan_begin_src,
27020ffe 795 TRIG_FOLLOW | TRIG_TIMER | TRIG_EXT);
51ec1db9
IA		 796 err |= comedi_check_trigger_src(&cmd->convert_src,
797 TRIG_TIMER | TRIG_EXT);
798 err |= comedi_check_trigger_src(&cmd->scan_end_src,
27020ffe 799 TRIG_NONE | TRIG_COUNT);
51ec1db9 800 err |= comedi_check_trigger_src(&cmd->stop_src, TRIG_NONE | TRIG_COUNT);
27020ffe 801
82675f35 802 if (err)
e55c95a3 803 return 1;
e55c95a3 804
27020ffe
HS		 805 /* Step 2a : make sure trigger sources are unique */
806
51ec1db9
IA		 807 err |= comedi_check_trigger_is_unique(cmd->start_src);
808 err |= comedi_check_trigger_is_unique(cmd->scan_begin_src);
809 err |= comedi_check_trigger_is_unique(cmd->convert_src);
810 err |= comedi_check_trigger_is_unique(cmd->scan_end_src);
811 err |= comedi_check_trigger_is_unique(cmd->stop_src);
27020ffe
HS		 812
813 /* Step 2b : and mutually compatible */
814
e55c95a3 815 if (cmd->start_src == TRIG_NOW &&
0a85b6f0
MT		 816 cmd->scan_begin_src == TRIG_TIMER &&
817 cmd->convert_src == TRIG_TIMER) {
e55c95a3 818 } else if (cmd->start_src == TRIG_NOW &&
0a85b6f0
MT		 819 cmd->scan_begin_src == TRIG_FOLLOW &&
820 cmd->convert_src == TRIG_TIMER) {
e55c95a3 821 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 822 cmd->scan_begin_src == TRIG_TIMER &&
823 cmd->convert_src == TRIG_TIMER) {
e55c95a3 824 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 825 cmd->scan_begin_src == TRIG_FOLLOW &&
826 cmd->convert_src == TRIG_TIMER) {
e55c95a3 827 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 828 cmd->scan_begin_src == TRIG_EXT &&
829 cmd->convert_src == TRIG_TIMER) {
e55c95a3 830 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 831 cmd->scan_begin_src == TRIG_EXT &&
832 cmd->convert_src == TRIG_EXT) {
e55c95a3 833 } else {
27020ffe 834 err |= -EINVAL;
e55c95a3
GG		 835 }
836
82675f35 837 if (err)
e55c95a3 838 return 2;
e55c95a3 839
8c6c5a69
HS		 840 /* Step 3: check if arguments are trivially valid */
841
51ec1db9 842 err |= comedi_check_trigger_arg_is(&cmd->start_arg, 0);
025b9187 843
e55c95a3 844 if (cmd->chanlist_len < 1) {
e55c95a3 845 cmd->chanlist_len = 1;
8c6c5a69 846 err |= -EINVAL;
e55c95a3
GG		 847 }
848 if (init_ticks < 66) {
e55c95a3 849 cmd->start_arg = 2000;
8c6c5a69 850 err |= -EINVAL;
e55c95a3
GG		 851 }
852 if (scan_ticks && scan_ticks < 67) {
e55c95a3 853 cmd->scan_begin_arg = 2031;
8c6c5a69 854 err |= -EINVAL;
e55c95a3
GG		 855 }
856 if (chan_ticks < 66) {
e55c95a3 857 cmd->convert_arg = 2000;
8c6c5a69 858 err |= -EINVAL;
e55c95a3 859 }
82675f35 860
76af50dd 861 if (cmd->stop_src == TRIG_COUNT)
51ec1db9 862 err |= comedi_check_trigger_arg_min(&cmd->stop_arg, 1);
76af50dd 863 else /* TRIG_NONE */
51ec1db9 864 err |= comedi_check_trigger_arg_is(&cmd->stop_arg, 0);
76af50dd 865
82675f35 866 if (err)
e55c95a3 867 return 3;
e55c95a3
GG		 868
869 /*
870 * Stage 4. Check for argument conflicts.
871 */
872 if (cmd->start_src == TRIG_NOW &&
0a85b6f0
MT		 873 cmd->scan_begin_src == TRIG_TIMER &&
874 cmd->convert_src == TRIG_TIMER) {
e55c95a3
GG		 875 /* Check timer arguments */
876 if (init_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 877 dev_err(dev->class_dev, "Invalid start arg\n");
b6c77757 878 cmd->start_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 879 err++;
880 }
881 if (chan_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 882 dev_err(dev->class_dev, "Invalid convert arg\n");
b6c77757 883 cmd->convert_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 884 err++;
885 }
886 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
5da80ee8 887 dev_err(dev->class_dev, "Invalid scan end arg\n");
b6241fda
GS		 888
889 /* At least one tick more */
890 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
e55c95a3
GG		 891 err++;
892 }
893 } else if (cmd->start_src == TRIG_NOW &&
0a85b6f0
MT		 894 cmd->scan_begin_src == TRIG_FOLLOW &&
895 cmd->convert_src == TRIG_TIMER) {
e55c95a3
GG		 896 /* Check timer arguments */
897 if (init_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 898 dev_err(dev->class_dev, "Invalid start arg\n");
b6c77757 899 cmd->start_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 900 err++;
901 }
902 if (chan_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 903 dev_err(dev->class_dev, "Invalid convert arg\n");
b6c77757 904 cmd->convert_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 905 err++;
906 }
907 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 908 cmd->scan_begin_src == TRIG_TIMER &&
909 cmd->convert_src == TRIG_TIMER) {
e55c95a3
GG		 910 /* Check timer arguments */
911 if (init_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 912 dev_err(dev->class_dev, "Invalid start arg\n");
b6c77757 913 cmd->start_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 914 err++;
915 }
916 if (chan_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 917 dev_err(dev->class_dev, "Invalid convert arg\n");
b6c77757 918 cmd->convert_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 919 err++;
920 }
921 if (scan_ticks <= cmd->chanlist_len * chan_ticks) {
5da80ee8 922 dev_err(dev->class_dev, "Invalid scan end arg\n");
b6241fda
GS		 923
924 /* At least one tick more */
925 cmd->scan_end_arg = 2000 * cmd->chanlist_len + 31;
e55c95a3
GG		 926 err++;
927 }
928 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 929 cmd->scan_begin_src == TRIG_FOLLOW &&
930 cmd->convert_src == TRIG_TIMER) {
e55c95a3
GG		 931 /* Check timer arguments */
932 if (init_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 933 dev_err(dev->class_dev, "Invalid start arg\n");
b6c77757 934 cmd->start_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 935 err++;
936 }
937 if (chan_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 938 dev_err(dev->class_dev, "Invalid convert arg\n");
b6c77757 939 cmd->convert_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 940 err++;
941 }
942 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 943 cmd->scan_begin_src == TRIG_EXT &&
944 cmd->convert_src == TRIG_TIMER) {
e55c95a3
GG		 945 /* Check timer arguments */
946 if (init_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 947 dev_err(dev->class_dev, "Invalid start arg\n");
b6c77757 948 cmd->start_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 949 err++;
950 }
951 if (chan_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 952 dev_err(dev->class_dev, "Invalid convert arg\n");
b6c77757 953 cmd->convert_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 954 err++;
955 }
956 } else if (cmd->start_src == TRIG_EXT &&
0a85b6f0
MT		 957 cmd->scan_begin_src == TRIG_EXT &&
958 cmd->convert_src == TRIG_EXT) {
e55c95a3
GG		 959 /* Check timer arguments */
960 if (init_ticks < ME4000_AI_MIN_TICKS) {
5da80ee8 961 dev_err(dev->class_dev, "Invalid start arg\n");
b6c77757 962 cmd->start_arg = 2000; /* 66 ticks at least */
e55c95a3
GG		 963 err++;
964 }
965 }
e55c95a3
GG		 966 if (cmd->scan_end_src == TRIG_COUNT) {
967 if (cmd->scan_end_arg == 0) {
5da80ee8 968 dev_err(dev->class_dev, "Invalid scan end arg\n");
e55c95a3
GG		 969 cmd->scan_end_arg = 1;
970 err++;
971 }
972 }
82675f35
BP		 973
974 if (err)
e55c95a3 975 return 4;
e55c95a3 976
926e5073
HS		 977 /* Step 5: check channel list if it exists */
978 if (cmd->chanlist && cmd->chanlist_len > 0)
979 err |= me4000_ai_check_chanlist(dev, s, cmd);
980
981 if (err)
e55c95a3
GG		 982 return 5;
983
984 return 0;
985}
986
70265d24 987static irqreturn_t me4000_ai_isr(int irq, void *dev_id)
e55c95a3
GG		 988{
989 unsigned int tmp;
71b5f4f1 990 struct comedi_device *dev = dev_id;
b3403f2e 991 struct comedi_subdevice *s = dev->read_subdev;
e55c95a3
GG		 992 int i;
993 int c = 0;
ac2832f8 994 unsigned int lval;
e55c95a3 995
ef5bbfcb 996 if (!dev->attached)
e55c95a3 997 return IRQ_NONE;
e55c95a3 998
b08bfa38 999 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
0a85b6f0 1000 ME4000_IRQ_STATUS_BIT_AI_HF) {
e55c95a3 1001 /* Read status register to find out what happened */
b08bfa38 1002 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 1003
1004 if (!(tmp & ME4000_AI_STATUS_BIT_FF_DATA) &&
0a85b6f0
MT		 1005 !(tmp & ME4000_AI_STATUS_BIT_HF_DATA) &&
1006 (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
e55c95a3
GG		 1007 c = ME4000_AI_FIFO_COUNT;
1008
b6241fda
GS		 1009 /*
1010 * FIFO overflow, so stop conversion
1011 * and disable all interrupts
1012 */
e55c95a3
GG		 1013 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1014 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
0a85b6f0 1015 ME4000_AI_CTRL_BIT_SC_IRQ);
b08bfa38 1016 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3 1017
3e6cb74f 1018 s->async->events |= COMEDI_CB_ERROR;
e55c95a3 1019
5da80ee8 1020 dev_err(dev->class_dev, "FIFO overflow\n");
e55c95a3 1021 } else if ((tmp & ME4000_AI_STATUS_BIT_FF_DATA)
0a85b6f0
MT		 1022 && !(tmp & ME4000_AI_STATUS_BIT_HF_DATA)
1023 && (tmp & ME4000_AI_STATUS_BIT_EF_DATA)) {
e55c95a3
GG		 1024 c = ME4000_AI_FIFO_COUNT / 2;
1025 } else {
5da80ee8
HS		 1026 dev_err(dev->class_dev,
1027 "Can't determine state of fifo\n");
e55c95a3
GG		 1028 c = 0;
1029
b6241fda
GS		 1030 /*
1031 * Undefined state, so stop conversion
1032 * and disable all interrupts
1033 */
e55c95a3
GG		 1034 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1035 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
0a85b6f0 1036 ME4000_AI_CTRL_BIT_SC_IRQ);
b08bfa38 1037 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3 1038
3e6cb74f 1039 s->async->events |= COMEDI_CB_ERROR;
e55c95a3 1040
5da80ee8 1041 dev_err(dev->class_dev, "Undefined FIFO state\n");
e55c95a3
GG		 1042 }
1043
e55c95a3
GG		 1044 for (i = 0; i < c; i++) {
1045 /* Read value from data fifo */
b08bfa38 1046 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
e55c95a3
GG		 1047 lval ^= 0x8000;
1048
de88924f 1049 if (!comedi_buf_write_samples(s, &lval, 1)) {
b6241fda
GS		 1050 /*
1051 * Buffer overflow, so stop conversion
1052 * and disable all interrupts
1053 */
e55c95a3
GG		 1054 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1055 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ |
0a85b6f0 1056 ME4000_AI_CTRL_BIT_SC_IRQ);
b08bfa38 1057 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 1058 break;
1059 }
1060 }
1061
1062 /* Work is done, so reset the interrupt */
e55c95a3 1063 tmp |= ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
b08bfa38 1064 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3 1065 tmp &= ~ME4000_AI_CTRL_BIT_HF_IRQ_RESET;
b08bfa38 1066 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 1067 }
1068
b08bfa38
HS		 1069 if (inl(dev->iobase + ME4000_IRQ_STATUS_REG) &
1070 ME4000_IRQ_STATUS_BIT_SC) {
de88924f 1071 s->async->events |= COMEDI_CB_EOA;
e55c95a3 1072
b6241fda
GS		 1073 /*
1074 * Acquisition is complete, so stop
1075 * conversion and disable all interrupts
1076 */
b08bfa38 1077 tmp = inl(dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 1078 tmp |= ME4000_AI_CTRL_BIT_IMMEDIATE_STOP;
1079 tmp &= ~(ME4000_AI_CTRL_BIT_HF_IRQ | ME4000_AI_CTRL_BIT_SC_IRQ);
b08bfa38 1080 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 1081
1082 /* Poll data until fifo empty */
b08bfa38
HS		 1083 while (inl(dev->iobase + ME4000_AI_CTRL_REG) &
1084 ME4000_AI_STATUS_BIT_EF_DATA) {
e55c95a3 1085 /* Read value from data fifo */
b08bfa38 1086 lval = inl(dev->iobase + ME4000_AI_DATA_REG) & 0xFFFF;
e55c95a3
GG		 1087 lval ^= 0x8000;
1088
de88924f 1089 if (!comedi_buf_write_samples(s, &lval, 1))
e55c95a3 1090 break;
e55c95a3
GG		 1091 }
1092
1093 /* Work is done, so reset the interrupt */
e55c95a3 1094 tmp |= ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
b08bfa38 1095 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3 1096 tmp &= ~ME4000_AI_CTRL_BIT_SC_IRQ_RESET;
b08bfa38 1097 outl(tmp, dev->iobase + ME4000_AI_CTRL_REG);
e55c95a3
GG		 1098 }
1099
3fa1eb64 1100 comedi_handle_events(dev, s);
e55c95a3
GG		 1101
1102 return IRQ_HANDLED;
1103}
1104
71b5f4f1 1105static int me4000_ao_insn_write(struct comedi_device *dev,
0a85b6f0 1106 struct comedi_subdevice *s,
97e658d1
HS		 1107 struct comedi_insn *insn,
1108 unsigned int *data)
e55c95a3 1109{
e55c95a3 1110 int chan = CR_CHAN(insn->chanspec);
ac2832f8 1111 unsigned int tmp;
e55c95a3 1112
e55c95a3 1113 /* Stop any running conversion */
e1d7ccb7 1114 tmp = inl(dev->iobase + ME4000_AO_CTRL_REG(chan));
e55c95a3 1115 tmp |= ME4000_AO_CTRL_BIT_IMMEDIATE_STOP;
e1d7ccb7 1116 outl(tmp, dev->iobase + ME4000_AO_CTRL_REG(chan));
e55c95a3
GG		 1117
1118 /* Clear control register and set to single mode */
e1d7ccb7 1119 outl(0x0, dev->iobase + ME4000_AO_CTRL_REG(chan));
e55c95a3
GG		 1120
1121 /* Write data value */
e1d7ccb7 1122 outl(data[0], dev->iobase + ME4000_AO_SINGLE_REG(chan));
e55c95a3
GG		 1123
1124 /* Store in the mirror */
081b6ee6 1125 s->readback[chan] = data[0];
e55c95a3
GG		 1126
1127 return 1;
1128}
1129
71b5f4f1 1130static int me4000_dio_insn_bits(struct comedi_device *dev,
0a85b6f0 1131 struct comedi_subdevice *s,
b523c2b2
HS		 1132 struct comedi_insn *insn,
1133 unsigned int *data)
e55c95a3 1134{
b523c2b2 1135 if (comedi_dio_update_state(s, data)) {
d6cbe537 1136 outl((s->state >> 0) & 0xFF,
6c7d2c8b 1137 dev->iobase + ME4000_DIO_PORT_0_REG);
d6cbe537 1138 outl((s->state >> 8) & 0xFF,
6c7d2c8b 1139 dev->iobase + ME4000_DIO_PORT_1_REG);
d6cbe537 1140 outl((s->state >> 16) & 0xFF,
6c7d2c8b 1141 dev->iobase + ME4000_DIO_PORT_2_REG);
d6cbe537 1142 outl((s->state >> 24) & 0xFF,
6c7d2c8b 1143 dev->iobase + ME4000_DIO_PORT_3_REG);
e55c95a3
GG		 1144 }
1145
da755d15
HS		 1146 data[1] = ((inl(dev->iobase + ME4000_DIO_PORT_0_REG) & 0xFF) << 0) |
1147 ((inl(dev->iobase + ME4000_DIO_PORT_1_REG) & 0xFF) << 8) |
1148 ((inl(dev->iobase + ME4000_DIO_PORT_2_REG) & 0xFF) << 16) |
1149 ((inl(dev->iobase + ME4000_DIO_PORT_3_REG) & 0xFF) << 24);
e55c95a3 1150
a2714e3e 1151 return insn->n;
e55c95a3
GG		 1152}
1153
71b5f4f1 1154static int me4000_dio_insn_config(struct comedi_device *dev,
0a85b6f0 1155 struct comedi_subdevice *s,
5dacadcc
HS		 1156 struct comedi_insn *insn,
1157 unsigned int *data)
e55c95a3 1158{
5dacadcc
HS		 1159 unsigned int chan = CR_CHAN(insn->chanspec);
1160 unsigned int mask;
1161 unsigned int tmp;
1162 int ret;
e55c95a3 1163
5dacadcc
HS		 1164 if (chan < 8)
1165 mask = 0x000000ff;
1166 else if (chan < 16)
1167 mask = 0x0000ff00;
1168 else if (chan < 24)
1169 mask = 0x00ff0000;
1170 else
1171 mask = 0xff000000;
e55c95a3 1172
5dacadcc
HS		 1173 ret = comedi_dio_insn_config(dev, s, insn, data, mask);
1174 if (ret)
1175 return ret;
e55c95a3 1176
da755d15 1177 tmp = inl(dev->iobase + ME4000_DIO_CTRL_REG);
5dacadcc
HS		 1178 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_0 | ME4000_DIO_CTRL_BIT_MODE_1 |
1179 ME4000_DIO_CTRL_BIT_MODE_2 | ME4000_DIO_CTRL_BIT_MODE_3 |
1180 ME4000_DIO_CTRL_BIT_MODE_4 | ME4000_DIO_CTRL_BIT_MODE_5 |
1181 ME4000_DIO_CTRL_BIT_MODE_6 | ME4000_DIO_CTRL_BIT_MODE_7);
1182 if (s->io_bits & 0x000000ff)
1183 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1184 if (s->io_bits & 0x0000ff00)
1185 tmp |= ME4000_DIO_CTRL_BIT_MODE_2;
1186 if (s->io_bits & 0x00ff0000)
1187 tmp |= ME4000_DIO_CTRL_BIT_MODE_4;
1188 if (s->io_bits & 0xff000000)
1189 tmp |= ME4000_DIO_CTRL_BIT_MODE_6;
e55c95a3 1190
5dacadcc
HS		 1191 /*
1192 * Check for optoisolated ME-4000 version.
1193 * If one the first port is a fixed output
1194 * port and the second is a fixed input port.
1195 */
1196 if (inl(dev->iobase + ME4000_DIO_DIR_REG)) {
1197 s->io_bits |= 0x000000ff;
1198 s->io_bits &= ~0x0000ff00;
1199 tmp |= ME4000_DIO_CTRL_BIT_MODE_0;
1200 tmp &= ~(ME4000_DIO_CTRL_BIT_MODE_2 |
1201 ME4000_DIO_CTRL_BIT_MODE_3);
e55c95a3
GG		 1202 }
1203
da755d15 1204 outl(tmp, dev->iobase + ME4000_DIO_CTRL_REG);
e55c95a3 1205
5dacadcc 1206 return insn->n;
e55c95a3
GG		 1207}
1208
a690b7e5 1209static int me4000_auto_attach(struct comedi_device *dev,
8c355509 1210 unsigned long context)
ba5cb4ba 1211{
750af5e5 1212 struct pci_dev *pcidev = comedi_to_pci_dev(dev);
49ef9c85 1213 const struct me4000_board *board = NULL;
3674a87e 1214 struct me4000_private *devpriv;
ba5cb4ba
HS		 1215 struct comedi_subdevice *s;
1216 int result;
4b2f15f1 1217
8c355509 1218 if (context < ARRAY_SIZE(me4000_boards))
49ef9c85
HS		 1219 board = &me4000_boards[context];
1220 if (!board)
5f8f8d43 1221 return -ENODEV;
49ef9c85
HS		 1222 dev->board_ptr = board;
1223 dev->board_name = board->name;
4b2f15f1 1224
3674a87e
HS		 1225 devpriv = comedi_alloc_devpriv(dev, sizeof(*devpriv));
1226 if (!devpriv)
c34fa261 1227 return -ENOMEM;
4b2f15f1 1228
818f569f 1229 result = comedi_pci_enable(dev);
ba5cb4ba
HS		 1230 if (result)
1231 return result;
1232
3674a87e 1233 devpriv->plx_regbase = pci_resource_start(pcidev, 1);
ba5cb4ba 1234 dev->iobase = pci_resource_start(pcidev, 2);
3674a87e 1235 if (!devpriv->plx_regbase || !dev->iobase)
4b2f15f1
HS		 1236 return -ENODEV;
1237
ac584af5
HS		 1238 result = comedi_load_firmware(dev, &pcidev->dev, ME4000_FIRMWARE,
1239 me4000_xilinx_download, 0);
1240 if (result < 0)
4b2f15f1
HS		 1241 return result;
1242
2f348ecd 1243 me4000_reset(dev);
4b2f15f1 1244
a9b7ff93
HS		 1245 if (pcidev->irq > 0) {
1246 result = request_irq(pcidev->irq, me4000_ai_isr, IRQF_SHARED,
6c7d2c8b 1247 dev->board_name, dev);
a9b7ff93
HS		 1248 if (result == 0)
1249 dev->irq = pcidev->irq;
1250 }
1251
8b6c5694
HS		 1252 result = comedi_alloc_subdevices(dev, 4);
1253 if (result)
1254 return result;
3af09830 1255
14aa4789 1256 /* Analog Input subdevice */
8aaf2717 1257 s = &dev->subdevices[0];
14aa4789 1258 s->type = COMEDI_SUBD_AI;
31bebc03 1259 s->subdev_flags = SDF_READABLE | SDF_COMMON | SDF_GROUND;
56f71de6 1260 if (board->can_do_diff_ai)
31bebc03 1261 s->subdev_flags |= SDF_DIFF;
14aa4789
HS		 1262 s->n_chan = board->ai_nchan;
1263 s->maxdata = 0xffff;
1264 s->len_chanlist = ME4000_AI_CHANNEL_LIST_COUNT;
1265 s->range_table = &me4000_ai_range;
1266 s->insn_read = me4000_ai_insn_read;
1267
1268 if (dev->irq) {
1269 dev->read_subdev = s;
1270 s->subdev_flags |= SDF_CMD_READ;
1271 s->cancel = me4000_ai_cancel;
1272 s->do_cmdtest = me4000_ai_do_cmd_test;
1273 s->do_cmd = me4000_ai_do_cmd;
3af09830
HS		 1274 }
1275
1276 /*=========================================================================
1277 Analog output subdevice
1278 ========================================================================*/
1279
8aaf2717 1280 s = &dev->subdevices[1];
3af09830 1281
aed9b663 1282 if (board->has_ao) {
3af09830 1283 s->type = COMEDI_SUBD_AO;
ef49d832 1284 s->subdev_flags = SDF_WRITABLE | SDF_COMMON | SDF_GROUND;
aed9b663 1285 s->n_chan = 4;
3af09830 1286 s->maxdata = 0xFFFF; /* 16 bit DAC */
4683f9f8 1287 s->range_table = &range_bipolar10;
3af09830 1288 s->insn_write = me4000_ao_insn_write;
081b6ee6
HS		 1289
1290 result = comedi_alloc_subdev_readback(s);
1291 if (result)
1292 return result;
3af09830
HS		 1293 } else {
1294 s->type = COMEDI_SUBD_UNUSED;
1295 }
1296
d8553701 1297 /* Digital I/O subdevice */
8aaf2717 1298 s = &dev->subdevices[2];
d8553701
HS		 1299 s->type = COMEDI_SUBD_DIO;
1300 s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
1301 s->n_chan = 32;
1302 s->maxdata = 1;
1303 s->range_table = &range_digital;
1304 s->insn_bits = me4000_dio_insn_bits;
1305 s->insn_config = me4000_dio_insn_config;
3af09830
HS		 1306
1307 /*
1308 * Check for optoisolated ME-4000 version. If one the first
1309 * port is a fixed output port and the second is a fixed input port.
1310 */
da755d15 1311 if (!inl(dev->iobase + ME4000_DIO_DIR_REG)) {
3af09830 1312 s->io_bits |= 0xFF;
da755d15 1313 outl(ME4000_DIO_CTRL_BIT_MODE_0,
6c7d2c8b 1314 dev->iobase + ME4000_DIO_DIR_REG);
3af09830
HS		 1315 }
1316
d92d39d9 1317 /* Counter subdevice (8254) */
8aaf2717 1318 s = &dev->subdevices[3];
49ef9c85 1319 if (board->has_counter) {
d92d39d9
HS		 1320 unsigned long timer_base = pci_resource_start(pcidev, 3);
1321
1322 if (!timer_base)
1323 return -ENODEV;
1324
1325 dev->pacer = comedi_8254_init(timer_base, 0, I8254_IO8, 0);
1326 if (!dev->pacer)
1327 return -ENOMEM;
1328
1329 comedi_8254_subdevice_init(s, dev->pacer);
3af09830
HS		 1330 } else {
1331 s->type = COMEDI_SUBD_UNUSED;
1332 }
1333
1334 return 0;
1335}
1336
484ecc95 1337static void me4000_detach(struct comedi_device *dev)
3af09830 1338{
7f072f54
HS		 1339 if (dev->iobase)
1340 me4000_reset(dev);
aac307f9 1341 comedi_pci_detach(dev);
3af09830
HS		 1342}
1343
75e6301b 1344static struct comedi_driver me4000_driver = {
3af09830
HS		 1345 .driver_name = "me4000",
1346 .module = THIS_MODULE,
750af5e5 1347 .auto_attach = me4000_auto_attach,
3af09830
HS		 1348 .detach = me4000_detach,
1349};
1350
a690b7e5 1351static int me4000_pci_probe(struct pci_dev *dev,
b8f4ac23 1352 const struct pci_device_id *id)
727b286b 1353{
b8f4ac23 1354 return comedi_pci_auto_config(dev, &me4000_driver, id->driver_data);
727b286b
AT		 1355}
1356
41e043fc 1357static const struct pci_device_id me4000_pci_table[] = {
8c355509
HS		 1358 { PCI_VDEVICE(MEILHAUS, 0x4650), BOARD_ME4650 },
1359 { PCI_VDEVICE(MEILHAUS, 0x4660), BOARD_ME4660 },
1360 { PCI_VDEVICE(MEILHAUS, 0x4661), BOARD_ME4660I },
1361 { PCI_VDEVICE(MEILHAUS, 0x4662), BOARD_ME4660S },
1362 { PCI_VDEVICE(MEILHAUS, 0x4663), BOARD_ME4660IS },
1363 { PCI_VDEVICE(MEILHAUS, 0x4670), BOARD_ME4670 },
1364 { PCI_VDEVICE(MEILHAUS, 0x4671), BOARD_ME4670I },
1365 { PCI_VDEVICE(MEILHAUS, 0x4672), BOARD_ME4670S },
1366 { PCI_VDEVICE(MEILHAUS, 0x4673), BOARD_ME4670IS },
1367 { PCI_VDEVICE(MEILHAUS, 0x4680), BOARD_ME4680 },
1368 { PCI_VDEVICE(MEILHAUS, 0x4681), BOARD_ME4680I },
1369 { PCI_VDEVICE(MEILHAUS, 0x4682), BOARD_ME4680S },
1370 { PCI_VDEVICE(MEILHAUS, 0x4683), BOARD_ME4680IS },
1371 { 0 }
3af09830
HS		 1372};
1373MODULE_DEVICE_TABLE(pci, me4000_pci_table);
1374
75e6301b
HS		 1375static struct pci_driver me4000_pci_driver = {
1376 .name = "me4000",
3af09830 1377 .id_table = me4000_pci_table,
75e6301b 1378 .probe = me4000_pci_probe,
9901a4d7 1379 .remove = comedi_pci_auto_unconfig,
727b286b 1380};
75e6301b 1381module_comedi_pci_driver(me4000_driver, me4000_pci_driver);
90f703d3
AT		 1382
1383MODULE_AUTHOR("Comedi http://www.comedi.org");
1384MODULE_DESCRIPTION("Comedi low-level driver");
1385MODULE_LICENSE("GPL");
ac584af5 1386MODULE_FIRMWARE(ME4000_FIRMWARE);
Linux kernel - Deliverables
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