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Merge 3.9-rc5 into staging-next
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_at_a2150.c
CommitLineData
01b0a258
FMH		 1/*
2 comedi/drivers/ni_at_a2150.c
3 Driver for National Instruments AT-A2150 boards
4 Copyright (C) 2001, 2002 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 COMEDI - Linux Control and Measurement Device Interface
7 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22
23************************************************************************
24*/
25/*
26Driver: ni_at_a2150
27Description: National Instruments AT-A2150
28Author: Frank Mori Hess
29Status: works
30Devices: [National Instruments] AT-A2150C (at_a2150c), AT-2150S (at_a2150s)
31
32If you want to ac couple the board's inputs, use AREF_OTHER.
33
34Configuration options:
35 [0] - I/O port base address
36 [1] - IRQ (optional, required for timed conversions)
37 [2] - DMA (optional, required for timed conversions)
38
39*/
40/*
41Yet another driver for obsolete hardware brought to you by Frank Hess.
42Testing and debugging help provided by Dave Andruczyk.
43
44This driver supports the boards:
45
46AT-A2150C
47AT-A2150S
48
49The only difference is their master clock frequencies.
50
51Options:
52 [0] - base io address
53 [1] - irq
54 [2] - dma channel
55
56References (from ftp://ftp.natinst.com/support/manuals):
57
58 320360.pdf AT-A2150 User Manual
59
60TODO:
61
62analog level triggering
63TRIG_WAKE_EOS
64
65*/
66
25436dc9 67#include <linux/interrupt.h>
5a0e3ad6 68#include <linux/slab.h>
01b0a258
FMH		 69#include "../comedidev.h"
70
71#include <linux/ioport.h>
845d131e 72#include <linux/io.h>
01b0a258
FMH		 73#include <asm/dma.h>
74
75#include "8253.h"
76#include "comedi_fc.h"
77
78#define A2150_SIZE 28
30c687c1 79#define A2150_DMA_BUFFER_SIZE 0xff00 /* size in bytes of dma buffer */
01b0a258 80
30c687c1
BP		 81/* #define A2150_DEBUG enable debugging code */
82#undef A2150_DEBUG /* disable debugging code */
01b0a258
FMH		 83
84/* Registers and bits */
85#define CONFIG_REG 0x0
86#define CHANNEL_BITS(x) ((x) & 0x7)
87#define CHANNEL_MASK 0x7
88#define CLOCK_SELECT_BITS(x) (((x) & 0x3) << 3)
89#define CLOCK_DIVISOR_BITS(x) (((x) & 0x3) << 5)
90#define CLOCK_MASK (0xf << 3)
30c687c1
BP		 91#define ENABLE0_BIT 0x80 /* enable (don't internally ground) channels 0 and 1 */
92#define ENABLE1_BIT 0x100 /* enable (don't internally ground) channels 2 and 3 */
93#define AC0_BIT 0x200 /* ac couple channels 0,1 */
94#define AC1_BIT 0x400 /* ac couple channels 2,3 */
95#define APD_BIT 0x800 /* analog power down */
96#define DPD_BIT 0x1000 /* digital power down */
97#define TRIGGER_REG 0x2 /* trigger config register */
01b0a258
FMH		 98#define POST_TRIGGER_BITS 0x2
99#define DELAY_TRIGGER_BITS 0x3
30c687c1
BP		 100#define HW_TRIG_EN 0x10 /* enable hardware trigger */
101#define FIFO_START_REG 0x6 /* software start aquistion trigger */
102#define FIFO_RESET_REG 0x8 /* clears fifo + fifo flags */
103#define FIFO_DATA_REG 0xa /* read data */
104#define DMA_TC_CLEAR_REG 0xe /* clear dma terminal count interrupt */
105#define STATUS_REG 0x12 /* read only */
106#define FNE_BIT 0x1 /* fifo not empty */
107#define OVFL_BIT 0x8 /* fifo overflow */
25985edc 108#define EDAQ_BIT 0x10 /* end of acquisition interrupt */
30c687c1 109#define DCAL_BIT 0x20 /* offset calibration in progress */
25985edc
LDM		 110#define INTR_BIT 0x40 /* interrupt has occurred */
111#define DMA_TC_BIT 0x80 /* dma terminal count interrupt has occurred */
01b0a258 112#define ID_BITS(x) (((x) >> 8) & 0x3)
30c687c1
BP		 113#define IRQ_DMA_CNTRL_REG 0x12 /* write only */
114#define DMA_CHAN_BITS(x) ((x) & 0x7) /* sets dma channel */
115#define DMA_EN_BIT 0x8 /* enables dma */
116#define IRQ_LVL_BITS(x) (((x) & 0xf) << 4) /* sets irq level */
117#define FIFO_INTR_EN_BIT 0x100 /* enable fifo interrupts */
118#define FIFO_INTR_FHF_BIT 0x200 /* interrupt fifo half full */
119#define DMA_INTR_EN_BIT 0x800 /* enable interrupt on dma terminal count */
120#define DMA_DEM_EN_BIT 0x1000 /* enables demand mode dma */
01b0a258
FMH		 121#define I8253_BASE_REG 0x14
122#define I8253_MODE_REG 0x17
30c687c1 123#define HW_COUNT_DISABLE 0x30 /* disable hardware counting of conversions */
01b0a258 124
92b635c5 125struct a2150_board {
01b0a258 126 const char *name;
30c687c1
BP		 127 int clock[4]; /* master clock periods, in nanoseconds */
128 int num_clocks; /* number of available master clock speeds */
129 int ai_speed; /* maximum conversion rate in nanoseconds */
92b635c5 130};
01b0a258 131
30c687c1 132/* analog input range */
9ced1de6 133static const struct comedi_lrange range_a2150 = {
01b0a258
FMH		 134 1,
135 {
0a85b6f0
MT		 136 RANGE(-2.828, 2.828),
137 }
01b0a258
FMH		 138};
139
30c687c1 140/* enum must match board indices */
01b0a258 141enum { a2150_c, a2150_s };
92b635c5 142static const struct a2150_board a2150_boards[] = {
01b0a258 143 {
0a85b6f0
MT		 144 .name = "at-a2150c",
145 .clock = {31250, 22676, 20833, 19531},
146 .num_clocks = 4,
147 .ai_speed = 19531,
148 },
01b0a258 149 {
0a85b6f0
MT		 150 .name = "at-a2150s",
151 .clock = {62500, 50000, 41667, 0},
152 .num_clocks = 3,
153 .ai_speed = 41667,
154 },
01b0a258
FMH		 155};
156
157/*
158 * Useful for shorthand access to the particular board structure
159 */
92b635c5 160#define thisboard ((const struct a2150_board *)dev->board_ptr)
01b0a258 161
3cc3872b
BP		 162struct a2150_private {
163
01b0a258 164 volatile unsigned int count; /* number of data points left to be taken */
30c687c1
BP		 165 unsigned int dma; /* dma channel */
166 s16 *dma_buffer; /* dma buffer */
167 unsigned int dma_transfer_size; /* size in bytes of dma transfers */
168 int irq_dma_bits; /* irq/dma register bits */
169 int config_bits; /* config register bits */
3cc3872b
BP		 170};
171
da91b269 172static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
01b0a258 173
814900c9 174static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,
0a85b6f0 175 int flags);
0a85b6f0
MT		 176static int a2150_set_chanlist(struct comedi_device *dev,
177 unsigned int start_channel,
178 unsigned int num_channels);
01b0a258
FMH		 179#ifdef A2150_DEBUG
180
da91b269 181static void ni_dump_regs(struct comedi_device *dev)
01b0a258 182{
9a1a6cf8
HS		 183 struct a2150_private *devpriv = dev->private;
184
5f74ea14
GKH		 185 printk("config bits 0x%x\n", devpriv->config_bits);
186 printk("irq dma bits 0x%x\n", devpriv->irq_dma_bits);
187 printk("status bits 0x%x\n", inw(dev->iobase + STATUS_REG));
01b0a258
FMH		 188}
189
190#endif
191
192/* interrupt service routine */
70265d24 193static irqreturn_t a2150_interrupt(int irq, void *d)
01b0a258
FMH		 194{
195 int i;
196 int status;
197 unsigned long flags;
71b5f4f1 198 struct comedi_device *dev = d;
9a1a6cf8 199 struct a2150_private *devpriv = dev->private;
34c43922 200 struct comedi_subdevice *s = dev->read_subdev;
d163679c 201 struct comedi_async *async;
ea6d0d4c 202 struct comedi_cmd *cmd;
01b0a258 203 unsigned int max_points, num_points, residue, leftover;
790c5541 204 short dpnt;
01b0a258
FMH		 205 static const int sample_size = sizeof(devpriv->dma_buffer[0]);
206
a7401cdd 207 if (!dev->attached) {
01b0a258
FMH		 208 comedi_error(dev, "premature interrupt");
209 return IRQ_HANDLED;
210 }
30c687c1 211 /* initialize async here to make sure s is not NULL */
01b0a258
FMH		 212 async = s->async;
213 async->events = 0;
214 cmd = &async->cmd;
215
216 status = inw(dev->iobase + STATUS_REG);
217
218 if ((status & INTR_BIT) == 0) {
219 comedi_error(dev, "spurious interrupt");
220 return IRQ_NONE;
221 }
222
223 if (status & OVFL_BIT) {
224 comedi_error(dev, "fifo overflow");
225 a2150_cancel(dev, s);
226 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
227 }
228
229 if ((status & DMA_TC_BIT) == 0) {
230 comedi_error(dev, "caught non-dma interrupt? Aborting.");
231 a2150_cancel(dev, s);
232 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
233 comedi_event(dev, s);
234 return IRQ_HANDLED;
235 }
236
237 flags = claim_dma_lock();
238 disable_dma(devpriv->dma);
239 /* clear flip-flop to make sure 2-byte registers for
240 * count and address get set correctly */
241 clear_dma_ff(devpriv->dma);
242
30c687c1 243 /* figure out how many points to read */
01b0a258
FMH		 244 max_points = devpriv->dma_transfer_size / sample_size;
245 /* residue is the number of points left to be done on the dma
246 * transfer. It should always be zero at this point unless
247 * the stop_src is set to external triggering.
248 */
249 residue = get_dma_residue(devpriv->dma) / sample_size;
250 num_points = max_points - residue;
251 if (devpriv->count < num_points && cmd->stop_src == TRIG_COUNT)
252 num_points = devpriv->count;
253
30c687c1 254 /* figure out how many points will be stored next time */
01b0a258
FMH		 255 leftover = 0;
256 if (cmd->stop_src == TRIG_NONE) {
257 leftover = devpriv->dma_transfer_size / sample_size;
258 } else if (devpriv->count > max_points) {
259 leftover = devpriv->count - max_points;
260 if (leftover > max_points)
261 leftover = max_points;
262 }
263 /* there should only be a residue if collection was stopped by having
264 * the stop_src set to an external trigger, in which case there
265 * will be no more data
266 */
267 if (residue)
268 leftover = 0;
269
270 for (i = 0; i < num_points; i++) {
271 /* write data point to comedi buffer */
272 dpnt = devpriv->dma_buffer[i];
30c687c1 273 /* convert from 2's complement to unsigned coding */
01b0a258
FMH		 274 dpnt ^= 0x8000;
275 cfc_write_to_buffer(s, dpnt);
276 if (cmd->stop_src == TRIG_COUNT) {
277 if (--devpriv->count == 0) { /* end of acquisition */
278 a2150_cancel(dev, s);
279 async->events |= COMEDI_CB_EOA;
280 break;
281 }
282 }
283 }
30c687c1 284 /* re-enable dma */
01b0a258
FMH		 285 if (leftover) {
286 set_dma_addr(devpriv->dma, virt_to_bus(devpriv->dma_buffer));
287 set_dma_count(devpriv->dma, leftover * sample_size);
288 enable_dma(devpriv->dma);
289 }
290 release_dma_lock(flags);
291
292 async->events |= COMEDI_CB_BLOCK;
293
294 comedi_event(dev, s);
295
296 /* clear interrupt */
297 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
298
299 return IRQ_HANDLED;
300}
301
da91b269 302static int a2150_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
01b0a258 303{
9a1a6cf8
HS		 304 struct a2150_private *devpriv = dev->private;
305
30c687c1 306 /* disable dma on card */
01b0a258
FMH		 307 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
308 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
309
30c687c1 310 /* disable computer's dma */
01b0a258
FMH		 311 disable_dma(devpriv->dma);
312
30c687c1 313 /* clear fifo and reset triggering circuitry */
01b0a258
FMH		 314 outw(0, dev->iobase + FIFO_RESET_REG);
315
316 return 0;
317}
318
0a85b6f0
MT		 319static int a2150_ai_cmdtest(struct comedi_device *dev,
320 struct comedi_subdevice *s, struct comedi_cmd *cmd)
01b0a258
FMH		 321{
322 int err = 0;
323 int tmp;
324 int startChan;
325 int i;
326
27020ffe 327 /* Step 1 : check if triggers are trivially valid */
01b0a258 328
27020ffe
HS		 329 err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT);
330 err |= cfc_check_trigger_src(&cmd->scan_begin_src, TRIG_TIMER);
331 err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_NOW);
332 err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT);
333 err |= cfc_check_trigger_src(&cmd->stop_src, TRIG_COUNT | TRIG_NONE);
01b0a258
FMH		 334
335 if (err)
336 return 1;
337
27020ffe 338 /* Step 2a : make sure trigger sources are unique */
01b0a258 339
27020ffe
HS		 340 err |= cfc_check_trigger_is_unique(cmd->start_src);
341 err |= cfc_check_trigger_is_unique(cmd->stop_src);
342
343 /* Step 2b : and mutually compatible */
01b0a258
FMH		 344
345 if (err)
346 return 2;
347
dd254844 348 /* Step 3: check if arguments are trivially valid */
01b0a258 349
dd254844
HS		 350 err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0);
351
352 if (cmd->convert_src == TRIG_TIMER)
353 err |= cfc_check_trigger_arg_min(&cmd->convert_arg,
354 thisboard->ai_speed);
355
356 err |= cfc_check_trigger_arg_min(&cmd->chanlist_len, 1);
357 err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len);
358
359 if (cmd->stop_src == TRIG_COUNT)
360 err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1);
361 else /* TRIG_NONE */
362 err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0);
01b0a258
FMH		 363
364 if (err)
365 return 3;
366
367 /* step 4: fix up any arguments */
368
369 if (cmd->scan_begin_src == TRIG_TIMER) {
370 tmp = cmd->scan_begin_arg;
371 a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags);
372 if (tmp != cmd->scan_begin_arg)
373 err++;
374 }
375
376 if (err)
377 return 4;
378
30c687c1 379 /* check channel/gain list against card's limitations */
01b0a258
FMH		 380 if (cmd->chanlist) {
381 startChan = CR_CHAN(cmd->chanlist[0]);
382 for (i = 1; i < cmd->chanlist_len; i++) {
383 if (CR_CHAN(cmd->chanlist[i]) != (startChan + i)) {
384 comedi_error(dev,
0a85b6f0 385 "entries in chanlist must be consecutive channels, counting upwards\n");
01b0a258
FMH		 386 err++;
387 }
388 }
389 if (cmd->chanlist_len == 2 && CR_CHAN(cmd->chanlist[0]) == 1) {
390 comedi_error(dev,
0a85b6f0 391 "length 2 chanlist must be channels 0,1 or channels 2,3");
01b0a258
FMH		 392 err++;
393 }
394 if (cmd->chanlist_len == 3) {
395 comedi_error(dev,
0a85b6f0 396 "chanlist must have 1,2 or 4 channels");
01b0a258
FMH		 397 err++;
398 }
399 if (CR_AREF(cmd->chanlist[0]) != CR_AREF(cmd->chanlist[1]) ||
0a85b6f0 400 CR_AREF(cmd->chanlist[2]) != CR_AREF(cmd->chanlist[3])) {
01b0a258 401 comedi_error(dev,
0a85b6f0 402 "channels 0/1 and 2/3 must have the same analog reference");
01b0a258
FMH		 403 err++;
404 }
405 }
406
407 if (err)
408 return 5;
409
410 return 0;
411}
412
da91b269 413static int a2150_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
01b0a258 414{
9a1a6cf8 415 struct a2150_private *devpriv = dev->private;
d163679c 416 struct comedi_async *async = s->async;
ea6d0d4c 417 struct comedi_cmd *cmd = &async->cmd;
01b0a258
FMH		 418 unsigned long lock_flags;
419 unsigned int old_config_bits = devpriv->config_bits;
420 unsigned int trigger_bits;
421
422 if (!dev->irq || !devpriv->dma) {
423 comedi_error(dev,
0a85b6f0 424 " irq and dma required, cannot do hardware conversions");
01b0a258
FMH		 425 return -1;
426 }
427 if (cmd->flags & TRIG_RT) {
428 comedi_error(dev,
0a85b6f0 429 " dma incompatible with hard real-time interrupt (TRIG_RT), aborting");
01b0a258
FMH		 430 return -1;
431 }
30c687c1 432 /* clear fifo and reset triggering circuitry */
01b0a258
FMH		 433 outw(0, dev->iobase + FIFO_RESET_REG);
434
435 /* setup chanlist */
436 if (a2150_set_chanlist(dev, CR_CHAN(cmd->chanlist[0]),
0a85b6f0 437 cmd->chanlist_len) < 0)
01b0a258
FMH		 438 return -1;
439
30c687c1 440 /* setup ac/dc coupling */
01b0a258
FMH		 441 if (CR_AREF(cmd->chanlist[0]) == AREF_OTHER)
442 devpriv->config_bits |= AC0_BIT;
443 else
444 devpriv->config_bits &= ~AC0_BIT;
445 if (CR_AREF(cmd->chanlist[2]) == AREF_OTHER)
446 devpriv->config_bits |= AC1_BIT;
447 else
448 devpriv->config_bits &= ~AC1_BIT;
449
30c687c1 450 /* setup timing */
01b0a258
FMH		 451 a2150_get_timing(dev, &cmd->scan_begin_arg, cmd->flags);
452
30c687c1 453 /* send timing, channel, config bits */
01b0a258
FMH		 454 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
455
30c687c1 456 /* initialize number of samples remaining */
01b0a258
FMH		 457 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
458
30c687c1 459 /* enable computer's dma */
01b0a258
FMH		 460 lock_flags = claim_dma_lock();
461 disable_dma(devpriv->dma);
462 /* clear flip-flop to make sure 2-byte registers for
463 * count and address get set correctly */
464 clear_dma_ff(devpriv->dma);
465 set_dma_addr(devpriv->dma, virt_to_bus(devpriv->dma_buffer));
30c687c1 466 /* set size of transfer to fill in 1/3 second */
01b0a258
FMH		 467#define ONE_THIRD_SECOND 333333333
468 devpriv->dma_transfer_size =
0a85b6f0
MT		 469 sizeof(devpriv->dma_buffer[0]) * cmd->chanlist_len *
470 ONE_THIRD_SECOND / cmd->scan_begin_arg;
01b0a258
FMH		 471 if (devpriv->dma_transfer_size > A2150_DMA_BUFFER_SIZE)
472 devpriv->dma_transfer_size = A2150_DMA_BUFFER_SIZE;
473 if (devpriv->dma_transfer_size < sizeof(devpriv->dma_buffer[0]))
474 devpriv->dma_transfer_size = sizeof(devpriv->dma_buffer[0]);
475 devpriv->dma_transfer_size -=
0a85b6f0 476 devpriv->dma_transfer_size % sizeof(devpriv->dma_buffer[0]);
01b0a258
FMH		 477 set_dma_count(devpriv->dma, devpriv->dma_transfer_size);
478 enable_dma(devpriv->dma);
479 release_dma_lock(lock_flags);
480
481 /* clear dma interrupt before enabling it, to try and get rid of that
482 * one spurious interrupt that has been happening */
483 outw(0x00, dev->iobase + DMA_TC_CLEAR_REG);
484
30c687c1 485 /* enable dma on card */
01b0a258
FMH		 486 devpriv->irq_dma_bits |= DMA_INTR_EN_BIT | DMA_EN_BIT;
487 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
488
30c687c1 489 /* may need to wait 72 sampling periods if timing was changed */
01b0a258
FMH		 490 i8254_load(dev->iobase + I8253_BASE_REG, 0, 2, 72, 0);
491
30c687c1 492 /* setup start triggering */
01b0a258 493 trigger_bits = 0;
30c687c1 494 /* decide if we need to wait 72 periods for valid data */
01b0a258 495 if (cmd->start_src == TRIG_NOW &&
0a85b6f0
MT		 496 (old_config_bits & CLOCK_MASK) !=
497 (devpriv->config_bits & CLOCK_MASK)) {
30c687c1 498 /* set trigger source to delay trigger */
01b0a258
FMH		 499 trigger_bits |= DELAY_TRIGGER_BITS;
500 } else {
30c687c1 501 /* otherwise no delay */
01b0a258
FMH		 502 trigger_bits |= POST_TRIGGER_BITS;
503 }
30c687c1 504 /* enable external hardware trigger */
01b0a258
FMH		 505 if (cmd->start_src == TRIG_EXT) {
506 trigger_bits |= HW_TRIG_EN;
507 } else if (cmd->start_src == TRIG_OTHER) {
30c687c1 508 /* XXX add support for level/slope start trigger using TRIG_OTHER */
01b0a258
FMH		 509 comedi_error(dev, "you shouldn't see this?");
510 }
30c687c1 511 /* send trigger config bits */
01b0a258
FMH		 512 outw(trigger_bits, dev->iobase + TRIGGER_REG);
513
25985edc 514 /* start acquisition for soft trigger */
a96b98f2 515 if (cmd->start_src == TRIG_NOW)
01b0a258 516 outw(0, dev->iobase + FIFO_START_REG);
01b0a258
FMH		 517#ifdef A2150_DEBUG
518 ni_dump_regs(dev);
519#endif
520
521 return 0;
522}
523
da91b269 524static int a2150_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 525 struct comedi_insn *insn, unsigned int *data)
01b0a258 526{
9a1a6cf8 527 struct a2150_private *devpriv = dev->private;
01b0a258
FMH		 528 unsigned int i, n;
529 static const int timeout = 100000;
530 static const int filter_delay = 36;
531
30c687c1 532 /* clear fifo and reset triggering circuitry */
01b0a258
FMH		 533 outw(0, dev->iobase + FIFO_RESET_REG);
534
535 /* setup chanlist */
536 if (a2150_set_chanlist(dev, CR_CHAN(insn->chanspec), 1) < 0)
537 return -1;
538
30c687c1 539 /* set dc coupling */
01b0a258
FMH		 540 devpriv->config_bits &= ~AC0_BIT;
541 devpriv->config_bits &= ~AC1_BIT;
542
30c687c1 543 /* send timing, channel, config bits */
01b0a258
FMH		 544 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
545
30c687c1 546 /* disable dma on card */
01b0a258
FMH		 547 devpriv->irq_dma_bits &= ~DMA_INTR_EN_BIT & ~DMA_EN_BIT;
548 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
549
30c687c1 550 /* setup start triggering */
01b0a258
FMH		 551 outw(0, dev->iobase + TRIGGER_REG);
552
25985edc 553 /* start acquisition for soft trigger */
01b0a258
FMH		 554 outw(0, dev->iobase + FIFO_START_REG);
555
949fd38c
RKM		 556 /*
557 * there is a 35.6 sample delay for data to get through the
558 * antialias filter
559 */
01b0a258
FMH		 560 for (n = 0; n < filter_delay; n++) {
561 for (i = 0; i < timeout; i++) {
562 if (inw(dev->iobase + STATUS_REG) & FNE_BIT)
563 break;
5f74ea14 564 udelay(1);
01b0a258
FMH		 565 }
566 if (i == timeout) {
567 comedi_error(dev, "timeout");
568 return -ETIME;
569 }
570 inw(dev->iobase + FIFO_DATA_REG);
571 }
572
30c687c1 573 /* read data */
01b0a258
FMH		 574 for (n = 0; n < insn->n; n++) {
575 for (i = 0; i < timeout; i++) {
576 if (inw(dev->iobase + STATUS_REG) & FNE_BIT)
577 break;
5f74ea14 578 udelay(1);
01b0a258
FMH		 579 }
580 if (i == timeout) {
581 comedi_error(dev, "timeout");
582 return -ETIME;
583 }
584#ifdef A2150_DEBUG
585 ni_dump_regs(dev);
586#endif
587 data[n] = inw(dev->iobase + FIFO_DATA_REG);
588#ifdef A2150_DEBUG
5f74ea14 589 printk(" data is %i\n", data[n]);
01b0a258
FMH		 590#endif
591 data[n] ^= 0x8000;
592 }
593
30c687c1 594 /* clear fifo and reset triggering circuitry */
01b0a258
FMH		 595 outw(0, dev->iobase + FIFO_RESET_REG);
596
597 return n;
598}
599
949fd38c
RKM		 600/*
601 * sets bits in devpriv->clock_bits to nearest approximation of requested
602 * period, adjusts requested period to actual timing.
603 */
da91b269 604static int a2150_get_timing(struct comedi_device *dev, unsigned int *period,
0a85b6f0 605 int flags)
01b0a258 606{
9a1a6cf8 607 struct a2150_private *devpriv = dev->private;
01b0a258
FMH		 608 int lub, glb, temp;
609 int lub_divisor_shift, lub_index, glb_divisor_shift, glb_index;
610 int i, j;
611
30c687c1 612 /* initialize greatest lower and least upper bounds */
01b0a258
FMH		 613 lub_divisor_shift = 3;
614 lub_index = 0;
615 lub = thisboard->clock[lub_index] * (1 << lub_divisor_shift);
616 glb_divisor_shift = 0;
617 glb_index = thisboard->num_clocks - 1;
618 glb = thisboard->clock[glb_index] * (1 << glb_divisor_shift);
619
30c687c1 620 /* make sure period is in available range */
01b0a258
FMH		 621 if (*period < glb)
622 *period = glb;
623 if (*period > lub)
624 *period = lub;
625
30c687c1 626 /* we can multiply period by 1, 2, 4, or 8, using (1 << i) */
01b0a258 627 for (i = 0; i < 4; i++) {
30c687c1 628 /* there are a maximum of 4 master clocks */
01b0a258 629 for (j = 0; j < thisboard->num_clocks; j++) {
30c687c1 630 /* temp is the period in nanosec we are evaluating */
01b0a258 631 temp = thisboard->clock[j] * (1 << i);
30c687c1 632 /* if it is the best match yet */
01b0a258
FMH		 633 if (temp < lub && temp >= *period) {
634 lub_divisor_shift = i;
635 lub_index = j;
636 lub = temp;
637 }
638 if (temp > glb && temp <= *period) {
639 glb_divisor_shift = i;
640 glb_index = j;
641 glb = temp;
642 }
643 }
644 }
645 flags &= TRIG_ROUND_MASK;
646 switch (flags) {
647 case TRIG_ROUND_NEAREST:
648 default:
30c687c1 649 /* if least upper bound is better approximation */
a96b98f2 650 if (lub - *period < *period - glb)
01b0a258 651 *period = lub;
a96b98f2 652 else
01b0a258 653 *period = glb;
01b0a258
FMH		 654 break;
655 case TRIG_ROUND_UP:
656 *period = lub;
657 break;
658 case TRIG_ROUND_DOWN:
659 *period = glb;
660 break;
661 }
662
30c687c1 663 /* set clock bits for config register appropriately */
01b0a258
FMH		 664 devpriv->config_bits &= ~CLOCK_MASK;
665 if (*period == lub) {
666 devpriv->config_bits |=
0a85b6f0
MT		 667 CLOCK_SELECT_BITS(lub_index) |
668 CLOCK_DIVISOR_BITS(lub_divisor_shift);
01b0a258
FMH		 669 } else {
670 devpriv->config_bits |=
0a85b6f0
MT		 671 CLOCK_SELECT_BITS(glb_index) |
672 CLOCK_DIVISOR_BITS(glb_divisor_shift);
01b0a258
FMH		 673 }
674
675 return 0;
676}
677
0a85b6f0
MT		 678static int a2150_set_chanlist(struct comedi_device *dev,
679 unsigned int start_channel,
680 unsigned int num_channels)
01b0a258 681{
9a1a6cf8
HS		 682 struct a2150_private *devpriv = dev->private;
683
01b0a258
FMH		 684 if (start_channel + num_channels > 4)
685 return -1;
686
687 devpriv->config_bits &= ~CHANNEL_MASK;
688
689 switch (num_channels) {
690 case 1:
691 devpriv->config_bits |= CHANNEL_BITS(0x4 | start_channel);
692 break;
693 case 2:
694 if (start_channel == 0) {
695 devpriv->config_bits |= CHANNEL_BITS(0x2);
696 } else if (start_channel == 2) {
697 devpriv->config_bits |= CHANNEL_BITS(0x3);
698 } else {
699 return -1;
700 }
701 break;
702 case 4:
703 devpriv->config_bits |= CHANNEL_BITS(0x1);
704 break;
705 default:
706 return -1;
707 break;
708 }
709
710 return 0;
711}
90f703d3 712
fe14fa2b
HS		 713/* probes board type, returns offset */
714static int a2150_probe(struct comedi_device *dev)
715{
716 int status = inw(dev->iobase + STATUS_REG);
717 return ID_BITS(status);
718}
719
720static int a2150_attach(struct comedi_device *dev, struct comedi_devconfig *it)
721{
9a1a6cf8 722 struct a2150_private *devpriv;
fe14fa2b
HS		 723 struct comedi_subdevice *s;
724 unsigned long iobase = it->options[0];
725 unsigned int irq = it->options[1];
726 unsigned int dma = it->options[2];
727 static const int timeout = 2000;
728 int i;
8b6c5694 729 int ret;
fe14fa2b
HS		 730
731 printk("comedi%d: %s: io 0x%lx", dev->minor, dev->driver->driver_name,
732 iobase);
733 if (irq) {
734 printk(", irq %u", irq);
735 } else {
736 printk(", no irq");
737 }
738 if (dma) {
739 printk(", dma %u", dma);
740 } else {
741 printk(", no dma");
742 }
743 printk("\n");
744
c34fa261
HS		 745 devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
746 if (!devpriv)
747 return -ENOMEM;
748 dev->private = devpriv;
fe14fa2b
HS		 749
750 if (iobase == 0) {
751 printk(" io base address required\n");
752 return -EINVAL;
753 }
754
755 /* check if io addresses are available */
756 if (!request_region(iobase, A2150_SIZE, dev->driver->driver_name)) {
757 printk(" I/O port conflict\n");
758 return -EIO;
759 }
760 dev->iobase = iobase;
761
762 /* grab our IRQ */
763 if (irq) {
764 /* check that irq is supported */
765 if (irq < 3 || irq == 8 || irq == 13 || irq > 15) {
766 printk(" invalid irq line %u\n", irq);
767 return -EINVAL;
768 }
769 if (request_irq(irq, a2150_interrupt, 0,
770 dev->driver->driver_name, dev)) {
771 printk("unable to allocate irq %u\n", irq);
772 return -EINVAL;
773 }
774 devpriv->irq_dma_bits |= IRQ_LVL_BITS(irq);
775 dev->irq = irq;
776 }
777 /* initialize dma */
778 if (dma) {
779 if (dma == 4 || dma > 7) {
780 printk(" invalid dma channel %u\n", dma);
781 return -EINVAL;
782 }
783 if (request_dma(dma, dev->driver->driver_name)) {
784 printk(" failed to allocate dma channel %u\n", dma);
785 return -EINVAL;
786 }
787 devpriv->dma = dma;
788 devpriv->dma_buffer =
789 kmalloc(A2150_DMA_BUFFER_SIZE, GFP_KERNEL | GFP_DMA);
790 if (devpriv->dma_buffer == NULL)
791 return -ENOMEM;
792
793 disable_dma(dma);
794 set_dma_mode(dma, DMA_MODE_READ);
795
796 devpriv->irq_dma_bits |= DMA_CHAN_BITS(dma);
797 }
798
799 dev->board_ptr = a2150_boards + a2150_probe(dev);
800 dev->board_name = thisboard->name;
801
8b6c5694
HS		 802 ret = comedi_alloc_subdevices(dev, 1);
803 if (ret)
804 return ret;
fe14fa2b
HS		 805
806 /* analog input subdevice */
ca3caabb 807 s = &dev->subdevices[0];
fe14fa2b
HS		 808 dev->read_subdev = s;
809 s->type = COMEDI_SUBD_AI;
810 s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_OTHER | SDF_CMD_READ;
811 s->n_chan = 4;
812 s->len_chanlist = 4;
813 s->maxdata = 0xffff;
814 s->range_table = &range_a2150;
815 s->do_cmd = a2150_ai_cmd;
816 s->do_cmdtest = a2150_ai_cmdtest;
817 s->insn_read = a2150_ai_rinsn;
818 s->cancel = a2150_cancel;
819
820 /* need to do this for software counting of completed conversions, to
821 * prevent hardware count from stopping acquisition */
822 outw(HW_COUNT_DISABLE, dev->iobase + I8253_MODE_REG);
823
824 /* set card's irq and dma levels */
825 outw(devpriv->irq_dma_bits, dev->iobase + IRQ_DMA_CNTRL_REG);
826
827 /* reset and sync adc clock circuitry */
828 outw_p(DPD_BIT | APD_BIT, dev->iobase + CONFIG_REG);
829 outw_p(DPD_BIT, dev->iobase + CONFIG_REG);
830 /* initialize configuration register */
831 devpriv->config_bits = 0;
832 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
833 /* wait until offset calibration is done, then enable analog inputs */
834 for (i = 0; i < timeout; i++) {
835 if ((DCAL_BIT & inw(dev->iobase + STATUS_REG)) == 0)
836 break;
837 udelay(1000);
838 }
839 if (i == timeout) {
840 printk
841 (" timed out waiting for offset calibration to complete\n");
842 return -ETIME;
843 }
844 devpriv->config_bits |= ENABLE0_BIT | ENABLE1_BIT;
845 outw(devpriv->config_bits, dev->iobase + CONFIG_REG);
846
847 return 0;
848};
849
484ecc95 850static void a2150_detach(struct comedi_device *dev)
fe14fa2b 851{
9a1a6cf8
HS		 852 struct a2150_private *devpriv = dev->private;
853
fe14fa2b 854 if (dev->iobase) {
fe14fa2b
HS		 855 outw(APD_BIT | DPD_BIT, dev->iobase + CONFIG_REG);
856 release_region(dev->iobase, A2150_SIZE);
857 }
fe14fa2b
HS		 858 if (dev->irq)
859 free_irq(dev->irq, dev);
860 if (devpriv) {
861 if (devpriv->dma)
862 free_dma(devpriv->dma);
863 kfree(devpriv->dma_buffer);
864 }
fe14fa2b
HS		 865};
866
867static struct comedi_driver ni_at_a2150_driver = {
868 .driver_name = "ni_at_a2150",
869 .module = THIS_MODULE,
870 .attach = a2150_attach,
871 .detach = a2150_detach,
872};
873module_comedi_driver(ni_at_a2150_driver);
874
90f703d3
AT		 875MODULE_AUTHOR("Comedi http://www.comedi.org");
876MODULE_DESCRIPTION("Comedi low-level driver");
877MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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