[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_at_ao.c

/*
    comedi/drivers/ni_at_ao.c
    Driver for NI AT-AO-6/10 boards

    COMEDI - Linux Control and Measurement Device Interface
    Copyright (C) 2000,2002 David A. Schleef <ds@schleef.org>

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
*/
/*
Driver: ni_at_ao
Description: National Instruments AT-AO-6/10
Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
Status: should work
Author: ds
Updated: Sun Dec 26 12:26:28 EST 2004

Configuration options:
  [0] - I/O port base address
  [1] - IRQ (unused)
  [2] - DMA (unused)
  [3] - analog output range, set by jumpers on hardware (0 for -10 to 10V
	bipolar, 1 for 0V to 10V unipolar)

*/
/*
 * Register-level programming information can be found in NI
 * document 320379.pdf.
 */

#include "../comedidev.h"

#include <linux/ioport.h>

/* board egisters */
/* registers with _2_ are accessed when GRP2WR is set in CFG1 */

#define ATAO_SIZE 0x20

#define ATAO_2_DMATCCLR		0x00	/* W 16 */
#define ATAO_DIN		0x00	/* R 16 */
#define ATAO_DOUT		0x00	/* W 16 */

#define ATAO_CFG2		0x02	/* W 16 */
#define CALLD1	0x8000
#define CALLD0	0x4000
#define FFRTEN	0x2000
#define DAC2S8	0x1000
#define DAC2S6	0x0800
#define DAC2S4	0x0400
#define DAC2S2	0x0200
#define DAC2S0	0x0100
#define LDAC8		0x0080
#define LDAC6		0x0040
#define LDAC4		0x0020
#define LDAC2		0x0010
#define LDAC0		0x0008
#define PROMEN	0x0004
#define SCLK		0x0002
#define SDATA		0x0001

#define ATAO_2_INT1CLR		0x02	/* W 16 */

#define ATAO_CFG3		0x04	/* W 16 */
#define DMAMODE	0x0040
#define CLKOUT	0x0020
#define RCLKEN	0x0010
#define DOUTEN2	0x0008
#define DOUTEN1	0x0004
#define EN2_5V	0x0002
#define SCANEN	0x0001

#define ATAO_2_INT2CLR		0x04	/* W 16 */

#define ATAO_82C53_BASE		0x06	/* RW 8 */

#define ATAO_82C53_CNTR1	0x06	/* RW 8 */
#define ATAO_82C53_CNTR2	0x07	/* RW 8 */
#define ATAO_82C53_CNTR3	0x08	/* RW 8 */
#define ATAO_82C53_CNTRCMD	0x09	/* W 8 */
#define CNTRSEL1	0x80
#define CNTRSEL0	0x40
#define RWSEL1	0x20
#define RWSEL0	0x10
#define MODESEL2	0x08
#define MODESEL1	0x04
#define MODESEL0	0x02
#define BCDSEL	0x01
  /* read-back command */
#define COUNT		0x20
#define STATUS	0x10
#define CNTR3		0x08
#define CNTR2		0x04
#define CNTR1		0x02
  /* status */
#define OUT		0x80
#define _NULL		0x40
#define RW1		0x20
#define RW0		0x10
#define MODE2		0x08
#define MODE1		0x04
#define MODE0		0x02
#define BCD		0x01

#define ATAO_2_RTSISHFT		0x06	/* W 8 */
#define RSI		0x01

#define ATAO_2_RTSISTRB		0x07	/* W 8 */

#define ATAO_CFG1		0x0a	/* W 16 */
#define EXTINT2EN	0x8000
#define EXTINT1EN	0x4000
#define CNTINT2EN	0x2000
#define CNTINT1EN	0x1000
#define TCINTEN	0x0800
#define CNT1SRC	0x0400
#define CNT2SRC	0x0200
#define FIFOEN	0x0100
#define GRP2WR	0x0080
#define EXTUPDEN	0x0040
#define DMARQ		0x0020
#define DMAEN		0x0010
#define CH_mask	0x000f
#define ATAO_STATUS		0x0a	/* R 16 */
#define FH		0x0040
#define FE		0x0020
#define FF		0x0010
#define INT2		0x0008
#define INT1		0x0004
#define TCINT		0x0002
#define PROMOUT	0x0001

#define ATAO_FIFO_WRITE		0x0c	/* W 16 */
#define ATAO_FIFO_CLEAR		0x0c	/* R 16 */
#define ATAO_DACn(x)		(0x0c + 2*(x))	/* W */

/*
 * Board descriptions for two imaginary boards.  Describing the
 * boards in this way is optional, and completely driver-dependent.
 * Some drivers use arrays such as this, other do not.
 */
struct atao_board {
	const char *name;
	int n_ao_chans;
};

struct atao_private {

	unsigned short cfg1;
	unsigned short cfg2;
	unsigned short cfg3;

	/* Used for AO readback */
	unsigned int ao_readback[10];
};

static void atao_reset(struct comedi_device *dev)
{
	struct atao_private *devpriv = dev->private;

	/* This is the reset sequence described in the manual */

	devpriv->cfg1 = 0;
	outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);

	outb(RWSEL0 | MODESEL2, dev->iobase + ATAO_82C53_CNTRCMD);
	outb(0x03, dev->iobase + ATAO_82C53_CNTR1);
	outb(CNTRSEL0 | RWSEL0 | MODESEL2, dev->iobase + ATAO_82C53_CNTRCMD);

	devpriv->cfg2 = 0;
	outw(devpriv->cfg2, dev->iobase + ATAO_CFG2);

	devpriv->cfg3 = 0;
	outw(devpriv->cfg3, dev->iobase + ATAO_CFG3);

	inw(dev->iobase + ATAO_FIFO_CLEAR);

	devpriv->cfg1 |= GRP2WR;
	outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);

	outw(0, dev->iobase + ATAO_2_INT1CLR);
	outw(0, dev->iobase + ATAO_2_INT2CLR);
	outw(0, dev->iobase + ATAO_2_DMATCCLR);

	devpriv->cfg1 &= ~GRP2WR;
	outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
}

static int atao_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
			 struct comedi_insn *insn, unsigned int *data)
{
	struct atao_private *devpriv = dev->private;
	int i;
	int chan = CR_CHAN(insn->chanspec);
	short bits;

	for (i = 0; i < insn->n; i++) {
		bits = data[i] - 0x800;
		if (chan == 0) {
			devpriv->cfg1 |= GRP2WR;
			outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
		}
		outw(bits, dev->iobase + ATAO_DACn(chan));
		if (chan == 0) {
			devpriv->cfg1 &= ~GRP2WR;
			outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
		}
		devpriv->ao_readback[chan] = data[i];
	}

	return i;
}

static int atao_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
			 struct comedi_insn *insn, unsigned int *data)
{
	struct atao_private *devpriv = dev->private;
	int i;
	int chan = CR_CHAN(insn->chanspec);

	for (i = 0; i < insn->n; i++)
		data[i] = devpriv->ao_readback[chan];

	return i;
}

static int atao_dio_insn_bits(struct comedi_device *dev,
			      struct comedi_subdevice *s,
			      struct comedi_insn *insn, unsigned int *data)
{
	if (data[0]) {
		s->state &= ~data[0];
		s->state |= data[0] & data[1];
		outw(s->state, dev->iobase + ATAO_DOUT);
	}

	data[1] = inw(dev->iobase + ATAO_DIN);

	return insn->n;
}

static int atao_dio_insn_config(struct comedi_device *dev,
				struct comedi_subdevice *s,
				struct comedi_insn *insn, unsigned int *data)
{
	struct atao_private *devpriv = dev->private;
	int chan = CR_CHAN(insn->chanspec);
	unsigned int mask, bit;

	/* The input or output configuration of each digital line is
	 * configured by a special insn_config instruction.  chanspec
	 * contains the channel to be changed, and data[0] contains the
	 * value COMEDI_INPUT or COMEDI_OUTPUT. */

	mask = (chan < 4) ? 0x0f : 0xf0;
	bit = (chan < 4) ? DOUTEN1 : DOUTEN2;

	switch (data[0]) {
	case INSN_CONFIG_DIO_OUTPUT:
		s->io_bits |= mask;
		devpriv->cfg3 |= bit;
		break;
	case INSN_CONFIG_DIO_INPUT:
		s->io_bits &= ~mask;
		devpriv->cfg3 &= ~bit;
		break;
	case INSN_CONFIG_DIO_QUERY:
		data[1] =
		    (s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
		return insn->n;
		break;
	default:
		return -EINVAL;
		break;
	}

	outw(devpriv->cfg3, dev->iobase + ATAO_CFG3);

	return 1;
}

/*
 * Figure 2-1 in the manual shows 3 chips labeled DAC8800, which
 * are 8-channel 8-bit DACs.  These are most likely the calibration
 * DACs.  It is not explicitly stated in the manual how to access
 * the caldacs, but we can guess.
 */
static int atao_calib_insn_read(struct comedi_device *dev,
				struct comedi_subdevice *s,
				struct comedi_insn *insn, unsigned int *data)
{
	int i;
	for (i = 0; i < insn->n; i++)
		data[i] = 0;	/* XXX */
	return insn->n;
}

static int atao_calib_insn_write(struct comedi_device *dev,
				 struct comedi_subdevice *s,
				 struct comedi_insn *insn, unsigned int *data)
{
	struct atao_private *devpriv = dev->private;
	unsigned int bitstring, bit;
	unsigned int chan = CR_CHAN(insn->chanspec);

	bitstring = ((chan & 0x7) << 8) | (data[insn->n - 1] & 0xff);

	for (bit = 1 << (11 - 1); bit; bit >>= 1) {
		outw(devpriv->cfg2 | ((bit & bitstring) ? SDATA : 0),
		     dev->iobase + ATAO_CFG2);
		outw(devpriv->cfg2 | SCLK | ((bit & bitstring) ? SDATA : 0),
		     dev->iobase + ATAO_CFG2);
	}
	/* strobe the appropriate caldac */
	outw(devpriv->cfg2 | (((chan >> 3) + 1) << 14),
	     dev->iobase + ATAO_CFG2);
	outw(devpriv->cfg2, dev->iobase + ATAO_CFG2);

	return insn->n;
}

static int atao_attach(struct comedi_device *dev, struct comedi_devconfig *it)
{
	const struct atao_board *board = comedi_board(dev);
	struct atao_private *devpriv;
	struct comedi_subdevice *s;
	int ao_unipolar;
	int ret;

	ao_unipolar = it->options[3];

	ret = comedi_request_region(dev, it->options[0], ATAO_SIZE);
	if (ret)
		return ret;

	devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
	if (!devpriv)
		return -ENOMEM;
	dev->private = devpriv;

	ret = comedi_alloc_subdevices(dev, 4);
	if (ret)
		return ret;

	s = &dev->subdevices[0];
	/* analog output subdevice */
	s->type = COMEDI_SUBD_AO;
	s->subdev_flags = SDF_WRITABLE;
	s->n_chan = board->n_ao_chans;
	s->maxdata = (1 << 12) - 1;
	if (ao_unipolar)
		s->range_table = &range_unipolar10;
	else
		s->range_table = &range_bipolar10;
	s->insn_write = &atao_ao_winsn;
	s->insn_read = &atao_ao_rinsn;

	s = &dev->subdevices[1];
	/* digital i/o subdevice */
	s->type = COMEDI_SUBD_DIO;
	s->subdev_flags = SDF_READABLE | SDF_WRITABLE;
	s->n_chan = 8;
	s->maxdata = 1;
	s->range_table = &range_digital;
	s->insn_bits = atao_dio_insn_bits;
	s->insn_config = atao_dio_insn_config;

	s = &dev->subdevices[2];
	/* caldac subdevice */
	s->type = COMEDI_SUBD_CALIB;
	s->subdev_flags = SDF_WRITABLE | SDF_INTERNAL;
	s->n_chan = 21;
	s->maxdata = 0xff;
	s->insn_read = atao_calib_insn_read;
	s->insn_write = atao_calib_insn_write;

	s = &dev->subdevices[3];
	/* eeprom subdevice */
	/* s->type=COMEDI_SUBD_EEPROM; */
	s->type = COMEDI_SUBD_UNUSED;

	atao_reset(dev);

	printk(KERN_INFO "\n");

	return 0;
}

static const struct atao_board atao_boards[] = {
	{
		.name		= "ai-ao-6",
		.n_ao_chans	= 6,
	}, {
		.name		= "ai-ao-10",
		.n_ao_chans	= 10,
	},
};

static struct comedi_driver ni_at_ao_driver = {
	.driver_name	= "ni_at_ao",
	.module		= THIS_MODULE,
	.attach		= atao_attach,
	.detach		= comedi_legacy_detach,
	.board_name	= &atao_boards[0].name,
	.offset		= sizeof(struct atao_board),
	.num_names	= ARRAY_SIZE(atao_boards),
};
module_comedi_driver(ni_at_ao_driver);

MODULE_AUTHOR("Comedi http://www.comedi.org");
MODULE_DESCRIPTION("Comedi low-level driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
6a9d800f DS	1	/*
	2	comedi/drivers/ni_at_ao.c
	3	Driver for NI AT-AO-6/10 boards
	4
	5	COMEDI - Linux Control and Measurement Device Interface
	6	Copyright (C) 2000,2002 David A. Schleef <ds@schleef.org>
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
6a9d800f DS	17	*/
	18	/*
	19	Driver: ni_at_ao
	20	Description: National Instruments AT-AO-6/10
	21	Devices: [National Instruments] AT-AO-6 (at-ao-6), AT-AO-10 (at-ao-10)
	22	Status: should work
	23	Author: ds
	24	Updated: Sun Dec 26 12:26:28 EST 2004
	25
	26	Configuration options:
	27	[0] - I/O port base address
	28	[1] - IRQ (unused)
	29	[2] - DMA (unused)
d1a04408 AR	30	[3] - analog output range, set by jumpers on hardware (0 for -10 to 10V
d1a04408 AR	31	bipolar, 1 for 0V to 10V unipolar)
6a9d800f DS	32
	33	*/
	34	/*
	35	* Register-level programming information can be found in NI
	36	* document 320379.pdf.
	37	*/
	38
	39	#include "../comedidev.h"
	40
	41	#include <linux/ioport.h>
	42
	43	/* board egisters */
	44	/* registers with _2_ are accessed when GRP2WR is set in CFG1 */
	45
	46	#define ATAO_SIZE 0x20
	47
	48	#define ATAO_2_DMATCCLR 0x00 /* W 16 */
	49	#define ATAO_DIN 0x00 /* R 16 */
	50	#define ATAO_DOUT 0x00 /* W 16 */
	51
	52	#define ATAO_CFG2 0x02 /* W 16 */
	53	#define CALLD1 0x8000
	54	#define CALLD0 0x4000
	55	#define FFRTEN 0x2000
	56	#define DAC2S8 0x1000
	57	#define DAC2S6 0x0800
	58	#define DAC2S4 0x0400
	59	#define DAC2S2 0x0200
	60	#define DAC2S0 0x0100
	61	#define LDAC8 0x0080
	62	#define LDAC6 0x0040
	63	#define LDAC4 0x0020
	64	#define LDAC2 0x0010
	65	#define LDAC0 0x0008
	66	#define PROMEN 0x0004
	67	#define SCLK 0x0002
	68	#define SDATA 0x0001
	69
	70	#define ATAO_2_INT1CLR 0x02 /* W 16 */
	71
	72	#define ATAO_CFG3 0x04 /* W 16 */
	73	#define DMAMODE 0x0040
	74	#define CLKOUT 0x0020
	75	#define RCLKEN 0x0010
	76	#define DOUTEN2 0x0008
	77	#define DOUTEN1 0x0004
	78	#define EN2_5V 0x0002
	79	#define SCANEN 0x0001
	80
	81	#define ATAO_2_INT2CLR 0x04 /* W 16 */
	82
	83	#define ATAO_82C53_BASE 0x06 /* RW 8 */
	84
	85	#define ATAO_82C53_CNTR1 0x06 /* RW 8 */
	86	#define ATAO_82C53_CNTR2 0x07 /* RW 8 */
	87	#define ATAO_82C53_CNTR3 0x08 /* RW 8 */
	88	#define ATAO_82C53_CNTRCMD 0x09 /* W 8 */
	89	#define CNTRSEL1 0x80
	90	#define CNTRSEL0 0x40
	91	#define RWSEL1 0x20
	92	#define RWSEL0 0x10
	93	#define MODESEL2 0x08
	94	#define MODESEL1 0x04
	95	#define MODESEL0 0x02
96	#define BCDSEL 0x01
97	/* read-back command */
98	#define COUNT 0x20
99	#define STATUS 0x10
100	#define CNTR3 0x08
101	#define CNTR2 0x04
102	#define CNTR1 0x02
103	/* status */
104	#define OUT 0x80
105	#define _NULL 0x40
106	#define RW1 0x20
107	#define RW0 0x10
108	#define MODE2 0x08
109	#define MODE1 0x04
110	#define MODE0 0x02
111	#define BCD 0x01
112
113	#define ATAO_2_RTSISHFT 0x06 /* W 8 */
114	#define RSI 0x01
115
116	#define ATAO_2_RTSISTRB 0x07 /* W 8 */
117
118	#define ATAO_CFG1 0x0a /* W 16 */
119	#define EXTINT2EN 0x8000
120	#define EXTINT1EN 0x4000
121	#define CNTINT2EN 0x2000
122	#define CNTINT1EN 0x1000
123	#define TCINTEN 0x0800
124	#define CNT1SRC 0x0400
125	#define CNT2SRC 0x0200
126	#define FIFOEN 0x0100
127	#define GRP2WR 0x0080
128	#define EXTUPDEN 0x0040
129	#define DMARQ 0x0020
130	#define DMAEN 0x0010
131	#define CH_mask 0x000f
132	#define ATAO_STATUS 0x0a /* R 16 */
133	#define FH 0x0040
134	#define FE 0x0020
135	#define FF 0x0010
136	#define INT2 0x0008
137	#define INT1 0x0004
138	#define TCINT 0x0002
139	#define PROMOUT 0x0001
140
141	#define ATAO_FIFO_WRITE 0x0c /* W 16 */
142	#define ATAO_FIFO_CLEAR 0x0c /* R 16 */
143	#define ATAO_DACn(x) (0x0c + 2(x)) / W */
144
145	/*
146	* Board descriptions for two imaginary boards. Describing the
147	* boards in this way is optional, and completely driver-dependent.
148	* Some drivers use arrays such as this, other do not.
149	*/
01983c39	150	struct atao_board {
6a9d800f DS	151	const char *name;
6a9d800f DS	152	int n_ao_chans;
01983c39 BP	153	};
01983c39 BP	154
75b80739 BP	155	struct atao_private {
75b80739 BP	156
6a9d800f DS	157	unsigned short cfg1;
	158	unsigned short cfg2;
	159	unsigned short cfg3;
	160
	161	/* Used for AO readback */
790c5541	162	unsigned int ao_readback[10];
75b80739 BP	163	};
75b80739 BP	164
da91b269	165	static void atao_reset(struct comedi_device *dev)
6a9d800f	166	{
9a1a6cf8 HS	167	struct atao_private *devpriv = dev->private;
9a1a6cf8 HS	168
6a9d800f DS	169	/* This is the reset sequence described in the manual */
	170
	171	devpriv->cfg1 = 0;
	172	outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
	173
	174	outb(RWSEL0 \| MODESEL2, dev->iobase + ATAO_82C53_CNTRCMD);
	175	outb(0x03, dev->iobase + ATAO_82C53_CNTR1);
	176	outb(CNTRSEL0 \| RWSEL0 \| MODESEL2, dev->iobase + ATAO_82C53_CNTRCMD);
	177
	178	devpriv->cfg2 = 0;
	179	outw(devpriv->cfg2, dev->iobase + ATAO_CFG2);
	180
	181	devpriv->cfg3 = 0;
	182	outw(devpriv->cfg3, dev->iobase + ATAO_CFG3);
	183
	184	inw(dev->iobase + ATAO_FIFO_CLEAR);
	185
	186	devpriv->cfg1 \|= GRP2WR;
	187	outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
	188
	189	outw(0, dev->iobase + ATAO_2_INT1CLR);
	190	outw(0, dev->iobase + ATAO_2_INT2CLR);
	191	outw(0, dev->iobase + ATAO_2_DMATCCLR);
	192
	193	devpriv->cfg1 &= ~GRP2WR;
	194	outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
	195	}
	196
da91b269	197	static int atao_ao_winsn(struct comedi_device dev, struct comedi_subdevice s,
0a85b6f0	198	struct comedi_insn insn, unsigned int data)
6a9d800f	199	{
9a1a6cf8	200	struct atao_private *devpriv = dev->private;
6a9d800f DS	201	int i;
	202	int chan = CR_CHAN(insn->chanspec);
	203	short bits;
	204
	205	for (i = 0; i < insn->n; i++) {
	206	bits = data[i] - 0x800;
	207	if (chan == 0) {
	208	devpriv->cfg1 \|= GRP2WR;
	209	outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
	210	}
	211	outw(bits, dev->iobase + ATAO_DACn(chan));
	212	if (chan == 0) {
	213	devpriv->cfg1 &= ~GRP2WR;
	214	outw(devpriv->cfg1, dev->iobase + ATAO_CFG1);
	215	}
	216	devpriv->ao_readback[chan] = data[i];
	217	}
	218
	219	return i;
	220	}
	221
da91b269	222	static int atao_ao_rinsn(struct comedi_device dev, struct comedi_subdevice s,
0a85b6f0	223	struct comedi_insn insn, unsigned int data)
6a9d800f	224	{
9a1a6cf8	225	struct atao_private *devpriv = dev->private;
6a9d800f DS	226	int i;
	227	int chan = CR_CHAN(insn->chanspec);
	228
	229	for (i = 0; i < insn->n; i++)
	230	data[i] = devpriv->ao_readback[chan];
	231
	232	return i;
	233	}
	234
0a85b6f0 MT	235	static int atao_dio_insn_bits(struct comedi_device *dev,
	236	struct comedi_subdevice *s,
	237	struct comedi_insn insn, unsigned int data)
6a9d800f	238	{
6a9d800f DS	239	if (data[0]) {
	240	s->state &= ~data[0];
	241	s->state \|= data[0] & data[1];
	242	outw(s->state, dev->iobase + ATAO_DOUT);
	243	}
	244
	245	data[1] = inw(dev->iobase + ATAO_DIN);
	246
a2714e3e	247	return insn->n;
6a9d800f DS	248	}
6a9d800f DS	249
0a85b6f0 MT	250	static int atao_dio_insn_config(struct comedi_device *dev,
	251	struct comedi_subdevice *s,
	252	struct comedi_insn insn, unsigned int data)
6a9d800f	253	{
9a1a6cf8	254	struct atao_private *devpriv = dev->private;
6a9d800f DS	255	int chan = CR_CHAN(insn->chanspec);
	256	unsigned int mask, bit;
	257
	258	/* The input or output configuration of each digital line is
	259	* configured by a special insn_config instruction. chanspec
	260	* contains the channel to be changed, and data[0] contains the
	261	* value COMEDI_INPUT or COMEDI_OUTPUT. */
	262
	263	mask = (chan < 4) ? 0x0f : 0xf0;
	264	bit = (chan < 4) ? DOUTEN1 : DOUTEN2;
	265
	266	switch (data[0]) {
	267	case INSN_CONFIG_DIO_OUTPUT:
	268	s->io_bits \|= mask;
	269	devpriv->cfg3 \|= bit;
	270	break;
	271	case INSN_CONFIG_DIO_INPUT:
	272	s->io_bits &= ~mask;
	273	devpriv->cfg3 &= ~bit;
	274	break;
	275	case INSN_CONFIG_DIO_QUERY:
	276	data[1] =
0a85b6f0	277	(s->io_bits & (1 << chan)) ? COMEDI_OUTPUT : COMEDI_INPUT;
6a9d800f DS	278	return insn->n;
	279	break;
	280	default:
	281	return -EINVAL;
	282	break;
	283	}
	284
	285	outw(devpriv->cfg3, dev->iobase + ATAO_CFG3);
	286
	287	return 1;
	288	}
	289
	290	/*
	291	* Figure 2-1 in the manual shows 3 chips labeled DAC8800, which
	292	* are 8-channel 8-bit DACs. These are most likely the calibration
	293	* DACs. It is not explicitly stated in the manual how to access
	294	* the caldacs, but we can guess.
	295	*/
0a85b6f0 MT	296	static int atao_calib_insn_read(struct comedi_device *dev,
	297	struct comedi_subdevice *s,
	298	struct comedi_insn insn, unsigned int data)
6a9d800f DS	299	{
6a9d800f DS	300	int i;
d1a04408	301	for (i = 0; i < insn->n; i++)
6a9d800f	302	data[i] = 0; /* XXX */
6a9d800f DS	303	return insn->n;
	304	}
	305
0a85b6f0 MT	306	static int atao_calib_insn_write(struct comedi_device *dev,
	307	struct comedi_subdevice *s,
	308	struct comedi_insn insn, unsigned int data)
6a9d800f	309	{
9a1a6cf8	310	struct atao_private *devpriv = dev->private;
6a9d800f DS	311	unsigned int bitstring, bit;
	312	unsigned int chan = CR_CHAN(insn->chanspec);
	313
	314	bitstring = ((chan & 0x7) << 8) \| (data[insn->n - 1] & 0xff);
	315
	316	for (bit = 1 << (11 - 1); bit; bit >>= 1) {
	317	outw(devpriv->cfg2 \| ((bit & bitstring) ? SDATA : 0),
0a85b6f0	318	dev->iobase + ATAO_CFG2);
6a9d800f	319	outw(devpriv->cfg2 \| SCLK \| ((bit & bitstring) ? SDATA : 0),
0a85b6f0	320	dev->iobase + ATAO_CFG2);
6a9d800f DS	321	}
	322	/* strobe the appropriate caldac */
	323	outw(devpriv->cfg2 \| (((chan >> 3) + 1) << 14),
0a85b6f0	324	dev->iobase + ATAO_CFG2);
6a9d800f DS	325	outw(devpriv->cfg2, dev->iobase + ATAO_CFG2);
	326
	327	return insn->n;
	328	}
90f703d3	329
b48ed623 HS	330	static int atao_attach(struct comedi_device dev, struct comedi_devconfig it)
b48ed623 HS	331	{
75b9ad9e	332	const struct atao_board *board = comedi_board(dev);
9a1a6cf8	333	struct atao_private *devpriv;
b48ed623	334	struct comedi_subdevice *s;
b48ed623	335	int ao_unipolar;
8b6c5694	336	int ret;
b48ed623	337
b48ed623 HS	338	ao_unipolar = it->options[3];
b48ed623 HS	339
6bb3395e HS	340	ret = comedi_request_region(dev, it->options[0], ATAO_SIZE);
	341	if (ret)
	342	return ret;
b48ed623	343
c34fa261 HS	344	devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL);
	345	if (!devpriv)
	346	return -ENOMEM;
	347	dev->private = devpriv;
b48ed623	348
8b6c5694 HS	349	ret = comedi_alloc_subdevices(dev, 4);
	350	if (ret)
	351	return ret;
b48ed623	352
66c5beee	353	s = &dev->subdevices[0];
b48ed623 HS	354	/* analog output subdevice */
	355	s->type = COMEDI_SUBD_AO;
	356	s->subdev_flags = SDF_WRITABLE;
75b9ad9e	357	s->n_chan = board->n_ao_chans;
b48ed623 HS	358	s->maxdata = (1 << 12) - 1;
	359	if (ao_unipolar)
	360	s->range_table = &range_unipolar10;
	361	else
	362	s->range_table = &range_bipolar10;
	363	s->insn_write = &atao_ao_winsn;
	364	s->insn_read = &atao_ao_rinsn;
	365
66c5beee	366	s = &dev->subdevices[1];
b48ed623 HS	367	/* digital i/o subdevice */
	368	s->type = COMEDI_SUBD_DIO;
	369	s->subdev_flags = SDF_READABLE \| SDF_WRITABLE;
	370	s->n_chan = 8;
	371	s->maxdata = 1;
	372	s->range_table = &range_digital;
	373	s->insn_bits = atao_dio_insn_bits;
	374	s->insn_config = atao_dio_insn_config;
	375
66c5beee	376	s = &dev->subdevices[2];
b48ed623 HS	377	/* caldac subdevice */
	378	s->type = COMEDI_SUBD_CALIB;
	379	s->subdev_flags = SDF_WRITABLE \| SDF_INTERNAL;
	380	s->n_chan = 21;
	381	s->maxdata = 0xff;
	382	s->insn_read = atao_calib_insn_read;
	383	s->insn_write = atao_calib_insn_write;
	384
66c5beee	385	s = &dev->subdevices[3];
b48ed623 HS	386	/* eeprom subdevice */
	387	/* s->type=COMEDI_SUBD_EEPROM; */
	388	s->type = COMEDI_SUBD_UNUSED;
	389
	390	atao_reset(dev);
	391
	392	printk(KERN_INFO "\n");
	393
	394	return 0;
	395	}
	396
b48ed623 HS	397	static const struct atao_board atao_boards[] = {
	398	{
	399	.name = "ai-ao-6",
	400	.n_ao_chans = 6,
	401	}, {
	402	.name = "ai-ao-10",
	403	.n_ao_chans = 10,
	404	},
	405	};
	406
	407	static struct comedi_driver ni_at_ao_driver = {
	408	.driver_name = "ni_at_ao",
	409	.module = THIS_MODULE,
	410	.attach = atao_attach,
21208519	411	.detach = comedi_legacy_detach,
b48ed623 HS	412	.board_name = &atao_boards[0].name,
	413	.offset = sizeof(struct atao_board),
	414	.num_names = ARRAY_SIZE(atao_boards),
	415	};
	416	module_comedi_driver(ni_at_ao_driver);
	417
90f703d3 AT	418	MODULE_AUTHOR("Comedi http://www.comedi.org");
	419	MODULE_DESCRIPTION("Comedi low-level driver");
	420	MODULE_LICENSE("GPL");