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124b13b2 FMH |
1 | /* |
2 | comedi/drivers/ni_labpc.c | |
3 | Driver for National Instruments Lab-PC series boards and compatibles | |
4 | Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | ************************************************************************ | |
21 | */ | |
22 | /* | |
23 | Driver: ni_labpc | |
24 | Description: National Instruments Lab-PC (& compatibles) | |
25 | Author: Frank Mori Hess <fmhess@users.sourceforge.net> | |
26 | Devices: [National Instruments] Lab-PC-1200 (labpc-1200), | |
27 | Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) | |
28 | Status: works | |
29 | ||
30 | Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges | |
31 | and analog references will work, the available ranges/arefs will | |
32 | depend on how you have configured the jumpers on your board | |
33 | (see your owner's manual). | |
34 | ||
35 | Kernel-level ISA plug-and-play support for the lab-pc-1200 | |
36 | boards has not | |
37 | yet been added to the driver, mainly due to the fact that | |
38 | I don't know the device id numbers. If you have one | |
39 | of these boards, | |
631dd1a8 | 40 | please file a bug report at http://comedi.org/ |
124b13b2 FMH |
41 | so I can get the necessary information from you. |
42 | ||
43 | The 1200 series boards have onboard calibration dacs for correcting | |
44 | analog input/output offsets and gains. The proper settings for these | |
45 | caldacs are stored on the board's eeprom. To read the caldac values | |
46 | from the eeprom and store them into a file that can be then be used by | |
47 | comedilib, use the comedi_calibrate program. | |
48 | ||
49 | Configuration options - ISA boards: | |
50 | [0] - I/O port base address | |
51 | [1] - IRQ (optional, required for timed or externally triggered conversions) | |
52 | [2] - DMA channel (optional) | |
53 | ||
54 | Configuration options - PCI boards: | |
55 | [0] - bus (optional) | |
56 | [1] - slot (optional) | |
57 | ||
58 | The Lab-pc+ has quirky chanlist requirements | |
59 | when scanning multiple channels. Multiple channel scan | |
60 | sequence must start at highest channel, then decrement down to | |
61 | channel 0. The rest of the cards can scan down like lab-pc+ or scan | |
62 | up from channel zero. Chanlists consisting of all one channel | |
63 | are also legal, and allow you to pace conversions in bursts. | |
64 | ||
65 | */ | |
66 | ||
67 | /* | |
68 | ||
69 | NI manuals: | |
70 | 341309a (labpc-1200 register manual) | |
71 | 340914a (pci-1200) | |
72 | 320502b (lab-pc+) | |
73 | ||
74 | */ | |
75 | ||
25436dc9 | 76 | #include <linux/interrupt.h> |
5a0e3ad6 | 77 | #include <linux/slab.h> |
845d131e | 78 | #include <linux/io.h> |
124b13b2 FMH |
79 | #include "../comedidev.h" |
80 | ||
81 | #include <linux/delay.h> | |
82 | #include <asm/dma.h> | |
83 | ||
84 | #include "8253.h" | |
85 | #include "8255.h" | |
86 | #include "mite.h" | |
87 | #include "comedi_fc.h" | |
88 | #include "ni_labpc.h" | |
89 | ||
90 | #define DRV_NAME "ni_labpc" | |
91 | ||
e41a6f6d SR |
92 | /* size of io region used by board */ |
93 | #define LABPC_SIZE 32 | |
94 | /* 2 MHz master clock */ | |
95 | #define LABPC_TIMER_BASE 500 | |
124b13b2 FMH |
96 | |
97 | /* Registers for the lab-pc+ */ | |
98 | ||
f6b49620 | 99 | /* write-only registers */ |
124b13b2 FMH |
100 | #define COMMAND1_REG 0x0 |
101 | #define ADC_GAIN_MASK (0x7 << 4) | |
102 | #define ADC_CHAN_BITS(x) ((x) & 0x7) | |
e41a6f6d SR |
103 | /* enables multi channel scans */ |
104 | #define ADC_SCAN_EN_BIT 0x80 | |
124b13b2 | 105 | #define COMMAND2_REG 0x1 |
e41a6f6d SR |
106 | /* enable pretriggering (used in conjunction with SWTRIG) */ |
107 | #define PRETRIG_BIT 0x1 | |
108 | /* enable paced conversions on external trigger */ | |
109 | #define HWTRIG_BIT 0x2 | |
110 | /* enable paced conversions */ | |
111 | #define SWTRIG_BIT 0x4 | |
112 | /* use two cascaded counters for pacing */ | |
113 | #define CASCADE_BIT 0x8 | |
124b13b2 FMH |
114 | #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) |
115 | #define COMMAND3_REG 0x2 | |
e41a6f6d SR |
116 | /* enable dma transfers */ |
117 | #define DMA_EN_BIT 0x1 | |
118 | /* enable interrupts for 8255 */ | |
119 | #define DIO_INTR_EN_BIT 0x2 | |
120 | /* enable dma terminal count interrupt */ | |
121 | #define DMATC_INTR_EN_BIT 0x4 | |
122 | /* enable timer interrupt */ | |
123 | #define TIMER_INTR_EN_BIT 0x8 | |
124 | /* enable error interrupt */ | |
125 | #define ERR_INTR_EN_BIT 0x10 | |
126 | /* enable fifo not empty interrupt */ | |
127 | #define ADC_FNE_INTR_EN_BIT 0x20 | |
124b13b2 FMH |
128 | #define ADC_CONVERT_REG 0x3 |
129 | #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) | |
130 | #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) | |
131 | #define ADC_CLEAR_REG 0x8 | |
132 | #define DMATC_CLEAR_REG 0xa | |
133 | #define TIMER_CLEAR_REG 0xc | |
e41a6f6d SR |
134 | /* 1200 boards only */ |
135 | #define COMMAND6_REG 0xe | |
136 | /* select ground or common-mode reference */ | |
137 | #define ADC_COMMON_BIT 0x1 | |
138 | /* adc unipolar */ | |
139 | #define ADC_UNIP_BIT 0x2 | |
140 | /* dac unipolar */ | |
141 | #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) | |
142 | /* enable fifo half full interrupt */ | |
143 | #define ADC_FHF_INTR_EN_BIT 0x20 | |
144 | /* enable interrupt on end of hardware count */ | |
145 | #define A1_INTR_EN_BIT 0x40 | |
146 | /* scan up from channel zero instead of down to zero */ | |
147 | #define ADC_SCAN_UP_BIT 0x80 | |
124b13b2 | 148 | #define COMMAND4_REG 0xf |
e41a6f6d SR |
149 | /* enables 'interval' scanning */ |
150 | #define INTERVAL_SCAN_EN_BIT 0x1 | |
151 | /* enables external signal on counter b1 output to trigger scan */ | |
152 | #define EXT_SCAN_EN_BIT 0x2 | |
153 | /* chooses direction (output or input) for EXTCONV* line */ | |
154 | #define EXT_CONVERT_OUT_BIT 0x4 | |
155 | /* chooses differential inputs for adc (in conjunction with board jumper) */ | |
156 | #define ADC_DIFF_BIT 0x8 | |
124b13b2 | 157 | #define EXT_CONVERT_DISABLE_BIT 0x10 |
e41a6f6d SR |
158 | /* 1200 boards only, calibration stuff */ |
159 | #define COMMAND5_REG 0x1c | |
160 | /* enable eeprom for write */ | |
161 | #define EEPROM_WRITE_UNPROTECT_BIT 0x4 | |
162 | /* enable dithering */ | |
163 | #define DITHER_EN_BIT 0x8 | |
164 | /* load calibration dac */ | |
165 | #define CALDAC_LOAD_BIT 0x10 | |
166 | /* serial clock - rising edge writes, falling edge reads */ | |
167 | #define SCLOCK_BIT 0x20 | |
168 | /* serial data bit for writing to eeprom or calibration dacs */ | |
169 | #define SDATA_BIT 0x40 | |
170 | /* enable eeprom for read/write */ | |
171 | #define EEPROM_EN_BIT 0x80 | |
124b13b2 FMH |
172 | #define INTERVAL_COUNT_REG 0x1e |
173 | #define INTERVAL_LOAD_REG 0x1f | |
174 | #define INTERVAL_LOAD_BITS 0x1 | |
175 | ||
f6b49620 | 176 | /* read-only registers */ |
124b13b2 | 177 | #define STATUS1_REG 0x0 |
e41a6f6d SR |
178 | /* data is available in fifo */ |
179 | #define DATA_AVAIL_BIT 0x1 | |
180 | /* overrun has occurred */ | |
181 | #define OVERRUN_BIT 0x2 | |
182 | /* fifo overflow */ | |
183 | #define OVERFLOW_BIT 0x4 | |
25985edc | 184 | /* timer interrupt has occurred */ |
e41a6f6d | 185 | #define TIMER_BIT 0x8 |
25985edc | 186 | /* dma terminal count has occurred */ |
e41a6f6d | 187 | #define DMATC_BIT 0x10 |
25985edc | 188 | /* external trigger has occurred */ |
e41a6f6d SR |
189 | #define EXT_TRIG_BIT 0x40 |
190 | /* 1200 boards only */ | |
191 | #define STATUS2_REG 0x1d | |
192 | /* programmable eeprom serial output */ | |
193 | #define EEPROM_OUT_BIT 0x1 | |
194 | /* counter A1 terminal count */ | |
195 | #define A1_TC_BIT 0x2 | |
196 | /* fifo not half full */ | |
197 | #define FNHF_BIT 0x4 | |
124b13b2 FMH |
198 | #define ADC_FIFO_REG 0xa |
199 | ||
200 | #define DIO_BASE_REG 0x10 | |
201 | #define COUNTER_A_BASE_REG 0x14 | |
202 | #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) | |
e41a6f6d SR |
203 | /* check modes put conversion pacer output in harmless state (a0 mode 2) */ |
204 | #define INIT_A0_BITS 0x14 | |
205 | /* put hardware conversion counter output in harmless state (a1 mode 0) */ | |
206 | #define INIT_A1_BITS 0x70 | |
124b13b2 FMH |
207 | #define COUNTER_B_BASE_REG 0x18 |
208 | ||
814900c9 | 209 | static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); |
70265d24 | 210 | static irqreturn_t labpc_interrupt(int irq, void *d); |
814900c9 | 211 | static int labpc_drain_fifo(struct comedi_device *dev); |
3297d6c7 | 212 | #ifdef CONFIG_ISA_DMA_API |
814900c9 BP |
213 | static void labpc_drain_dma(struct comedi_device *dev); |
214 | static void handle_isa_dma(struct comedi_device *dev); | |
3297d6c7 | 215 | #endif |
814900c9 | 216 | static void labpc_drain_dregs(struct comedi_device *dev); |
0a85b6f0 MT |
217 | static int labpc_ai_cmdtest(struct comedi_device *dev, |
218 | struct comedi_subdevice *s, struct comedi_cmd *cmd); | |
814900c9 BP |
219 | static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); |
220 | static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, | |
0a85b6f0 | 221 | struct comedi_insn *insn, unsigned int *data); |
814900c9 | 222 | static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 223 | struct comedi_insn *insn, unsigned int *data); |
814900c9 | 224 | static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 MT |
225 | struct comedi_insn *insn, unsigned int *data); |
226 | static int labpc_calib_read_insn(struct comedi_device *dev, | |
227 | struct comedi_subdevice *s, | |
228 | struct comedi_insn *insn, unsigned int *data); | |
229 | static int labpc_calib_write_insn(struct comedi_device *dev, | |
230 | struct comedi_subdevice *s, | |
231 | struct comedi_insn *insn, unsigned int *data); | |
232 | static int labpc_eeprom_read_insn(struct comedi_device *dev, | |
233 | struct comedi_subdevice *s, | |
234 | struct comedi_insn *insn, unsigned int *data); | |
235 | static int labpc_eeprom_write_insn(struct comedi_device *dev, | |
236 | struct comedi_subdevice *s, | |
237 | struct comedi_insn *insn, | |
238 | unsigned int *data); | |
814900c9 | 239 | static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); |
d6aa8366 | 240 | #ifdef CONFIG_ISA_DMA_API |
3297d6c7 | 241 | static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd); |
d6aa8366 | 242 | #endif |
124b13b2 | 243 | static int labpc_dio_mem_callback(int dir, int port, int data, |
0a85b6f0 | 244 | unsigned long arg); |
814900c9 | 245 | static void labpc_serial_out(struct comedi_device *dev, unsigned int value, |
0a85b6f0 | 246 | unsigned int num_bits); |
814900c9 BP |
247 | static unsigned int labpc_serial_in(struct comedi_device *dev); |
248 | static unsigned int labpc_eeprom_read(struct comedi_device *dev, | |
0a85b6f0 | 249 | unsigned int address); |
814900c9 | 250 | static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); |
d6269644 | 251 | static int labpc_eeprom_write(struct comedi_device *dev, |
0a85b6f0 MT |
252 | unsigned int address, |
253 | unsigned int value); | |
814900c9 | 254 | static void write_caldac(struct comedi_device *dev, unsigned int channel, |
0a85b6f0 | 255 | unsigned int value); |
124b13b2 FMH |
256 | |
257 | enum scan_mode { | |
258 | MODE_SINGLE_CHAN, | |
259 | MODE_SINGLE_CHAN_INTERVAL, | |
260 | MODE_MULT_CHAN_UP, | |
261 | MODE_MULT_CHAN_DOWN, | |
262 | }; | |
263 | ||
f6b49620 | 264 | /* analog input ranges */ |
124b13b2 | 265 | #define NUM_LABPC_PLUS_AI_RANGES 16 |
f6b49620 | 266 | /* indicates unipolar ranges */ |
124b13b2 FMH |
267 | static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { |
268 | 0, | |
269 | 0, | |
270 | 0, | |
271 | 0, | |
272 | 0, | |
273 | 0, | |
274 | 0, | |
275 | 0, | |
276 | 1, | |
277 | 1, | |
278 | 1, | |
279 | 1, | |
280 | 1, | |
281 | 1, | |
282 | 1, | |
283 | 1, | |
284 | }; | |
285 | ||
f6b49620 | 286 | /* map range index to gain bits */ |
124b13b2 FMH |
287 | static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { |
288 | 0x00, | |
289 | 0x10, | |
290 | 0x20, | |
291 | 0x30, | |
292 | 0x40, | |
293 | 0x50, | |
294 | 0x60, | |
295 | 0x70, | |
296 | 0x00, | |
297 | 0x10, | |
298 | 0x20, | |
299 | 0x30, | |
300 | 0x40, | |
301 | 0x50, | |
302 | 0x60, | |
303 | 0x70, | |
304 | }; | |
0a85b6f0 | 305 | |
9ced1de6 | 306 | static const struct comedi_lrange range_labpc_plus_ai = { |
124b13b2 FMH |
307 | NUM_LABPC_PLUS_AI_RANGES, |
308 | { | |
0a85b6f0 MT |
309 | BIP_RANGE(5), |
310 | BIP_RANGE(4), | |
311 | BIP_RANGE(2.5), | |
312 | BIP_RANGE(1), | |
313 | BIP_RANGE(0.5), | |
314 | BIP_RANGE(0.25), | |
315 | BIP_RANGE(0.1), | |
316 | BIP_RANGE(0.05), | |
317 | UNI_RANGE(10), | |
318 | UNI_RANGE(8), | |
319 | UNI_RANGE(5), | |
320 | UNI_RANGE(2), | |
321 | UNI_RANGE(1), | |
322 | UNI_RANGE(0.5), | |
323 | UNI_RANGE(0.2), | |
324 | UNI_RANGE(0.1), | |
325 | } | |
124b13b2 FMH |
326 | }; |
327 | ||
328 | #define NUM_LABPC_1200_AI_RANGES 14 | |
f6b49620 | 329 | /* indicates unipolar ranges */ |
124b13b2 FMH |
330 | const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { |
331 | 0, | |
332 | 0, | |
333 | 0, | |
334 | 0, | |
335 | 0, | |
336 | 0, | |
337 | 0, | |
338 | 1, | |
339 | 1, | |
340 | 1, | |
341 | 1, | |
342 | 1, | |
343 | 1, | |
344 | 1, | |
345 | }; | |
0656bb35 | 346 | EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); |
124b13b2 | 347 | |
f6b49620 | 348 | /* map range index to gain bits */ |
124b13b2 FMH |
349 | const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { |
350 | 0x00, | |
351 | 0x20, | |
352 | 0x30, | |
353 | 0x40, | |
354 | 0x50, | |
355 | 0x60, | |
356 | 0x70, | |
357 | 0x00, | |
358 | 0x20, | |
359 | 0x30, | |
360 | 0x40, | |
361 | 0x50, | |
362 | 0x60, | |
363 | 0x70, | |
364 | }; | |
0656bb35 | 365 | EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); |
0a85b6f0 | 366 | |
9ced1de6 | 367 | const struct comedi_lrange range_labpc_1200_ai = { |
124b13b2 FMH |
368 | NUM_LABPC_1200_AI_RANGES, |
369 | { | |
0a85b6f0 MT |
370 | BIP_RANGE(5), |
371 | BIP_RANGE(2.5), | |
372 | BIP_RANGE(1), | |
373 | BIP_RANGE(0.5), | |
374 | BIP_RANGE(0.25), | |
375 | BIP_RANGE(0.1), | |
376 | BIP_RANGE(0.05), | |
377 | UNI_RANGE(10), | |
378 | UNI_RANGE(5), | |
379 | UNI_RANGE(2), | |
380 | UNI_RANGE(1), | |
381 | UNI_RANGE(0.5), | |
382 | UNI_RANGE(0.2), | |
383 | UNI_RANGE(0.1), | |
384 | } | |
124b13b2 | 385 | }; |
0656bb35 | 386 | EXPORT_SYMBOL_GPL(range_labpc_1200_ai); |
124b13b2 | 387 | |
f6b49620 | 388 | /* analog output ranges */ |
124b13b2 | 389 | #define AO_RANGE_IS_UNIPOLAR 0x1 |
9ced1de6 | 390 | static const struct comedi_lrange range_labpc_ao = { |
124b13b2 FMH |
391 | 2, |
392 | { | |
0a85b6f0 MT |
393 | BIP_RANGE(5), |
394 | UNI_RANGE(10), | |
395 | } | |
124b13b2 FMH |
396 | }; |
397 | ||
398 | /* functions that do inb/outb and readb/writeb so we can use | |
399 | * function pointers to decide which to use */ | |
400 | static inline unsigned int labpc_inb(unsigned long address) | |
401 | { | |
402 | return inb(address); | |
403 | } | |
0a85b6f0 | 404 | |
124b13b2 FMH |
405 | static inline void labpc_outb(unsigned int byte, unsigned long address) |
406 | { | |
407 | outb(byte, address); | |
408 | } | |
0a85b6f0 | 409 | |
124b13b2 FMH |
410 | static inline unsigned int labpc_readb(unsigned long address) |
411 | { | |
412 | return readb((void *)address); | |
413 | } | |
0a85b6f0 | 414 | |
124b13b2 FMH |
415 | static inline void labpc_writeb(unsigned int byte, unsigned long address) |
416 | { | |
417 | writeb(byte, (void *)address); | |
418 | } | |
419 | ||
9ad00740 | 420 | static const struct labpc_board_struct labpc_boards[] = { |
124b13b2 | 421 | { |
0a85b6f0 MT |
422 | .name = "lab-pc-1200", |
423 | .ai_speed = 10000, | |
424 | .bustype = isa_bustype, | |
425 | .register_layout = labpc_1200_layout, | |
426 | .has_ao = 1, | |
427 | .ai_range_table = &range_labpc_1200_ai, | |
428 | .ai_range_code = labpc_1200_ai_gain_bits, | |
429 | .ai_range_is_unipolar = labpc_1200_is_unipolar, | |
430 | .ai_scan_up = 1, | |
431 | .memory_mapped_io = 0, | |
432 | }, | |
124b13b2 | 433 | { |
0a85b6f0 MT |
434 | .name = "lab-pc-1200ai", |
435 | .ai_speed = 10000, | |
436 | .bustype = isa_bustype, | |
437 | .register_layout = labpc_1200_layout, | |
438 | .has_ao = 0, | |
439 | .ai_range_table = &range_labpc_1200_ai, | |
440 | .ai_range_code = labpc_1200_ai_gain_bits, | |
441 | .ai_range_is_unipolar = labpc_1200_is_unipolar, | |
442 | .ai_scan_up = 1, | |
443 | .memory_mapped_io = 0, | |
444 | }, | |
124b13b2 | 445 | { |
0a85b6f0 MT |
446 | .name = "lab-pc+", |
447 | .ai_speed = 12000, | |
448 | .bustype = isa_bustype, | |
449 | .register_layout = labpc_plus_layout, | |
450 | .has_ao = 1, | |
451 | .ai_range_table = &range_labpc_plus_ai, | |
452 | .ai_range_code = labpc_plus_ai_gain_bits, | |
453 | .ai_range_is_unipolar = labpc_plus_is_unipolar, | |
454 | .ai_scan_up = 0, | |
455 | .memory_mapped_io = 0, | |
456 | }, | |
d6aa8366 | 457 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
124b13b2 | 458 | { |
0a85b6f0 MT |
459 | .name = "pci-1200", |
460 | .device_id = 0x161, | |
461 | .ai_speed = 10000, | |
462 | .bustype = pci_bustype, | |
463 | .register_layout = labpc_1200_layout, | |
464 | .has_ao = 1, | |
465 | .ai_range_table = &range_labpc_1200_ai, | |
466 | .ai_range_code = labpc_1200_ai_gain_bits, | |
467 | .ai_range_is_unipolar = labpc_1200_is_unipolar, | |
468 | .ai_scan_up = 1, | |
469 | .memory_mapped_io = 1, | |
470 | }, | |
e41a6f6d | 471 | /* dummy entry so pci board works when comedi_config is passed driver name */ |
124b13b2 | 472 | { |
0a85b6f0 MT |
473 | .name = DRV_NAME, |
474 | .bustype = pci_bustype, | |
475 | }, | |
124b13b2 FMH |
476 | #endif |
477 | }; | |
478 | ||
479 | /* | |
480 | * Useful for shorthand access to the particular board structure | |
481 | */ | |
9ad00740 | 482 | #define thisboard ((struct labpc_board_struct *)dev->board_ptr) |
124b13b2 | 483 | |
e41a6f6d SR |
484 | /* size in bytes of dma buffer */ |
485 | static const int dma_buffer_size = 0xff00; | |
486 | /* 2 bytes per sample */ | |
487 | static const int sample_size = 2; | |
124b13b2 | 488 | |
0a4eb4b6 | 489 | #define devpriv ((struct labpc_private *)dev->private) |
124b13b2 | 490 | |
da91b269 | 491 | static inline int labpc_counter_load(struct comedi_device *dev, |
0a85b6f0 MT |
492 | unsigned long base_address, |
493 | unsigned int counter_number, | |
494 | unsigned int count, unsigned int mode) | |
124b13b2 FMH |
495 | { |
496 | if (thisboard->memory_mapped_io) | |
497 | return i8254_mm_load((void *)base_address, 0, counter_number, | |
0a85b6f0 | 498 | count, mode); |
124b13b2 FMH |
499 | else |
500 | return i8254_load(base_address, 0, counter_number, count, mode); | |
501 | } | |
502 | ||
da91b269 | 503 | int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, |
0a85b6f0 | 504 | unsigned int irq, unsigned int dma_chan) |
124b13b2 | 505 | { |
34c43922 | 506 | struct comedi_subdevice *s; |
124b13b2 | 507 | int i; |
3297d6c7 RD |
508 | unsigned long isr_flags; |
509 | #ifdef CONFIG_ISA_DMA_API | |
510 | unsigned long dma_flags; | |
511 | #endif | |
124b13b2 | 512 | short lsb, msb; |
8b6c5694 | 513 | int ret; |
124b13b2 | 514 | |
1cabcd31 | 515 | dev_info(dev->class_dev, "ni_labpc: %s\n", thisboard->name); |
124b13b2 | 516 | if (iobase == 0) { |
1cabcd31 | 517 | dev_err(dev->class_dev, "io base address is zero!\n"); |
124b13b2 FMH |
518 | return -EINVAL; |
519 | } | |
f6b49620 | 520 | /* request io regions for isa boards */ |
124b13b2 FMH |
521 | if (thisboard->bustype == isa_bustype) { |
522 | /* check if io addresses are available */ | |
5e51f0db | 523 | if (!request_region(iobase, LABPC_SIZE, DRV_NAME)) { |
1cabcd31 | 524 | dev_err(dev->class_dev, "I/O port conflict\n"); |
124b13b2 FMH |
525 | return -EIO; |
526 | } | |
527 | } | |
528 | dev->iobase = iobase; | |
529 | ||
530 | if (thisboard->memory_mapped_io) { | |
531 | devpriv->read_byte = labpc_readb; | |
532 | devpriv->write_byte = labpc_writeb; | |
533 | } else { | |
534 | devpriv->read_byte = labpc_inb; | |
535 | devpriv->write_byte = labpc_outb; | |
536 | } | |
e41a6f6d | 537 | /* initialize board's command registers */ |
124b13b2 FMH |
538 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); |
539 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
540 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
541 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); | |
542 | if (thisboard->register_layout == labpc_1200_layout) { | |
543 | devpriv->write_byte(devpriv->command5_bits, | |
0a85b6f0 | 544 | dev->iobase + COMMAND5_REG); |
124b13b2 | 545 | devpriv->write_byte(devpriv->command6_bits, |
0a85b6f0 | 546 | dev->iobase + COMMAND6_REG); |
124b13b2 FMH |
547 | } |
548 | ||
549 | /* grab our IRQ */ | |
550 | if (irq) { | |
551 | isr_flags = 0; | |
d1ce3184 IA |
552 | if (thisboard->bustype == pci_bustype |
553 | || thisboard->bustype == pcmcia_bustype) | |
124b13b2 | 554 | isr_flags |= IRQF_SHARED; |
5f74ea14 | 555 | if (request_irq(irq, labpc_interrupt, isr_flags, |
5e51f0db | 556 | DRV_NAME, dev)) { |
1cabcd31 IA |
557 | dev_err(dev->class_dev, "unable to allocate irq %u\n", |
558 | irq); | |
124b13b2 FMH |
559 | return -EINVAL; |
560 | } | |
561 | } | |
562 | dev->irq = irq; | |
563 | ||
3297d6c7 | 564 | #ifdef CONFIG_ISA_DMA_API |
e41a6f6d | 565 | /* grab dma channel */ |
124b13b2 | 566 | if (dma_chan > 3) { |
1cabcd31 | 567 | dev_err(dev->class_dev, "invalid dma channel %u\n", dma_chan); |
124b13b2 FMH |
568 | return -EINVAL; |
569 | } else if (dma_chan) { | |
e41a6f6d | 570 | /* allocate dma buffer */ |
124b13b2 | 571 | devpriv->dma_buffer = |
0a85b6f0 | 572 | kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); |
124b13b2 | 573 | if (devpriv->dma_buffer == NULL) { |
1cabcd31 IA |
574 | dev_err(dev->class_dev, |
575 | "failed to allocate dma buffer\n"); | |
124b13b2 FMH |
576 | return -ENOMEM; |
577 | } | |
5e51f0db | 578 | if (request_dma(dma_chan, DRV_NAME)) { |
1cabcd31 IA |
579 | dev_err(dev->class_dev, |
580 | "failed to allocate dma channel %u\n", | |
581 | dma_chan); | |
124b13b2 FMH |
582 | return -EINVAL; |
583 | } | |
584 | devpriv->dma_chan = dma_chan; | |
585 | dma_flags = claim_dma_lock(); | |
586 | disable_dma(devpriv->dma_chan); | |
587 | set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); | |
588 | release_dma_lock(dma_flags); | |
589 | } | |
3297d6c7 | 590 | #endif |
124b13b2 FMH |
591 | |
592 | dev->board_name = thisboard->name; | |
593 | ||
8b6c5694 HS |
594 | ret = comedi_alloc_subdevices(dev, 5); |
595 | if (ret) | |
596 | return ret; | |
124b13b2 FMH |
597 | |
598 | /* analog input subdevice */ | |
c65e3be1 | 599 | s = &dev->subdevices[0]; |
124b13b2 FMH |
600 | dev->read_subdev = s; |
601 | s->type = COMEDI_SUBD_AI; | |
602 | s->subdev_flags = | |
0a85b6f0 | 603 | SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; |
124b13b2 FMH |
604 | s->n_chan = 8; |
605 | s->len_chanlist = 8; | |
e41a6f6d | 606 | s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ |
124b13b2 FMH |
607 | s->range_table = thisboard->ai_range_table; |
608 | s->do_cmd = labpc_ai_cmd; | |
609 | s->do_cmdtest = labpc_ai_cmdtest; | |
610 | s->insn_read = labpc_ai_rinsn; | |
611 | s->cancel = labpc_cancel; | |
612 | ||
613 | /* analog output */ | |
c65e3be1 | 614 | s = &dev->subdevices[1]; |
124b13b2 | 615 | if (thisboard->has_ao) { |
639b9f1e SR |
616 | /* |
617 | * Could provide command support, except it only has a | |
412bd046 | 618 | * one sample hardware buffer for analog output and no |
639b9f1e SR |
619 | * underrun flag. |
620 | */ | |
124b13b2 FMH |
621 | s->type = COMEDI_SUBD_AO; |
622 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; | |
623 | s->n_chan = NUM_AO_CHAN; | |
f6b49620 | 624 | s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ |
124b13b2 FMH |
625 | s->range_table = &range_labpc_ao; |
626 | s->insn_read = labpc_ao_rinsn; | |
627 | s->insn_write = labpc_ao_winsn; | |
628 | /* initialize analog outputs to a known value */ | |
629 | for (i = 0; i < s->n_chan; i++) { | |
630 | devpriv->ao_value[i] = s->maxdata / 2; | |
631 | lsb = devpriv->ao_value[i] & 0xff; | |
632 | msb = (devpriv->ao_value[i] >> 8) & 0xff; | |
633 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); | |
634 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); | |
635 | } | |
636 | } else { | |
637 | s->type = COMEDI_SUBD_UNUSED; | |
638 | } | |
639 | ||
640 | /* 8255 dio */ | |
c65e3be1 | 641 | s = &dev->subdevices[2]; |
412bd046 | 642 | /* if board uses io memory we have to give a custom callback |
643 | * function to the 8255 driver */ | |
124b13b2 FMH |
644 | if (thisboard->memory_mapped_io) |
645 | subdev_8255_init(dev, s, labpc_dio_mem_callback, | |
0a85b6f0 | 646 | (unsigned long)(dev->iobase + DIO_BASE_REG)); |
124b13b2 FMH |
647 | else |
648 | subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); | |
649 | ||
f6b49620 | 650 | /* calibration subdevices for boards that have one */ |
c65e3be1 | 651 | s = &dev->subdevices[3]; |
124b13b2 FMH |
652 | if (thisboard->register_layout == labpc_1200_layout) { |
653 | s->type = COMEDI_SUBD_CALIB; | |
654 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; | |
655 | s->n_chan = 16; | |
656 | s->maxdata = 0xff; | |
657 | s->insn_read = labpc_calib_read_insn; | |
658 | s->insn_write = labpc_calib_write_insn; | |
659 | ||
660 | for (i = 0; i < s->n_chan; i++) | |
661 | write_caldac(dev, i, s->maxdata / 2); | |
662 | } else | |
663 | s->type = COMEDI_SUBD_UNUSED; | |
664 | ||
665 | /* EEPROM */ | |
c65e3be1 | 666 | s = &dev->subdevices[4]; |
124b13b2 FMH |
667 | if (thisboard->register_layout == labpc_1200_layout) { |
668 | s->type = COMEDI_SUBD_MEMORY; | |
669 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; | |
670 | s->n_chan = EEPROM_SIZE; | |
671 | s->maxdata = 0xff; | |
672 | s->insn_read = labpc_eeprom_read_insn; | |
673 | s->insn_write = labpc_eeprom_write_insn; | |
674 | ||
412bd046 | 675 | for (i = 0; i < EEPROM_SIZE; i++) |
124b13b2 | 676 | devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); |
124b13b2 FMH |
677 | } else |
678 | s->type = COMEDI_SUBD_UNUSED; | |
679 | ||
680 | return 0; | |
681 | } | |
0656bb35 | 682 | EXPORT_SYMBOL_GPL(labpc_common_attach); |
124b13b2 | 683 | |
7e2716cd IA |
684 | static const struct labpc_board_struct * |
685 | labpc_pci_find_boardinfo(struct pci_dev *pcidev) | |
686 | { | |
687 | unsigned int device_id = pcidev->device; | |
688 | unsigned int n; | |
689 | ||
690 | for (n = 0; n < ARRAY_SIZE(labpc_boards); n++) { | |
691 | const struct labpc_board_struct *board = &labpc_boards[n]; | |
692 | if (board->bustype == pci_bustype && | |
693 | board->device_id == device_id) | |
694 | return board; | |
695 | } | |
696 | return NULL; | |
697 | } | |
698 | ||
7e2716cd IA |
699 | static int __devinit labpc_attach_pci(struct comedi_device *dev, |
700 | struct pci_dev *pcidev) | |
701 | { | |
702 | unsigned long iobase; | |
703 | unsigned int irq; | |
704 | int ret; | |
705 | ||
706 | if (!IS_ENABLED(CONFIG_COMEDI_PCI_DRIVERS)) | |
707 | return -ENODEV; | |
708 | ret = alloc_private(dev, sizeof(struct labpc_private)); | |
709 | if (ret < 0) | |
710 | return ret; | |
711 | dev->board_ptr = labpc_pci_find_boardinfo(pcidev); | |
712 | if (!dev->board_ptr) | |
713 | return -ENODEV; | |
e4ff75b5 | 714 | devpriv->mite = mite_alloc(pcidev); |
7e2716cd | 715 | if (!devpriv->mite) |
e4ff75b5 | 716 | return -ENOMEM; |
7e2716cd IA |
717 | ret = mite_setup(devpriv->mite); |
718 | if (ret < 0) | |
719 | return ret; | |
720 | iobase = (unsigned long)devpriv->mite->daq_io_addr; | |
721 | irq = mite_irq(devpriv->mite); | |
722 | return labpc_common_attach(dev, iobase, irq, 0); | |
723 | } | |
724 | ||
da91b269 | 725 | static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) |
124b13b2 FMH |
726 | { |
727 | unsigned long iobase = 0; | |
728 | unsigned int irq = 0; | |
729 | unsigned int dma_chan = 0; | |
124b13b2 FMH |
730 | |
731 | /* allocate and initialize dev->private */ | |
0a4eb4b6 | 732 | if (alloc_private(dev, sizeof(struct labpc_private)) < 0) |
124b13b2 FMH |
733 | return -ENOMEM; |
734 | ||
e41a6f6d | 735 | /* get base address, irq etc. based on bustype */ |
124b13b2 FMH |
736 | switch (thisboard->bustype) { |
737 | case isa_bustype: | |
3297d6c7 | 738 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 FMH |
739 | iobase = it->options[0]; |
740 | irq = it->options[1]; | |
741 | dma_chan = it->options[2]; | |
3297d6c7 | 742 | #else |
1cabcd31 IA |
743 | dev_err(dev->class_dev, |
744 | "ni_labpc driver has not been built with ISA DMA support.\n"); | |
3297d6c7 RD |
745 | return -EINVAL; |
746 | #endif | |
124b13b2 FMH |
747 | break; |
748 | case pci_bustype: | |
d6aa8366 | 749 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
7e2716cd IA |
750 | dev_err(dev->class_dev, |
751 | "manual configuration of PCI board '%s' is not supported\n", | |
752 | thisboard->name); | |
753 | return -EINVAL; | |
124b13b2 | 754 | #else |
1cabcd31 IA |
755 | dev_err(dev->class_dev, |
756 | "ni_labpc driver has not been built with PCI support.\n"); | |
124b13b2 FMH |
757 | return -EINVAL; |
758 | #endif | |
759 | break; | |
124b13b2 | 760 | default: |
1cabcd31 IA |
761 | dev_err(dev->class_dev, |
762 | "ni_labpc: bug! couldn't determine board type\n"); | |
124b13b2 FMH |
763 | return -EINVAL; |
764 | break; | |
765 | } | |
766 | ||
767 | return labpc_common_attach(dev, iobase, irq, dma_chan); | |
768 | } | |
769 | ||
484ecc95 | 770 | void labpc_common_detach(struct comedi_device *dev) |
124b13b2 | 771 | { |
c65e3be1 HS |
772 | struct comedi_subdevice *s; |
773 | ||
774 | if (dev->subdevices) { | |
775 | s = &dev->subdevices[2]; | |
776 | subdev_8255_cleanup(dev, s); | |
777 | } | |
3297d6c7 | 778 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 | 779 | /* only free stuff if it has been allocated by _attach */ |
e4e1f289 | 780 | kfree(devpriv->dma_buffer); |
124b13b2 FMH |
781 | if (devpriv->dma_chan) |
782 | free_dma(devpriv->dma_chan); | |
3297d6c7 | 783 | #endif |
124b13b2 | 784 | if (dev->irq) |
5f74ea14 | 785 | free_irq(dev->irq, dev); |
124b13b2 FMH |
786 | if (thisboard->bustype == isa_bustype && dev->iobase) |
787 | release_region(dev->iobase, LABPC_SIZE); | |
d6aa8366 | 788 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
e4ff75b5 | 789 | if (devpriv->mite) { |
124b13b2 | 790 | mite_unsetup(devpriv->mite); |
e4ff75b5 IA |
791 | mite_free(devpriv->mite); |
792 | } | |
124b13b2 | 793 | #endif |
124b13b2 | 794 | }; |
0656bb35 | 795 | EXPORT_SYMBOL_GPL(labpc_common_detach); |
124b13b2 | 796 | |
da91b269 | 797 | static void labpc_clear_adc_fifo(const struct comedi_device *dev) |
124b13b2 FMH |
798 | { |
799 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); | |
800 | devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
801 | devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
802 | } | |
803 | ||
da91b269 | 804 | static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
124b13b2 FMH |
805 | { |
806 | unsigned long flags; | |
807 | ||
5f74ea14 | 808 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
809 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
810 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 811 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
812 | |
813 | devpriv->command3_bits = 0; | |
814 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
815 | ||
816 | return 0; | |
817 | } | |
818 | ||
da91b269 | 819 | static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) |
124b13b2 FMH |
820 | { |
821 | if (cmd->chanlist_len == 1) | |
822 | return MODE_SINGLE_CHAN; | |
823 | ||
824 | /* chanlist may be NULL during cmdtest. */ | |
825 | if (cmd->chanlist == NULL) | |
826 | return MODE_MULT_CHAN_UP; | |
827 | ||
828 | if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) | |
829 | return MODE_SINGLE_CHAN_INTERVAL; | |
830 | ||
831 | if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) | |
832 | return MODE_MULT_CHAN_UP; | |
833 | ||
834 | if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) | |
835 | return MODE_MULT_CHAN_DOWN; | |
836 | ||
1cabcd31 | 837 | pr_err("ni_labpc: bug! cannot determine AI scan mode\n"); |
124b13b2 FMH |
838 | return 0; |
839 | } | |
840 | ||
da91b269 | 841 | static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, |
0a85b6f0 | 842 | const struct comedi_cmd *cmd) |
124b13b2 FMH |
843 | { |
844 | int mode, channel, range, aref, i; | |
845 | ||
846 | if (cmd->chanlist == NULL) | |
847 | return 0; | |
848 | ||
849 | mode = labpc_ai_scan_mode(cmd); | |
850 | ||
851 | if (mode == MODE_SINGLE_CHAN) | |
852 | return 0; | |
853 | ||
854 | if (mode == MODE_SINGLE_CHAN_INTERVAL) { | |
855 | if (cmd->chanlist_len > 0xff) { | |
856 | comedi_error(dev, | |
0a85b6f0 | 857 | "ni_labpc: chanlist too long for single channel interval mode\n"); |
124b13b2 FMH |
858 | return 1; |
859 | } | |
860 | } | |
861 | ||
862 | channel = CR_CHAN(cmd->chanlist[0]); | |
863 | range = CR_RANGE(cmd->chanlist[0]); | |
864 | aref = CR_AREF(cmd->chanlist[0]); | |
865 | ||
866 | for (i = 0; i < cmd->chanlist_len; i++) { | |
867 | ||
868 | switch (mode) { | |
869 | case MODE_SINGLE_CHAN_INTERVAL: | |
870 | if (CR_CHAN(cmd->chanlist[i]) != channel) { | |
871 | comedi_error(dev, | |
0a85b6f0 | 872 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
124b13b2 FMH |
873 | return 1; |
874 | } | |
875 | break; | |
876 | case MODE_MULT_CHAN_UP: | |
877 | if (CR_CHAN(cmd->chanlist[i]) != i) { | |
878 | comedi_error(dev, | |
0a85b6f0 | 879 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
124b13b2 FMH |
880 | return 1; |
881 | } | |
882 | break; | |
883 | case MODE_MULT_CHAN_DOWN: | |
884 | if (CR_CHAN(cmd->chanlist[i]) != | |
0a85b6f0 | 885 | cmd->chanlist_len - i - 1) { |
124b13b2 | 886 | comedi_error(dev, |
0a85b6f0 | 887 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
124b13b2 FMH |
888 | return 1; |
889 | } | |
890 | break; | |
891 | default: | |
1cabcd31 IA |
892 | dev_err(dev->class_dev, |
893 | "ni_labpc: bug! in chanlist check\n"); | |
124b13b2 FMH |
894 | return 1; |
895 | break; | |
896 | } | |
897 | ||
898 | if (CR_RANGE(cmd->chanlist[i]) != range) { | |
899 | comedi_error(dev, | |
0a85b6f0 | 900 | "entries in chanlist must all have the same range\n"); |
124b13b2 FMH |
901 | return 1; |
902 | } | |
903 | ||
904 | if (CR_AREF(cmd->chanlist[i]) != aref) { | |
905 | comedi_error(dev, | |
0a85b6f0 | 906 | "entries in chanlist must all have the same reference\n"); |
124b13b2 FMH |
907 | return 1; |
908 | } | |
909 | } | |
910 | ||
911 | return 0; | |
912 | } | |
913 | ||
da91b269 | 914 | static int labpc_use_continuous_mode(const struct comedi_cmd *cmd) |
124b13b2 FMH |
915 | { |
916 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN) | |
917 | return 1; | |
918 | ||
919 | if (cmd->scan_begin_src == TRIG_FOLLOW) | |
920 | return 1; | |
921 | ||
922 | return 0; | |
923 | } | |
924 | ||
da91b269 | 925 | static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd) |
124b13b2 FMH |
926 | { |
927 | if (cmd->convert_src != TRIG_TIMER) | |
928 | return 0; | |
929 | ||
930 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && | |
0a85b6f0 | 931 | cmd->scan_begin_src == TRIG_TIMER) |
124b13b2 FMH |
932 | return cmd->scan_begin_arg; |
933 | ||
934 | return cmd->convert_arg; | |
935 | } | |
936 | ||
da91b269 | 937 | static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns) |
124b13b2 FMH |
938 | { |
939 | if (cmd->convert_src != TRIG_TIMER) | |
940 | return; | |
941 | ||
942 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && | |
0a85b6f0 | 943 | cmd->scan_begin_src == TRIG_TIMER) { |
124b13b2 FMH |
944 | cmd->scan_begin_arg = ns; |
945 | if (cmd->convert_arg > cmd->scan_begin_arg) | |
946 | cmd->convert_arg = cmd->scan_begin_arg; | |
947 | } else | |
948 | cmd->convert_arg = ns; | |
949 | } | |
950 | ||
da91b269 | 951 | static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd) |
124b13b2 FMH |
952 | { |
953 | if (cmd->scan_begin_src != TRIG_TIMER) | |
954 | return 0; | |
955 | ||
956 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && | |
0a85b6f0 | 957 | cmd->convert_src == TRIG_TIMER) |
124b13b2 FMH |
958 | return 0; |
959 | ||
960 | return cmd->scan_begin_arg; | |
961 | } | |
962 | ||
da91b269 | 963 | static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns) |
124b13b2 FMH |
964 | { |
965 | if (cmd->scan_begin_src != TRIG_TIMER) | |
966 | return; | |
967 | ||
968 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && | |
0a85b6f0 | 969 | cmd->convert_src == TRIG_TIMER) |
124b13b2 FMH |
970 | return; |
971 | ||
972 | cmd->scan_begin_arg = ns; | |
973 | } | |
974 | ||
0a85b6f0 MT |
975 | static int labpc_ai_cmdtest(struct comedi_device *dev, |
976 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
124b13b2 FMH |
977 | { |
978 | int err = 0; | |
979 | int tmp, tmp2; | |
980 | int stop_mask; | |
981 | ||
982 | /* step 1: make sure trigger sources are trivially valid */ | |
983 | ||
984 | tmp = cmd->start_src; | |
985 | cmd->start_src &= TRIG_NOW | TRIG_EXT; | |
986 | if (!cmd->start_src || tmp != cmd->start_src) | |
987 | err++; | |
988 | ||
989 | tmp = cmd->scan_begin_src; | |
990 | cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT; | |
991 | if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) | |
992 | err++; | |
993 | ||
994 | tmp = cmd->convert_src; | |
995 | cmd->convert_src &= TRIG_TIMER | TRIG_EXT; | |
996 | if (!cmd->convert_src || tmp != cmd->convert_src) | |
997 | err++; | |
998 | ||
999 | tmp = cmd->scan_end_src; | |
1000 | cmd->scan_end_src &= TRIG_COUNT; | |
1001 | if (!cmd->scan_end_src || tmp != cmd->scan_end_src) | |
1002 | err++; | |
1003 | ||
1004 | tmp = cmd->stop_src; | |
1005 | stop_mask = TRIG_COUNT | TRIG_NONE; | |
1006 | if (thisboard->register_layout == labpc_1200_layout) | |
1007 | stop_mask |= TRIG_EXT; | |
1008 | cmd->stop_src &= stop_mask; | |
1009 | if (!cmd->stop_src || tmp != cmd->stop_src) | |
1010 | err++; | |
1011 | ||
1012 | if (err) | |
1013 | return 1; | |
1014 | ||
1015 | /* step 2: make sure trigger sources are unique and mutually compatible */ | |
1016 | ||
1017 | if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) | |
1018 | err++; | |
1019 | if (cmd->scan_begin_src != TRIG_TIMER && | |
0a85b6f0 MT |
1020 | cmd->scan_begin_src != TRIG_FOLLOW && |
1021 | cmd->scan_begin_src != TRIG_EXT) | |
124b13b2 FMH |
1022 | err++; |
1023 | if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) | |
1024 | err++; | |
1025 | if (cmd->stop_src != TRIG_COUNT && | |
0a85b6f0 | 1026 | cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) |
124b13b2 FMH |
1027 | err++; |
1028 | ||
e41a6f6d | 1029 | /* can't have external stop and start triggers at once */ |
124b13b2 FMH |
1030 | if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) |
1031 | err++; | |
1032 | ||
1033 | if (err) | |
1034 | return 2; | |
1035 | ||
1036 | /* step 3: make sure arguments are trivially compatible */ | |
1037 | ||
1038 | if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { | |
1039 | cmd->start_arg = 0; | |
1040 | err++; | |
1041 | } | |
1042 | ||
412bd046 | 1043 | if (!cmd->chanlist_len) |
124b13b2 | 1044 | err++; |
412bd046 | 1045 | |
124b13b2 FMH |
1046 | if (cmd->scan_end_arg != cmd->chanlist_len) { |
1047 | cmd->scan_end_arg = cmd->chanlist_len; | |
1048 | err++; | |
1049 | } | |
1050 | ||
1051 | if (cmd->convert_src == TRIG_TIMER) { | |
1052 | if (cmd->convert_arg < thisboard->ai_speed) { | |
1053 | cmd->convert_arg = thisboard->ai_speed; | |
1054 | err++; | |
1055 | } | |
1056 | } | |
e41a6f6d | 1057 | /* make sure scan timing is not too fast */ |
124b13b2 FMH |
1058 | if (cmd->scan_begin_src == TRIG_TIMER) { |
1059 | if (cmd->convert_src == TRIG_TIMER && | |
0a85b6f0 MT |
1060 | cmd->scan_begin_arg < |
1061 | cmd->convert_arg * cmd->chanlist_len) { | |
124b13b2 | 1062 | cmd->scan_begin_arg = |
0a85b6f0 | 1063 | cmd->convert_arg * cmd->chanlist_len; |
124b13b2 FMH |
1064 | err++; |
1065 | } | |
1066 | if (cmd->scan_begin_arg < | |
0a85b6f0 | 1067 | thisboard->ai_speed * cmd->chanlist_len) { |
124b13b2 | 1068 | cmd->scan_begin_arg = |
0a85b6f0 | 1069 | thisboard->ai_speed * cmd->chanlist_len; |
124b13b2 FMH |
1070 | err++; |
1071 | } | |
1072 | } | |
e41a6f6d | 1073 | /* stop source */ |
124b13b2 FMH |
1074 | switch (cmd->stop_src) { |
1075 | case TRIG_COUNT: | |
1076 | if (!cmd->stop_arg) { | |
1077 | cmd->stop_arg = 1; | |
1078 | err++; | |
1079 | } | |
1080 | break; | |
1081 | case TRIG_NONE: | |
1082 | if (cmd->stop_arg != 0) { | |
1083 | cmd->stop_arg = 0; | |
1084 | err++; | |
1085 | } | |
1086 | break; | |
1309e617 MD |
1087 | /* |
1088 | * TRIG_EXT doesn't care since it doesn't | |
1089 | * trigger off a numbered channel | |
1090 | */ | |
124b13b2 FMH |
1091 | default: |
1092 | break; | |
1093 | } | |
1094 | ||
1095 | if (err) | |
1096 | return 3; | |
1097 | ||
1098 | /* step 4: fix up any arguments */ | |
1099 | ||
1100 | tmp = cmd->convert_arg; | |
1101 | tmp2 = cmd->scan_begin_arg; | |
1102 | labpc_adc_timing(dev, cmd); | |
1103 | if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) | |
1104 | err++; | |
1105 | ||
1106 | if (err) | |
1107 | return 4; | |
1108 | ||
1109 | if (labpc_ai_chanlist_invalid(dev, cmd)) | |
1110 | return 5; | |
1111 | ||
1112 | return 0; | |
1113 | } | |
1114 | ||
da91b269 | 1115 | static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
124b13b2 FMH |
1116 | { |
1117 | int channel, range, aref; | |
3297d6c7 | 1118 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 | 1119 | unsigned long irq_flags; |
3297d6c7 | 1120 | #endif |
124b13b2 | 1121 | int ret; |
d163679c | 1122 | struct comedi_async *async = s->async; |
ea6d0d4c | 1123 | struct comedi_cmd *cmd = &async->cmd; |
124b13b2 FMH |
1124 | enum transfer_type xfer; |
1125 | unsigned long flags; | |
1126 | ||
1127 | if (!dev->irq) { | |
1128 | comedi_error(dev, "no irq assigned, cannot perform command"); | |
1129 | return -1; | |
1130 | } | |
1131 | ||
1132 | range = CR_RANGE(cmd->chanlist[0]); | |
1133 | aref = CR_AREF(cmd->chanlist[0]); | |
1134 | ||
25985edc | 1135 | /* make sure board is disabled before setting up acquisition */ |
5f74ea14 | 1136 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
1137 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
1138 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 1139 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1140 | |
1141 | devpriv->command3_bits = 0; | |
1142 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
1143 | ||
f6b49620 | 1144 | /* initialize software conversion count */ |
412bd046 | 1145 | if (cmd->stop_src == TRIG_COUNT) |
124b13b2 | 1146 | devpriv->count = cmd->stop_arg * cmd->chanlist_len; |
65d6d26c | 1147 | |
f6b49620 | 1148 | /* setup hardware conversion counter */ |
124b13b2 | 1149 | if (cmd->stop_src == TRIG_EXT) { |
1309e617 MD |
1150 | /* |
1151 | * load counter a1 with count of 3 | |
1152 | * (pc+ manual says this is minimum allowed) using mode 0 | |
1153 | */ | |
124b13b2 | 1154 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
0a85b6f0 | 1155 | 1, 3, 0); |
124b13b2 FMH |
1156 | if (ret < 0) { |
1157 | comedi_error(dev, "error loading counter a1"); | |
1158 | return -1; | |
1159 | } | |
1309e617 MD |
1160 | } else /* |
1161 | * otherwise, just put a1 in mode 0 | |
1162 | * with no count to set its output low | |
1163 | */ | |
124b13b2 | 1164 | devpriv->write_byte(INIT_A1_BITS, |
0a85b6f0 | 1165 | dev->iobase + COUNTER_A_CONTROL_REG); |
124b13b2 | 1166 | |
3297d6c7 | 1167 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 BP |
1168 | /* figure out what method we will use to transfer data */ |
1169 | if (devpriv->dma_chan && /* need a dma channel allocated */ | |
1309e617 MD |
1170 | /* |
1171 | * dma unsafe at RT priority, | |
1172 | * and too much setup time for TRIG_WAKE_EOS for | |
1173 | */ | |
0a85b6f0 MT |
1174 | (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && |
1175 | /* only available on the isa boards */ | |
1176 | thisboard->bustype == isa_bustype) { | |
124b13b2 | 1177 | xfer = isa_dma_transfer; |
1309e617 | 1178 | /* pc-plus has no fifo-half full interrupt */ |
3297d6c7 RD |
1179 | } else |
1180 | #endif | |
1181 | if (thisboard->register_layout == labpc_1200_layout && | |
0a85b6f0 MT |
1182 | /* wake-end-of-scan should interrupt on fifo not empty */ |
1183 | (cmd->flags & TRIG_WAKE_EOS) == 0 && | |
1184 | /* make sure we are taking more than just a few points */ | |
1185 | (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { | |
124b13b2 FMH |
1186 | xfer = fifo_half_full_transfer; |
1187 | } else | |
1188 | xfer = fifo_not_empty_transfer; | |
1189 | devpriv->current_transfer = xfer; | |
1190 | ||
f6b49620 | 1191 | /* setup command6 register for 1200 boards */ |
124b13b2 | 1192 | if (thisboard->register_layout == labpc_1200_layout) { |
f6b49620 | 1193 | /* reference inputs to ground or common? */ |
124b13b2 FMH |
1194 | if (aref != AREF_GROUND) |
1195 | devpriv->command6_bits |= ADC_COMMON_BIT; | |
1196 | else | |
1197 | devpriv->command6_bits &= ~ADC_COMMON_BIT; | |
f6b49620 | 1198 | /* bipolar or unipolar range? */ |
124b13b2 FMH |
1199 | if (thisboard->ai_range_is_unipolar[range]) |
1200 | devpriv->command6_bits |= ADC_UNIP_BIT; | |
1201 | else | |
1202 | devpriv->command6_bits &= ~ADC_UNIP_BIT; | |
f6b49620 | 1203 | /* interrupt on fifo half full? */ |
124b13b2 FMH |
1204 | if (xfer == fifo_half_full_transfer) |
1205 | devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; | |
1206 | else | |
1207 | devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; | |
f6b49620 | 1208 | /* enable interrupt on counter a1 terminal count? */ |
124b13b2 FMH |
1209 | if (cmd->stop_src == TRIG_EXT) |
1210 | devpriv->command6_bits |= A1_INTR_EN_BIT; | |
1211 | else | |
1212 | devpriv->command6_bits &= ~A1_INTR_EN_BIT; | |
f6b49620 | 1213 | /* are we scanning up or down through channels? */ |
124b13b2 FMH |
1214 | if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) |
1215 | devpriv->command6_bits |= ADC_SCAN_UP_BIT; | |
1216 | else | |
1217 | devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; | |
f6b49620 | 1218 | /* write to register */ |
124b13b2 | 1219 | devpriv->write_byte(devpriv->command6_bits, |
0a85b6f0 | 1220 | dev->iobase + COMMAND6_REG); |
124b13b2 FMH |
1221 | } |
1222 | ||
1223 | /* setup channel list, etc (command1 register) */ | |
1224 | devpriv->command1_bits = 0; | |
1225 | if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) | |
1226 | channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); | |
1227 | else | |
1228 | channel = CR_CHAN(cmd->chanlist[0]); | |
e41a6f6d | 1229 | /* munge channel bits for differential / scan disabled mode */ |
124b13b2 FMH |
1230 | if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) |
1231 | channel *= 2; | |
1232 | devpriv->command1_bits |= ADC_CHAN_BITS(channel); | |
1233 | devpriv->command1_bits |= thisboard->ai_range_code[range]; | |
1234 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); | |
e41a6f6d | 1235 | /* manual says to set scan enable bit on second pass */ |
124b13b2 | 1236 | if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || |
0a85b6f0 | 1237 | labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { |
124b13b2 | 1238 | devpriv->command1_bits |= ADC_SCAN_EN_BIT; |
e41a6f6d SR |
1239 | /* need a brief delay before enabling scan, or scan |
1240 | * list will get screwed when you switch | |
124b13b2 | 1241 | * between scan up to scan down mode - dunno why */ |
5f74ea14 | 1242 | udelay(1); |
124b13b2 | 1243 | devpriv->write_byte(devpriv->command1_bits, |
0a85b6f0 | 1244 | dev->iobase + COMMAND1_REG); |
124b13b2 | 1245 | } |
f6b49620 | 1246 | /* setup any external triggering/pacing (command4 register) */ |
124b13b2 FMH |
1247 | devpriv->command4_bits = 0; |
1248 | if (cmd->convert_src != TRIG_EXT) | |
1249 | devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; | |
1250 | /* XXX should discard first scan when using interval scanning | |
1251 | * since manual says it is not synced with scan clock */ | |
1252 | if (labpc_use_continuous_mode(cmd) == 0) { | |
1253 | devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; | |
1254 | if (cmd->scan_begin_src == TRIG_EXT) | |
1255 | devpriv->command4_bits |= EXT_SCAN_EN_BIT; | |
1256 | } | |
f6b49620 | 1257 | /* single-ended/differential */ |
124b13b2 FMH |
1258 | if (aref == AREF_DIFF) |
1259 | devpriv->command4_bits |= ADC_DIFF_BIT; | |
1260 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); | |
1261 | ||
1262 | devpriv->write_byte(cmd->chanlist_len, | |
0a85b6f0 | 1263 | dev->iobase + INTERVAL_COUNT_REG); |
f6b49620 | 1264 | /* load count */ |
124b13b2 | 1265 | devpriv->write_byte(INTERVAL_LOAD_BITS, |
0a85b6f0 | 1266 | dev->iobase + INTERVAL_LOAD_REG); |
124b13b2 FMH |
1267 | |
1268 | if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { | |
f6b49620 | 1269 | /* set up pacing */ |
124b13b2 | 1270 | labpc_adc_timing(dev, cmd); |
f6b49620 | 1271 | /* load counter b0 in mode 3 */ |
124b13b2 | 1272 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
0a85b6f0 | 1273 | 0, devpriv->divisor_b0, 3); |
124b13b2 FMH |
1274 | if (ret < 0) { |
1275 | comedi_error(dev, "error loading counter b0"); | |
1276 | return -1; | |
1277 | } | |
1278 | } | |
f6b49620 | 1279 | /* set up conversion pacing */ |
124b13b2 | 1280 | if (labpc_ai_convert_period(cmd)) { |
f6b49620 | 1281 | /* load counter a0 in mode 2 */ |
124b13b2 | 1282 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
0a85b6f0 | 1283 | 0, devpriv->divisor_a0, 2); |
124b13b2 FMH |
1284 | if (ret < 0) { |
1285 | comedi_error(dev, "error loading counter a0"); | |
1286 | return -1; | |
1287 | } | |
1288 | } else | |
1289 | devpriv->write_byte(INIT_A0_BITS, | |
0a85b6f0 | 1290 | dev->iobase + COUNTER_A_CONTROL_REG); |
124b13b2 | 1291 | |
f6b49620 | 1292 | /* set up scan pacing */ |
124b13b2 | 1293 | if (labpc_ai_scan_period(cmd)) { |
f6b49620 | 1294 | /* load counter b1 in mode 2 */ |
124b13b2 | 1295 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
0a85b6f0 | 1296 | 1, devpriv->divisor_b1, 2); |
124b13b2 FMH |
1297 | if (ret < 0) { |
1298 | comedi_error(dev, "error loading counter b1"); | |
1299 | return -1; | |
1300 | } | |
1301 | } | |
1302 | ||
1303 | labpc_clear_adc_fifo(dev); | |
1304 | ||
3297d6c7 | 1305 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 | 1306 | /* set up dma transfer */ |
124b13b2 FMH |
1307 | if (xfer == isa_dma_transfer) { |
1308 | irq_flags = claim_dma_lock(); | |
1309 | disable_dma(devpriv->dma_chan); | |
1310 | /* clear flip-flop to make sure 2-byte registers for | |
1311 | * count and address get set correctly */ | |
1312 | clear_dma_ff(devpriv->dma_chan); | |
1313 | set_dma_addr(devpriv->dma_chan, | |
0a85b6f0 | 1314 | virt_to_bus(devpriv->dma_buffer)); |
f6b49620 | 1315 | /* set appropriate size of transfer */ |
124b13b2 FMH |
1316 | devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd); |
1317 | if (cmd->stop_src == TRIG_COUNT && | |
0a85b6f0 | 1318 | devpriv->count * sample_size < devpriv->dma_transfer_size) { |
124b13b2 | 1319 | devpriv->dma_transfer_size = |
0a85b6f0 | 1320 | devpriv->count * sample_size; |
124b13b2 FMH |
1321 | } |
1322 | set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); | |
1323 | enable_dma(devpriv->dma_chan); | |
1324 | release_dma_lock(irq_flags); | |
f6b49620 | 1325 | /* enable board's dma */ |
124b13b2 FMH |
1326 | devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; |
1327 | } else | |
1328 | devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; | |
3297d6c7 | 1329 | #endif |
124b13b2 | 1330 | |
f6b49620 | 1331 | /* enable error interrupts */ |
124b13b2 | 1332 | devpriv->command3_bits |= ERR_INTR_EN_BIT; |
f6b49620 | 1333 | /* enable fifo not empty interrupt? */ |
124b13b2 FMH |
1334 | if (xfer == fifo_not_empty_transfer) |
1335 | devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; | |
1336 | else | |
1337 | devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; | |
1338 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
1339 | ||
25985edc | 1340 | /* startup acquisition */ |
124b13b2 | 1341 | |
f6b49620 BP |
1342 | /* command2 reg */ |
1343 | /* use 2 cascaded counters for pacing */ | |
5f74ea14 | 1344 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
1345 | devpriv->command2_bits |= CASCADE_BIT; |
1346 | switch (cmd->start_src) { | |
1347 | case TRIG_EXT: | |
1348 | devpriv->command2_bits |= HWTRIG_BIT; | |
1349 | devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; | |
1350 | break; | |
1351 | case TRIG_NOW: | |
1352 | devpriv->command2_bits |= SWTRIG_BIT; | |
1353 | devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; | |
1354 | break; | |
1355 | default: | |
1356 | comedi_error(dev, "bug with start_src"); | |
513e48f9 | 1357 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1358 | return -1; |
1359 | break; | |
1360 | } | |
1361 | switch (cmd->stop_src) { | |
1362 | case TRIG_EXT: | |
1363 | devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; | |
1364 | break; | |
1365 | case TRIG_COUNT: | |
1366 | case TRIG_NONE: | |
1367 | break; | |
1368 | default: | |
1369 | comedi_error(dev, "bug with stop_src"); | |
513e48f9 | 1370 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1371 | return -1; |
1372 | } | |
1373 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 1374 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1375 | |
1376 | return 0; | |
1377 | } | |
1378 | ||
1379 | /* interrupt service routine */ | |
70265d24 | 1380 | static irqreturn_t labpc_interrupt(int irq, void *d) |
124b13b2 | 1381 | { |
71b5f4f1 | 1382 | struct comedi_device *dev = d; |
34c43922 | 1383 | struct comedi_subdevice *s = dev->read_subdev; |
d163679c | 1384 | struct comedi_async *async; |
ea6d0d4c | 1385 | struct comedi_cmd *cmd; |
124b13b2 FMH |
1386 | |
1387 | if (dev->attached == 0) { | |
1388 | comedi_error(dev, "premature interrupt"); | |
1389 | return IRQ_HANDLED; | |
1390 | } | |
1391 | ||
1392 | async = s->async; | |
1393 | cmd = &async->cmd; | |
1394 | async->events = 0; | |
1395 | ||
e41a6f6d | 1396 | /* read board status */ |
124b13b2 FMH |
1397 | devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); |
1398 | if (thisboard->register_layout == labpc_1200_layout) | |
1399 | devpriv->status2_bits = | |
0a85b6f0 | 1400 | devpriv->read_byte(dev->iobase + STATUS2_REG); |
124b13b2 FMH |
1401 | |
1402 | if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | | |
0a85b6f0 MT |
1403 | OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 |
1404 | && (devpriv->status2_bits & A1_TC_BIT) == 0 | |
1405 | && (devpriv->status2_bits & FNHF_BIT)) { | |
124b13b2 FMH |
1406 | return IRQ_NONE; |
1407 | } | |
1408 | ||
1409 | if (devpriv->status1_bits & OVERRUN_BIT) { | |
e41a6f6d | 1410 | /* clear error interrupt */ |
124b13b2 FMH |
1411 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); |
1412 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
1413 | comedi_event(dev, s); | |
1414 | comedi_error(dev, "overrun"); | |
1415 | return IRQ_HANDLED; | |
1416 | } | |
1417 | ||
3297d6c7 | 1418 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 | 1419 | if (devpriv->current_transfer == isa_dma_transfer) { |
639b9f1e SR |
1420 | /* |
1421 | * if a dma terminal count of external stop trigger | |
1422 | * has occurred | |
1423 | */ | |
124b13b2 | 1424 | if (devpriv->status1_bits & DMATC_BIT || |
0a85b6f0 MT |
1425 | (thisboard->register_layout == labpc_1200_layout |
1426 | && devpriv->status2_bits & A1_TC_BIT)) { | |
124b13b2 FMH |
1427 | handle_isa_dma(dev); |
1428 | } | |
1429 | } else | |
3297d6c7 | 1430 | #endif |
124b13b2 FMH |
1431 | labpc_drain_fifo(dev); |
1432 | ||
1433 | if (devpriv->status1_bits & TIMER_BIT) { | |
1434 | comedi_error(dev, "handled timer interrupt?"); | |
f6b49620 | 1435 | /* clear it */ |
124b13b2 FMH |
1436 | devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); |
1437 | } | |
1438 | ||
1439 | if (devpriv->status1_bits & OVERFLOW_BIT) { | |
f6b49620 | 1440 | /* clear error interrupt */ |
124b13b2 FMH |
1441 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); |
1442 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
1443 | comedi_event(dev, s); | |
1444 | comedi_error(dev, "overflow"); | |
1445 | return IRQ_HANDLED; | |
1446 | } | |
f6b49620 | 1447 | /* handle external stop trigger */ |
124b13b2 FMH |
1448 | if (cmd->stop_src == TRIG_EXT) { |
1449 | if (devpriv->status2_bits & A1_TC_BIT) { | |
1450 | labpc_drain_dregs(dev); | |
1451 | labpc_cancel(dev, s); | |
1452 | async->events |= COMEDI_CB_EOA; | |
1453 | } | |
1454 | } | |
1455 | ||
1456 | /* TRIG_COUNT end of acquisition */ | |
1457 | if (cmd->stop_src == TRIG_COUNT) { | |
1458 | if (devpriv->count == 0) { | |
1459 | labpc_cancel(dev, s); | |
1460 | async->events |= COMEDI_CB_EOA; | |
1461 | } | |
1462 | } | |
1463 | ||
1464 | comedi_event(dev, s); | |
1465 | return IRQ_HANDLED; | |
1466 | } | |
1467 | ||
f6b49620 | 1468 | /* read all available samples from ai fifo */ |
da91b269 | 1469 | static int labpc_drain_fifo(struct comedi_device *dev) |
124b13b2 FMH |
1470 | { |
1471 | unsigned int lsb, msb; | |
790c5541 | 1472 | short data; |
d163679c | 1473 | struct comedi_async *async = dev->read_subdev->async; |
124b13b2 FMH |
1474 | const int timeout = 10000; |
1475 | unsigned int i; | |
1476 | ||
1477 | devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); | |
1478 | ||
1479 | for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; | |
0a85b6f0 | 1480 | i++) { |
f6b49620 | 1481 | /* quit if we have all the data we want */ |
124b13b2 FMH |
1482 | if (async->cmd.stop_src == TRIG_COUNT) { |
1483 | if (devpriv->count == 0) | |
1484 | break; | |
1485 | devpriv->count--; | |
1486 | } | |
1487 | lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
1488 | msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
1489 | data = (msb << 8) | lsb; | |
1490 | cfc_write_to_buffer(dev->read_subdev, data); | |
1491 | devpriv->status1_bits = | |
0a85b6f0 | 1492 | devpriv->read_byte(dev->iobase + STATUS1_REG); |
124b13b2 FMH |
1493 | } |
1494 | if (i == timeout) { | |
1495 | comedi_error(dev, "ai timeout, fifo never empties"); | |
1496 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
1497 | return -1; | |
1498 | } | |
1499 | ||
1500 | return 0; | |
1501 | } | |
1502 | ||
3297d6c7 | 1503 | #ifdef CONFIG_ISA_DMA_API |
da91b269 | 1504 | static void labpc_drain_dma(struct comedi_device *dev) |
124b13b2 | 1505 | { |
34c43922 | 1506 | struct comedi_subdevice *s = dev->read_subdev; |
d163679c | 1507 | struct comedi_async *async = s->async; |
124b13b2 FMH |
1508 | int status; |
1509 | unsigned long flags; | |
1510 | unsigned int max_points, num_points, residue, leftover; | |
1511 | int i; | |
1512 | ||
1513 | status = devpriv->status1_bits; | |
1514 | ||
1515 | flags = claim_dma_lock(); | |
1516 | disable_dma(devpriv->dma_chan); | |
1517 | /* clear flip-flop to make sure 2-byte registers for | |
1518 | * count and address get set correctly */ | |
1519 | clear_dma_ff(devpriv->dma_chan); | |
1520 | ||
f6b49620 | 1521 | /* figure out how many points to read */ |
124b13b2 FMH |
1522 | max_points = devpriv->dma_transfer_size / sample_size; |
1523 | /* residue is the number of points left to be done on the dma | |
1524 | * transfer. It should always be zero at this point unless | |
1525 | * the stop_src is set to external triggering. | |
1526 | */ | |
1527 | residue = get_dma_residue(devpriv->dma_chan) / sample_size; | |
1528 | num_points = max_points - residue; | |
1529 | if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) | |
1530 | num_points = devpriv->count; | |
1531 | ||
f6b49620 | 1532 | /* figure out how many points will be stored next time */ |
124b13b2 FMH |
1533 | leftover = 0; |
1534 | if (async->cmd.stop_src != TRIG_COUNT) { | |
1535 | leftover = devpriv->dma_transfer_size / sample_size; | |
1536 | } else if (devpriv->count > num_points) { | |
1537 | leftover = devpriv->count - num_points; | |
1538 | if (leftover > max_points) | |
1539 | leftover = max_points; | |
1540 | } | |
1541 | ||
1542 | /* write data to comedi buffer */ | |
412bd046 | 1543 | for (i = 0; i < num_points; i++) |
124b13b2 | 1544 | cfc_write_to_buffer(s, devpriv->dma_buffer[i]); |
65d6d26c | 1545 | |
124b13b2 FMH |
1546 | if (async->cmd.stop_src == TRIG_COUNT) |
1547 | devpriv->count -= num_points; | |
1548 | ||
f6b49620 | 1549 | /* set address and count for next transfer */ |
124b13b2 FMH |
1550 | set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); |
1551 | set_dma_count(devpriv->dma_chan, leftover * sample_size); | |
1552 | release_dma_lock(flags); | |
1553 | ||
1554 | async->events |= COMEDI_CB_BLOCK; | |
1555 | } | |
1556 | ||
da91b269 | 1557 | static void handle_isa_dma(struct comedi_device *dev) |
124b13b2 FMH |
1558 | { |
1559 | labpc_drain_dma(dev); | |
1560 | ||
1561 | enable_dma(devpriv->dma_chan); | |
1562 | ||
f6b49620 | 1563 | /* clear dma tc interrupt */ |
124b13b2 FMH |
1564 | devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); |
1565 | } | |
3297d6c7 | 1566 | #endif |
124b13b2 | 1567 | |
25985edc LDM |
1568 | /* makes sure all data acquired by board is transferred to comedi (used |
1569 | * when acquisition is terminated by stop_src == TRIG_EXT). */ | |
da91b269 | 1570 | static void labpc_drain_dregs(struct comedi_device *dev) |
124b13b2 | 1571 | { |
3297d6c7 | 1572 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 FMH |
1573 | if (devpriv->current_transfer == isa_dma_transfer) |
1574 | labpc_drain_dma(dev); | |
3297d6c7 | 1575 | #endif |
124b13b2 FMH |
1576 | |
1577 | labpc_drain_fifo(dev); | |
1578 | } | |
1579 | ||
da91b269 | 1580 | static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 1581 | struct comedi_insn *insn, unsigned int *data) |
124b13b2 FMH |
1582 | { |
1583 | int i, n; | |
1584 | int chan, range; | |
1585 | int lsb, msb; | |
1586 | int timeout = 1000; | |
1587 | unsigned long flags; | |
1588 | ||
f6b49620 | 1589 | /* disable timed conversions */ |
5f74ea14 | 1590 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
1591 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
1592 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 1593 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 | 1594 | |
f6b49620 | 1595 | /* disable interrupt generation and dma */ |
124b13b2 FMH |
1596 | devpriv->command3_bits = 0; |
1597 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
1598 | ||
1599 | /* set gain and channel */ | |
1600 | devpriv->command1_bits = 0; | |
1601 | chan = CR_CHAN(insn->chanspec); | |
1602 | range = CR_RANGE(insn->chanspec); | |
1603 | devpriv->command1_bits |= thisboard->ai_range_code[range]; | |
e41a6f6d | 1604 | /* munge channel bits for differential/scan disabled mode */ |
124b13b2 FMH |
1605 | if (CR_AREF(insn->chanspec) == AREF_DIFF) |
1606 | chan *= 2; | |
1607 | devpriv->command1_bits |= ADC_CHAN_BITS(chan); | |
1608 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); | |
1609 | ||
e41a6f6d | 1610 | /* setup command6 register for 1200 boards */ |
124b13b2 | 1611 | if (thisboard->register_layout == labpc_1200_layout) { |
f6b49620 | 1612 | /* reference inputs to ground or common? */ |
124b13b2 FMH |
1613 | if (CR_AREF(insn->chanspec) != AREF_GROUND) |
1614 | devpriv->command6_bits |= ADC_COMMON_BIT; | |
1615 | else | |
1616 | devpriv->command6_bits &= ~ADC_COMMON_BIT; | |
e41a6f6d | 1617 | /* bipolar or unipolar range? */ |
124b13b2 FMH |
1618 | if (thisboard->ai_range_is_unipolar[range]) |
1619 | devpriv->command6_bits |= ADC_UNIP_BIT; | |
1620 | else | |
1621 | devpriv->command6_bits &= ~ADC_UNIP_BIT; | |
e41a6f6d | 1622 | /* don't interrupt on fifo half full */ |
124b13b2 | 1623 | devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; |
e41a6f6d | 1624 | /* don't enable interrupt on counter a1 terminal count? */ |
124b13b2 | 1625 | devpriv->command6_bits &= ~A1_INTR_EN_BIT; |
e41a6f6d | 1626 | /* write to register */ |
124b13b2 | 1627 | devpriv->write_byte(devpriv->command6_bits, |
0a85b6f0 | 1628 | dev->iobase + COMMAND6_REG); |
124b13b2 | 1629 | } |
e41a6f6d | 1630 | /* setup command4 register */ |
124b13b2 FMH |
1631 | devpriv->command4_bits = 0; |
1632 | devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; | |
e41a6f6d | 1633 | /* single-ended/differential */ |
124b13b2 FMH |
1634 | if (CR_AREF(insn->chanspec) == AREF_DIFF) |
1635 | devpriv->command4_bits |= ADC_DIFF_BIT; | |
1636 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); | |
1637 | ||
1309e617 MD |
1638 | /* |
1639 | * initialize pacer counter output to make sure it doesn't | |
1640 | * cause any problems | |
1641 | */ | |
124b13b2 FMH |
1642 | devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); |
1643 | ||
1644 | labpc_clear_adc_fifo(dev); | |
1645 | ||
1646 | for (n = 0; n < insn->n; n++) { | |
1647 | /* trigger conversion */ | |
1648 | devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); | |
1649 | ||
1650 | for (i = 0; i < timeout; i++) { | |
1651 | if (devpriv->read_byte(dev->iobase + | |
0a85b6f0 | 1652 | STATUS1_REG) & DATA_AVAIL_BIT) |
124b13b2 | 1653 | break; |
5f74ea14 | 1654 | udelay(1); |
124b13b2 FMH |
1655 | } |
1656 | if (i == timeout) { | |
1657 | comedi_error(dev, "timeout"); | |
1658 | return -ETIME; | |
1659 | } | |
1660 | lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
1661 | msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
1662 | data[n] = (msb << 8) | lsb; | |
1663 | } | |
1664 | ||
1665 | return n; | |
1666 | } | |
1667 | ||
f6b49620 | 1668 | /* analog output insn */ |
da91b269 | 1669 | static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 1670 | struct comedi_insn *insn, unsigned int *data) |
124b13b2 FMH |
1671 | { |
1672 | int channel, range; | |
1673 | unsigned long flags; | |
1674 | int lsb, msb; | |
1675 | ||
1676 | channel = CR_CHAN(insn->chanspec); | |
1677 | ||
e41a6f6d | 1678 | /* turn off pacing of analog output channel */ |
124b13b2 FMH |
1679 | /* note: hardware bug in daqcard-1200 means pacing cannot |
1680 | * be independently enabled/disabled for its the two channels */ | |
5f74ea14 | 1681 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
1682 | devpriv->command2_bits &= ~DAC_PACED_BIT(channel); |
1683 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 1684 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 | 1685 | |
e41a6f6d | 1686 | /* set range */ |
124b13b2 FMH |
1687 | if (thisboard->register_layout == labpc_1200_layout) { |
1688 | range = CR_RANGE(insn->chanspec); | |
1689 | if (range & AO_RANGE_IS_UNIPOLAR) | |
1690 | devpriv->command6_bits |= DAC_UNIP_BIT(channel); | |
1691 | else | |
1692 | devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); | |
f6b49620 | 1693 | /* write to register */ |
124b13b2 | 1694 | devpriv->write_byte(devpriv->command6_bits, |
0a85b6f0 | 1695 | dev->iobase + COMMAND6_REG); |
124b13b2 | 1696 | } |
e41a6f6d | 1697 | /* send data */ |
124b13b2 FMH |
1698 | lsb = data[0] & 0xff; |
1699 | msb = (data[0] >> 8) & 0xff; | |
1700 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); | |
1701 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); | |
1702 | ||
e41a6f6d | 1703 | /* remember value for readback */ |
124b13b2 FMH |
1704 | devpriv->ao_value[channel] = data[0]; |
1705 | ||
1706 | return 1; | |
1707 | } | |
1708 | ||
f6b49620 | 1709 | /* analog output readback insn */ |
da91b269 | 1710 | static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 1711 | struct comedi_insn *insn, unsigned int *data) |
124b13b2 FMH |
1712 | { |
1713 | data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; | |
1714 | ||
1715 | return 1; | |
1716 | } | |
1717 | ||
0a85b6f0 MT |
1718 | static int labpc_calib_read_insn(struct comedi_device *dev, |
1719 | struct comedi_subdevice *s, | |
1720 | struct comedi_insn *insn, unsigned int *data) | |
124b13b2 FMH |
1721 | { |
1722 | data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; | |
1723 | ||
1724 | return 1; | |
1725 | } | |
1726 | ||
0a85b6f0 MT |
1727 | static int labpc_calib_write_insn(struct comedi_device *dev, |
1728 | struct comedi_subdevice *s, | |
1729 | struct comedi_insn *insn, unsigned int *data) | |
124b13b2 FMH |
1730 | { |
1731 | int channel = CR_CHAN(insn->chanspec); | |
1732 | ||
1733 | write_caldac(dev, channel, data[0]); | |
1734 | return 1; | |
1735 | } | |
1736 | ||
0a85b6f0 MT |
1737 | static int labpc_eeprom_read_insn(struct comedi_device *dev, |
1738 | struct comedi_subdevice *s, | |
1739 | struct comedi_insn *insn, unsigned int *data) | |
124b13b2 FMH |
1740 | { |
1741 | data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; | |
1742 | ||
1743 | return 1; | |
1744 | } | |
1745 | ||
0a85b6f0 MT |
1746 | static int labpc_eeprom_write_insn(struct comedi_device *dev, |
1747 | struct comedi_subdevice *s, | |
1748 | struct comedi_insn *insn, unsigned int *data) | |
124b13b2 FMH |
1749 | { |
1750 | int channel = CR_CHAN(insn->chanspec); | |
1751 | int ret; | |
1752 | ||
f6b49620 | 1753 | /* only allow writes to user area of eeprom */ |
124b13b2 | 1754 | if (channel < 16 || channel > 127) { |
1cabcd31 IA |
1755 | dev_dbg(dev->class_dev, |
1756 | "eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)\n"); | |
124b13b2 FMH |
1757 | return -EINVAL; |
1758 | } | |
1759 | ||
1760 | ret = labpc_eeprom_write(dev, channel, data[0]); | |
1761 | if (ret < 0) | |
1762 | return ret; | |
1763 | ||
1764 | return 1; | |
1765 | } | |
1766 | ||
3297d6c7 | 1767 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 | 1768 | /* utility function that suggests a dma transfer size in bytes */ |
ea6d0d4c | 1769 | static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) |
124b13b2 FMH |
1770 | { |
1771 | unsigned int size; | |
1772 | unsigned int freq; | |
1773 | ||
1774 | if (cmd.convert_src == TRIG_TIMER) | |
1775 | freq = 1000000000 / cmd.convert_arg; | |
e41a6f6d | 1776 | /* return some default value */ |
124b13b2 FMH |
1777 | else |
1778 | freq = 0xffffffff; | |
1779 | ||
e41a6f6d | 1780 | /* make buffer fill in no more than 1/3 second */ |
124b13b2 FMH |
1781 | size = (freq / 3) * sample_size; |
1782 | ||
e41a6f6d | 1783 | /* set a minimum and maximum size allowed */ |
124b13b2 FMH |
1784 | if (size > dma_buffer_size) |
1785 | size = dma_buffer_size - dma_buffer_size % sample_size; | |
1786 | else if (size < sample_size) | |
1787 | size = sample_size; | |
1788 | ||
1789 | return size; | |
1790 | } | |
3297d6c7 | 1791 | #endif |
124b13b2 | 1792 | |
f6b49620 | 1793 | /* figures out what counter values to use based on command */ |
da91b269 | 1794 | static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) |
124b13b2 | 1795 | { |
e41a6f6d SR |
1796 | /* max value for 16 bit counter in mode 2 */ |
1797 | const int max_counter_value = 0x10000; | |
1798 | /* min value for 16 bit counter in mode 2 */ | |
1799 | const int min_counter_value = 2; | |
124b13b2 FMH |
1800 | unsigned int base_period; |
1801 | ||
e41a6f6d SR |
1802 | /* |
1803 | * if both convert and scan triggers are TRIG_TIMER, then they | |
1804 | * both rely on counter b0 | |
1805 | */ | |
124b13b2 | 1806 | if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { |
e41a6f6d SR |
1807 | /* |
1808 | * pick the lowest b0 divisor value we can (for maximum input | |
1809 | * clock speed on convert and scan counters) | |
1810 | */ | |
124b13b2 | 1811 | devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / |
0a85b6f0 | 1812 | (LABPC_TIMER_BASE * max_counter_value) + 1; |
124b13b2 FMH |
1813 | if (devpriv->divisor_b0 < min_counter_value) |
1814 | devpriv->divisor_b0 = min_counter_value; | |
1815 | if (devpriv->divisor_b0 > max_counter_value) | |
1816 | devpriv->divisor_b0 = max_counter_value; | |
1817 | ||
1818 | base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; | |
1819 | ||
f6b49620 | 1820 | /* set a0 for conversion frequency and b1 for scan frequency */ |
124b13b2 FMH |
1821 | switch (cmd->flags & TRIG_ROUND_MASK) { |
1822 | default: | |
1823 | case TRIG_ROUND_NEAREST: | |
1824 | devpriv->divisor_a0 = | |
0a85b6f0 MT |
1825 | (labpc_ai_convert_period(cmd) + |
1826 | (base_period / 2)) / base_period; | |
124b13b2 | 1827 | devpriv->divisor_b1 = |
0a85b6f0 MT |
1828 | (labpc_ai_scan_period(cmd) + |
1829 | (base_period / 2)) / base_period; | |
124b13b2 FMH |
1830 | break; |
1831 | case TRIG_ROUND_UP: | |
1832 | devpriv->divisor_a0 = | |
0a85b6f0 MT |
1833 | (labpc_ai_convert_period(cmd) + (base_period - |
1834 | 1)) / base_period; | |
124b13b2 | 1835 | devpriv->divisor_b1 = |
0a85b6f0 MT |
1836 | (labpc_ai_scan_period(cmd) + (base_period - |
1837 | 1)) / base_period; | |
124b13b2 FMH |
1838 | break; |
1839 | case TRIG_ROUND_DOWN: | |
1840 | devpriv->divisor_a0 = | |
0a85b6f0 | 1841 | labpc_ai_convert_period(cmd) / base_period; |
124b13b2 | 1842 | devpriv->divisor_b1 = |
0a85b6f0 | 1843 | labpc_ai_scan_period(cmd) / base_period; |
124b13b2 FMH |
1844 | break; |
1845 | } | |
f6b49620 | 1846 | /* make sure a0 and b1 values are acceptable */ |
124b13b2 FMH |
1847 | if (devpriv->divisor_a0 < min_counter_value) |
1848 | devpriv->divisor_a0 = min_counter_value; | |
1849 | if (devpriv->divisor_a0 > max_counter_value) | |
1850 | devpriv->divisor_a0 = max_counter_value; | |
1851 | if (devpriv->divisor_b1 < min_counter_value) | |
1852 | devpriv->divisor_b1 = min_counter_value; | |
1853 | if (devpriv->divisor_b1 > max_counter_value) | |
1854 | devpriv->divisor_b1 = max_counter_value; | |
f6b49620 | 1855 | /* write corrected timings to command */ |
124b13b2 | 1856 | labpc_set_ai_convert_period(cmd, |
0a85b6f0 | 1857 | base_period * devpriv->divisor_a0); |
124b13b2 | 1858 | labpc_set_ai_scan_period(cmd, |
0a85b6f0 | 1859 | base_period * devpriv->divisor_b1); |
e41a6f6d SR |
1860 | /* |
1861 | * if only one TRIG_TIMER is used, we can employ the generic | |
1862 | * cascaded timing functions | |
1863 | */ | |
124b13b2 FMH |
1864 | } else if (labpc_ai_scan_period(cmd)) { |
1865 | unsigned int scan_period; | |
1866 | ||
1867 | scan_period = labpc_ai_scan_period(cmd); | |
1309e617 MD |
1868 | /* |
1869 | * calculate cascaded counter values | |
1870 | * that give desired scan timing | |
1871 | */ | |
124b13b2 | 1872 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, |
0a85b6f0 MT |
1873 | &(devpriv->divisor_b1), |
1874 | &(devpriv->divisor_b0), | |
1875 | &scan_period, | |
1876 | cmd->flags & TRIG_ROUND_MASK); | |
124b13b2 FMH |
1877 | labpc_set_ai_scan_period(cmd, scan_period); |
1878 | } else if (labpc_ai_convert_period(cmd)) { | |
1879 | unsigned int convert_period; | |
1880 | ||
1881 | convert_period = labpc_ai_convert_period(cmd); | |
1309e617 MD |
1882 | /* |
1883 | * calculate cascaded counter values | |
1884 | * that give desired conversion timing | |
1885 | */ | |
124b13b2 | 1886 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, |
0a85b6f0 MT |
1887 | &(devpriv->divisor_a0), |
1888 | &(devpriv->divisor_b0), | |
1889 | &convert_period, | |
1890 | cmd->flags & TRIG_ROUND_MASK); | |
124b13b2 FMH |
1891 | labpc_set_ai_convert_period(cmd, convert_period); |
1892 | } | |
1893 | } | |
1894 | ||
1895 | static int labpc_dio_mem_callback(int dir, int port, int data, | |
0a85b6f0 | 1896 | unsigned long iobase) |
124b13b2 FMH |
1897 | { |
1898 | if (dir) { | |
1899 | writeb(data, (void *)(iobase + port)); | |
1900 | return 0; | |
1901 | } else { | |
1902 | return readb((void *)(iobase + port)); | |
1903 | } | |
1904 | } | |
1905 | ||
f6b49620 | 1906 | /* lowlevel write to eeprom/dac */ |
da91b269 | 1907 | static void labpc_serial_out(struct comedi_device *dev, unsigned int value, |
0a85b6f0 | 1908 | unsigned int value_width) |
124b13b2 FMH |
1909 | { |
1910 | int i; | |
1911 | ||
1912 | for (i = 1; i <= value_width; i++) { | |
f6b49620 | 1913 | /* clear serial clock */ |
124b13b2 | 1914 | devpriv->command5_bits &= ~SCLOCK_BIT; |
f6b49620 | 1915 | /* send bits most significant bit first */ |
124b13b2 FMH |
1916 | if (value & (1 << (value_width - i))) |
1917 | devpriv->command5_bits |= SDATA_BIT; | |
1918 | else | |
1919 | devpriv->command5_bits &= ~SDATA_BIT; | |
5f74ea14 | 1920 | udelay(1); |
124b13b2 | 1921 | devpriv->write_byte(devpriv->command5_bits, |
0a85b6f0 | 1922 | dev->iobase + COMMAND5_REG); |
f6b49620 | 1923 | /* set clock to load bit */ |
124b13b2 | 1924 | devpriv->command5_bits |= SCLOCK_BIT; |
5f74ea14 | 1925 | udelay(1); |
124b13b2 | 1926 | devpriv->write_byte(devpriv->command5_bits, |
0a85b6f0 | 1927 | dev->iobase + COMMAND5_REG); |
124b13b2 FMH |
1928 | } |
1929 | } | |
1930 | ||
f6b49620 | 1931 | /* lowlevel read from eeprom */ |
da91b269 | 1932 | static unsigned int labpc_serial_in(struct comedi_device *dev) |
124b13b2 FMH |
1933 | { |
1934 | unsigned int value = 0; | |
1935 | int i; | |
f6b49620 | 1936 | const int value_width = 8; /* number of bits wide values are */ |
124b13b2 FMH |
1937 | |
1938 | for (i = 1; i <= value_width; i++) { | |
f6b49620 | 1939 | /* set serial clock */ |
124b13b2 | 1940 | devpriv->command5_bits |= SCLOCK_BIT; |
5f74ea14 | 1941 | udelay(1); |
124b13b2 | 1942 | devpriv->write_byte(devpriv->command5_bits, |
0a85b6f0 | 1943 | dev->iobase + COMMAND5_REG); |
f6b49620 | 1944 | /* clear clock bit */ |
124b13b2 | 1945 | devpriv->command5_bits &= ~SCLOCK_BIT; |
5f74ea14 | 1946 | udelay(1); |
124b13b2 | 1947 | devpriv->write_byte(devpriv->command5_bits, |
0a85b6f0 | 1948 | dev->iobase + COMMAND5_REG); |
f6b49620 | 1949 | /* read bits most significant bit first */ |
5f74ea14 | 1950 | udelay(1); |
124b13b2 | 1951 | devpriv->status2_bits = |
0a85b6f0 | 1952 | devpriv->read_byte(dev->iobase + STATUS2_REG); |
412bd046 | 1953 | if (devpriv->status2_bits & EEPROM_OUT_BIT) |
124b13b2 | 1954 | value |= 1 << (value_width - i); |
124b13b2 FMH |
1955 | } |
1956 | ||
1957 | return value; | |
1958 | } | |
1959 | ||
0a85b6f0 MT |
1960 | static unsigned int labpc_eeprom_read(struct comedi_device *dev, |
1961 | unsigned int address) | |
124b13b2 FMH |
1962 | { |
1963 | unsigned int value; | |
e41a6f6d SR |
1964 | /* bits to tell eeprom to expect a read */ |
1965 | const int read_instruction = 0x3; | |
1966 | /* 8 bit write lengths to eeprom */ | |
1967 | const int write_length = 8; | |
124b13b2 | 1968 | |
f6b49620 | 1969 | /* enable read/write to eeprom */ |
124b13b2 | 1970 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
5f74ea14 | 1971 | udelay(1); |
124b13b2 FMH |
1972 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
1973 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; | |
5f74ea14 | 1974 | udelay(1); |
124b13b2 FMH |
1975 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
1976 | ||
f6b49620 | 1977 | /* send read instruction */ |
124b13b2 | 1978 | labpc_serial_out(dev, read_instruction, write_length); |
f6b49620 | 1979 | /* send 8 bit address to read from */ |
124b13b2 | 1980 | labpc_serial_out(dev, address, write_length); |
f6b49620 | 1981 | /* read result */ |
124b13b2 FMH |
1982 | value = labpc_serial_in(dev); |
1983 | ||
f6b49620 | 1984 | /* disable read/write to eeprom */ |
124b13b2 | 1985 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
5f74ea14 | 1986 | udelay(1); |
124b13b2 FMH |
1987 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
1988 | ||
1989 | return value; | |
1990 | } | |
1991 | ||
d6269644 JL |
1992 | static int labpc_eeprom_write(struct comedi_device *dev, |
1993 | unsigned int address, unsigned int value) | |
124b13b2 FMH |
1994 | { |
1995 | const int write_enable_instruction = 0x6; | |
1996 | const int write_instruction = 0x2; | |
f6b49620 | 1997 | const int write_length = 8; /* 8 bit write lengths to eeprom */ |
124b13b2 FMH |
1998 | const int write_in_progress_bit = 0x1; |
1999 | const int timeout = 10000; | |
2000 | int i; | |
2001 | ||
f6b49620 | 2002 | /* make sure there isn't already a write in progress */ |
124b13b2 FMH |
2003 | for (i = 0; i < timeout; i++) { |
2004 | if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == | |
0a85b6f0 | 2005 | 0) |
124b13b2 FMH |
2006 | break; |
2007 | } | |
2008 | if (i == timeout) { | |
2009 | comedi_error(dev, "eeprom write timed out"); | |
2010 | return -ETIME; | |
2011 | } | |
f6b49620 | 2012 | /* update software copy of eeprom */ |
124b13b2 FMH |
2013 | devpriv->eeprom_data[address] = value; |
2014 | ||
f6b49620 | 2015 | /* enable read/write to eeprom */ |
124b13b2 | 2016 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
5f74ea14 | 2017 | udelay(1); |
124b13b2 FMH |
2018 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2019 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; | |
5f74ea14 | 2020 | udelay(1); |
124b13b2 FMH |
2021 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2022 | ||
f6b49620 | 2023 | /* send write_enable instruction */ |
124b13b2 FMH |
2024 | labpc_serial_out(dev, write_enable_instruction, write_length); |
2025 | devpriv->command5_bits &= ~EEPROM_EN_BIT; | |
5f74ea14 | 2026 | udelay(1); |
124b13b2 FMH |
2027 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2028 | ||
f6b49620 | 2029 | /* send write instruction */ |
124b13b2 | 2030 | devpriv->command5_bits |= EEPROM_EN_BIT; |
5f74ea14 | 2031 | udelay(1); |
124b13b2 FMH |
2032 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2033 | labpc_serial_out(dev, write_instruction, write_length); | |
f6b49620 | 2034 | /* send 8 bit address to write to */ |
124b13b2 | 2035 | labpc_serial_out(dev, address, write_length); |
f6b49620 | 2036 | /* write value */ |
124b13b2 FMH |
2037 | labpc_serial_out(dev, value, write_length); |
2038 | devpriv->command5_bits &= ~EEPROM_EN_BIT; | |
5f74ea14 | 2039 | udelay(1); |
124b13b2 FMH |
2040 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2041 | ||
f6b49620 | 2042 | /* disable read/write to eeprom */ |
124b13b2 | 2043 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
5f74ea14 | 2044 | udelay(1); |
124b13b2 FMH |
2045 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2046 | ||
2047 | return 0; | |
2048 | } | |
2049 | ||
da91b269 | 2050 | static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) |
124b13b2 FMH |
2051 | { |
2052 | unsigned int value; | |
2053 | const int read_status_instruction = 0x5; | |
f6b49620 | 2054 | const int write_length = 8; /* 8 bit write lengths to eeprom */ |
124b13b2 | 2055 | |
f6b49620 | 2056 | /* enable read/write to eeprom */ |
124b13b2 | 2057 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
5f74ea14 | 2058 | udelay(1); |
124b13b2 FMH |
2059 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2060 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; | |
5f74ea14 | 2061 | udelay(1); |
124b13b2 FMH |
2062 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2063 | ||
f6b49620 | 2064 | /* send read status instruction */ |
124b13b2 | 2065 | labpc_serial_out(dev, read_status_instruction, write_length); |
f6b49620 | 2066 | /* read result */ |
124b13b2 FMH |
2067 | value = labpc_serial_in(dev); |
2068 | ||
f6b49620 | 2069 | /* disable read/write to eeprom */ |
124b13b2 | 2070 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
5f74ea14 | 2071 | udelay(1); |
124b13b2 FMH |
2072 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2073 | ||
2074 | return value; | |
2075 | } | |
2076 | ||
f6b49620 | 2077 | /* writes to 8 bit calibration dacs */ |
da91b269 | 2078 | static void write_caldac(struct comedi_device *dev, unsigned int channel, |
0a85b6f0 | 2079 | unsigned int value) |
124b13b2 FMH |
2080 | { |
2081 | if (value == devpriv->caldac[channel]) | |
2082 | return; | |
2083 | devpriv->caldac[channel] = value; | |
2084 | ||
f6b49620 | 2085 | /* clear caldac load bit and make sure we don't write to eeprom */ |
124b13b2 | 2086 | devpriv->command5_bits &= |
0a85b6f0 | 2087 | ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
5f74ea14 | 2088 | udelay(1); |
124b13b2 FMH |
2089 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2090 | ||
f6b49620 | 2091 | /* write 4 bit channel */ |
124b13b2 | 2092 | labpc_serial_out(dev, channel, 4); |
f6b49620 | 2093 | /* write 8 bit caldac value */ |
124b13b2 FMH |
2094 | labpc_serial_out(dev, value, 8); |
2095 | ||
f6b49620 | 2096 | /* set and clear caldac bit to load caldac value */ |
124b13b2 | 2097 | devpriv->command5_bits |= CALDAC_LOAD_BIT; |
5f74ea14 | 2098 | udelay(1); |
124b13b2 FMH |
2099 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2100 | devpriv->command5_bits &= ~CALDAC_LOAD_BIT; | |
5f74ea14 | 2101 | udelay(1); |
124b13b2 FMH |
2102 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2103 | } | |
2104 | ||
5e51f0db IA |
2105 | static struct comedi_driver labpc_driver = { |
2106 | .driver_name = DRV_NAME, | |
2107 | .module = THIS_MODULE, | |
2108 | .attach = labpc_attach, | |
7e2716cd | 2109 | .attach_pci = labpc_attach_pci, |
5e51f0db IA |
2110 | .detach = labpc_common_detach, |
2111 | .num_names = ARRAY_SIZE(labpc_boards), | |
2112 | .board_name = &labpc_boards[0].name, | |
2113 | .offset = sizeof(struct labpc_board_struct), | |
2114 | }; | |
2115 | ||
d6aa8366 | 2116 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
5e51f0db IA |
2117 | static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { |
2118 | {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)}, | |
2119 | {0} | |
2120 | }; | |
2121 | MODULE_DEVICE_TABLE(pci, labpc_pci_table); | |
2122 | ||
3faeeecb IA |
2123 | static int __devinit labpc_pci_probe(struct pci_dev *dev, |
2124 | const struct pci_device_id *ent) | |
727b286b | 2125 | { |
3faeeecb | 2126 | return comedi_pci_auto_config(dev, &labpc_driver); |
727b286b AT |
2127 | } |
2128 | ||
3faeeecb | 2129 | static void __devexit labpc_pci_remove(struct pci_dev *dev) |
727b286b AT |
2130 | { |
2131 | comedi_pci_auto_unconfig(dev); | |
2132 | } | |
2133 | ||
3faeeecb IA |
2134 | static struct pci_driver labpc_pci_driver = { |
2135 | .name = DRV_NAME, | |
727b286b | 2136 | .id_table = labpc_pci_table, |
3faeeecb IA |
2137 | .probe = labpc_pci_probe, |
2138 | .remove = __devexit_p(labpc_pci_remove) | |
727b286b | 2139 | }; |
3faeeecb | 2140 | module_comedi_pci_driver(labpc_driver, labpc_pci_driver); |
124b13b2 | 2141 | #else |
3faeeecb | 2142 | module_comedi_driver(labpc_driver); |
124b13b2 FMH |
2143 | #endif |
2144 | ||
90f703d3 AT |
2145 | |
2146 | MODULE_AUTHOR("Comedi http://www.comedi.org"); | |
2147 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
2148 | MODULE_LICENSE("GPL"); |