Commit | Line | Data |
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124b13b2 | 1 | /* |
31922394 HS |
2 | * comedi/drivers/ni_labpc.c |
3 | * Driver for National Instruments Lab-PC series boards and compatibles | |
4 | * Copyright (C) 2001-2003 Frank Mori Hess <fmhess@users.sourceforge.net> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
31922394 | 15 | */ |
124b13b2 FMH |
16 | |
17 | /* | |
31922394 HS |
18 | * Driver: ni_labpc |
19 | * Description: National Instruments Lab-PC (& compatibles) | |
20 | * Devices: (National Instruments) Lab-PC-1200 [lab-pc-1200] | |
21 | * (National Instruments) Lab-PC-1200AI [lab-pc-1200ai] | |
22 | * (National Instruments) Lab-PC+ [lab-pc+] | |
31922394 HS |
23 | * Author: Frank Mori Hess <fmhess@users.sourceforge.net> |
24 | * Status: works | |
25 | * | |
26 | * Configuration options - ISA boards: | |
27 | * [0] - I/O port base address | |
28 | * [1] - IRQ (optional, required for timed or externally triggered | |
29 | * conversions) | |
30 | * [2] - DMA channel (optional) | |
31 | * | |
31922394 HS |
32 | * Tested with lab-pc-1200. For the older Lab-PC+, not all input |
33 | * ranges and analog references will work, the available ranges/arefs | |
34 | * will depend on how you have configured the jumpers on your board | |
35 | * (see your owner's manual). | |
36 | * | |
37 | * Kernel-level ISA plug-and-play support for the lab-pc-1200 boards | |
38 | * has not yet been added to the driver, mainly due to the fact that | |
39 | * I don't know the device id numbers. If you have one of these boards, | |
40 | * please file a bug report at http://comedi.org/ so I can get the | |
41 | * necessary information from you. | |
42 | * | |
43 | * The 1200 series boards have onboard calibration dacs for correcting | |
44 | * analog input/output offsets and gains. The proper settings for these | |
45 | * caldacs are stored on the board's eeprom. To read the caldac values | |
46 | * from the eeprom and store them into a file that can be then be used | |
47 | * by comedilib, use the comedi_calibrate program. | |
48 | * | |
49 | * The Lab-pc+ has quirky chanlist requirements when scanning multiple | |
50 | * channels. Multiple channel scan sequence must start at highest channel, | |
51 | * then decrement down to channel 0. The rest of the cards can scan down | |
52 | * like lab-pc+ or scan up from channel zero. Chanlists consisting of all | |
53 | * one channel are also legal, and allow you to pace conversions in bursts. | |
54 | * | |
55 | * NI manuals: | |
56 | * 341309a (labpc-1200 register manual) | |
31922394 HS |
57 | * 320502b (lab-pc+) |
58 | */ | |
124b13b2 | 59 | |
25436dc9 | 60 | #include <linux/interrupt.h> |
5a0e3ad6 | 61 | #include <linux/slab.h> |
845d131e | 62 | #include <linux/io.h> |
33782dd5 HS |
63 | #include <linux/delay.h> |
64 | ||
124b13b2 FMH |
65 | #include "../comedidev.h" |
66 | ||
124b13b2 FMH |
67 | #include <asm/dma.h> |
68 | ||
69 | #include "8253.h" | |
70 | #include "8255.h" | |
124b13b2 FMH |
71 | #include "comedi_fc.h" |
72 | #include "ni_labpc.h" | |
73 | ||
42cb6a82 HS |
74 | /* |
75 | * Register map (all registers are 8-bit) | |
76 | */ | |
77 | #define STAT1_REG 0x00 /* R: Status 1 reg */ | |
78 | #define STAT1_DAVAIL (1 << 0) | |
79 | #define STAT1_OVERRUN (1 << 1) | |
80 | #define STAT1_OVERFLOW (1 << 2) | |
81 | #define STAT1_CNTINT (1 << 3) | |
82 | #define STAT1_GATA0 (1 << 5) | |
83 | #define STAT1_EXTGATA0 (1 << 6) | |
84 | #define CMD1_REG 0x00 /* W: Command 1 reg */ | |
85 | #define CMD1_MA(x) (((x) & 0x7) << 0) | |
86 | #define CMD1_TWOSCMP (1 << 3) | |
87 | #define CMD1_GAIN_MASK (7 << 4) | |
88 | #define CMD1_SCANEN (1 << 7) | |
89 | #define CMD2_REG 0x01 /* W: Command 2 reg */ | |
90 | #define CMD2_PRETRIG (1 << 0) | |
91 | #define CMD2_HWTRIG (1 << 1) | |
92 | #define CMD2_SWTRIG (1 << 2) | |
93 | #define CMD2_TBSEL (1 << 3) | |
94 | #define CMD2_2SDAC0 (1 << 4) | |
95 | #define CMD2_2SDAC1 (1 << 5) | |
96 | #define CMD2_LDAC(x) (1 << (6 + (x))) | |
97 | #define CMD3_REG 0x02 /* W: Command 3 reg */ | |
98 | #define CMD3_DMAEN (1 << 0) | |
99 | #define CMD3_DIOINTEN (1 << 1) | |
100 | #define CMD3_DMATCINTEN (1 << 2) | |
101 | #define CMD3_CNTINTEN (1 << 3) | |
102 | #define CMD3_ERRINTEN (1 << 4) | |
103 | #define CMD3_FIFOINTEN (1 << 5) | |
104 | #define ADC_START_CONVERT_REG 0x03 /* W: Start Convert reg */ | |
105 | #define DAC_LSB_REG(x) (0x04 + 2 * (x)) /* W: DAC0/1 LSB reg */ | |
106 | #define DAC_MSB_REG(x) (0x05 + 2 * (x)) /* W: DAC0/1 MSB reg */ | |
107 | #define ADC_FIFO_CLEAR_REG 0x08 /* W: A/D FIFO Clear reg */ | |
108 | #define ADC_FIFO_REG 0x0a /* R: A/D FIFO reg */ | |
109 | #define DMATC_CLEAR_REG 0x0a /* W: DMA Interrupt Clear reg */ | |
110 | #define TIMER_CLEAR_REG 0x0c /* W: Timer Interrupt Clear reg */ | |
111 | #define CMD6_REG 0x0e /* W: Command 6 reg */ | |
112 | #define CMD6_NRSE (1 << 0) | |
113 | #define CMD6_ADCUNI (1 << 1) | |
114 | #define CMD6_DACUNI(x) (1 << (2 + (x))) | |
115 | #define CMD6_HFINTEN (1 << 5) | |
116 | #define CMD6_DQINTEN (1 << 6) | |
117 | #define CMD6_SCANUP (1 << 7) | |
118 | #define CMD4_REG 0x0f /* W: Command 3 reg */ | |
119 | #define CMD4_INTSCAN (1 << 0) | |
120 | #define CMD4_EOIRCV (1 << 1) | |
121 | #define CMD4_ECLKDRV (1 << 2) | |
122 | #define CMD4_SEDIFF (1 << 3) | |
123 | #define CMD4_ECLKRCV (1 << 4) | |
124 | #define DIO_BASE_REG 0x10 /* R/W: 8255 DIO base reg */ | |
125 | #define COUNTER_A_BASE_REG 0x14 /* R/W: 8253 Counter A base reg */ | |
42cb6a82 HS |
126 | #define COUNTER_B_BASE_REG 0x18 /* R/W: 8253 Counter B base reg */ |
127 | #define CMD5_REG 0x1c /* W: Command 5 reg */ | |
128 | #define CMD5_WRTPRT (1 << 2) | |
129 | #define CMD5_DITHEREN (1 << 3) | |
130 | #define CMD5_CALDACLD (1 << 4) | |
131 | #define CMD5_SCLK (1 << 5) | |
132 | #define CMD5_SDATA (1 << 6) | |
133 | #define CMD5_EEPROMCS (1 << 7) | |
134 | #define STAT2_REG 0x1d /* R: Status 2 reg */ | |
135 | #define STAT2_PROMOUT (1 << 0) | |
136 | #define STAT2_OUTA1 (1 << 1) | |
137 | #define STAT2_FIFONHF (1 << 2) | |
138 | #define INTERVAL_COUNT_REG 0x1e /* W: Interval Counter Data reg */ | |
139 | #define INTERVAL_STROBE_REG 0x1f /* W: Interval Counter Strobe reg */ | |
124b13b2 | 140 | |
488ec9f1 HS |
141 | #define LABPC_SIZE 0x20 /* size of ISA io region */ |
142 | #define LABPC_TIMER_BASE 500 /* 2 MHz master clock */ | |
810c73c7 HS |
143 | #define LABPC_ADC_TIMEOUT 1000 |
144 | ||
6f73fbce IA |
145 | enum scan_mode { |
146 | MODE_SINGLE_CHAN, | |
147 | MODE_SINGLE_CHAN_INTERVAL, | |
148 | MODE_MULT_CHAN_UP, | |
149 | MODE_MULT_CHAN_DOWN, | |
150 | }; | |
151 | ||
1b3e0c80 HS |
152 | static const int labpc_plus_ai_gain_bits[] = { |
153 | 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, | |
154 | 0x00, 0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, | |
124b13b2 | 155 | }; |
0a85b6f0 | 156 | |
9ced1de6 | 157 | static const struct comedi_lrange range_labpc_plus_ai = { |
1b3e0c80 HS |
158 | 16, { |
159 | BIP_RANGE(5), | |
160 | BIP_RANGE(4), | |
161 | BIP_RANGE(2.5), | |
162 | BIP_RANGE(1), | |
163 | BIP_RANGE(0.5), | |
164 | BIP_RANGE(0.25), | |
165 | BIP_RANGE(0.1), | |
166 | BIP_RANGE(0.05), | |
167 | UNI_RANGE(10), | |
168 | UNI_RANGE(8), | |
169 | UNI_RANGE(5), | |
170 | UNI_RANGE(2), | |
171 | UNI_RANGE(1), | |
172 | UNI_RANGE(0.5), | |
173 | UNI_RANGE(0.2), | |
174 | UNI_RANGE(0.1) | |
175 | } | |
124b13b2 FMH |
176 | }; |
177 | ||
1b3e0c80 HS |
178 | const int labpc_1200_ai_gain_bits[] = { |
179 | 0x00, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, | |
180 | 0x00, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, | |
124b13b2 | 181 | }; |
0656bb35 | 182 | EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); |
0a85b6f0 | 183 | |
70d52bce | 184 | static const struct comedi_lrange range_labpc_1200_ai = { |
1b3e0c80 HS |
185 | 14, { |
186 | BIP_RANGE(5), | |
187 | BIP_RANGE(2.5), | |
188 | BIP_RANGE(1), | |
189 | BIP_RANGE(0.5), | |
190 | BIP_RANGE(0.25), | |
191 | BIP_RANGE(0.1), | |
192 | BIP_RANGE(0.05), | |
193 | UNI_RANGE(10), | |
194 | UNI_RANGE(5), | |
195 | UNI_RANGE(2), | |
196 | UNI_RANGE(1), | |
197 | UNI_RANGE(0.5), | |
198 | UNI_RANGE(0.2), | |
199 | UNI_RANGE(0.1) | |
200 | } | |
124b13b2 FMH |
201 | }; |
202 | ||
9ced1de6 | 203 | static const struct comedi_lrange range_labpc_ao = { |
1b3e0c80 HS |
204 | 2, { |
205 | BIP_RANGE(5), | |
206 | UNI_RANGE(10) | |
207 | } | |
124b13b2 FMH |
208 | }; |
209 | ||
210 | /* functions that do inb/outb and readb/writeb so we can use | |
211 | * function pointers to decide which to use */ | |
212 | static inline unsigned int labpc_inb(unsigned long address) | |
213 | { | |
214 | return inb(address); | |
215 | } | |
0a85b6f0 | 216 | |
124b13b2 FMH |
217 | static inline void labpc_outb(unsigned int byte, unsigned long address) |
218 | { | |
219 | outb(byte, address); | |
220 | } | |
0a85b6f0 | 221 | |
124b13b2 FMH |
222 | static inline unsigned int labpc_readb(unsigned long address) |
223 | { | |
5743aaac | 224 | return readb((void __iomem *)address); |
124b13b2 | 225 | } |
0a85b6f0 | 226 | |
124b13b2 FMH |
227 | static inline void labpc_writeb(unsigned int byte, unsigned long address) |
228 | { | |
5743aaac | 229 | writeb(byte, (void __iomem *)address); |
124b13b2 FMH |
230 | } |
231 | ||
a0eeed40 | 232 | #if IS_ENABLED(CONFIG_COMEDI_NI_LABPC_ISA) |
f65d971d | 233 | static const struct labpc_boardinfo labpc_boards[] = { |
124b13b2 | 234 | { |
f2c447ca | 235 | .name = "lab-pc-1200", |
f2c447ca | 236 | .ai_range_code = labpc_1200_ai_gain_bits, |
63d6ba20 | 237 | .ai_speed = 10000, |
f2c447ca | 238 | .ai_scan_up = 1, |
63d6ba20 HS |
239 | .has_ao = 1, |
240 | .is_labpc1200 = 1, | |
f2c447ca HS |
241 | }, { |
242 | .name = "lab-pc-1200ai", | |
f2c447ca | 243 | .ai_range_code = labpc_1200_ai_gain_bits, |
63d6ba20 | 244 | .ai_speed = 10000, |
f2c447ca | 245 | .ai_scan_up = 1, |
63d6ba20 | 246 | .is_labpc1200 = 1, |
f2c447ca HS |
247 | }, { |
248 | .name = "lab-pc+", | |
f2c447ca | 249 | .ai_range_code = labpc_plus_ai_gain_bits, |
63d6ba20 HS |
250 | .ai_speed = 12000, |
251 | .has_ao = 1, | |
f2c447ca | 252 | }, |
124b13b2 | 253 | }; |
fa3cb219 | 254 | #endif |
124b13b2 | 255 | |
e41a6f6d SR |
256 | /* size in bytes of dma buffer */ |
257 | static const int dma_buffer_size = 0xff00; | |
258 | /* 2 bytes per sample */ | |
259 | static const int sample_size = 2; | |
124b13b2 | 260 | |
fbca05d6 HS |
261 | static int labpc_counter_load(struct comedi_device *dev, |
262 | unsigned long base_address, | |
263 | unsigned int counter_number, | |
264 | unsigned int count, unsigned int mode) | |
265 | { | |
266 | const struct labpc_boardinfo *board = comedi_board(dev); | |
267 | ||
268 | if (board->has_mmio) | |
269 | return i8254_mm_load((void __iomem *)base_address, 0, | |
270 | counter_number, count, mode); | |
271 | else | |
272 | return i8254_load(base_address, 0, counter_number, count, mode); | |
273 | } | |
274 | ||
463f9304 HS |
275 | static int labpc_counter_set_mode(struct comedi_device *dev, |
276 | unsigned long base_address, | |
277 | unsigned int counter_number, | |
278 | unsigned int mode) | |
279 | { | |
280 | const struct labpc_boardinfo *board = comedi_board(dev); | |
281 | ||
282 | if (board->has_mmio) | |
283 | return i8254_mm_set_mode((void __iomem *)base_address, 0, | |
284 | counter_number, mode); | |
285 | else | |
286 | return i8254_set_mode(base_address, 0, counter_number, mode); | |
287 | } | |
288 | ||
43a9411a HS |
289 | static bool labpc_range_is_unipolar(struct comedi_subdevice *s, |
290 | unsigned int range) | |
291 | { | |
43d092c6 | 292 | return s->range_table->range[range].min >= 0; |
43a9411a HS |
293 | } |
294 | ||
8a498667 HS |
295 | static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
296 | { | |
297 | struct labpc_private *devpriv = dev->private; | |
298 | unsigned long flags; | |
299 | ||
300 | spin_lock_irqsave(&dev->spinlock, flags); | |
42cb6a82 HS |
301 | devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); |
302 | devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); | |
8a498667 HS |
303 | spin_unlock_irqrestore(&dev->spinlock, flags); |
304 | ||
305 | devpriv->cmd3 = 0; | |
42cb6a82 | 306 | devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); |
8a498667 HS |
307 | |
308 | return 0; | |
309 | } | |
310 | ||
8c2bc333 HS |
311 | static void labpc_ai_set_chan_and_gain(struct comedi_device *dev, |
312 | enum scan_mode mode, | |
313 | unsigned int chan, | |
314 | unsigned int range, | |
315 | unsigned int aref) | |
316 | { | |
317 | const struct labpc_boardinfo *board = comedi_board(dev); | |
318 | struct labpc_private *devpriv = dev->private; | |
319 | ||
320 | /* munge channel bits for differential/scan disabled mode */ | |
321 | if ((mode == MODE_SINGLE_CHAN || mode == MODE_SINGLE_CHAN_INTERVAL) && | |
322 | aref == AREF_DIFF) | |
323 | chan *= 2; | |
42cb6a82 | 324 | devpriv->cmd1 = CMD1_MA(chan); |
8c2bc333 HS |
325 | devpriv->cmd1 |= board->ai_range_code[range]; |
326 | ||
42cb6a82 | 327 | devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); |
8c2bc333 HS |
328 | } |
329 | ||
359553bb HS |
330 | static void labpc_setup_cmd6_reg(struct comedi_device *dev, |
331 | struct comedi_subdevice *s, | |
332 | enum scan_mode mode, | |
333 | enum transfer_type xfer, | |
334 | unsigned int range, | |
335 | unsigned int aref, | |
336 | bool ena_intr) | |
337 | { | |
338 | const struct labpc_boardinfo *board = comedi_board(dev); | |
339 | struct labpc_private *devpriv = dev->private; | |
340 | ||
63d6ba20 | 341 | if (!board->is_labpc1200) |
359553bb HS |
342 | return; |
343 | ||
344 | /* reference inputs to ground or common? */ | |
345 | if (aref != AREF_GROUND) | |
42cb6a82 | 346 | devpriv->cmd6 |= CMD6_NRSE; |
359553bb | 347 | else |
42cb6a82 | 348 | devpriv->cmd6 &= ~CMD6_NRSE; |
359553bb HS |
349 | |
350 | /* bipolar or unipolar range? */ | |
351 | if (labpc_range_is_unipolar(s, range)) | |
42cb6a82 | 352 | devpriv->cmd6 |= CMD6_ADCUNI; |
359553bb | 353 | else |
42cb6a82 | 354 | devpriv->cmd6 &= ~CMD6_ADCUNI; |
359553bb HS |
355 | |
356 | /* interrupt on fifo half full? */ | |
357 | if (xfer == fifo_half_full_transfer) | |
42cb6a82 | 358 | devpriv->cmd6 |= CMD6_HFINTEN; |
359553bb | 359 | else |
42cb6a82 | 360 | devpriv->cmd6 &= ~CMD6_HFINTEN; |
359553bb HS |
361 | |
362 | /* enable interrupt on counter a1 terminal count? */ | |
363 | if (ena_intr) | |
42cb6a82 | 364 | devpriv->cmd6 |= CMD6_DQINTEN; |
359553bb | 365 | else |
42cb6a82 | 366 | devpriv->cmd6 &= ~CMD6_DQINTEN; |
359553bb HS |
367 | |
368 | /* are we scanning up or down through channels? */ | |
369 | if (mode == MODE_MULT_CHAN_UP) | |
42cb6a82 | 370 | devpriv->cmd6 |= CMD6_SCANUP; |
359553bb | 371 | else |
42cb6a82 | 372 | devpriv->cmd6 &= ~CMD6_SCANUP; |
359553bb | 373 | |
42cb6a82 | 374 | devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); |
359553bb HS |
375 | } |
376 | ||
3c4dfac8 HS |
377 | static unsigned int labpc_read_adc_fifo(struct comedi_device *dev) |
378 | { | |
379 | struct labpc_private *devpriv = dev->private; | |
380 | unsigned int lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
381 | unsigned int msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
382 | ||
383 | return (msb << 8) | lsb; | |
384 | } | |
385 | ||
386 | static void labpc_clear_adc_fifo(struct comedi_device *dev) | |
124b13b2 | 387 | { |
9a1a6cf8 | 388 | struct labpc_private *devpriv = dev->private; |
78110bb8 | 389 | |
42cb6a82 | 390 | devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); |
3c4dfac8 | 391 | labpc_read_adc_fifo(dev); |
dd2aef64 | 392 | } |
124b13b2 | 393 | |
810c73c7 HS |
394 | static int labpc_ai_wait_for_data(struct comedi_device *dev, |
395 | int timeout) | |
396 | { | |
397 | struct labpc_private *devpriv = dev->private; | |
398 | int i; | |
399 | ||
400 | for (i = 0; i < timeout; i++) { | |
42cb6a82 HS |
401 | devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); |
402 | if (devpriv->stat1 & STAT1_DAVAIL) | |
810c73c7 HS |
403 | return 0; |
404 | udelay(1); | |
405 | } | |
406 | return -ETIME; | |
407 | } | |
408 | ||
28a10930 HS |
409 | static int labpc_ai_insn_read(struct comedi_device *dev, |
410 | struct comedi_subdevice *s, | |
411 | struct comedi_insn *insn, | |
412 | unsigned int *data) | |
dd2aef64 HS |
413 | { |
414 | struct labpc_private *devpriv = dev->private; | |
73f2b1d2 HS |
415 | unsigned int chan = CR_CHAN(insn->chanspec); |
416 | unsigned int range = CR_RANGE(insn->chanspec); | |
417 | unsigned int aref = CR_AREF(insn->chanspec); | |
810c73c7 HS |
418 | int ret; |
419 | int i; | |
124b13b2 | 420 | |
8a498667 HS |
421 | /* disable timed conversions, interrupt generation and dma */ |
422 | labpc_cancel(dev, s); | |
124b13b2 | 423 | |
8c2bc333 | 424 | labpc_ai_set_chan_and_gain(dev, MODE_SINGLE_CHAN, chan, range, aref); |
124b13b2 | 425 | |
359553bb HS |
426 | labpc_setup_cmd6_reg(dev, s, MODE_SINGLE_CHAN, fifo_not_empty_transfer, |
427 | range, aref, false); | |
428 | ||
74df5760 HS |
429 | /* setup cmd4 register */ |
430 | devpriv->cmd4 = 0; | |
42cb6a82 | 431 | devpriv->cmd4 |= CMD4_ECLKRCV; |
af81f093 | 432 | /* single-ended/differential */ |
73f2b1d2 | 433 | if (aref == AREF_DIFF) |
42cb6a82 HS |
434 | devpriv->cmd4 |= CMD4_SEDIFF; |
435 | devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); | |
124b13b2 | 436 | |
463f9304 | 437 | /* initialize pacer counter to prevent any problems */ |
f06563f0 HS |
438 | ret = labpc_counter_set_mode(dev, dev->iobase + COUNTER_A_BASE_REG, |
439 | 0, I8254_MODE2); | |
440 | if (ret) | |
441 | return ret; | |
7e2716cd | 442 | |
af81f093 | 443 | labpc_clear_adc_fifo(dev); |
7e2716cd | 444 | |
810c73c7 | 445 | for (i = 0; i < insn->n; i++) { |
af81f093 | 446 | /* trigger conversion */ |
42cb6a82 | 447 | devpriv->write_byte(0x1, dev->iobase + ADC_START_CONVERT_REG); |
7e2716cd | 448 | |
810c73c7 HS |
449 | ret = labpc_ai_wait_for_data(dev, LABPC_ADC_TIMEOUT); |
450 | if (ret) | |
451 | return ret; | |
452 | ||
453 | data[i] = labpc_read_adc_fifo(dev); | |
dd2aef64 | 454 | } |
9a1a6cf8 | 455 | |
810c73c7 | 456 | return insn->n; |
af81f093 | 457 | } |
124b13b2 | 458 | |
af81f093 HS |
459 | #ifdef CONFIG_ISA_DMA_API |
460 | /* utility function that suggests a dma transfer size in bytes */ | |
461 | static unsigned int labpc_suggest_transfer_size(const struct comedi_cmd *cmd) | |
462 | { | |
463 | unsigned int size; | |
464 | unsigned int freq; | |
124b13b2 | 465 | |
af81f093 HS |
466 | if (cmd->convert_src == TRIG_TIMER) |
467 | freq = 1000000000 / cmd->convert_arg; | |
468 | /* return some default value */ | |
469 | else | |
470 | freq = 0xffffffff; | |
124b13b2 | 471 | |
af81f093 HS |
472 | /* make buffer fill in no more than 1/3 second */ |
473 | size = (freq / 3) * sample_size; | |
124b13b2 | 474 | |
af81f093 HS |
475 | /* set a minimum and maximum size allowed */ |
476 | if (size > dma_buffer_size) | |
477 | size = dma_buffer_size - dma_buffer_size % sample_size; | |
478 | else if (size < sample_size) | |
479 | size = sample_size; | |
124b13b2 | 480 | |
af81f093 | 481 | return size; |
124b13b2 | 482 | } |
af81f093 | 483 | #endif |
124b13b2 | 484 | |
63a93381 HS |
485 | static bool labpc_use_continuous_mode(const struct comedi_cmd *cmd, |
486 | enum scan_mode mode) | |
124b13b2 | 487 | { |
63a93381 HS |
488 | if (mode == MODE_SINGLE_CHAN || cmd->scan_begin_src == TRIG_FOLLOW) |
489 | return true; | |
124b13b2 | 490 | |
63a93381 | 491 | return false; |
124b13b2 FMH |
492 | } |
493 | ||
6f73fbce IA |
494 | static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd, |
495 | enum scan_mode mode) | |
124b13b2 FMH |
496 | { |
497 | if (cmd->convert_src != TRIG_TIMER) | |
498 | return 0; | |
499 | ||
6f73fbce | 500 | if (mode == MODE_SINGLE_CHAN && cmd->scan_begin_src == TRIG_TIMER) |
124b13b2 FMH |
501 | return cmd->scan_begin_arg; |
502 | ||
503 | return cmd->convert_arg; | |
504 | } | |
505 | ||
6f73fbce IA |
506 | static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, |
507 | enum scan_mode mode, unsigned int ns) | |
124b13b2 FMH |
508 | { |
509 | if (cmd->convert_src != TRIG_TIMER) | |
510 | return; | |
511 | ||
6f73fbce | 512 | if (mode == MODE_SINGLE_CHAN && |
0a85b6f0 | 513 | cmd->scan_begin_src == TRIG_TIMER) { |
124b13b2 FMH |
514 | cmd->scan_begin_arg = ns; |
515 | if (cmd->convert_arg > cmd->scan_begin_arg) | |
516 | cmd->convert_arg = cmd->scan_begin_arg; | |
517 | } else | |
518 | cmd->convert_arg = ns; | |
519 | } | |
520 | ||
6f73fbce IA |
521 | static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd, |
522 | enum scan_mode mode) | |
124b13b2 FMH |
523 | { |
524 | if (cmd->scan_begin_src != TRIG_TIMER) | |
525 | return 0; | |
526 | ||
6f73fbce | 527 | if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) |
124b13b2 FMH |
528 | return 0; |
529 | ||
530 | return cmd->scan_begin_arg; | |
531 | } | |
532 | ||
af81f093 HS |
533 | static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, |
534 | enum scan_mode mode, unsigned int ns) | |
535 | { | |
536 | if (cmd->scan_begin_src != TRIG_TIMER) | |
537 | return; | |
538 | ||
539 | if (mode == MODE_SINGLE_CHAN && cmd->convert_src == TRIG_TIMER) | |
540 | return; | |
541 | ||
542 | cmd->scan_begin_arg = ns; | |
543 | } | |
544 | ||
545 | /* figures out what counter values to use based on command */ | |
546 | static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd, | |
547 | enum scan_mode mode) | |
548 | { | |
549 | struct labpc_private *devpriv = dev->private; | |
550 | /* max value for 16 bit counter in mode 2 */ | |
551 | const int max_counter_value = 0x10000; | |
552 | /* min value for 16 bit counter in mode 2 */ | |
553 | const int min_counter_value = 2; | |
554 | unsigned int base_period; | |
555 | unsigned int scan_period; | |
556 | unsigned int convert_period; | |
557 | ||
558 | /* | |
559 | * if both convert and scan triggers are TRIG_TIMER, then they | |
560 | * both rely on counter b0 | |
561 | */ | |
562 | convert_period = labpc_ai_convert_period(cmd, mode); | |
563 | scan_period = labpc_ai_scan_period(cmd, mode); | |
564 | if (convert_period && scan_period) { | |
565 | /* | |
566 | * pick the lowest b0 divisor value we can (for maximum input | |
567 | * clock speed on convert and scan counters) | |
568 | */ | |
569 | devpriv->divisor_b0 = (scan_period - 1) / | |
570 | (LABPC_TIMER_BASE * max_counter_value) + 1; | |
571 | if (devpriv->divisor_b0 < min_counter_value) | |
572 | devpriv->divisor_b0 = min_counter_value; | |
573 | if (devpriv->divisor_b0 > max_counter_value) | |
574 | devpriv->divisor_b0 = max_counter_value; | |
575 | ||
576 | base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; | |
577 | ||
578 | /* set a0 for conversion frequency and b1 for scan frequency */ | |
579 | switch (cmd->flags & TRIG_ROUND_MASK) { | |
580 | default: | |
581 | case TRIG_ROUND_NEAREST: | |
582 | devpriv->divisor_a0 = | |
583 | (convert_period + (base_period / 2)) / base_period; | |
584 | devpriv->divisor_b1 = | |
585 | (scan_period + (base_period / 2)) / base_period; | |
586 | break; | |
587 | case TRIG_ROUND_UP: | |
588 | devpriv->divisor_a0 = | |
589 | (convert_period + (base_period - 1)) / base_period; | |
590 | devpriv->divisor_b1 = | |
591 | (scan_period + (base_period - 1)) / base_period; | |
592 | break; | |
593 | case TRIG_ROUND_DOWN: | |
594 | devpriv->divisor_a0 = convert_period / base_period; | |
595 | devpriv->divisor_b1 = scan_period / base_period; | |
596 | break; | |
597 | } | |
598 | /* make sure a0 and b1 values are acceptable */ | |
599 | if (devpriv->divisor_a0 < min_counter_value) | |
600 | devpriv->divisor_a0 = min_counter_value; | |
601 | if (devpriv->divisor_a0 > max_counter_value) | |
602 | devpriv->divisor_a0 = max_counter_value; | |
603 | if (devpriv->divisor_b1 < min_counter_value) | |
604 | devpriv->divisor_b1 = min_counter_value; | |
605 | if (devpriv->divisor_b1 > max_counter_value) | |
606 | devpriv->divisor_b1 = max_counter_value; | |
607 | /* write corrected timings to command */ | |
608 | labpc_set_ai_convert_period(cmd, mode, | |
609 | base_period * devpriv->divisor_a0); | |
610 | labpc_set_ai_scan_period(cmd, mode, | |
611 | base_period * devpriv->divisor_b1); | |
612 | /* | |
613 | * if only one TRIG_TIMER is used, we can employ the generic | |
614 | * cascaded timing functions | |
615 | */ | |
616 | } else if (scan_period) { | |
617 | /* | |
618 | * calculate cascaded counter values | |
619 | * that give desired scan timing | |
620 | */ | |
621 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, | |
622 | &(devpriv->divisor_b1), | |
623 | &(devpriv->divisor_b0), | |
624 | &scan_period, | |
625 | cmd->flags & TRIG_ROUND_MASK); | |
626 | labpc_set_ai_scan_period(cmd, mode, scan_period); | |
627 | } else if (convert_period) { | |
628 | /* | |
629 | * calculate cascaded counter values | |
630 | * that give desired conversion timing | |
631 | */ | |
632 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, | |
633 | &(devpriv->divisor_a0), | |
634 | &(devpriv->divisor_b0), | |
635 | &convert_period, | |
636 | cmd->flags & TRIG_ROUND_MASK); | |
637 | labpc_set_ai_convert_period(cmd, mode, convert_period); | |
638 | } | |
639 | } | |
640 | ||
641 | static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) | |
642 | { | |
643 | if (cmd->chanlist_len == 1) | |
644 | return MODE_SINGLE_CHAN; | |
645 | ||
646 | /* chanlist may be NULL during cmdtest. */ | |
647 | if (cmd->chanlist == NULL) | |
648 | return MODE_MULT_CHAN_UP; | |
649 | ||
650 | if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) | |
651 | return MODE_SINGLE_CHAN_INTERVAL; | |
652 | ||
653 | if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) | |
654 | return MODE_MULT_CHAN_UP; | |
655 | ||
656 | if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) | |
657 | return MODE_MULT_CHAN_DOWN; | |
658 | ||
659 | pr_err("ni_labpc: bug! cannot determine AI scan mode\n"); | |
660 | return 0; | |
661 | } | |
662 | ||
663 | static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, | |
664 | const struct comedi_cmd *cmd, | |
665 | enum scan_mode mode) | |
666 | { | |
667 | int channel, range, aref, i; | |
668 | ||
669 | if (cmd->chanlist == NULL) | |
670 | return 0; | |
671 | ||
672 | if (mode == MODE_SINGLE_CHAN) | |
673 | return 0; | |
674 | ||
675 | if (mode == MODE_SINGLE_CHAN_INTERVAL) { | |
676 | if (cmd->chanlist_len > 0xff) { | |
677 | comedi_error(dev, | |
678 | "ni_labpc: chanlist too long for single channel interval mode\n"); | |
679 | return 1; | |
680 | } | |
681 | } | |
682 | ||
683 | channel = CR_CHAN(cmd->chanlist[0]); | |
684 | range = CR_RANGE(cmd->chanlist[0]); | |
685 | aref = CR_AREF(cmd->chanlist[0]); | |
686 | ||
687 | for (i = 0; i < cmd->chanlist_len; i++) { | |
688 | ||
689 | switch (mode) { | |
690 | case MODE_SINGLE_CHAN_INTERVAL: | |
691 | if (CR_CHAN(cmd->chanlist[i]) != channel) { | |
692 | comedi_error(dev, | |
693 | "channel scanning order specified in chanlist is not supported by hardware.\n"); | |
694 | return 1; | |
695 | } | |
696 | break; | |
697 | case MODE_MULT_CHAN_UP: | |
698 | if (CR_CHAN(cmd->chanlist[i]) != i) { | |
699 | comedi_error(dev, | |
700 | "channel scanning order specified in chanlist is not supported by hardware.\n"); | |
701 | return 1; | |
702 | } | |
703 | break; | |
704 | case MODE_MULT_CHAN_DOWN: | |
705 | if (CR_CHAN(cmd->chanlist[i]) != | |
706 | cmd->chanlist_len - i - 1) { | |
707 | comedi_error(dev, | |
708 | "channel scanning order specified in chanlist is not supported by hardware.\n"); | |
709 | return 1; | |
710 | } | |
711 | break; | |
712 | default: | |
713 | dev_err(dev->class_dev, | |
714 | "ni_labpc: bug! in chanlist check\n"); | |
715 | return 1; | |
716 | break; | |
717 | } | |
718 | ||
719 | if (CR_RANGE(cmd->chanlist[i]) != range) { | |
720 | comedi_error(dev, | |
721 | "entries in chanlist must all have the same range\n"); | |
722 | return 1; | |
723 | } | |
124b13b2 | 724 | |
af81f093 HS |
725 | if (CR_AREF(cmd->chanlist[i]) != aref) { |
726 | comedi_error(dev, | |
727 | "entries in chanlist must all have the same reference\n"); | |
728 | return 1; | |
729 | } | |
730 | } | |
124b13b2 | 731 | |
af81f093 | 732 | return 0; |
124b13b2 FMH |
733 | } |
734 | ||
0a85b6f0 MT |
735 | static int labpc_ai_cmdtest(struct comedi_device *dev, |
736 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
124b13b2 | 737 | { |
d0baa0c1 | 738 | const struct labpc_boardinfo *board = comedi_board(dev); |
124b13b2 FMH |
739 | int err = 0; |
740 | int tmp, tmp2; | |
27020ffe | 741 | unsigned int stop_mask; |
6f73fbce | 742 | enum scan_mode mode; |
124b13b2 | 743 | |
27020ffe | 744 | /* Step 1 : check if triggers are trivially valid */ |
124b13b2 | 745 | |
27020ffe HS |
746 | err |= cfc_check_trigger_src(&cmd->start_src, TRIG_NOW | TRIG_EXT); |
747 | err |= cfc_check_trigger_src(&cmd->scan_begin_src, | |
748 | TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT); | |
749 | err |= cfc_check_trigger_src(&cmd->convert_src, TRIG_TIMER | TRIG_EXT); | |
750 | err |= cfc_check_trigger_src(&cmd->scan_end_src, TRIG_COUNT); | |
124b13b2 | 751 | |
124b13b2 | 752 | stop_mask = TRIG_COUNT | TRIG_NONE; |
63d6ba20 | 753 | if (board->is_labpc1200) |
124b13b2 | 754 | stop_mask |= TRIG_EXT; |
27020ffe | 755 | err |= cfc_check_trigger_src(&cmd->stop_src, stop_mask); |
124b13b2 FMH |
756 | |
757 | if (err) | |
758 | return 1; | |
759 | ||
27020ffe | 760 | /* Step 2a : make sure trigger sources are unique */ |
124b13b2 | 761 | |
27020ffe HS |
762 | err |= cfc_check_trigger_is_unique(cmd->start_src); |
763 | err |= cfc_check_trigger_is_unique(cmd->scan_begin_src); | |
764 | err |= cfc_check_trigger_is_unique(cmd->convert_src); | |
765 | err |= cfc_check_trigger_is_unique(cmd->stop_src); | |
766 | ||
767 | /* Step 2b : and mutually compatible */ | |
124b13b2 | 768 | |
e41a6f6d | 769 | /* can't have external stop and start triggers at once */ |
124b13b2 FMH |
770 | if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) |
771 | err++; | |
772 | ||
773 | if (err) | |
774 | return 2; | |
775 | ||
88c79301 | 776 | /* Step 3: check if arguments are trivially valid */ |
124b13b2 | 777 | |
88c79301 HS |
778 | if (cmd->start_arg == TRIG_NOW) |
779 | err |= cfc_check_trigger_arg_is(&cmd->start_arg, 0); | |
124b13b2 | 780 | |
412bd046 | 781 | if (!cmd->chanlist_len) |
88c79301 HS |
782 | err |= -EINVAL; |
783 | err |= cfc_check_trigger_arg_is(&cmd->scan_end_arg, cmd->chanlist_len); | |
412bd046 | 784 | |
88c79301 HS |
785 | if (cmd->convert_src == TRIG_TIMER) |
786 | err |= cfc_check_trigger_arg_min(&cmd->convert_arg, | |
d0baa0c1 | 787 | board->ai_speed); |
124b13b2 | 788 | |
e41a6f6d | 789 | /* make sure scan timing is not too fast */ |
124b13b2 | 790 | if (cmd->scan_begin_src == TRIG_TIMER) { |
88c79301 HS |
791 | if (cmd->convert_src == TRIG_TIMER) |
792 | err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, | |
793 | cmd->convert_arg * cmd->chanlist_len); | |
794 | err |= cfc_check_trigger_arg_min(&cmd->scan_begin_arg, | |
d0baa0c1 | 795 | board->ai_speed * cmd->chanlist_len); |
124b13b2 | 796 | } |
88c79301 | 797 | |
124b13b2 FMH |
798 | switch (cmd->stop_src) { |
799 | case TRIG_COUNT: | |
88c79301 | 800 | err |= cfc_check_trigger_arg_min(&cmd->stop_arg, 1); |
124b13b2 FMH |
801 | break; |
802 | case TRIG_NONE: | |
88c79301 | 803 | err |= cfc_check_trigger_arg_is(&cmd->stop_arg, 0); |
124b13b2 | 804 | break; |
1309e617 MD |
805 | /* |
806 | * TRIG_EXT doesn't care since it doesn't | |
807 | * trigger off a numbered channel | |
808 | */ | |
124b13b2 FMH |
809 | default: |
810 | break; | |
811 | } | |
812 | ||
813 | if (err) | |
814 | return 3; | |
815 | ||
816 | /* step 4: fix up any arguments */ | |
817 | ||
818 | tmp = cmd->convert_arg; | |
819 | tmp2 = cmd->scan_begin_arg; | |
6f73fbce IA |
820 | mode = labpc_ai_scan_mode(cmd); |
821 | labpc_adc_timing(dev, cmd, mode); | |
124b13b2 FMH |
822 | if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) |
823 | err++; | |
824 | ||
825 | if (err) | |
826 | return 4; | |
827 | ||
6f73fbce | 828 | if (labpc_ai_chanlist_invalid(dev, cmd, mode)) |
124b13b2 FMH |
829 | return 5; |
830 | ||
831 | return 0; | |
832 | } | |
833 | ||
da91b269 | 834 | static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
124b13b2 | 835 | { |
d0baa0c1 | 836 | const struct labpc_boardinfo *board = comedi_board(dev); |
9a1a6cf8 | 837 | struct labpc_private *devpriv = dev->private; |
d163679c | 838 | struct comedi_async *async = s->async; |
ea6d0d4c | 839 | struct comedi_cmd *cmd = &async->cmd; |
8a67a67f HS |
840 | enum scan_mode mode = labpc_ai_scan_mode(cmd); |
841 | unsigned int chanspec = (mode == MODE_MULT_CHAN_UP) | |
842 | ? cmd->chanlist[cmd->chanlist_len - 1] | |
843 | : cmd->chanlist[0]; | |
844 | unsigned int chan = CR_CHAN(chanspec); | |
845 | unsigned int range = CR_RANGE(chanspec); | |
846 | unsigned int aref = CR_AREF(chanspec); | |
124b13b2 FMH |
847 | enum transfer_type xfer; |
848 | unsigned long flags; | |
8a67a67f | 849 | int ret; |
124b13b2 | 850 | |
25985edc | 851 | /* make sure board is disabled before setting up acquisition */ |
8a498667 | 852 | labpc_cancel(dev, s); |
124b13b2 | 853 | |
f6b49620 | 854 | /* initialize software conversion count */ |
412bd046 | 855 | if (cmd->stop_src == TRIG_COUNT) |
124b13b2 | 856 | devpriv->count = cmd->stop_arg * cmd->chanlist_len; |
65d6d26c | 857 | |
f6b49620 | 858 | /* setup hardware conversion counter */ |
124b13b2 | 859 | if (cmd->stop_src == TRIG_EXT) { |
1309e617 MD |
860 | /* |
861 | * load counter a1 with count of 3 | |
862 | * (pc+ manual says this is minimum allowed) using mode 0 | |
863 | */ | |
124b13b2 | 864 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
fbca05d6 | 865 | 1, 3, I8254_MODE0); |
463f9304 HS |
866 | } else { |
867 | /* just put counter a1 in mode 0 to set its output low */ | |
f06563f0 HS |
868 | ret = labpc_counter_set_mode(dev, |
869 | dev->iobase + COUNTER_A_BASE_REG, | |
870 | 1, I8254_MODE0); | |
871 | } | |
872 | if (ret) { | |
873 | comedi_error(dev, "error loading counter a1"); | |
874 | return ret; | |
463f9304 | 875 | } |
124b13b2 | 876 | |
3297d6c7 | 877 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 BP |
878 | /* figure out what method we will use to transfer data */ |
879 | if (devpriv->dma_chan && /* need a dma channel allocated */ | |
1309e617 MD |
880 | /* |
881 | * dma unsafe at RT priority, | |
882 | * and too much setup time for TRIG_WAKE_EOS for | |
883 | */ | |
3a0a73b3 | 884 | (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0) { |
124b13b2 | 885 | xfer = isa_dma_transfer; |
1309e617 | 886 | /* pc-plus has no fifo-half full interrupt */ |
3297d6c7 RD |
887 | } else |
888 | #endif | |
63d6ba20 | 889 | if (board->is_labpc1200 && |
0a85b6f0 MT |
890 | /* wake-end-of-scan should interrupt on fifo not empty */ |
891 | (cmd->flags & TRIG_WAKE_EOS) == 0 && | |
892 | /* make sure we are taking more than just a few points */ | |
893 | (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { | |
124b13b2 FMH |
894 | xfer = fifo_half_full_transfer; |
895 | } else | |
896 | xfer = fifo_not_empty_transfer; | |
897 | devpriv->current_transfer = xfer; | |
898 | ||
8c2bc333 HS |
899 | labpc_ai_set_chan_and_gain(dev, mode, chan, range, aref); |
900 | ||
359553bb HS |
901 | labpc_setup_cmd6_reg(dev, s, mode, xfer, range, aref, |
902 | (cmd->stop_src == TRIG_EXT)); | |
903 | ||
e41a6f6d | 904 | /* manual says to set scan enable bit on second pass */ |
6f73fbce | 905 | if (mode == MODE_MULT_CHAN_UP || mode == MODE_MULT_CHAN_DOWN) { |
42cb6a82 | 906 | devpriv->cmd1 |= CMD1_SCANEN; |
e41a6f6d SR |
907 | /* need a brief delay before enabling scan, or scan |
908 | * list will get screwed when you switch | |
124b13b2 | 909 | * between scan up to scan down mode - dunno why */ |
5f74ea14 | 910 | udelay(1); |
42cb6a82 | 911 | devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); |
124b13b2 | 912 | } |
124b13b2 FMH |
913 | |
914 | devpriv->write_byte(cmd->chanlist_len, | |
0a85b6f0 | 915 | dev->iobase + INTERVAL_COUNT_REG); |
f6b49620 | 916 | /* load count */ |
42cb6a82 | 917 | devpriv->write_byte(0x1, dev->iobase + INTERVAL_STROBE_REG); |
124b13b2 | 918 | |
d5c8d9c4 HS |
919 | if (cmd->convert_src == TRIG_TIMER || |
920 | cmd->scan_begin_src == TRIG_TIMER) { | |
f6b49620 | 921 | /* set up pacing */ |
6f73fbce | 922 | labpc_adc_timing(dev, cmd, mode); |
f6b49620 | 923 | /* load counter b0 in mode 3 */ |
124b13b2 | 924 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
fbca05d6 | 925 | 0, devpriv->divisor_b0, I8254_MODE3); |
124b13b2 FMH |
926 | if (ret < 0) { |
927 | comedi_error(dev, "error loading counter b0"); | |
928 | return -1; | |
929 | } | |
930 | } | |
f6b49620 | 931 | /* set up conversion pacing */ |
6f73fbce | 932 | if (labpc_ai_convert_period(cmd, mode)) { |
f6b49620 | 933 | /* load counter a0 in mode 2 */ |
124b13b2 | 934 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
fbca05d6 | 935 | 0, devpriv->divisor_a0, I8254_MODE2); |
463f9304 HS |
936 | } else { |
937 | /* initialize pacer counter to prevent any problems */ | |
f06563f0 HS |
938 | ret = labpc_counter_set_mode(dev, |
939 | dev->iobase + COUNTER_A_BASE_REG, | |
940 | 0, I8254_MODE2); | |
941 | } | |
942 | if (ret) { | |
943 | comedi_error(dev, "error loading counter a0"); | |
944 | return ret; | |
463f9304 | 945 | } |
124b13b2 | 946 | |
f6b49620 | 947 | /* set up scan pacing */ |
6f73fbce | 948 | if (labpc_ai_scan_period(cmd, mode)) { |
f6b49620 | 949 | /* load counter b1 in mode 2 */ |
124b13b2 | 950 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
fbca05d6 | 951 | 1, devpriv->divisor_b1, I8254_MODE2); |
124b13b2 FMH |
952 | if (ret < 0) { |
953 | comedi_error(dev, "error loading counter b1"); | |
954 | return -1; | |
955 | } | |
956 | } | |
957 | ||
958 | labpc_clear_adc_fifo(dev); | |
959 | ||
3297d6c7 | 960 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 | 961 | /* set up dma transfer */ |
124b13b2 | 962 | if (xfer == isa_dma_transfer) { |
fe7fc72a HS |
963 | unsigned long irq_flags; |
964 | ||
124b13b2 FMH |
965 | irq_flags = claim_dma_lock(); |
966 | disable_dma(devpriv->dma_chan); | |
967 | /* clear flip-flop to make sure 2-byte registers for | |
968 | * count and address get set correctly */ | |
969 | clear_dma_ff(devpriv->dma_chan); | |
970 | set_dma_addr(devpriv->dma_chan, | |
0a85b6f0 | 971 | virt_to_bus(devpriv->dma_buffer)); |
f6b49620 | 972 | /* set appropriate size of transfer */ |
62fea8c8 | 973 | devpriv->dma_transfer_size = labpc_suggest_transfer_size(cmd); |
124b13b2 | 974 | if (cmd->stop_src == TRIG_COUNT && |
0a85b6f0 | 975 | devpriv->count * sample_size < devpriv->dma_transfer_size) { |
124b13b2 | 976 | devpriv->dma_transfer_size = |
0a85b6f0 | 977 | devpriv->count * sample_size; |
124b13b2 FMH |
978 | } |
979 | set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); | |
980 | enable_dma(devpriv->dma_chan); | |
981 | release_dma_lock(irq_flags); | |
f6b49620 | 982 | /* enable board's dma */ |
42cb6a82 | 983 | devpriv->cmd3 |= (CMD3_DMAEN | CMD3_DMATCINTEN); |
124b13b2 | 984 | } else |
42cb6a82 | 985 | devpriv->cmd3 &= ~(CMD3_DMAEN | CMD3_DMATCINTEN); |
3297d6c7 | 986 | #endif |
124b13b2 | 987 | |
f6b49620 | 988 | /* enable error interrupts */ |
42cb6a82 | 989 | devpriv->cmd3 |= CMD3_ERRINTEN; |
f6b49620 | 990 | /* enable fifo not empty interrupt? */ |
124b13b2 | 991 | if (xfer == fifo_not_empty_transfer) |
42cb6a82 | 992 | devpriv->cmd3 |= CMD3_FIFOINTEN; |
124b13b2 | 993 | else |
42cb6a82 HS |
994 | devpriv->cmd3 &= ~CMD3_FIFOINTEN; |
995 | devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); | |
124b13b2 | 996 | |
74df5760 HS |
997 | /* setup any external triggering/pacing (cmd4 register) */ |
998 | devpriv->cmd4 = 0; | |
22056e2b | 999 | if (cmd->convert_src != TRIG_EXT) |
42cb6a82 | 1000 | devpriv->cmd4 |= CMD4_ECLKRCV; |
22056e2b IA |
1001 | /* XXX should discard first scan when using interval scanning |
1002 | * since manual says it is not synced with scan clock */ | |
63a93381 | 1003 | if (!labpc_use_continuous_mode(cmd, mode)) { |
42cb6a82 | 1004 | devpriv->cmd4 |= CMD4_INTSCAN; |
22056e2b | 1005 | if (cmd->scan_begin_src == TRIG_EXT) |
42cb6a82 | 1006 | devpriv->cmd4 |= CMD4_EOIRCV; |
22056e2b IA |
1007 | } |
1008 | /* single-ended/differential */ | |
1009 | if (aref == AREF_DIFF) | |
42cb6a82 HS |
1010 | devpriv->cmd4 |= CMD4_SEDIFF; |
1011 | devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); | |
22056e2b | 1012 | |
25985edc | 1013 | /* startup acquisition */ |
124b13b2 | 1014 | |
5f74ea14 | 1015 | spin_lock_irqsave(&dev->spinlock, flags); |
58cd9b91 HS |
1016 | |
1017 | /* use 2 cascaded counters for pacing */ | |
42cb6a82 | 1018 | devpriv->cmd2 |= CMD2_TBSEL; |
58cd9b91 HS |
1019 | |
1020 | devpriv->cmd2 &= ~(CMD2_SWTRIG | CMD2_HWTRIG | CMD2_PRETRIG); | |
1021 | if (cmd->start_src == TRIG_EXT) | |
42cb6a82 | 1022 | devpriv->cmd2 |= CMD2_HWTRIG; |
58cd9b91 | 1023 | else |
42cb6a82 | 1024 | devpriv->cmd2 |= CMD2_SWTRIG; |
58cd9b91 | 1025 | if (cmd->stop_src == TRIG_EXT) |
42cb6a82 | 1026 | devpriv->cmd2 |= (CMD2_HWTRIG | CMD2_PRETRIG); |
58cd9b91 | 1027 | |
42cb6a82 | 1028 | devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); |
58cd9b91 | 1029 | |
5f74ea14 | 1030 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1031 | |
1032 | return 0; | |
1033 | } | |
1034 | ||
571e06c1 HS |
1035 | #ifdef CONFIG_ISA_DMA_API |
1036 | static void labpc_drain_dma(struct comedi_device *dev) | |
1037 | { | |
1038 | struct labpc_private *devpriv = dev->private; | |
1039 | struct comedi_subdevice *s = dev->read_subdev; | |
1040 | struct comedi_async *async = s->async; | |
1041 | int status; | |
1042 | unsigned long flags; | |
1043 | unsigned int max_points, num_points, residue, leftover; | |
1044 | int i; | |
1045 | ||
74df5760 | 1046 | status = devpriv->stat1; |
571e06c1 HS |
1047 | |
1048 | flags = claim_dma_lock(); | |
1049 | disable_dma(devpriv->dma_chan); | |
1050 | /* clear flip-flop to make sure 2-byte registers for | |
1051 | * count and address get set correctly */ | |
1052 | clear_dma_ff(devpriv->dma_chan); | |
1053 | ||
1054 | /* figure out how many points to read */ | |
1055 | max_points = devpriv->dma_transfer_size / sample_size; | |
1056 | /* residue is the number of points left to be done on the dma | |
1057 | * transfer. It should always be zero at this point unless | |
1058 | * the stop_src is set to external triggering. | |
1059 | */ | |
1060 | residue = get_dma_residue(devpriv->dma_chan) / sample_size; | |
1061 | num_points = max_points - residue; | |
1062 | if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) | |
1063 | num_points = devpriv->count; | |
1064 | ||
1065 | /* figure out how many points will be stored next time */ | |
1066 | leftover = 0; | |
1067 | if (async->cmd.stop_src != TRIG_COUNT) { | |
1068 | leftover = devpriv->dma_transfer_size / sample_size; | |
1069 | } else if (devpriv->count > num_points) { | |
1070 | leftover = devpriv->count - num_points; | |
1071 | if (leftover > max_points) | |
1072 | leftover = max_points; | |
1073 | } | |
1074 | ||
1075 | /* write data to comedi buffer */ | |
1076 | for (i = 0; i < num_points; i++) | |
1077 | cfc_write_to_buffer(s, devpriv->dma_buffer[i]); | |
1078 | ||
1079 | if (async->cmd.stop_src == TRIG_COUNT) | |
1080 | devpriv->count -= num_points; | |
1081 | ||
1082 | /* set address and count for next transfer */ | |
1083 | set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); | |
1084 | set_dma_count(devpriv->dma_chan, leftover * sample_size); | |
1085 | release_dma_lock(flags); | |
1086 | ||
1087 | async->events |= COMEDI_CB_BLOCK; | |
1088 | } | |
1089 | ||
1090 | static void handle_isa_dma(struct comedi_device *dev) | |
1091 | { | |
1092 | struct labpc_private *devpriv = dev->private; | |
1093 | ||
1094 | labpc_drain_dma(dev); | |
1095 | ||
1096 | enable_dma(devpriv->dma_chan); | |
1097 | ||
1098 | /* clear dma tc interrupt */ | |
1099 | devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); | |
1100 | } | |
1101 | #endif | |
1102 | ||
1103 | /* read all available samples from ai fifo */ | |
1104 | static int labpc_drain_fifo(struct comedi_device *dev) | |
1105 | { | |
1106 | struct labpc_private *devpriv = dev->private; | |
571e06c1 HS |
1107 | short data; |
1108 | struct comedi_async *async = dev->read_subdev->async; | |
1109 | const int timeout = 10000; | |
1110 | unsigned int i; | |
1111 | ||
42cb6a82 | 1112 | devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); |
571e06c1 | 1113 | |
42cb6a82 | 1114 | for (i = 0; (devpriv->stat1 & STAT1_DAVAIL) && i < timeout; |
571e06c1 HS |
1115 | i++) { |
1116 | /* quit if we have all the data we want */ | |
1117 | if (async->cmd.stop_src == TRIG_COUNT) { | |
1118 | if (devpriv->count == 0) | |
1119 | break; | |
1120 | devpriv->count--; | |
1121 | } | |
3c4dfac8 | 1122 | data = labpc_read_adc_fifo(dev); |
571e06c1 | 1123 | cfc_write_to_buffer(dev->read_subdev, data); |
42cb6a82 | 1124 | devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); |
571e06c1 HS |
1125 | } |
1126 | if (i == timeout) { | |
1127 | comedi_error(dev, "ai timeout, fifo never empties"); | |
1128 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
1129 | return -1; | |
1130 | } | |
1131 | ||
1132 | return 0; | |
1133 | } | |
1134 | ||
1135 | /* makes sure all data acquired by board is transferred to comedi (used | |
1136 | * when acquisition is terminated by stop_src == TRIG_EXT). */ | |
1137 | static void labpc_drain_dregs(struct comedi_device *dev) | |
1138 | { | |
1139 | #ifdef CONFIG_ISA_DMA_API | |
1140 | struct labpc_private *devpriv = dev->private; | |
1141 | ||
1142 | if (devpriv->current_transfer == isa_dma_transfer) | |
1143 | labpc_drain_dma(dev); | |
1144 | #endif | |
1145 | ||
1146 | labpc_drain_fifo(dev); | |
1147 | } | |
1148 | ||
1149 | /* interrupt service routine */ | |
1150 | static irqreturn_t labpc_interrupt(int irq, void *d) | |
1151 | { | |
1152 | struct comedi_device *dev = d; | |
d0baa0c1 | 1153 | const struct labpc_boardinfo *board = comedi_board(dev); |
571e06c1 HS |
1154 | struct labpc_private *devpriv = dev->private; |
1155 | struct comedi_subdevice *s = dev->read_subdev; | |
1156 | struct comedi_async *async; | |
1157 | struct comedi_cmd *cmd; | |
1158 | ||
1159 | if (!dev->attached) { | |
1160 | comedi_error(dev, "premature interrupt"); | |
1161 | return IRQ_HANDLED; | |
1162 | } | |
1163 | ||
1164 | async = s->async; | |
1165 | cmd = &async->cmd; | |
1166 | async->events = 0; | |
1167 | ||
1168 | /* read board status */ | |
42cb6a82 | 1169 | devpriv->stat1 = devpriv->read_byte(dev->iobase + STAT1_REG); |
63d6ba20 | 1170 | if (board->is_labpc1200) |
42cb6a82 | 1171 | devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG); |
571e06c1 | 1172 | |
42cb6a82 HS |
1173 | if ((devpriv->stat1 & (STAT1_GATA0 | STAT1_CNTINT | STAT1_OVERFLOW | |
1174 | STAT1_OVERRUN | STAT1_DAVAIL)) == 0 | |
1175 | && (devpriv->stat2 & STAT2_OUTA1) == 0 | |
1176 | && (devpriv->stat2 & STAT2_FIFONHF)) { | |
571e06c1 HS |
1177 | return IRQ_NONE; |
1178 | } | |
1179 | ||
42cb6a82 | 1180 | if (devpriv->stat1 & STAT1_OVERRUN) { |
571e06c1 | 1181 | /* clear error interrupt */ |
42cb6a82 | 1182 | devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); |
571e06c1 HS |
1183 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; |
1184 | comedi_event(dev, s); | |
1185 | comedi_error(dev, "overrun"); | |
1186 | return IRQ_HANDLED; | |
1187 | } | |
1188 | ||
1189 | #ifdef CONFIG_ISA_DMA_API | |
1190 | if (devpriv->current_transfer == isa_dma_transfer) { | |
1191 | /* | |
1192 | * if a dma terminal count of external stop trigger | |
1193 | * has occurred | |
1194 | */ | |
42cb6a82 | 1195 | if (devpriv->stat1 & STAT1_GATA0 || |
63d6ba20 | 1196 | (board->is_labpc1200 && devpriv->stat2 & STAT2_OUTA1)) { |
571e06c1 HS |
1197 | handle_isa_dma(dev); |
1198 | } | |
1199 | } else | |
1200 | #endif | |
1201 | labpc_drain_fifo(dev); | |
1202 | ||
42cb6a82 | 1203 | if (devpriv->stat1 & STAT1_CNTINT) { |
571e06c1 HS |
1204 | comedi_error(dev, "handled timer interrupt?"); |
1205 | /* clear it */ | |
1206 | devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); | |
1207 | } | |
1208 | ||
42cb6a82 | 1209 | if (devpriv->stat1 & STAT1_OVERFLOW) { |
571e06c1 | 1210 | /* clear error interrupt */ |
42cb6a82 | 1211 | devpriv->write_byte(0x1, dev->iobase + ADC_FIFO_CLEAR_REG); |
571e06c1 HS |
1212 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; |
1213 | comedi_event(dev, s); | |
1214 | comedi_error(dev, "overflow"); | |
1215 | return IRQ_HANDLED; | |
1216 | } | |
1217 | /* handle external stop trigger */ | |
1218 | if (cmd->stop_src == TRIG_EXT) { | |
42cb6a82 | 1219 | if (devpriv->stat2 & STAT2_OUTA1) { |
571e06c1 HS |
1220 | labpc_drain_dregs(dev); |
1221 | labpc_cancel(dev, s); | |
1222 | async->events |= COMEDI_CB_EOA; | |
1223 | } | |
1224 | } | |
1225 | ||
1226 | /* TRIG_COUNT end of acquisition */ | |
1227 | if (cmd->stop_src == TRIG_COUNT) { | |
1228 | if (devpriv->count == 0) { | |
1229 | labpc_cancel(dev, s); | |
1230 | async->events |= COMEDI_CB_EOA; | |
1231 | } | |
1232 | } | |
1233 | ||
1234 | comedi_event(dev, s); | |
1235 | return IRQ_HANDLED; | |
1236 | } | |
1237 | ||
28a10930 HS |
1238 | static int labpc_ao_insn_write(struct comedi_device *dev, |
1239 | struct comedi_subdevice *s, | |
1240 | struct comedi_insn *insn, | |
1241 | unsigned int *data) | |
8913491d | 1242 | { |
d0baa0c1 | 1243 | const struct labpc_boardinfo *board = comedi_board(dev); |
8913491d HS |
1244 | struct labpc_private *devpriv = dev->private; |
1245 | int channel, range; | |
1246 | unsigned long flags; | |
1247 | int lsb, msb; | |
1248 | ||
1249 | channel = CR_CHAN(insn->chanspec); | |
1250 | ||
1251 | /* turn off pacing of analog output channel */ | |
1252 | /* note: hardware bug in daqcard-1200 means pacing cannot | |
1253 | * be independently enabled/disabled for its the two channels */ | |
1254 | spin_lock_irqsave(&dev->spinlock, flags); | |
42cb6a82 HS |
1255 | devpriv->cmd2 &= ~CMD2_LDAC(channel); |
1256 | devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); | |
8913491d HS |
1257 | spin_unlock_irqrestore(&dev->spinlock, flags); |
1258 | ||
1259 | /* set range */ | |
63d6ba20 | 1260 | if (board->is_labpc1200) { |
8913491d | 1261 | range = CR_RANGE(insn->chanspec); |
43a9411a | 1262 | if (labpc_range_is_unipolar(s, range)) |
42cb6a82 | 1263 | devpriv->cmd6 |= CMD6_DACUNI(channel); |
8913491d | 1264 | else |
42cb6a82 | 1265 | devpriv->cmd6 &= ~CMD6_DACUNI(channel); |
8913491d | 1266 | /* write to register */ |
42cb6a82 | 1267 | devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); |
8913491d HS |
1268 | } |
1269 | /* send data */ | |
1270 | lsb = data[0] & 0xff; | |
1271 | msb = (data[0] >> 8) & 0xff; | |
1272 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); | |
1273 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); | |
1274 | ||
1275 | /* remember value for readback */ | |
1276 | devpriv->ao_value[channel] = data[0]; | |
1277 | ||
1278 | return 1; | |
1279 | } | |
1280 | ||
28a10930 HS |
1281 | static int labpc_ao_insn_read(struct comedi_device *dev, |
1282 | struct comedi_subdevice *s, | |
1283 | struct comedi_insn *insn, | |
1284 | unsigned int *data) | |
8913491d HS |
1285 | { |
1286 | struct labpc_private *devpriv = dev->private; | |
1287 | ||
1288 | data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; | |
1289 | ||
1290 | return 1; | |
1291 | } | |
1292 | ||
370c8e1f | 1293 | static int labpc_8255_mmio(int dir, int port, int data, unsigned long iobase) |
124b13b2 FMH |
1294 | { |
1295 | if (dir) { | |
5743aaac | 1296 | writeb(data, (void __iomem *)(iobase + port)); |
124b13b2 FMH |
1297 | return 0; |
1298 | } else { | |
5743aaac | 1299 | return readb((void __iomem *)(iobase + port)); |
124b13b2 FMH |
1300 | } |
1301 | } | |
1302 | ||
f6b49620 | 1303 | /* lowlevel write to eeprom/dac */ |
da91b269 | 1304 | static void labpc_serial_out(struct comedi_device *dev, unsigned int value, |
0a85b6f0 | 1305 | unsigned int value_width) |
124b13b2 | 1306 | { |
9a1a6cf8 | 1307 | struct labpc_private *devpriv = dev->private; |
124b13b2 FMH |
1308 | int i; |
1309 | ||
1310 | for (i = 1; i <= value_width; i++) { | |
f6b49620 | 1311 | /* clear serial clock */ |
42cb6a82 | 1312 | devpriv->cmd5 &= ~CMD5_SCLK; |
f6b49620 | 1313 | /* send bits most significant bit first */ |
124b13b2 | 1314 | if (value & (1 << (value_width - i))) |
42cb6a82 | 1315 | devpriv->cmd5 |= CMD5_SDATA; |
124b13b2 | 1316 | else |
42cb6a82 | 1317 | devpriv->cmd5 &= ~CMD5_SDATA; |
5f74ea14 | 1318 | udelay(1); |
42cb6a82 | 1319 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
f6b49620 | 1320 | /* set clock to load bit */ |
42cb6a82 | 1321 | devpriv->cmd5 |= CMD5_SCLK; |
5f74ea14 | 1322 | udelay(1); |
42cb6a82 | 1323 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 FMH |
1324 | } |
1325 | } | |
1326 | ||
f6b49620 | 1327 | /* lowlevel read from eeprom */ |
da91b269 | 1328 | static unsigned int labpc_serial_in(struct comedi_device *dev) |
124b13b2 | 1329 | { |
9a1a6cf8 | 1330 | struct labpc_private *devpriv = dev->private; |
124b13b2 FMH |
1331 | unsigned int value = 0; |
1332 | int i; | |
f6b49620 | 1333 | const int value_width = 8; /* number of bits wide values are */ |
124b13b2 FMH |
1334 | |
1335 | for (i = 1; i <= value_width; i++) { | |
f6b49620 | 1336 | /* set serial clock */ |
42cb6a82 | 1337 | devpriv->cmd5 |= CMD5_SCLK; |
5f74ea14 | 1338 | udelay(1); |
42cb6a82 | 1339 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
f6b49620 | 1340 | /* clear clock bit */ |
42cb6a82 | 1341 | devpriv->cmd5 &= ~CMD5_SCLK; |
5f74ea14 | 1342 | udelay(1); |
42cb6a82 | 1343 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
f6b49620 | 1344 | /* read bits most significant bit first */ |
5f74ea14 | 1345 | udelay(1); |
42cb6a82 HS |
1346 | devpriv->stat2 = devpriv->read_byte(dev->iobase + STAT2_REG); |
1347 | if (devpriv->stat2 & STAT2_PROMOUT) | |
124b13b2 | 1348 | value |= 1 << (value_width - i); |
124b13b2 FMH |
1349 | } |
1350 | ||
1351 | return value; | |
1352 | } | |
1353 | ||
0a85b6f0 MT |
1354 | static unsigned int labpc_eeprom_read(struct comedi_device *dev, |
1355 | unsigned int address) | |
124b13b2 | 1356 | { |
9a1a6cf8 | 1357 | struct labpc_private *devpriv = dev->private; |
124b13b2 | 1358 | unsigned int value; |
e41a6f6d SR |
1359 | /* bits to tell eeprom to expect a read */ |
1360 | const int read_instruction = 0x3; | |
1361 | /* 8 bit write lengths to eeprom */ | |
1362 | const int write_length = 8; | |
124b13b2 | 1363 | |
f6b49620 | 1364 | /* enable read/write to eeprom */ |
42cb6a82 | 1365 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
5f74ea14 | 1366 | udelay(1); |
42cb6a82 HS |
1367 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1368 | devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); | |
5f74ea14 | 1369 | udelay(1); |
42cb6a82 | 1370 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1371 | |
f6b49620 | 1372 | /* send read instruction */ |
124b13b2 | 1373 | labpc_serial_out(dev, read_instruction, write_length); |
f6b49620 | 1374 | /* send 8 bit address to read from */ |
124b13b2 | 1375 | labpc_serial_out(dev, address, write_length); |
f6b49620 | 1376 | /* read result */ |
124b13b2 FMH |
1377 | value = labpc_serial_in(dev); |
1378 | ||
f6b49620 | 1379 | /* disable read/write to eeprom */ |
42cb6a82 | 1380 | devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); |
5f74ea14 | 1381 | udelay(1); |
42cb6a82 | 1382 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 FMH |
1383 | |
1384 | return value; | |
1385 | } | |
1386 | ||
bc3fc446 HS |
1387 | static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) |
1388 | { | |
1389 | struct labpc_private *devpriv = dev->private; | |
1390 | unsigned int value; | |
1391 | const int read_status_instruction = 0x5; | |
1392 | const int write_length = 8; /* 8 bit write lengths to eeprom */ | |
1393 | ||
1394 | /* enable read/write to eeprom */ | |
42cb6a82 | 1395 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
bc3fc446 | 1396 | udelay(1); |
42cb6a82 HS |
1397 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1398 | devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); | |
bc3fc446 | 1399 | udelay(1); |
42cb6a82 | 1400 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
bc3fc446 HS |
1401 | |
1402 | /* send read status instruction */ | |
1403 | labpc_serial_out(dev, read_status_instruction, write_length); | |
1404 | /* read result */ | |
1405 | value = labpc_serial_in(dev); | |
1406 | ||
1407 | /* disable read/write to eeprom */ | |
42cb6a82 | 1408 | devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); |
bc3fc446 | 1409 | udelay(1); |
42cb6a82 | 1410 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
bc3fc446 HS |
1411 | |
1412 | return value; | |
1413 | } | |
1414 | ||
d6269644 JL |
1415 | static int labpc_eeprom_write(struct comedi_device *dev, |
1416 | unsigned int address, unsigned int value) | |
124b13b2 | 1417 | { |
9a1a6cf8 | 1418 | struct labpc_private *devpriv = dev->private; |
124b13b2 FMH |
1419 | const int write_enable_instruction = 0x6; |
1420 | const int write_instruction = 0x2; | |
f6b49620 | 1421 | const int write_length = 8; /* 8 bit write lengths to eeprom */ |
124b13b2 FMH |
1422 | const int write_in_progress_bit = 0x1; |
1423 | const int timeout = 10000; | |
1424 | int i; | |
1425 | ||
f6b49620 | 1426 | /* make sure there isn't already a write in progress */ |
124b13b2 FMH |
1427 | for (i = 0; i < timeout; i++) { |
1428 | if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == | |
0a85b6f0 | 1429 | 0) |
124b13b2 FMH |
1430 | break; |
1431 | } | |
1432 | if (i == timeout) { | |
1433 | comedi_error(dev, "eeprom write timed out"); | |
1434 | return -ETIME; | |
1435 | } | |
f6b49620 | 1436 | /* update software copy of eeprom */ |
124b13b2 FMH |
1437 | devpriv->eeprom_data[address] = value; |
1438 | ||
f6b49620 | 1439 | /* enable read/write to eeprom */ |
42cb6a82 | 1440 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
5f74ea14 | 1441 | udelay(1); |
42cb6a82 HS |
1442 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1443 | devpriv->cmd5 |= (CMD5_EEPROMCS | CMD5_WRTPRT); | |
5f74ea14 | 1444 | udelay(1); |
42cb6a82 | 1445 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1446 | |
f6b49620 | 1447 | /* send write_enable instruction */ |
124b13b2 | 1448 | labpc_serial_out(dev, write_enable_instruction, write_length); |
42cb6a82 | 1449 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
5f74ea14 | 1450 | udelay(1); |
42cb6a82 | 1451 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1452 | |
f6b49620 | 1453 | /* send write instruction */ |
42cb6a82 | 1454 | devpriv->cmd5 |= CMD5_EEPROMCS; |
5f74ea14 | 1455 | udelay(1); |
42cb6a82 | 1456 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1457 | labpc_serial_out(dev, write_instruction, write_length); |
f6b49620 | 1458 | /* send 8 bit address to write to */ |
124b13b2 | 1459 | labpc_serial_out(dev, address, write_length); |
f6b49620 | 1460 | /* write value */ |
124b13b2 | 1461 | labpc_serial_out(dev, value, write_length); |
42cb6a82 | 1462 | devpriv->cmd5 &= ~CMD5_EEPROMCS; |
5f74ea14 | 1463 | udelay(1); |
42cb6a82 | 1464 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1465 | |
f6b49620 | 1466 | /* disable read/write to eeprom */ |
42cb6a82 | 1467 | devpriv->cmd5 &= ~(CMD5_EEPROMCS | CMD5_WRTPRT); |
5f74ea14 | 1468 | udelay(1); |
42cb6a82 | 1469 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 FMH |
1470 | |
1471 | return 0; | |
1472 | } | |
1473 | ||
f6b49620 | 1474 | /* writes to 8 bit calibration dacs */ |
da91b269 | 1475 | static void write_caldac(struct comedi_device *dev, unsigned int channel, |
0a85b6f0 | 1476 | unsigned int value) |
124b13b2 | 1477 | { |
9a1a6cf8 HS |
1478 | struct labpc_private *devpriv = dev->private; |
1479 | ||
124b13b2 FMH |
1480 | if (value == devpriv->caldac[channel]) |
1481 | return; | |
1482 | devpriv->caldac[channel] = value; | |
1483 | ||
f6b49620 | 1484 | /* clear caldac load bit and make sure we don't write to eeprom */ |
42cb6a82 | 1485 | devpriv->cmd5 &= ~(CMD5_CALDACLD | CMD5_EEPROMCS | CMD5_WRTPRT); |
5f74ea14 | 1486 | udelay(1); |
42cb6a82 | 1487 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 | 1488 | |
f6b49620 | 1489 | /* write 4 bit channel */ |
124b13b2 | 1490 | labpc_serial_out(dev, channel, 4); |
f6b49620 | 1491 | /* write 8 bit caldac value */ |
124b13b2 FMH |
1492 | labpc_serial_out(dev, value, 8); |
1493 | ||
f6b49620 | 1494 | /* set and clear caldac bit to load caldac value */ |
42cb6a82 | 1495 | devpriv->cmd5 |= CMD5_CALDACLD; |
5f74ea14 | 1496 | udelay(1); |
42cb6a82 HS |
1497 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1498 | devpriv->cmd5 &= ~CMD5_CALDACLD; | |
5f74ea14 | 1499 | udelay(1); |
42cb6a82 | 1500 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
124b13b2 FMH |
1501 | } |
1502 | ||
28a10930 | 1503 | static int labpc_calib_insn_write(struct comedi_device *dev, |
bc3fc446 | 1504 | struct comedi_subdevice *s, |
28a10930 HS |
1505 | struct comedi_insn *insn, |
1506 | unsigned int *data) | |
bc3fc446 | 1507 | { |
7c00782b | 1508 | unsigned int chan = CR_CHAN(insn->chanspec); |
bc3fc446 | 1509 | |
7c00782b HS |
1510 | /* |
1511 | * Only write the last data value to the caldac. Preceding | |
1512 | * data would be overwritten anyway. | |
1513 | */ | |
1514 | if (insn->n > 0) | |
1515 | write_caldac(dev, chan, data[insn->n - 1]); | |
1516 | ||
1517 | return insn->n; | |
bc3fc446 HS |
1518 | } |
1519 | ||
28a10930 | 1520 | static int labpc_calib_insn_read(struct comedi_device *dev, |
bc3fc446 | 1521 | struct comedi_subdevice *s, |
28a10930 HS |
1522 | struct comedi_insn *insn, |
1523 | unsigned int *data) | |
bc3fc446 HS |
1524 | { |
1525 | struct labpc_private *devpriv = dev->private; | |
198ac9dc HS |
1526 | unsigned int chan = CR_CHAN(insn->chanspec); |
1527 | int i; | |
bc3fc446 | 1528 | |
198ac9dc HS |
1529 | for (i = 0; i < insn->n; i++) |
1530 | data[i] = devpriv->caldac[chan]; | |
bc3fc446 | 1531 | |
198ac9dc | 1532 | return insn->n; |
bc3fc446 HS |
1533 | } |
1534 | ||
28a10930 | 1535 | static int labpc_eeprom_insn_write(struct comedi_device *dev, |
bc3fc446 | 1536 | struct comedi_subdevice *s, |
28a10930 HS |
1537 | struct comedi_insn *insn, |
1538 | unsigned int *data) | |
bc3fc446 | 1539 | { |
e7a1aa62 | 1540 | unsigned int chan = CR_CHAN(insn->chanspec); |
bc3fc446 HS |
1541 | int ret; |
1542 | ||
e7a1aa62 HS |
1543 | /* only allow writes to user area of eeprom */ |
1544 | if (chan < 16 || chan > 127) | |
bc3fc446 | 1545 | return -EINVAL; |
bc3fc446 | 1546 | |
e7a1aa62 HS |
1547 | /* |
1548 | * Only write the last data value to the eeprom. Preceding | |
1549 | * data would be overwritten anyway. | |
1550 | */ | |
1551 | if (insn->n > 0) { | |
1552 | ret = labpc_eeprom_write(dev, chan, data[insn->n - 1]); | |
1553 | if (ret) | |
1554 | return ret; | |
1555 | } | |
bc3fc446 | 1556 | |
e7a1aa62 | 1557 | return insn->n; |
bc3fc446 HS |
1558 | } |
1559 | ||
28a10930 | 1560 | static int labpc_eeprom_insn_read(struct comedi_device *dev, |
bc3fc446 | 1561 | struct comedi_subdevice *s, |
28a10930 HS |
1562 | struct comedi_insn *insn, |
1563 | unsigned int *data) | |
bc3fc446 HS |
1564 | { |
1565 | struct labpc_private *devpriv = dev->private; | |
1330af4c HS |
1566 | unsigned int chan = CR_CHAN(insn->chanspec); |
1567 | int i; | |
bc3fc446 | 1568 | |
1330af4c HS |
1569 | for (i = 0; i < insn->n; i++) |
1570 | data[i] = devpriv->eeprom_data[chan]; | |
bc3fc446 | 1571 | |
1330af4c | 1572 | return insn->n; |
bc3fc446 HS |
1573 | } |
1574 | ||
de024b3d | 1575 | int labpc_common_attach(struct comedi_device *dev, |
3e034797 | 1576 | unsigned int irq, unsigned long isr_flags) |
dd2aef64 | 1577 | { |
d0baa0c1 | 1578 | const struct labpc_boardinfo *board = comedi_board(dev); |
dd2aef64 HS |
1579 | struct labpc_private *devpriv = dev->private; |
1580 | struct comedi_subdevice *s; | |
dd2aef64 | 1581 | int ret; |
cacedd0c | 1582 | int i; |
dd2aef64 | 1583 | |
4d3cc8ab | 1584 | if (board->has_mmio) { |
dd2aef64 HS |
1585 | devpriv->read_byte = labpc_readb; |
1586 | devpriv->write_byte = labpc_writeb; | |
1587 | } else { | |
1588 | devpriv->read_byte = labpc_inb; | |
1589 | devpriv->write_byte = labpc_outb; | |
1590 | } | |
83d75eff | 1591 | |
dd2aef64 | 1592 | /* initialize board's command registers */ |
42cb6a82 HS |
1593 | devpriv->write_byte(devpriv->cmd1, dev->iobase + CMD1_REG); |
1594 | devpriv->write_byte(devpriv->cmd2, dev->iobase + CMD2_REG); | |
1595 | devpriv->write_byte(devpriv->cmd3, dev->iobase + CMD3_REG); | |
1596 | devpriv->write_byte(devpriv->cmd4, dev->iobase + CMD4_REG); | |
63d6ba20 | 1597 | if (board->is_labpc1200) { |
42cb6a82 HS |
1598 | devpriv->write_byte(devpriv->cmd5, dev->iobase + CMD5_REG); |
1599 | devpriv->write_byte(devpriv->cmd6, dev->iobase + CMD6_REG); | |
dd2aef64 HS |
1600 | } |
1601 | ||
dd2aef64 | 1602 | if (irq) { |
0229979a HS |
1603 | ret = request_irq(irq, labpc_interrupt, isr_flags, |
1604 | dev->board_name, dev); | |
1605 | if (ret == 0) | |
1606 | dev->irq = irq; | |
dd2aef64 | 1607 | } |
dd2aef64 | 1608 | |
dd2aef64 HS |
1609 | ret = comedi_alloc_subdevices(dev, 5); |
1610 | if (ret) | |
1611 | return ret; | |
1612 | ||
1613 | /* analog input subdevice */ | |
1614 | s = &dev->subdevices[0]; | |
9bffb75d HS |
1615 | s->type = COMEDI_SUBD_AI; |
1616 | s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF; | |
1617 | s->n_chan = 8; | |
1618 | s->len_chanlist = 8; | |
1619 | s->maxdata = 0x0fff; | |
70d52bce HS |
1620 | s->range_table = board->is_labpc1200 |
1621 | ? &range_labpc_1200_ai : &range_labpc_plus_ai; | |
9bffb75d HS |
1622 | s->insn_read = labpc_ai_insn_read; |
1623 | if (dev->irq) { | |
1624 | dev->read_subdev = s; | |
1625 | s->subdev_flags |= SDF_CMD_READ; | |
1626 | s->do_cmd = labpc_ai_cmd; | |
1627 | s->do_cmdtest = labpc_ai_cmdtest; | |
1628 | s->cancel = labpc_cancel; | |
1629 | } | |
dd2aef64 HS |
1630 | |
1631 | /* analog output */ | |
1632 | s = &dev->subdevices[1]; | |
d0baa0c1 | 1633 | if (board->has_ao) { |
7d47f0f4 HS |
1634 | s->type = COMEDI_SUBD_AO; |
1635 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; | |
1636 | s->n_chan = NUM_AO_CHAN; | |
1637 | s->maxdata = 0x0fff; | |
1638 | s->range_table = &range_labpc_ao; | |
1639 | s->insn_read = labpc_ao_insn_read; | |
1640 | s->insn_write = labpc_ao_insn_write; | |
1641 | ||
dd2aef64 HS |
1642 | /* initialize analog outputs to a known value */ |
1643 | for (i = 0; i < s->n_chan; i++) { | |
7d47f0f4 HS |
1644 | short lsb, msb; |
1645 | ||
dd2aef64 HS |
1646 | devpriv->ao_value[i] = s->maxdata / 2; |
1647 | lsb = devpriv->ao_value[i] & 0xff; | |
1648 | msb = (devpriv->ao_value[i] >> 8) & 0xff; | |
1649 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); | |
1650 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); | |
1651 | } | |
1652 | } else { | |
7d47f0f4 | 1653 | s->type = COMEDI_SUBD_UNUSED; |
dd2aef64 HS |
1654 | } |
1655 | ||
1656 | /* 8255 dio */ | |
1657 | s = &dev->subdevices[2]; | |
370c8e1f HS |
1658 | ret = subdev_8255_init(dev, s, |
1659 | (board->has_mmio) ? labpc_8255_mmio : NULL, | |
1660 | dev->iobase + DIO_BASE_REG); | |
1661 | if (ret) | |
1662 | return ret; | |
dd2aef64 HS |
1663 | |
1664 | /* calibration subdevices for boards that have one */ | |
1665 | s = &dev->subdevices[3]; | |
63d6ba20 | 1666 | if (board->is_labpc1200) { |
7d47f0f4 HS |
1667 | s->type = COMEDI_SUBD_CALIB; |
1668 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; | |
1669 | s->n_chan = 16; | |
1670 | s->maxdata = 0xff; | |
1671 | s->insn_read = labpc_calib_insn_read; | |
1672 | s->insn_write = labpc_calib_insn_write; | |
dd2aef64 HS |
1673 | |
1674 | for (i = 0; i < s->n_chan; i++) | |
1675 | write_caldac(dev, i, s->maxdata / 2); | |
1676 | } else | |
7d47f0f4 | 1677 | s->type = COMEDI_SUBD_UNUSED; |
dd2aef64 HS |
1678 | |
1679 | /* EEPROM */ | |
1680 | s = &dev->subdevices[4]; | |
63d6ba20 | 1681 | if (board->is_labpc1200) { |
7d47f0f4 HS |
1682 | s->type = COMEDI_SUBD_MEMORY; |
1683 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; | |
1684 | s->n_chan = EEPROM_SIZE; | |
1685 | s->maxdata = 0xff; | |
1686 | s->insn_read = labpc_eeprom_insn_read; | |
1687 | s->insn_write = labpc_eeprom_insn_write; | |
1688 | ||
1689 | for (i = 0; i < s->n_chan; i++) | |
dd2aef64 HS |
1690 | devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); |
1691 | } else | |
7d47f0f4 | 1692 | s->type = COMEDI_SUBD_UNUSED; |
dd2aef64 HS |
1693 | |
1694 | return 0; | |
1695 | } | |
1696 | EXPORT_SYMBOL_GPL(labpc_common_attach); | |
1697 | ||
fa3cb219 HS |
1698 | void labpc_common_detach(struct comedi_device *dev) |
1699 | { | |
1700 | comedi_spriv_free(dev, 2); | |
1701 | } | |
1702 | EXPORT_SYMBOL_GPL(labpc_common_detach); | |
1703 | ||
a0eeed40 | 1704 | #if IS_ENABLED(CONFIG_COMEDI_NI_LABPC_ISA) |
dd2aef64 HS |
1705 | static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) |
1706 | { | |
dd2aef64 | 1707 | struct labpc_private *devpriv; |
fa3cb219 HS |
1708 | unsigned int irq = it->options[1]; |
1709 | unsigned int dma_chan = it->options[2]; | |
5b365a8a | 1710 | int ret; |
dd2aef64 HS |
1711 | |
1712 | devpriv = kzalloc(sizeof(*devpriv), GFP_KERNEL); | |
1713 | if (!devpriv) | |
1714 | return -ENOMEM; | |
1715 | dev->private = devpriv; | |
1716 | ||
fa3cb219 | 1717 | ret = comedi_request_region(dev, it->options[0], LABPC_SIZE); |
dd2aef64 HS |
1718 | if (ret) |
1719 | return ret; | |
1720 | ||
3e034797 | 1721 | ret = labpc_common_attach(dev, irq, 0); |
76730884 HS |
1722 | if (ret) |
1723 | return ret; | |
1724 | ||
1725 | #ifdef CONFIG_ISA_DMA_API | |
1726 | if (dev->irq && (dma_chan == 1 || dma_chan == 3)) { | |
1727 | devpriv->dma_buffer = kmalloc(dma_buffer_size, | |
1728 | GFP_KERNEL | GFP_DMA); | |
1729 | if (devpriv->dma_buffer) { | |
1730 | ret = request_dma(dma_chan, dev->board_name); | |
1731 | if (ret == 0) { | |
1732 | unsigned long dma_flags; | |
1733 | ||
1734 | devpriv->dma_chan = dma_chan; | |
1735 | dma_flags = claim_dma_lock(); | |
1736 | disable_dma(devpriv->dma_chan); | |
1737 | set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); | |
1738 | release_dma_lock(dma_flags); | |
1739 | } else { | |
1740 | kfree(devpriv->dma_buffer); | |
1741 | } | |
1742 | } | |
1743 | } | |
1744 | #endif | |
1745 | ||
1746 | return 0; | |
dd2aef64 HS |
1747 | } |
1748 | ||
a0eeed40 | 1749 | static void labpc_detach(struct comedi_device *dev) |
dd2aef64 | 1750 | { |
dd2aef64 | 1751 | struct labpc_private *devpriv = dev->private; |
dd2aef64 | 1752 | |
fa3cb219 HS |
1753 | labpc_common_detach(dev); |
1754 | ||
1755 | if (devpriv) { | |
1756 | kfree(devpriv->dma_buffer); | |
1757 | if (devpriv->dma_chan) | |
1758 | free_dma(devpriv->dma_chan); | |
3d1fe3f7 | 1759 | } |
fa3cb219 | 1760 | comedi_legacy_detach(dev); |
dd2aef64 | 1761 | } |
dd2aef64 | 1762 | |
5e51f0db | 1763 | static struct comedi_driver labpc_driver = { |
147a85d7 | 1764 | .driver_name = "ni_labpc", |
6e8bddf2 HS |
1765 | .module = THIS_MODULE, |
1766 | .attach = labpc_attach, | |
fa3cb219 | 1767 | .detach = labpc_detach, |
6e8bddf2 HS |
1768 | .num_names = ARRAY_SIZE(labpc_boards), |
1769 | .board_name = &labpc_boards[0].name, | |
1770 | .offset = sizeof(struct labpc_boardinfo), | |
5e51f0db | 1771 | }; |
fa3cb219 HS |
1772 | module_comedi_driver(labpc_driver); |
1773 | #else | |
1774 | static int __init labpc_common_init(void) | |
727b286b | 1775 | { |
fa3cb219 | 1776 | return 0; |
727b286b | 1777 | } |
fa3cb219 | 1778 | module_init(labpc_common_init); |
727b286b | 1779 | |
fa3cb219 HS |
1780 | static void __exit labpc_common_exit(void) |
1781 | { | |
1782 | } | |
1783 | module_exit(labpc_common_exit); | |
124b13b2 FMH |
1784 | #endif |
1785 | ||
90f703d3 AT |
1786 | MODULE_AUTHOR("Comedi http://www.comedi.org"); |
1787 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
1788 | MODULE_LICENSE("GPL"); |