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Staging: comedi: Remove COMEDI_INITCLEANUP macro
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_labpc.c
CommitLineData
124b13b2
FMH		 1/*
2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20************************************************************************
21*/
22/*
23Driver: ni_labpc
24Description: National Instruments Lab-PC (& compatibles)
25Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
28Status: works
29
30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31and analog references will work, the available ranges/arefs will
32depend on how you have configured the jumpers on your board
33(see your owner's manual).
34
35Kernel-level ISA plug-and-play support for the lab-pc-1200
36boards has not
37yet been added to the driver, mainly due to the fact that
38I don't know the device id numbers. If you have one
39of these boards,
40please file a bug report at https://bugs.comedi.org/
41so I can get the necessary information from you.
42
43The 1200 series boards have onboard calibration dacs for correcting
44analog input/output offsets and gains. The proper settings for these
45caldacs are stored on the board's eeprom. To read the caldac values
46from the eeprom and store them into a file that can be then be used by
47comedilib, use the comedi_calibrate program.
48
49Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
53
54Configuration options - PCI boards:
55 [0] - bus (optional)
56 [1] - slot (optional)
57
58The Lab-pc+ has quirky chanlist requirements
59when scanning multiple channels. Multiple channel scan
60sequence must start at highest channel, then decrement down to
61channel 0. The rest of the cards can scan down like lab-pc+ or scan
62up from channel zero. Chanlists consisting of all one channel
63are also legal, and allow you to pace conversions in bursts.
64
65*/
66
67/*
68
69NI manuals:
70341309a (labpc-1200 register manual)
71340914a (pci-1200)
72320502b (lab-pc+)
73
74*/
75
76#undef LABPC_DEBUG
f6b49620 77/* #define LABPC_DEBUG enable debugging messages */
124b13b2 78
25436dc9 79#include <linux/interrupt.h>
5a0e3ad6 80#include <linux/slab.h>
124b13b2
FMH		 81#include "../comedidev.h"
82
83#include <linux/delay.h>
84#include <asm/dma.h>
85
86#include "8253.h"
87#include "8255.h"
88#include "mite.h"
89#include "comedi_fc.h"
90#include "ni_labpc.h"
91
92#define DRV_NAME "ni_labpc"
93
e41a6f6d
SR		 94/* size of io region used by board */
95#define LABPC_SIZE 32
96/* 2 MHz master clock */
97#define LABPC_TIMER_BASE 500
124b13b2
FMH		 98
99/* Registers for the lab-pc+ */
100
f6b49620 101/* write-only registers */
124b13b2
FMH		 102#define COMMAND1_REG 0x0
103#define ADC_GAIN_MASK (0x7 << 4)
104#define ADC_CHAN_BITS(x) ((x) & 0x7)
e41a6f6d
SR		 105/* enables multi channel scans */
106#define ADC_SCAN_EN_BIT 0x80
124b13b2 107#define COMMAND2_REG 0x1
e41a6f6d
SR		 108/* enable pretriggering (used in conjunction with SWTRIG) */
109#define PRETRIG_BIT 0x1
110/* enable paced conversions on external trigger */
111#define HWTRIG_BIT 0x2
112/* enable paced conversions */
113#define SWTRIG_BIT 0x4
114/* use two cascaded counters for pacing */
115#define CASCADE_BIT 0x8
124b13b2
FMH		 116#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
117#define COMMAND3_REG 0x2
e41a6f6d
SR		 118/* enable dma transfers */
119#define DMA_EN_BIT 0x1
120/* enable interrupts for 8255 */
121#define DIO_INTR_EN_BIT 0x2
122/* enable dma terminal count interrupt */
123#define DMATC_INTR_EN_BIT 0x4
124/* enable timer interrupt */
125#define TIMER_INTR_EN_BIT 0x8
126/* enable error interrupt */
127#define ERR_INTR_EN_BIT 0x10
128/* enable fifo not empty interrupt */
129#define ADC_FNE_INTR_EN_BIT 0x20
124b13b2
FMH		 130#define ADC_CONVERT_REG 0x3
131#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
132#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
133#define ADC_CLEAR_REG 0x8
134#define DMATC_CLEAR_REG 0xa
135#define TIMER_CLEAR_REG 0xc
e41a6f6d
SR		 136/* 1200 boards only */
137#define COMMAND6_REG 0xe
138/* select ground or common-mode reference */
139#define ADC_COMMON_BIT 0x1
140/* adc unipolar */
141#define ADC_UNIP_BIT 0x2
142/* dac unipolar */
143#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
144/* enable fifo half full interrupt */
145#define ADC_FHF_INTR_EN_BIT 0x20
146/* enable interrupt on end of hardware count */
147#define A1_INTR_EN_BIT 0x40
148/* scan up from channel zero instead of down to zero */
149#define ADC_SCAN_UP_BIT 0x80
124b13b2 150#define COMMAND4_REG 0xf
e41a6f6d
SR		 151/* enables 'interval' scanning */
152#define INTERVAL_SCAN_EN_BIT 0x1
153/* enables external signal on counter b1 output to trigger scan */
154#define EXT_SCAN_EN_BIT 0x2
155/* chooses direction (output or input) for EXTCONV* line */
156#define EXT_CONVERT_OUT_BIT 0x4
157/* chooses differential inputs for adc (in conjunction with board jumper) */
158#define ADC_DIFF_BIT 0x8
124b13b2 159#define EXT_CONVERT_DISABLE_BIT 0x10
e41a6f6d
SR		 160/* 1200 boards only, calibration stuff */
161#define COMMAND5_REG 0x1c
162/* enable eeprom for write */
163#define EEPROM_WRITE_UNPROTECT_BIT 0x4
164/* enable dithering */
165#define DITHER_EN_BIT 0x8
166/* load calibration dac */
167#define CALDAC_LOAD_BIT 0x10
168/* serial clock - rising edge writes, falling edge reads */
169#define SCLOCK_BIT 0x20
170/* serial data bit for writing to eeprom or calibration dacs */
171#define SDATA_BIT 0x40
172/* enable eeprom for read/write */
173#define EEPROM_EN_BIT 0x80
124b13b2
FMH		 174#define INTERVAL_COUNT_REG 0x1e
175#define INTERVAL_LOAD_REG 0x1f
176#define INTERVAL_LOAD_BITS 0x1
177
f6b49620 178/* read-only registers */
124b13b2 179#define STATUS1_REG 0x0
e41a6f6d
SR		 180/* data is available in fifo */
181#define DATA_AVAIL_BIT 0x1
182/* overrun has occurred */
183#define OVERRUN_BIT 0x2
184/* fifo overflow */
185#define OVERFLOW_BIT 0x4
186/* timer interrupt has occured */
187#define TIMER_BIT 0x8
188/* dma terminal count has occured */
189#define DMATC_BIT 0x10
190/* external trigger has occured */
191#define EXT_TRIG_BIT 0x40
192/* 1200 boards only */
193#define STATUS2_REG 0x1d
194/* programmable eeprom serial output */
195#define EEPROM_OUT_BIT 0x1
196/* counter A1 terminal count */
197#define A1_TC_BIT 0x2
198/* fifo not half full */
199#define FNHF_BIT 0x4
124b13b2
FMH		 200#define ADC_FIFO_REG 0xa
201
202#define DIO_BASE_REG 0x10
203#define COUNTER_A_BASE_REG 0x14
204#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
e41a6f6d
SR		 205/* check modes put conversion pacer output in harmless state (a0 mode 2) */
206#define INIT_A0_BITS 0x14
207/* put hardware conversion counter output in harmless state (a1 mode 0) */
208#define INIT_A1_BITS 0x70
124b13b2
FMH		 209#define COUNTER_B_BASE_REG 0x18
210
814900c9
BP		 211static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it);
212static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
70265d24 213static irqreturn_t labpc_interrupt(int irq, void *d);
814900c9
BP		 214static int labpc_drain_fifo(struct comedi_device *dev);
215static void labpc_drain_dma(struct comedi_device *dev);
216static void handle_isa_dma(struct comedi_device *dev);
217static void labpc_drain_dregs(struct comedi_device *dev);
0a85b6f0
MT		 218static int labpc_ai_cmdtest(struct comedi_device *dev,
219 struct comedi_subdevice *s, struct comedi_cmd *cmd);
814900c9
BP		 220static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
221static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 222 struct comedi_insn *insn, unsigned int *data);
814900c9 223static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 224 struct comedi_insn *insn, unsigned int *data);
814900c9 225static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 226 struct comedi_insn *insn, unsigned int *data);
227static int labpc_calib_read_insn(struct comedi_device *dev,
228 struct comedi_subdevice *s,
229 struct comedi_insn *insn, unsigned int *data);
230static int labpc_calib_write_insn(struct comedi_device *dev,
231 struct comedi_subdevice *s,
232 struct comedi_insn *insn, unsigned int *data);
233static int labpc_eeprom_read_insn(struct comedi_device *dev,
234 struct comedi_subdevice *s,
235 struct comedi_insn *insn, unsigned int *data);
236static int labpc_eeprom_write_insn(struct comedi_device *dev,
237 struct comedi_subdevice *s,
238 struct comedi_insn *insn,
239 unsigned int *data);
ea6d0d4c 240static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd);
814900c9 241static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
124b13b2 242#ifdef CONFIG_COMEDI_PCI
71b5f4f1 243static int labpc_find_device(struct comedi_device *dev, int bus, int slot);
124b13b2
FMH		 244#endif
245static int labpc_dio_mem_callback(int dir, int port, int data,
0a85b6f0 246 unsigned long arg);
814900c9 247static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
0a85b6f0 248 unsigned int num_bits);
814900c9
BP		 249static unsigned int labpc_serial_in(struct comedi_device *dev);
250static unsigned int labpc_eeprom_read(struct comedi_device *dev,
0a85b6f0 251 unsigned int address);
814900c9
BP		 252static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
253static unsigned int labpc_eeprom_write(struct comedi_device *dev,
0a85b6f0
MT		 254 unsigned int address,
255 unsigned int value);
814900c9 256static void write_caldac(struct comedi_device *dev, unsigned int channel,
0a85b6f0 257 unsigned int value);
124b13b2
FMH		 258
259enum scan_mode {
260 MODE_SINGLE_CHAN,
261 MODE_SINGLE_CHAN_INTERVAL,
262 MODE_MULT_CHAN_UP,
263 MODE_MULT_CHAN_DOWN,
264};
265
f6b49620 266/* analog input ranges */
124b13b2 267#define NUM_LABPC_PLUS_AI_RANGES 16
f6b49620 268/* indicates unipolar ranges */
124b13b2
FMH		 269static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
270 0,
271 0,
272 0,
273 0,
274 0,
275 0,
276 0,
277 0,
278 1,
279 1,
280 1,
281 1,
282 1,
283 1,
284 1,
285 1,
286};
287
f6b49620 288/* map range index to gain bits */
124b13b2
FMH		 289static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
290 0x00,
291 0x10,
292 0x20,
293 0x30,
294 0x40,
295 0x50,
296 0x60,
297 0x70,
298 0x00,
299 0x10,
300 0x20,
301 0x30,
302 0x40,
303 0x50,
304 0x60,
305 0x70,
306};
0a85b6f0 307
9ced1de6 308static const struct comedi_lrange range_labpc_plus_ai = {
124b13b2
FMH		 309 NUM_LABPC_PLUS_AI_RANGES,
310 {
0a85b6f0
MT		 311 BIP_RANGE(5),
312 BIP_RANGE(4),
313 BIP_RANGE(2.5),
314 BIP_RANGE(1),
315 BIP_RANGE(0.5),
316 BIP_RANGE(0.25),
317 BIP_RANGE(0.1),
318 BIP_RANGE(0.05),
319 UNI_RANGE(10),
320 UNI_RANGE(8),
321 UNI_RANGE(5),
322 UNI_RANGE(2),
323 UNI_RANGE(1),
324 UNI_RANGE(0.5),
325 UNI_RANGE(0.2),
326 UNI_RANGE(0.1),
327 }
124b13b2
FMH		 328};
329
330#define NUM_LABPC_1200_AI_RANGES 14
f6b49620 331/* indicates unipolar ranges */
124b13b2
FMH		 332const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
333 0,
334 0,
335 0,
336 0,
337 0,
338 0,
339 0,
340 1,
341 1,
342 1,
343 1,
344 1,
345 1,
346 1,
347};
348
f6b49620 349/* map range index to gain bits */
124b13b2
FMH		 350const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
351 0x00,
352 0x20,
353 0x30,
354 0x40,
355 0x50,
356 0x60,
357 0x70,
358 0x00,
359 0x20,
360 0x30,
361 0x40,
362 0x50,
363 0x60,
364 0x70,
365};
0a85b6f0 366
9ced1de6 367const struct comedi_lrange range_labpc_1200_ai = {
124b13b2
FMH		 368 NUM_LABPC_1200_AI_RANGES,
369 {
0a85b6f0
MT		 370 BIP_RANGE(5),
371 BIP_RANGE(2.5),
372 BIP_RANGE(1),
373 BIP_RANGE(0.5),
374 BIP_RANGE(0.25),
375 BIP_RANGE(0.1),
376 BIP_RANGE(0.05),
377 UNI_RANGE(10),
378 UNI_RANGE(5),
379 UNI_RANGE(2),
380 UNI_RANGE(1),
381 UNI_RANGE(0.5),
382 UNI_RANGE(0.2),
383 UNI_RANGE(0.1),
384 }
124b13b2
FMH		 385};
386
f6b49620 387/* analog output ranges */
124b13b2 388#define AO_RANGE_IS_UNIPOLAR 0x1
9ced1de6 389static const struct comedi_lrange range_labpc_ao = {
124b13b2
FMH		 390 2,
391 {
0a85b6f0
MT		 392 BIP_RANGE(5),
393 UNI_RANGE(10),
394 }
124b13b2
FMH		 395};
396
397/* functions that do inb/outb and readb/writeb so we can use
398 * function pointers to decide which to use */
399static inline unsigned int labpc_inb(unsigned long address)
400{
401 return inb(address);
402}
0a85b6f0 403
124b13b2
FMH		 404static inline void labpc_outb(unsigned int byte, unsigned long address)
405{
406 outb(byte, address);
407}
0a85b6f0 408
124b13b2
FMH		 409static inline unsigned int labpc_readb(unsigned long address)
410{
411 return readb((void *)address);
412}
0a85b6f0 413
124b13b2
FMH		 414static inline void labpc_writeb(unsigned int byte, unsigned long address)
415{
416 writeb(byte, (void *)address);
417}
418
9ad00740 419static const struct labpc_board_struct labpc_boards[] = {
124b13b2 420 {
0a85b6f0
MT		 421 .name = "lab-pc-1200",
422 .ai_speed = 10000,
423 .bustype = isa_bustype,
424 .register_layout = labpc_1200_layout,
425 .has_ao = 1,
426 .ai_range_table = &range_labpc_1200_ai,
427 .ai_range_code = labpc_1200_ai_gain_bits,
428 .ai_range_is_unipolar = labpc_1200_is_unipolar,
429 .ai_scan_up = 1,
430 .memory_mapped_io = 0,
431 },
124b13b2 432 {
0a85b6f0
MT		 433 .name = "lab-pc-1200ai",
434 .ai_speed = 10000,
435 .bustype = isa_bustype,
436 .register_layout = labpc_1200_layout,
437 .has_ao = 0,
438 .ai_range_table = &range_labpc_1200_ai,
439 .ai_range_code = labpc_1200_ai_gain_bits,
440 .ai_range_is_unipolar = labpc_1200_is_unipolar,
441 .ai_scan_up = 1,
442 .memory_mapped_io = 0,
443 },
124b13b2 444 {
0a85b6f0
MT		 445 .name = "lab-pc+",
446 .ai_speed = 12000,
447 .bustype = isa_bustype,
448 .register_layout = labpc_plus_layout,
449 .has_ao = 1,
450 .ai_range_table = &range_labpc_plus_ai,
451 .ai_range_code = labpc_plus_ai_gain_bits,
452 .ai_range_is_unipolar = labpc_plus_is_unipolar,
453 .ai_scan_up = 0,
454 .memory_mapped_io = 0,
455 },
124b13b2
FMH		 456#ifdef CONFIG_COMEDI_PCI
457 {
0a85b6f0
MT		 458 .name = "pci-1200",
459 .device_id = 0x161,
460 .ai_speed = 10000,
461 .bustype = pci_bustype,
462 .register_layout = labpc_1200_layout,
463 .has_ao = 1,
464 .ai_range_table = &range_labpc_1200_ai,
465 .ai_range_code = labpc_1200_ai_gain_bits,
466 .ai_range_is_unipolar = labpc_1200_is_unipolar,
467 .ai_scan_up = 1,
468 .memory_mapped_io = 1,
469 },
e41a6f6d 470/* dummy entry so pci board works when comedi_config is passed driver name */
124b13b2 471 {
0a85b6f0
MT		 472 .name = DRV_NAME,
473 .bustype = pci_bustype,
474 },
124b13b2
FMH		 475#endif
476};
477
478/*
479 * Useful for shorthand access to the particular board structure
480 */
9ad00740 481#define thisboard ((struct labpc_board_struct *)dev->board_ptr)
124b13b2 482
e41a6f6d
SR		 483/* size in bytes of dma buffer */
484static const int dma_buffer_size = 0xff00;
485/* 2 bytes per sample */
486static const int sample_size = 2;
124b13b2 487
0a4eb4b6 488#define devpriv ((struct labpc_private *)dev->private)
124b13b2 489
139dfbdf 490static struct comedi_driver driver_labpc = {
124b13b2
FMH		 491 .driver_name = DRV_NAME,
492 .module = THIS_MODULE,
493 .attach = labpc_attach,
494 .detach = labpc_common_detach,
8629efa4 495 .num_names = ARRAY_SIZE(labpc_boards),
124b13b2 496 .board_name = &labpc_boards[0].name,
9ad00740 497 .offset = sizeof(struct labpc_board_struct),
124b13b2
FMH		 498};
499
500#ifdef CONFIG_COMEDI_PCI
501static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
4e40cee9
GKH		 502 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
503 {0}
124b13b2
FMH		 504};
505
506MODULE_DEVICE_TABLE(pci, labpc_pci_table);
507#endif /* CONFIG_COMEDI_PCI */
508
da91b269 509static inline int labpc_counter_load(struct comedi_device *dev,
0a85b6f0
MT		 510 unsigned long base_address,
511 unsigned int counter_number,
512 unsigned int count, unsigned int mode)
124b13b2
FMH		 513{
514 if (thisboard->memory_mapped_io)
515 return i8254_mm_load((void *)base_address, 0, counter_number,
0a85b6f0 516 count, mode);
124b13b2
FMH		 517 else
518 return i8254_load(base_address, 0, counter_number, count, mode);
519}
520
da91b269 521int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
0a85b6f0 522 unsigned int irq, unsigned int dma_chan)
124b13b2 523{
34c43922 524 struct comedi_subdevice *s;
124b13b2
FMH		 525 int i;
526 unsigned long dma_flags, isr_flags;
527 short lsb, msb;
528
88d8ed4b
MD		 529 printk(KERN_ERR "comedi%d: ni_labpc: %s, io 0x%lx", dev->minor,
530 thisboard->name,
0a85b6f0 531 iobase);
412bd046 532 if (irq)
124b13b2 533 printk(", irq %u", irq);
412bd046 534 if (dma_chan)
124b13b2 535 printk(", dma %u", dma_chan);
124b13b2
FMH		 536 printk("\n");
537
538 if (iobase == 0) {
177d4282 539 printk(KERN_ERR "io base address is zero!\n");
124b13b2
FMH		 540 return -EINVAL;
541 }
f6b49620 542 /* request io regions for isa boards */
124b13b2
FMH		 543 if (thisboard->bustype == isa_bustype) {
544 /* check if io addresses are available */
545 if (!request_region(iobase, LABPC_SIZE,
0a85b6f0 546 driver_labpc.driver_name)) {
88d8ed4b 547 printk(KERN_ERR "I/O port conflict\n");
124b13b2
FMH		 548 return -EIO;
549 }
550 }
551 dev->iobase = iobase;
552
553 if (thisboard->memory_mapped_io) {
554 devpriv->read_byte = labpc_readb;
555 devpriv->write_byte = labpc_writeb;
556 } else {
557 devpriv->read_byte = labpc_inb;
558 devpriv->write_byte = labpc_outb;
559 }
e41a6f6d 560 /* initialize board's command registers */
124b13b2
FMH		 561 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
562 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
563 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
564 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
565 if (thisboard->register_layout == labpc_1200_layout) {
566 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 567 dev->iobase + COMMAND5_REG);
124b13b2 568 devpriv->write_byte(devpriv->command6_bits,
0a85b6f0 569 dev->iobase + COMMAND6_REG);
124b13b2
FMH		 570 }
571
572 /* grab our IRQ */
573 if (irq) {
574 isr_flags = 0;
575 if (thisboard->bustype == pci_bustype)
576 isr_flags |= IRQF_SHARED;
5f74ea14 577 if (request_irq(irq, labpc_interrupt, isr_flags,
124b13b2 578 driver_labpc.driver_name, dev)) {
88d8ed4b 579 printk(KERN_ERR "unable to allocate irq %u\n", irq);
124b13b2
FMH		 580 return -EINVAL;
581 }
582 }
583 dev->irq = irq;
584
e41a6f6d 585 /* grab dma channel */
124b13b2 586 if (dma_chan > 3) {
88d8ed4b 587 printk(KERN_ERR " invalid dma channel %u\n", dma_chan);
124b13b2
FMH		 588 return -EINVAL;
589 } else if (dma_chan) {
e41a6f6d 590 /* allocate dma buffer */
124b13b2 591 devpriv->dma_buffer =
0a85b6f0 592 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
124b13b2 593 if (devpriv->dma_buffer == NULL) {
88d8ed4b 594 printk(KERN_ERR " failed to allocate dma buffer\n");
124b13b2
FMH		 595 return -ENOMEM;
596 }
597 if (request_dma(dma_chan, driver_labpc.driver_name)) {
88d8ed4b 598 printk(KERN_ERR " failed to allocate dma channel %u\n",
0a85b6f0 599 dma_chan);
124b13b2
FMH		 600 return -EINVAL;
601 }
602 devpriv->dma_chan = dma_chan;
603 dma_flags = claim_dma_lock();
604 disable_dma(devpriv->dma_chan);
605 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
606 release_dma_lock(dma_flags);
607 }
608
609 dev->board_name = thisboard->name;
610
611 if (alloc_subdevices(dev, 5) < 0)
612 return -ENOMEM;
613
614 /* analog input subdevice */
615 s = dev->subdevices + 0;
616 dev->read_subdev = s;
617 s->type = COMEDI_SUBD_AI;
618 s->subdev_flags =
0a85b6f0 619 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
124b13b2
FMH		 620 s->n_chan = 8;
621 s->len_chanlist = 8;
e41a6f6d 622 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
124b13b2
FMH		 623 s->range_table = thisboard->ai_range_table;
624 s->do_cmd = labpc_ai_cmd;
625 s->do_cmdtest = labpc_ai_cmdtest;
626 s->insn_read = labpc_ai_rinsn;
627 s->cancel = labpc_cancel;
628
629 /* analog output */
630 s = dev->subdevices + 1;
631 if (thisboard->has_ao) {
639b9f1e
SR		 632 /*
633 * Could provide command support, except it only has a
412bd046 634 * one sample hardware buffer for analog output and no
639b9f1e
SR		 635 * underrun flag.
636 */
124b13b2
FMH		 637 s->type = COMEDI_SUBD_AO;
638 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
639 s->n_chan = NUM_AO_CHAN;
f6b49620 640 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
124b13b2
FMH		 641 s->range_table = &range_labpc_ao;
642 s->insn_read = labpc_ao_rinsn;
643 s->insn_write = labpc_ao_winsn;
644 /* initialize analog outputs to a known value */
645 for (i = 0; i < s->n_chan; i++) {
646 devpriv->ao_value[i] = s->maxdata / 2;
647 lsb = devpriv->ao_value[i] & 0xff;
648 msb = (devpriv->ao_value[i] >> 8) & 0xff;
649 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
650 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
651 }
652 } else {
653 s->type = COMEDI_SUBD_UNUSED;
654 }
655
656 /* 8255 dio */
657 s = dev->subdevices + 2;
412bd046 658 /* if board uses io memory we have to give a custom callback
659 * function to the 8255 driver */
124b13b2
FMH		 660 if (thisboard->memory_mapped_io)
661 subdev_8255_init(dev, s, labpc_dio_mem_callback,
0a85b6f0 662 (unsigned long)(dev->iobase + DIO_BASE_REG));
124b13b2
FMH		 663 else
664 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
665
f6b49620 666 /* calibration subdevices for boards that have one */
124b13b2
FMH		 667 s = dev->subdevices + 3;
668 if (thisboard->register_layout == labpc_1200_layout) {
669 s->type = COMEDI_SUBD_CALIB;
670 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
671 s->n_chan = 16;
672 s->maxdata = 0xff;
673 s->insn_read = labpc_calib_read_insn;
674 s->insn_write = labpc_calib_write_insn;
675
676 for (i = 0; i < s->n_chan; i++)
677 write_caldac(dev, i, s->maxdata / 2);
678 } else
679 s->type = COMEDI_SUBD_UNUSED;
680
681 /* EEPROM */
682 s = dev->subdevices + 4;
683 if (thisboard->register_layout == labpc_1200_layout) {
684 s->type = COMEDI_SUBD_MEMORY;
685 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
686 s->n_chan = EEPROM_SIZE;
687 s->maxdata = 0xff;
688 s->insn_read = labpc_eeprom_read_insn;
689 s->insn_write = labpc_eeprom_write_insn;
690
412bd046 691 for (i = 0; i < EEPROM_SIZE; i++)
124b13b2 692 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
124b13b2 693#ifdef LABPC_DEBUG
88d8ed4b 694 printk(KERN_ERR " eeprom:");
412bd046 695 for (i = 0; i < EEPROM_SIZE; i++)
124b13b2 696 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]);
124b13b2
FMH		 697 printk("\n");
698#endif
699 } else
700 s->type = COMEDI_SUBD_UNUSED;
701
702 return 0;
703}
704
da91b269 705static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
124b13b2
FMH		 706{
707 unsigned long iobase = 0;
708 unsigned int irq = 0;
709 unsigned int dma_chan = 0;
710#ifdef CONFIG_COMEDI_PCI
711 int retval;
712#endif
713
714 /* allocate and initialize dev->private */
0a4eb4b6 715 if (alloc_private(dev, sizeof(struct labpc_private)) < 0)
124b13b2
FMH		 716 return -ENOMEM;
717
e41a6f6d 718 /* get base address, irq etc. based on bustype */
124b13b2
FMH		 719 switch (thisboard->bustype) {
720 case isa_bustype:
721 iobase = it->options[0];
722 irq = it->options[1];
723 dma_chan = it->options[2];
724 break;
725 case pci_bustype:
726#ifdef CONFIG_COMEDI_PCI
727 retval = labpc_find_device(dev, it->options[0], it->options[1]);
412bd046 728 if (retval < 0)
124b13b2 729 return retval;
124b13b2
FMH		 730 retval = mite_setup(devpriv->mite);
731 if (retval < 0)
732 return retval;
733 iobase = (unsigned long)devpriv->mite->daq_io_addr;
734 irq = mite_irq(devpriv->mite);
735#else
88d8ed4b
MD		 736 printk(KERN_ERR " this driver has not been built with PCI "
737 "support.\n");
124b13b2
FMH		 738 return -EINVAL;
739#endif
740 break;
741 case pcmcia_bustype:
0a85b6f0
MT		 742 printk
743 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n");
124b13b2
FMH		 744 return -EINVAL;
745 break;
746 default:
88d8ed4b 747 printk(KERN_ERR "bug! couldn't determine board type\n");
124b13b2
FMH		 748 return -EINVAL;
749 break;
750 }
751
752 return labpc_common_attach(dev, iobase, irq, dma_chan);
753}
754
f6b49620 755/* adapted from ni_pcimio for finding mite based boards (pc-1200) */
124b13b2 756#ifdef CONFIG_COMEDI_PCI
71b5f4f1 757static int labpc_find_device(struct comedi_device *dev, int bus, int slot)
124b13b2
FMH		 758{
759 struct mite_struct *mite;
760 int i;
761 for (mite = mite_devices; mite; mite = mite->next) {
762 if (mite->used)
763 continue;
e41a6f6d 764/* if bus/slot are specified then make sure we have the right bus/slot */
124b13b2
FMH		 765 if (bus || slot) {
766 if (bus != mite->pcidev->bus->number
0a85b6f0 767 || slot != PCI_SLOT(mite->pcidev->devfn))
124b13b2
FMH		 768 continue;
769 }
770 for (i = 0; i < driver_labpc.num_names; i++) {
771 if (labpc_boards[i].bustype != pci_bustype)
772 continue;
773 if (mite_device_id(mite) == labpc_boards[i].device_id) {
774 devpriv->mite = mite;
e41a6f6d 775/* fixup board pointer, in case we were using the dummy "ni_labpc" entry */
124b13b2
FMH		 776 dev->board_ptr = &labpc_boards[i];
777 return 0;
778 }
779 }
780 }
88d8ed4b 781 printk(KERN_ERR "no device found\n");
124b13b2
FMH		 782 mite_list_devices();
783 return -EIO;
784}
785#endif
786
da91b269 787int labpc_common_detach(struct comedi_device *dev)
124b13b2 788{
88d8ed4b 789 printk(KERN_ERR "comedi%d: ni_labpc: detach\n", dev->minor);
124b13b2
FMH		 790
791 if (dev->subdevices)
792 subdev_8255_cleanup(dev, dev->subdevices + 2);
793
794 /* only free stuff if it has been allocated by _attach */
795 if (devpriv->dma_buffer)
796 kfree(devpriv->dma_buffer);
797 if (devpriv->dma_chan)
798 free_dma(devpriv->dma_chan);
799 if (dev->irq)
5f74ea14 800 free_irq(dev->irq, dev);
124b13b2
FMH		 801 if (thisboard->bustype == isa_bustype && dev->iobase)
802 release_region(dev->iobase, LABPC_SIZE);
803#ifdef CONFIG_COMEDI_PCI
804 if (devpriv->mite)
805 mite_unsetup(devpriv->mite);
806#endif
807
808 return 0;
809};
810
da91b269 811static void labpc_clear_adc_fifo(const struct comedi_device *dev)
124b13b2
FMH		 812{
813 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
814 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
815 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
816}
817
da91b269 818static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
124b13b2
FMH		 819{
820 unsigned long flags;
821
5f74ea14 822 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 823 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
824 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 825 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2
FMH		 826
827 devpriv->command3_bits = 0;
828 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
829
830 return 0;
831}
832
da91b269 833static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
124b13b2
FMH		 834{
835 if (cmd->chanlist_len == 1)
836 return MODE_SINGLE_CHAN;
837
838 /* chanlist may be NULL during cmdtest. */
839 if (cmd->chanlist == NULL)
840 return MODE_MULT_CHAN_UP;
841
842 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
843 return MODE_SINGLE_CHAN_INTERVAL;
844
845 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
846 return MODE_MULT_CHAN_UP;
847
848 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
849 return MODE_MULT_CHAN_DOWN;
850
88d8ed4b 851 printk(KERN_ERR "ni_labpc: bug! this should never happen\n");
124b13b2
FMH		 852
853 return 0;
854}
855
da91b269 856static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
0a85b6f0 857 const struct comedi_cmd *cmd)
124b13b2
FMH		 858{
859 int mode, channel, range, aref, i;
860
861 if (cmd->chanlist == NULL)
862 return 0;
863
864 mode = labpc_ai_scan_mode(cmd);
865
866 if (mode == MODE_SINGLE_CHAN)
867 return 0;
868
869 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
870 if (cmd->chanlist_len > 0xff) {
871 comedi_error(dev,
0a85b6f0 872 "ni_labpc: chanlist too long for single channel interval mode\n");
124b13b2
FMH		 873 return 1;
874 }
875 }
876
877 channel = CR_CHAN(cmd->chanlist[0]);
878 range = CR_RANGE(cmd->chanlist[0]);
879 aref = CR_AREF(cmd->chanlist[0]);
880
881 for (i = 0; i < cmd->chanlist_len; i++) {
882
883 switch (mode) {
884 case MODE_SINGLE_CHAN_INTERVAL:
885 if (CR_CHAN(cmd->chanlist[i]) != channel) {
886 comedi_error(dev,
0a85b6f0 887 "channel scanning order specified in chanlist is not supported by hardware.\n");
124b13b2
FMH		 888 return 1;
889 }
890 break;
891 case MODE_MULT_CHAN_UP:
892 if (CR_CHAN(cmd->chanlist[i]) != i) {
893 comedi_error(dev,
0a85b6f0 894 "channel scanning order specified in chanlist is not supported by hardware.\n");
124b13b2
FMH		 895 return 1;
896 }
897 break;
898 case MODE_MULT_CHAN_DOWN:
899 if (CR_CHAN(cmd->chanlist[i]) !=
0a85b6f0 900 cmd->chanlist_len - i - 1) {
124b13b2 901 comedi_error(dev,
0a85b6f0 902 "channel scanning order specified in chanlist is not supported by hardware.\n");
124b13b2
FMH		 903 return 1;
904 }
905 break;
906 default:
88d8ed4b 907 printk(KERN_ERR "ni_labpc: bug! in chanlist check\n");
124b13b2
FMH		 908 return 1;
909 break;
910 }
911
912 if (CR_RANGE(cmd->chanlist[i]) != range) {
913 comedi_error(dev,
0a85b6f0 914 "entries in chanlist must all have the same range\n");
124b13b2
FMH		 915 return 1;
916 }
917
918 if (CR_AREF(cmd->chanlist[i]) != aref) {
919 comedi_error(dev,
0a85b6f0 920 "entries in chanlist must all have the same reference\n");
124b13b2
FMH		 921 return 1;
922 }
923 }
924
925 return 0;
926}
927
da91b269 928static int labpc_use_continuous_mode(const struct comedi_cmd *cmd)
124b13b2
FMH		 929{
930 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
931 return 1;
932
933 if (cmd->scan_begin_src == TRIG_FOLLOW)
934 return 1;
935
936 return 0;
937}
938
da91b269 939static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd)
124b13b2
FMH		 940{
941 if (cmd->convert_src != TRIG_TIMER)
942 return 0;
943
944 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
0a85b6f0 945 cmd->scan_begin_src == TRIG_TIMER)
124b13b2
FMH		 946 return cmd->scan_begin_arg;
947
948 return cmd->convert_arg;
949}
950
da91b269 951static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns)
124b13b2
FMH		 952{
953 if (cmd->convert_src != TRIG_TIMER)
954 return;
955
956 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
0a85b6f0 957 cmd->scan_begin_src == TRIG_TIMER) {
124b13b2
FMH		 958 cmd->scan_begin_arg = ns;
959 if (cmd->convert_arg > cmd->scan_begin_arg)
960 cmd->convert_arg = cmd->scan_begin_arg;
961 } else
962 cmd->convert_arg = ns;
963}
964
da91b269 965static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd)
124b13b2
FMH		 966{
967 if (cmd->scan_begin_src != TRIG_TIMER)
968 return 0;
969
970 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
0a85b6f0 971 cmd->convert_src == TRIG_TIMER)
124b13b2
FMH		 972 return 0;
973
974 return cmd->scan_begin_arg;
975}
976
da91b269 977static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns)
124b13b2
FMH		 978{
979 if (cmd->scan_begin_src != TRIG_TIMER)
980 return;
981
982 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
0a85b6f0 983 cmd->convert_src == TRIG_TIMER)
124b13b2
FMH		 984 return;
985
986 cmd->scan_begin_arg = ns;
987}
988
0a85b6f0
MT		 989static int labpc_ai_cmdtest(struct comedi_device *dev,
990 struct comedi_subdevice *s, struct comedi_cmd *cmd)
124b13b2
FMH		 991{
992 int err = 0;
993 int tmp, tmp2;
994 int stop_mask;
995
996 /* step 1: make sure trigger sources are trivially valid */
997
998 tmp = cmd->start_src;
999 cmd->start_src &= TRIG_NOW | TRIG_EXT;
1000 if (!cmd->start_src || tmp != cmd->start_src)
1001 err++;
1002
1003 tmp = cmd->scan_begin_src;
1004 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
1005 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1006 err++;
1007
1008 tmp = cmd->convert_src;
1009 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1010 if (!cmd->convert_src || tmp != cmd->convert_src)
1011 err++;
1012
1013 tmp = cmd->scan_end_src;
1014 cmd->scan_end_src &= TRIG_COUNT;
1015 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1016 err++;
1017
1018 tmp = cmd->stop_src;
1019 stop_mask = TRIG_COUNT | TRIG_NONE;
1020 if (thisboard->register_layout == labpc_1200_layout)
1021 stop_mask |= TRIG_EXT;
1022 cmd->stop_src &= stop_mask;
1023 if (!cmd->stop_src || tmp != cmd->stop_src)
1024 err++;
1025
1026 if (err)
1027 return 1;
1028
1029 /* step 2: make sure trigger sources are unique and mutually compatible */
1030
1031 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
1032 err++;
1033 if (cmd->scan_begin_src != TRIG_TIMER &&
0a85b6f0
MT		 1034 cmd->scan_begin_src != TRIG_FOLLOW &&
1035 cmd->scan_begin_src != TRIG_EXT)
124b13b2
FMH		 1036 err++;
1037 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1038 err++;
1039 if (cmd->stop_src != TRIG_COUNT &&
0a85b6f0 1040 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
124b13b2
FMH		 1041 err++;
1042
e41a6f6d 1043 /* can't have external stop and start triggers at once */
124b13b2
FMH		 1044 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1045 err++;
1046
1047 if (err)
1048 return 2;
1049
1050 /* step 3: make sure arguments are trivially compatible */
1051
1052 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
1053 cmd->start_arg = 0;
1054 err++;
1055 }
1056
412bd046 1057 if (!cmd->chanlist_len)
124b13b2 1058 err++;
412bd046 1059
124b13b2
FMH		 1060 if (cmd->scan_end_arg != cmd->chanlist_len) {
1061 cmd->scan_end_arg = cmd->chanlist_len;
1062 err++;
1063 }
1064
1065 if (cmd->convert_src == TRIG_TIMER) {
1066 if (cmd->convert_arg < thisboard->ai_speed) {
1067 cmd->convert_arg = thisboard->ai_speed;
1068 err++;
1069 }
1070 }
e41a6f6d 1071 /* make sure scan timing is not too fast */
124b13b2
FMH		 1072 if (cmd->scan_begin_src == TRIG_TIMER) {
1073 if (cmd->convert_src == TRIG_TIMER &&
0a85b6f0
MT		 1074 cmd->scan_begin_arg <
1075 cmd->convert_arg * cmd->chanlist_len) {
124b13b2 1076 cmd->scan_begin_arg =
0a85b6f0 1077 cmd->convert_arg * cmd->chanlist_len;
124b13b2
FMH		 1078 err++;
1079 }
1080 if (cmd->scan_begin_arg <
0a85b6f0 1081 thisboard->ai_speed * cmd->chanlist_len) {
124b13b2 1082 cmd->scan_begin_arg =
0a85b6f0 1083 thisboard->ai_speed * cmd->chanlist_len;
124b13b2
FMH		 1084 err++;
1085 }
1086 }
e41a6f6d 1087 /* stop source */
124b13b2
FMH		 1088 switch (cmd->stop_src) {
1089 case TRIG_COUNT:
1090 if (!cmd->stop_arg) {
1091 cmd->stop_arg = 1;
1092 err++;
1093 }
1094 break;
1095 case TRIG_NONE:
1096 if (cmd->stop_arg != 0) {
1097 cmd->stop_arg = 0;
1098 err++;
1099 }
1100 break;
f6b49620 1101 /* TRIG_EXT doesn't care since it doesn't trigger off a numbered channel */
124b13b2
FMH		 1102 default:
1103 break;
1104 }
1105
1106 if (err)
1107 return 3;
1108
1109 /* step 4: fix up any arguments */
1110
1111 tmp = cmd->convert_arg;
1112 tmp2 = cmd->scan_begin_arg;
1113 labpc_adc_timing(dev, cmd);
1114 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1115 err++;
1116
1117 if (err)
1118 return 4;
1119
1120 if (labpc_ai_chanlist_invalid(dev, cmd))
1121 return 5;
1122
1123 return 0;
1124}
1125
da91b269 1126static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
124b13b2
FMH		 1127{
1128 int channel, range, aref;
1129 unsigned long irq_flags;
1130 int ret;
d163679c 1131 struct comedi_async *async = s->async;
ea6d0d4c 1132 struct comedi_cmd *cmd = &async->cmd;
124b13b2
FMH		 1133 enum transfer_type xfer;
1134 unsigned long flags;
1135
1136 if (!dev->irq) {
1137 comedi_error(dev, "no irq assigned, cannot perform command");
1138 return -1;
1139 }
1140
1141 range = CR_RANGE(cmd->chanlist[0]);
1142 aref = CR_AREF(cmd->chanlist[0]);
1143
e41a6f6d 1144 /* make sure board is disabled before setting up aquisition */
5f74ea14 1145 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 1146 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1147 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 1148 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2
FMH		 1149
1150 devpriv->command3_bits = 0;
1151 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1152
f6b49620 1153 /* initialize software conversion count */
412bd046 1154 if (cmd->stop_src == TRIG_COUNT)
124b13b2 1155 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
65d6d26c 1156
f6b49620 1157 /* setup hardware conversion counter */
124b13b2 1158 if (cmd->stop_src == TRIG_EXT) {
f6b49620 1159 /* load counter a1 with count of 3 (pc+ manual says this is minimum allowed) using mode 0 */
124b13b2 1160 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
0a85b6f0 1161 1, 3, 0);
124b13b2
FMH		 1162 if (ret < 0) {
1163 comedi_error(dev, "error loading counter a1");
1164 return -1;
1165 }
f6b49620 1166 } else /* otherwise, just put a1 in mode 0 with no count to set its output low */
124b13b2 1167 devpriv->write_byte(INIT_A1_BITS,
0a85b6f0 1168 dev->iobase + COUNTER_A_CONTROL_REG);
124b13b2 1169
f6b49620
BP		 1170 /* figure out what method we will use to transfer data */
1171 if (devpriv->dma_chan && /* need a dma channel allocated */
0a85b6f0
MT		 1172 /* dma unsafe at RT priority, and too much setup time for TRIG_WAKE_EOS for */
1173 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1174 /* only available on the isa boards */
1175 thisboard->bustype == isa_bustype) {
124b13b2 1176 xfer = isa_dma_transfer;
f6b49620 1177 } else if (thisboard->register_layout == labpc_1200_layout && /* pc-plus has no fifo-half full interrupt */
0a85b6f0
MT		 1178 /* wake-end-of-scan should interrupt on fifo not empty */
1179 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1180 /* make sure we are taking more than just a few points */
1181 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
124b13b2
FMH		 1182 xfer = fifo_half_full_transfer;
1183 } else
1184 xfer = fifo_not_empty_transfer;
1185 devpriv->current_transfer = xfer;
1186
f6b49620 1187 /* setup command6 register for 1200 boards */
124b13b2 1188 if (thisboard->register_layout == labpc_1200_layout) {
f6b49620 1189 /* reference inputs to ground or common? */
124b13b2
FMH		 1190 if (aref != AREF_GROUND)
1191 devpriv->command6_bits |= ADC_COMMON_BIT;
1192 else
1193 devpriv->command6_bits &= ~ADC_COMMON_BIT;
f6b49620 1194 /* bipolar or unipolar range? */
124b13b2
FMH		 1195 if (thisboard->ai_range_is_unipolar[range])
1196 devpriv->command6_bits |= ADC_UNIP_BIT;
1197 else
1198 devpriv->command6_bits &= ~ADC_UNIP_BIT;
f6b49620 1199 /* interrupt on fifo half full? */
124b13b2
FMH		 1200 if (xfer == fifo_half_full_transfer)
1201 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1202 else
1203 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
f6b49620 1204 /* enable interrupt on counter a1 terminal count? */
124b13b2
FMH		 1205 if (cmd->stop_src == TRIG_EXT)
1206 devpriv->command6_bits |= A1_INTR_EN_BIT;
1207 else
1208 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
f6b49620 1209 /* are we scanning up or down through channels? */
124b13b2
FMH		 1210 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1211 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1212 else
1213 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
f6b49620 1214 /* write to register */
124b13b2 1215 devpriv->write_byte(devpriv->command6_bits,
0a85b6f0 1216 dev->iobase + COMMAND6_REG);
124b13b2
FMH		 1217 }
1218
1219 /* setup channel list, etc (command1 register) */
1220 devpriv->command1_bits = 0;
1221 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1222 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1223 else
1224 channel = CR_CHAN(cmd->chanlist[0]);
e41a6f6d 1225 /* munge channel bits for differential / scan disabled mode */
124b13b2
FMH		 1226 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1227 channel *= 2;
1228 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1229 devpriv->command1_bits |= thisboard->ai_range_code[range];
1230 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
e41a6f6d 1231 /* manual says to set scan enable bit on second pass */
124b13b2 1232 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
0a85b6f0 1233 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
124b13b2 1234 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
e41a6f6d
SR		 1235 /* need a brief delay before enabling scan, or scan
1236 * list will get screwed when you switch
124b13b2 1237 * between scan up to scan down mode - dunno why */
5f74ea14 1238 udelay(1);
124b13b2 1239 devpriv->write_byte(devpriv->command1_bits,
0a85b6f0 1240 dev->iobase + COMMAND1_REG);
124b13b2 1241 }
f6b49620 1242 /* setup any external triggering/pacing (command4 register) */
124b13b2
FMH		 1243 devpriv->command4_bits = 0;
1244 if (cmd->convert_src != TRIG_EXT)
1245 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1246 /* XXX should discard first scan when using interval scanning
1247 * since manual says it is not synced with scan clock */
1248 if (labpc_use_continuous_mode(cmd) == 0) {
1249 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1250 if (cmd->scan_begin_src == TRIG_EXT)
1251 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1252 }
f6b49620 1253 /* single-ended/differential */
124b13b2
FMH		 1254 if (aref == AREF_DIFF)
1255 devpriv->command4_bits |= ADC_DIFF_BIT;
1256 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1257
1258 devpriv->write_byte(cmd->chanlist_len,
0a85b6f0 1259 dev->iobase + INTERVAL_COUNT_REG);
f6b49620 1260 /* load count */
124b13b2 1261 devpriv->write_byte(INTERVAL_LOAD_BITS,
0a85b6f0 1262 dev->iobase + INTERVAL_LOAD_REG);
124b13b2
FMH		 1263
1264 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
f6b49620 1265 /* set up pacing */
124b13b2 1266 labpc_adc_timing(dev, cmd);
f6b49620 1267 /* load counter b0 in mode 3 */
124b13b2 1268 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
0a85b6f0 1269 0, devpriv->divisor_b0, 3);
124b13b2
FMH		 1270 if (ret < 0) {
1271 comedi_error(dev, "error loading counter b0");
1272 return -1;
1273 }
1274 }
f6b49620 1275 /* set up conversion pacing */
124b13b2 1276 if (labpc_ai_convert_period(cmd)) {
f6b49620 1277 /* load counter a0 in mode 2 */
124b13b2 1278 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
0a85b6f0 1279 0, devpriv->divisor_a0, 2);
124b13b2
FMH		 1280 if (ret < 0) {
1281 comedi_error(dev, "error loading counter a0");
1282 return -1;
1283 }
1284 } else
1285 devpriv->write_byte(INIT_A0_BITS,
0a85b6f0 1286 dev->iobase + COUNTER_A_CONTROL_REG);
124b13b2 1287
f6b49620 1288 /* set up scan pacing */
124b13b2 1289 if (labpc_ai_scan_period(cmd)) {
f6b49620 1290 /* load counter b1 in mode 2 */
124b13b2 1291 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
0a85b6f0 1292 1, devpriv->divisor_b1, 2);
124b13b2
FMH		 1293 if (ret < 0) {
1294 comedi_error(dev, "error loading counter b1");
1295 return -1;
1296 }
1297 }
1298
1299 labpc_clear_adc_fifo(dev);
1300
f6b49620 1301 /* set up dma transfer */
124b13b2
FMH		 1302 if (xfer == isa_dma_transfer) {
1303 irq_flags = claim_dma_lock();
1304 disable_dma(devpriv->dma_chan);
1305 /* clear flip-flop to make sure 2-byte registers for
1306 * count and address get set correctly */
1307 clear_dma_ff(devpriv->dma_chan);
1308 set_dma_addr(devpriv->dma_chan,
0a85b6f0 1309 virt_to_bus(devpriv->dma_buffer));
f6b49620 1310 /* set appropriate size of transfer */
124b13b2
FMH		 1311 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1312 if (cmd->stop_src == TRIG_COUNT &&
0a85b6f0 1313 devpriv->count * sample_size < devpriv->dma_transfer_size) {
124b13b2 1314 devpriv->dma_transfer_size =
0a85b6f0 1315 devpriv->count * sample_size;
124b13b2
FMH		 1316 }
1317 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1318 enable_dma(devpriv->dma_chan);
1319 release_dma_lock(irq_flags);
f6b49620 1320 /* enable board's dma */
124b13b2
FMH		 1321 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1322 } else
1323 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1324
f6b49620 1325 /* enable error interrupts */
124b13b2 1326 devpriv->command3_bits |= ERR_INTR_EN_BIT;
f6b49620 1327 /* enable fifo not empty interrupt? */
124b13b2
FMH		 1328 if (xfer == fifo_not_empty_transfer)
1329 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1330 else
1331 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1332 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1333
f6b49620 1334 /* startup aquisition */
124b13b2 1335
f6b49620
BP		 1336 /* command2 reg */
1337 /* use 2 cascaded counters for pacing */
5f74ea14 1338 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 1339 devpriv->command2_bits |= CASCADE_BIT;
1340 switch (cmd->start_src) {
1341 case TRIG_EXT:
1342 devpriv->command2_bits |= HWTRIG_BIT;
1343 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1344 break;
1345 case TRIG_NOW:
1346 devpriv->command2_bits |= SWTRIG_BIT;
1347 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1348 break;
1349 default:
1350 comedi_error(dev, "bug with start_src");
1351 return -1;
1352 break;
1353 }
1354 switch (cmd->stop_src) {
1355 case TRIG_EXT:
1356 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1357 break;
1358 case TRIG_COUNT:
1359 case TRIG_NONE:
1360 break;
1361 default:
1362 comedi_error(dev, "bug with stop_src");
1363 return -1;
1364 }
1365 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 1366 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2
FMH		 1367
1368 return 0;
1369}
1370
1371/* interrupt service routine */
70265d24 1372static irqreturn_t labpc_interrupt(int irq, void *d)
124b13b2 1373{
71b5f4f1 1374 struct comedi_device *dev = d;
34c43922 1375 struct comedi_subdevice *s = dev->read_subdev;
d163679c 1376 struct comedi_async *async;
ea6d0d4c 1377 struct comedi_cmd *cmd;
124b13b2
FMH		 1378
1379 if (dev->attached == 0) {
1380 comedi_error(dev, "premature interrupt");
1381 return IRQ_HANDLED;
1382 }
1383
1384 async = s->async;
1385 cmd = &async->cmd;
1386 async->events = 0;
1387
e41a6f6d 1388 /* read board status */
124b13b2
FMH		 1389 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1390 if (thisboard->register_layout == labpc_1200_layout)
1391 devpriv->status2_bits =
0a85b6f0 1392 devpriv->read_byte(dev->iobase + STATUS2_REG);
124b13b2
FMH		 1393
1394 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
0a85b6f0
MT		 1395 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1396 && (devpriv->status2_bits & A1_TC_BIT) == 0
1397 && (devpriv->status2_bits & FNHF_BIT)) {
124b13b2
FMH		 1398 return IRQ_NONE;
1399 }
1400
1401 if (devpriv->status1_bits & OVERRUN_BIT) {
e41a6f6d 1402 /* clear error interrupt */
124b13b2
FMH		 1403 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1404 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1405 comedi_event(dev, s);
1406 comedi_error(dev, "overrun");
1407 return IRQ_HANDLED;
1408 }
1409
1410 if (devpriv->current_transfer == isa_dma_transfer) {
639b9f1e
SR		 1411 /*
1412 * if a dma terminal count of external stop trigger
1413 * has occurred
1414 */
124b13b2 1415 if (devpriv->status1_bits & DMATC_BIT ||
0a85b6f0
MT		 1416 (thisboard->register_layout == labpc_1200_layout
1417 && devpriv->status2_bits & A1_TC_BIT)) {
124b13b2
FMH		 1418 handle_isa_dma(dev);
1419 }
1420 } else
1421 labpc_drain_fifo(dev);
1422
1423 if (devpriv->status1_bits & TIMER_BIT) {
1424 comedi_error(dev, "handled timer interrupt?");
f6b49620 1425 /* clear it */
124b13b2
FMH		 1426 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1427 }
1428
1429 if (devpriv->status1_bits & OVERFLOW_BIT) {
f6b49620 1430 /* clear error interrupt */
124b13b2
FMH		 1431 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1432 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1433 comedi_event(dev, s);
1434 comedi_error(dev, "overflow");
1435 return IRQ_HANDLED;
1436 }
f6b49620 1437 /* handle external stop trigger */
124b13b2
FMH		 1438 if (cmd->stop_src == TRIG_EXT) {
1439 if (devpriv->status2_bits & A1_TC_BIT) {
1440 labpc_drain_dregs(dev);
1441 labpc_cancel(dev, s);
1442 async->events |= COMEDI_CB_EOA;
1443 }
1444 }
1445
1446 /* TRIG_COUNT end of acquisition */
1447 if (cmd->stop_src == TRIG_COUNT) {
1448 if (devpriv->count == 0) {
1449 labpc_cancel(dev, s);
1450 async->events |= COMEDI_CB_EOA;
1451 }
1452 }
1453
1454 comedi_event(dev, s);
1455 return IRQ_HANDLED;
1456}
1457
f6b49620 1458/* read all available samples from ai fifo */
da91b269 1459static int labpc_drain_fifo(struct comedi_device *dev)
124b13b2
FMH		 1460{
1461 unsigned int lsb, msb;
790c5541 1462 short data;
d163679c 1463 struct comedi_async *async = dev->read_subdev->async;
124b13b2
FMH		 1464 const int timeout = 10000;
1465 unsigned int i;
1466
1467 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1468
1469 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
0a85b6f0 1470 i++) {
f6b49620 1471 /* quit if we have all the data we want */
124b13b2
FMH		 1472 if (async->cmd.stop_src == TRIG_COUNT) {
1473 if (devpriv->count == 0)
1474 break;
1475 devpriv->count--;
1476 }
1477 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1478 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1479 data = (msb << 8) | lsb;
1480 cfc_write_to_buffer(dev->read_subdev, data);
1481 devpriv->status1_bits =
0a85b6f0 1482 devpriv->read_byte(dev->iobase + STATUS1_REG);
124b13b2
FMH		 1483 }
1484 if (i == timeout) {
1485 comedi_error(dev, "ai timeout, fifo never empties");
1486 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1487 return -1;
1488 }
1489
1490 return 0;
1491}
1492
da91b269 1493static void labpc_drain_dma(struct comedi_device *dev)
124b13b2 1494{
34c43922 1495 struct comedi_subdevice *s = dev->read_subdev;
d163679c 1496 struct comedi_async *async = s->async;
124b13b2
FMH		 1497 int status;
1498 unsigned long flags;
1499 unsigned int max_points, num_points, residue, leftover;
1500 int i;
1501
1502 status = devpriv->status1_bits;
1503
1504 flags = claim_dma_lock();
1505 disable_dma(devpriv->dma_chan);
1506 /* clear flip-flop to make sure 2-byte registers for
1507 * count and address get set correctly */
1508 clear_dma_ff(devpriv->dma_chan);
1509
f6b49620 1510 /* figure out how many points to read */
124b13b2
FMH		 1511 max_points = devpriv->dma_transfer_size / sample_size;
1512 /* residue is the number of points left to be done on the dma
1513 * transfer. It should always be zero at this point unless
1514 * the stop_src is set to external triggering.
1515 */
1516 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1517 num_points = max_points - residue;
1518 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1519 num_points = devpriv->count;
1520
f6b49620 1521 /* figure out how many points will be stored next time */
124b13b2
FMH		 1522 leftover = 0;
1523 if (async->cmd.stop_src != TRIG_COUNT) {
1524 leftover = devpriv->dma_transfer_size / sample_size;
1525 } else if (devpriv->count > num_points) {
1526 leftover = devpriv->count - num_points;
1527 if (leftover > max_points)
1528 leftover = max_points;
1529 }
1530
1531 /* write data to comedi buffer */
412bd046 1532 for (i = 0; i < num_points; i++)
124b13b2 1533 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
65d6d26c 1534
124b13b2
FMH		 1535 if (async->cmd.stop_src == TRIG_COUNT)
1536 devpriv->count -= num_points;
1537
f6b49620 1538 /* set address and count for next transfer */
124b13b2
FMH		 1539 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1540 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1541 release_dma_lock(flags);
1542
1543 async->events |= COMEDI_CB_BLOCK;
1544}
1545
da91b269 1546static void handle_isa_dma(struct comedi_device *dev)
124b13b2
FMH		 1547{
1548 labpc_drain_dma(dev);
1549
1550 enable_dma(devpriv->dma_chan);
1551
f6b49620 1552 /* clear dma tc interrupt */
124b13b2
FMH		 1553 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1554}
1555
9d220c6b 1556/* makes sure all data acquired by board is transfered to comedi (used
124b13b2 1557 * when aquisition is terminated by stop_src == TRIG_EXT). */
da91b269 1558static void labpc_drain_dregs(struct comedi_device *dev)
124b13b2
FMH		 1559{
1560 if (devpriv->current_transfer == isa_dma_transfer)
1561 labpc_drain_dma(dev);
1562
1563 labpc_drain_fifo(dev);
1564}
1565
da91b269 1566static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 1567 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1568{
1569 int i, n;
1570 int chan, range;
1571 int lsb, msb;
1572 int timeout = 1000;
1573 unsigned long flags;
1574
f6b49620 1575 /* disable timed conversions */
5f74ea14 1576 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 1577 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1578 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 1579 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2 1580
f6b49620 1581 /* disable interrupt generation and dma */
124b13b2
FMH		 1582 devpriv->command3_bits = 0;
1583 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1584
1585 /* set gain and channel */
1586 devpriv->command1_bits = 0;
1587 chan = CR_CHAN(insn->chanspec);
1588 range = CR_RANGE(insn->chanspec);
1589 devpriv->command1_bits |= thisboard->ai_range_code[range];
e41a6f6d 1590 /* munge channel bits for differential/scan disabled mode */
124b13b2
FMH		 1591 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1592 chan *= 2;
1593 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1594 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1595
e41a6f6d 1596 /* setup command6 register for 1200 boards */
124b13b2 1597 if (thisboard->register_layout == labpc_1200_layout) {
f6b49620 1598 /* reference inputs to ground or common? */
124b13b2
FMH		 1599 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1600 devpriv->command6_bits |= ADC_COMMON_BIT;
1601 else
1602 devpriv->command6_bits &= ~ADC_COMMON_BIT;
e41a6f6d 1603 /* bipolar or unipolar range? */
124b13b2
FMH		 1604 if (thisboard->ai_range_is_unipolar[range])
1605 devpriv->command6_bits |= ADC_UNIP_BIT;
1606 else
1607 devpriv->command6_bits &= ~ADC_UNIP_BIT;
e41a6f6d 1608 /* don't interrupt on fifo half full */
124b13b2 1609 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
e41a6f6d 1610 /* don't enable interrupt on counter a1 terminal count? */
124b13b2 1611 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
e41a6f6d 1612 /* write to register */
124b13b2 1613 devpriv->write_byte(devpriv->command6_bits,
0a85b6f0 1614 dev->iobase + COMMAND6_REG);
124b13b2 1615 }
e41a6f6d 1616 /* setup command4 register */
124b13b2
FMH		 1617 devpriv->command4_bits = 0;
1618 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
e41a6f6d 1619 /* single-ended/differential */
124b13b2
FMH		 1620 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1621 devpriv->command4_bits |= ADC_DIFF_BIT;
1622 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1623
e41a6f6d 1624 /* initialize pacer counter output to make sure it doesn't cause any problems */
124b13b2
FMH		 1625 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1626
1627 labpc_clear_adc_fifo(dev);
1628
1629 for (n = 0; n < insn->n; n++) {
1630 /* trigger conversion */
1631 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1632
1633 for (i = 0; i < timeout; i++) {
1634 if (devpriv->read_byte(dev->iobase +
0a85b6f0 1635 STATUS1_REG) & DATA_AVAIL_BIT)
124b13b2 1636 break;
5f74ea14 1637 udelay(1);
124b13b2
FMH		 1638 }
1639 if (i == timeout) {
1640 comedi_error(dev, "timeout");
1641 return -ETIME;
1642 }
1643 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1644 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1645 data[n] = (msb << 8) | lsb;
1646 }
1647
1648 return n;
1649}
1650
f6b49620 1651/* analog output insn */
da91b269 1652static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 1653 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1654{
1655 int channel, range;
1656 unsigned long flags;
1657 int lsb, msb;
1658
1659 channel = CR_CHAN(insn->chanspec);
1660
e41a6f6d 1661 /* turn off pacing of analog output channel */
124b13b2
FMH		 1662 /* note: hardware bug in daqcard-1200 means pacing cannot
1663 * be independently enabled/disabled for its the two channels */
5f74ea14 1664 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 1665 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1666 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 1667 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2 1668
e41a6f6d 1669 /* set range */
124b13b2
FMH		 1670 if (thisboard->register_layout == labpc_1200_layout) {
1671 range = CR_RANGE(insn->chanspec);
1672 if (range & AO_RANGE_IS_UNIPOLAR)
1673 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1674 else
1675 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
f6b49620 1676 /* write to register */
124b13b2 1677 devpriv->write_byte(devpriv->command6_bits,
0a85b6f0 1678 dev->iobase + COMMAND6_REG);
124b13b2 1679 }
e41a6f6d 1680 /* send data */
124b13b2
FMH		 1681 lsb = data[0] & 0xff;
1682 msb = (data[0] >> 8) & 0xff;
1683 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1684 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1685
e41a6f6d 1686 /* remember value for readback */
124b13b2
FMH		 1687 devpriv->ao_value[channel] = data[0];
1688
1689 return 1;
1690}
1691
f6b49620 1692/* analog output readback insn */
da91b269 1693static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 1694 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1695{
1696 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1697
1698 return 1;
1699}
1700
0a85b6f0
MT		 1701static int labpc_calib_read_insn(struct comedi_device *dev,
1702 struct comedi_subdevice *s,
1703 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1704{
1705 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1706
1707 return 1;
1708}
1709
0a85b6f0
MT		 1710static int labpc_calib_write_insn(struct comedi_device *dev,
1711 struct comedi_subdevice *s,
1712 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1713{
1714 int channel = CR_CHAN(insn->chanspec);
1715
1716 write_caldac(dev, channel, data[0]);
1717 return 1;
1718}
1719
0a85b6f0
MT		 1720static int labpc_eeprom_read_insn(struct comedi_device *dev,
1721 struct comedi_subdevice *s,
1722 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1723{
1724 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1725
1726 return 1;
1727}
1728
0a85b6f0
MT		 1729static int labpc_eeprom_write_insn(struct comedi_device *dev,
1730 struct comedi_subdevice *s,
1731 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1732{
1733 int channel = CR_CHAN(insn->chanspec);
1734 int ret;
1735
f6b49620 1736 /* only allow writes to user area of eeprom */
124b13b2 1737 if (channel < 16 || channel > 127) {
0a85b6f0
MT		 1738 printk
1739 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)");
124b13b2
FMH		 1740 return -EINVAL;
1741 }
1742
1743 ret = labpc_eeprom_write(dev, channel, data[0]);
1744 if (ret < 0)
1745 return ret;
1746
1747 return 1;
1748}
1749
f6b49620 1750/* utility function that suggests a dma transfer size in bytes */
ea6d0d4c 1751static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd)
124b13b2
FMH		 1752{
1753 unsigned int size;
1754 unsigned int freq;
1755
1756 if (cmd.convert_src == TRIG_TIMER)
1757 freq = 1000000000 / cmd.convert_arg;
e41a6f6d 1758 /* return some default value */
124b13b2
FMH		 1759 else
1760 freq = 0xffffffff;
1761
e41a6f6d 1762 /* make buffer fill in no more than 1/3 second */
124b13b2
FMH		 1763 size = (freq / 3) * sample_size;
1764
e41a6f6d 1765 /* set a minimum and maximum size allowed */
124b13b2
FMH		 1766 if (size > dma_buffer_size)
1767 size = dma_buffer_size - dma_buffer_size % sample_size;
1768 else if (size < sample_size)
1769 size = sample_size;
1770
1771 return size;
1772}
1773
f6b49620 1774/* figures out what counter values to use based on command */
da91b269 1775static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
124b13b2 1776{
e41a6f6d
SR		 1777 /* max value for 16 bit counter in mode 2 */
1778 const int max_counter_value = 0x10000;
1779 /* min value for 16 bit counter in mode 2 */
1780 const int min_counter_value = 2;
124b13b2
FMH		 1781 unsigned int base_period;
1782
e41a6f6d
SR		 1783 /*
1784 * if both convert and scan triggers are TRIG_TIMER, then they
1785 * both rely on counter b0
1786 */
124b13b2 1787 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
e41a6f6d
SR		 1788 /*
1789 * pick the lowest b0 divisor value we can (for maximum input
1790 * clock speed on convert and scan counters)
1791 */
124b13b2 1792 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
0a85b6f0 1793 (LABPC_TIMER_BASE * max_counter_value) + 1;
124b13b2
FMH		 1794 if (devpriv->divisor_b0 < min_counter_value)
1795 devpriv->divisor_b0 = min_counter_value;
1796 if (devpriv->divisor_b0 > max_counter_value)
1797 devpriv->divisor_b0 = max_counter_value;
1798
1799 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1800
f6b49620 1801 /* set a0 for conversion frequency and b1 for scan frequency */
124b13b2
FMH		 1802 switch (cmd->flags & TRIG_ROUND_MASK) {
1803 default:
1804 case TRIG_ROUND_NEAREST:
1805 devpriv->divisor_a0 =
0a85b6f0
MT		 1806 (labpc_ai_convert_period(cmd) +
1807 (base_period / 2)) / base_period;
124b13b2 1808 devpriv->divisor_b1 =
0a85b6f0
MT		 1809 (labpc_ai_scan_period(cmd) +
1810 (base_period / 2)) / base_period;
124b13b2
FMH		 1811 break;
1812 case TRIG_ROUND_UP:
1813 devpriv->divisor_a0 =
0a85b6f0
MT		 1814 (labpc_ai_convert_period(cmd) + (base_period -
1815 1)) / base_period;
124b13b2 1816 devpriv->divisor_b1 =
0a85b6f0
MT		 1817 (labpc_ai_scan_period(cmd) + (base_period -
1818 1)) / base_period;
124b13b2
FMH		 1819 break;
1820 case TRIG_ROUND_DOWN:
1821 devpriv->divisor_a0 =
0a85b6f0 1822 labpc_ai_convert_period(cmd) / base_period;
124b13b2 1823 devpriv->divisor_b1 =
0a85b6f0 1824 labpc_ai_scan_period(cmd) / base_period;
124b13b2
FMH		 1825 break;
1826 }
f6b49620 1827 /* make sure a0 and b1 values are acceptable */
124b13b2
FMH		 1828 if (devpriv->divisor_a0 < min_counter_value)
1829 devpriv->divisor_a0 = min_counter_value;
1830 if (devpriv->divisor_a0 > max_counter_value)
1831 devpriv->divisor_a0 = max_counter_value;
1832 if (devpriv->divisor_b1 < min_counter_value)
1833 devpriv->divisor_b1 = min_counter_value;
1834 if (devpriv->divisor_b1 > max_counter_value)
1835 devpriv->divisor_b1 = max_counter_value;
f6b49620 1836 /* write corrected timings to command */
124b13b2 1837 labpc_set_ai_convert_period(cmd,
0a85b6f0 1838 base_period * devpriv->divisor_a0);
124b13b2 1839 labpc_set_ai_scan_period(cmd,
0a85b6f0 1840 base_period * devpriv->divisor_b1);
e41a6f6d
SR		 1841 /*
1842 * if only one TRIG_TIMER is used, we can employ the generic
1843 * cascaded timing functions
1844 */
124b13b2
FMH		 1845 } else if (labpc_ai_scan_period(cmd)) {
1846 unsigned int scan_period;
1847
1848 scan_period = labpc_ai_scan_period(cmd);
1849 /* calculate cascaded counter values that give desired scan timing */
1850 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
0a85b6f0
MT		 1851 &(devpriv->divisor_b1),
1852 &(devpriv->divisor_b0),
1853 &scan_period,
1854 cmd->flags & TRIG_ROUND_MASK);
124b13b2
FMH		 1855 labpc_set_ai_scan_period(cmd, scan_period);
1856 } else if (labpc_ai_convert_period(cmd)) {
1857 unsigned int convert_period;
1858
1859 convert_period = labpc_ai_convert_period(cmd);
1860 /* calculate cascaded counter values that give desired conversion timing */
1861 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
0a85b6f0
MT		 1862 &(devpriv->divisor_a0),
1863 &(devpriv->divisor_b0),
1864 &convert_period,
1865 cmd->flags & TRIG_ROUND_MASK);
124b13b2
FMH		 1866 labpc_set_ai_convert_period(cmd, convert_period);
1867 }
1868}
1869
1870static int labpc_dio_mem_callback(int dir, int port, int data,
0a85b6f0 1871 unsigned long iobase)
124b13b2
FMH		 1872{
1873 if (dir) {
1874 writeb(data, (void *)(iobase + port));
1875 return 0;
1876 } else {
1877 return readb((void *)(iobase + port));
1878 }
1879}
1880
f6b49620 1881/* lowlevel write to eeprom/dac */
da91b269 1882static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
0a85b6f0 1883 unsigned int value_width)
124b13b2
FMH		 1884{
1885 int i;
1886
1887 for (i = 1; i <= value_width; i++) {
f6b49620 1888 /* clear serial clock */
124b13b2 1889 devpriv->command5_bits &= ~SCLOCK_BIT;
f6b49620 1890 /* send bits most significant bit first */
124b13b2
FMH		 1891 if (value & (1 << (value_width - i)))
1892 devpriv->command5_bits |= SDATA_BIT;
1893 else
1894 devpriv->command5_bits &= ~SDATA_BIT;
5f74ea14 1895 udelay(1);
124b13b2 1896 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 1897 dev->iobase + COMMAND5_REG);
f6b49620 1898 /* set clock to load bit */
124b13b2 1899 devpriv->command5_bits |= SCLOCK_BIT;
5f74ea14 1900 udelay(1);
124b13b2 1901 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 1902 dev->iobase + COMMAND5_REG);
124b13b2
FMH		 1903 }
1904}
1905
f6b49620 1906/* lowlevel read from eeprom */
da91b269 1907static unsigned int labpc_serial_in(struct comedi_device *dev)
124b13b2
FMH		 1908{
1909 unsigned int value = 0;
1910 int i;
f6b49620 1911 const int value_width = 8; /* number of bits wide values are */
124b13b2
FMH		 1912
1913 for (i = 1; i <= value_width; i++) {
f6b49620 1914 /* set serial clock */
124b13b2 1915 devpriv->command5_bits |= SCLOCK_BIT;
5f74ea14 1916 udelay(1);
124b13b2 1917 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 1918 dev->iobase + COMMAND5_REG);
f6b49620 1919 /* clear clock bit */
124b13b2 1920 devpriv->command5_bits &= ~SCLOCK_BIT;
5f74ea14 1921 udelay(1);
124b13b2 1922 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 1923 dev->iobase + COMMAND5_REG);
f6b49620 1924 /* read bits most significant bit first */
5f74ea14 1925 udelay(1);
124b13b2 1926 devpriv->status2_bits =
0a85b6f0 1927 devpriv->read_byte(dev->iobase + STATUS2_REG);
412bd046 1928 if (devpriv->status2_bits & EEPROM_OUT_BIT)
124b13b2 1929 value |= 1 << (value_width - i);
124b13b2
FMH		 1930 }
1931
1932 return value;
1933}
1934
0a85b6f0
MT		 1935static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1936 unsigned int address)
124b13b2
FMH		 1937{
1938 unsigned int value;
e41a6f6d
SR		 1939 /* bits to tell eeprom to expect a read */
1940 const int read_instruction = 0x3;
1941 /* 8 bit write lengths to eeprom */
1942 const int write_length = 8;
124b13b2 1943
f6b49620 1944 /* enable read/write to eeprom */
124b13b2 1945 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 1946 udelay(1);
124b13b2
FMH		 1947 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1948 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 1949 udelay(1);
124b13b2
FMH		 1950 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1951
f6b49620 1952 /* send read instruction */
124b13b2 1953 labpc_serial_out(dev, read_instruction, write_length);
f6b49620 1954 /* send 8 bit address to read from */
124b13b2 1955 labpc_serial_out(dev, address, write_length);
f6b49620 1956 /* read result */
124b13b2
FMH		 1957 value = labpc_serial_in(dev);
1958
f6b49620 1959 /* disable read/write to eeprom */
124b13b2 1960 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 1961 udelay(1);
124b13b2
FMH		 1962 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1963
1964 return value;
1965}
1966
da91b269 1967static unsigned int labpc_eeprom_write(struct comedi_device *dev,
0a85b6f0 1968 unsigned int address, unsigned int value)
124b13b2
FMH		 1969{
1970 const int write_enable_instruction = 0x6;
1971 const int write_instruction = 0x2;
f6b49620 1972 const int write_length = 8; /* 8 bit write lengths to eeprom */
124b13b2
FMH		 1973 const int write_in_progress_bit = 0x1;
1974 const int timeout = 10000;
1975 int i;
1976
f6b49620 1977 /* make sure there isn't already a write in progress */
124b13b2
FMH		 1978 for (i = 0; i < timeout; i++) {
1979 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
0a85b6f0 1980 0)
124b13b2
FMH		 1981 break;
1982 }
1983 if (i == timeout) {
1984 comedi_error(dev, "eeprom write timed out");
1985 return -ETIME;
1986 }
f6b49620 1987 /* update software copy of eeprom */
124b13b2
FMH		 1988 devpriv->eeprom_data[address] = value;
1989
f6b49620 1990 /* enable read/write to eeprom */
124b13b2 1991 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 1992 udelay(1);
124b13b2
FMH		 1993 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1994 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 1995 udelay(1);
124b13b2
FMH		 1996 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1997
f6b49620 1998 /* send write_enable instruction */
124b13b2
FMH		 1999 labpc_serial_out(dev, write_enable_instruction, write_length);
2000 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 2001 udelay(1);
124b13b2
FMH		 2002 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2003
f6b49620 2004 /* send write instruction */
124b13b2 2005 devpriv->command5_bits |= EEPROM_EN_BIT;
5f74ea14 2006 udelay(1);
124b13b2
FMH		 2007 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2008 labpc_serial_out(dev, write_instruction, write_length);
f6b49620 2009 /* send 8 bit address to write to */
124b13b2 2010 labpc_serial_out(dev, address, write_length);
f6b49620 2011 /* write value */
124b13b2
FMH		 2012 labpc_serial_out(dev, value, write_length);
2013 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 2014 udelay(1);
124b13b2
FMH		 2015 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2016
f6b49620 2017 /* disable read/write to eeprom */
124b13b2 2018 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2019 udelay(1);
124b13b2
FMH		 2020 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2021
2022 return 0;
2023}
2024
da91b269 2025static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
124b13b2
FMH		 2026{
2027 unsigned int value;
2028 const int read_status_instruction = 0x5;
f6b49620 2029 const int write_length = 8; /* 8 bit write lengths to eeprom */
124b13b2 2030
f6b49620 2031 /* enable read/write to eeprom */
124b13b2 2032 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 2033 udelay(1);
124b13b2
FMH		 2034 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2035 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2036 udelay(1);
124b13b2
FMH		 2037 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2038
f6b49620 2039 /* send read status instruction */
124b13b2 2040 labpc_serial_out(dev, read_status_instruction, write_length);
f6b49620 2041 /* read result */
124b13b2
FMH		 2042 value = labpc_serial_in(dev);
2043
f6b49620 2044 /* disable read/write to eeprom */
124b13b2 2045 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2046 udelay(1);
124b13b2
FMH		 2047 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2048
2049 return value;
2050}
2051
f6b49620 2052/* writes to 8 bit calibration dacs */
da91b269 2053static void write_caldac(struct comedi_device *dev, unsigned int channel,
0a85b6f0 2054 unsigned int value)
124b13b2
FMH		 2055{
2056 if (value == devpriv->caldac[channel])
2057 return;
2058 devpriv->caldac[channel] = value;
2059
f6b49620 2060 /* clear caldac load bit and make sure we don't write to eeprom */
124b13b2 2061 devpriv->command5_bits &=
0a85b6f0 2062 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2063 udelay(1);
124b13b2
FMH		 2064 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2065
f6b49620 2066 /* write 4 bit channel */
124b13b2 2067 labpc_serial_out(dev, channel, 4);
f6b49620 2068 /* write 8 bit caldac value */
124b13b2
FMH		 2069 labpc_serial_out(dev, value, 8);
2070
f6b49620 2071 /* set and clear caldac bit to load caldac value */
124b13b2 2072 devpriv->command5_bits |= CALDAC_LOAD_BIT;
5f74ea14 2073 udelay(1);
124b13b2
FMH		 2074 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2075 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
5f74ea14 2076 udelay(1);
124b13b2
FMH		 2077 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2078}
2079
2080#ifdef CONFIG_COMEDI_PCI
2081COMEDI_PCI_INITCLEANUP(driver_labpc, labpc_pci_table);
2082#else
7114a280
AT		 2083static int __init driver_labpc_init_module(void)
2084{
2085 return comedi_driver_register(&driver_labpc);
2086}
2087
2088static void __exit driver_labpc_cleanup_module(void)
2089{
2090 comedi_driver_unregister(&driver_labpc);
2091}
2092
2093module_init(driver_labpc_init_module);
2094module_exit(driver_labpc_cleanup_module);
124b13b2
FMH		 2095#endif
2096
2097EXPORT_SYMBOL_GPL(labpc_common_attach);
2098EXPORT_SYMBOL_GPL(labpc_common_detach);
2099EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
2100EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
2101EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
90f703d3
AT		 2102
2103MODULE_AUTHOR("Comedi http://www.comedi.org");
2104MODULE_DESCRIPTION("Comedi low-level driver");
2105MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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