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staging: comedi: fix infoleak to userspace
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_labpc.c
CommitLineData
124b13b2
FMH		 1/*
2 comedi/drivers/ni_labpc.c
3 Driver for National Instruments Lab-PC series boards and compatibles
4 Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net>
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 2 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19
20************************************************************************
21*/
22/*
23Driver: ni_labpc
24Description: National Instruments Lab-PC (& compatibles)
25Author: Frank Mori Hess <fmhess@users.sourceforge.net>
26Devices: [National Instruments] Lab-PC-1200 (labpc-1200),
27 Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc)
28Status: works
29
30Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges
31and analog references will work, the available ranges/arefs will
32depend on how you have configured the jumpers on your board
33(see your owner's manual).
34
35Kernel-level ISA plug-and-play support for the lab-pc-1200
36boards has not
37yet been added to the driver, mainly due to the fact that
38I don't know the device id numbers. If you have one
39of these boards,
631dd1a8 40please file a bug report at http://comedi.org/
124b13b2
FMH		 41so I can get the necessary information from you.
42
43The 1200 series boards have onboard calibration dacs for correcting
44analog input/output offsets and gains. The proper settings for these
45caldacs are stored on the board's eeprom. To read the caldac values
46from the eeprom and store them into a file that can be then be used by
47comedilib, use the comedi_calibrate program.
48
49Configuration options - ISA boards:
50 [0] - I/O port base address
51 [1] - IRQ (optional, required for timed or externally triggered conversions)
52 [2] - DMA channel (optional)
53
54Configuration options - PCI boards:
55 [0] - bus (optional)
56 [1] - slot (optional)
57
58The Lab-pc+ has quirky chanlist requirements
59when scanning multiple channels. Multiple channel scan
60sequence must start at highest channel, then decrement down to
61channel 0. The rest of the cards can scan down like lab-pc+ or scan
62up from channel zero. Chanlists consisting of all one channel
63are also legal, and allow you to pace conversions in bursts.
64
65*/
66
67/*
68
69NI manuals:
70341309a (labpc-1200 register manual)
71340914a (pci-1200)
72320502b (lab-pc+)
73
74*/
75
76#undef LABPC_DEBUG
f6b49620 77/* #define LABPC_DEBUG enable debugging messages */
124b13b2 78
25436dc9 79#include <linux/interrupt.h>
5a0e3ad6 80#include <linux/slab.h>
845d131e 81#include <linux/io.h>
124b13b2
FMH		 82#include "../comedidev.h"
83
84#include <linux/delay.h>
85#include <asm/dma.h>
86
87#include "8253.h"
88#include "8255.h"
89#include "mite.h"
90#include "comedi_fc.h"
91#include "ni_labpc.h"
92
93#define DRV_NAME "ni_labpc"
94
e41a6f6d
SR		 95/* size of io region used by board */
96#define LABPC_SIZE 32
97/* 2 MHz master clock */
98#define LABPC_TIMER_BASE 500
124b13b2
FMH		 99
100/* Registers for the lab-pc+ */
101
f6b49620 102/* write-only registers */
124b13b2
FMH		 103#define COMMAND1_REG 0x0
104#define ADC_GAIN_MASK (0x7 << 4)
105#define ADC_CHAN_BITS(x) ((x) & 0x7)
e41a6f6d
SR		 106/* enables multi channel scans */
107#define ADC_SCAN_EN_BIT 0x80
124b13b2 108#define COMMAND2_REG 0x1
e41a6f6d
SR		 109/* enable pretriggering (used in conjunction with SWTRIG) */
110#define PRETRIG_BIT 0x1
111/* enable paced conversions on external trigger */
112#define HWTRIG_BIT 0x2
113/* enable paced conversions */
114#define SWTRIG_BIT 0x4
115/* use two cascaded counters for pacing */
116#define CASCADE_BIT 0x8
124b13b2
FMH		 117#define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1))
118#define COMMAND3_REG 0x2
e41a6f6d
SR		 119/* enable dma transfers */
120#define DMA_EN_BIT 0x1
121/* enable interrupts for 8255 */
122#define DIO_INTR_EN_BIT 0x2
123/* enable dma terminal count interrupt */
124#define DMATC_INTR_EN_BIT 0x4
125/* enable timer interrupt */
126#define TIMER_INTR_EN_BIT 0x8
127/* enable error interrupt */
128#define ERR_INTR_EN_BIT 0x10
129/* enable fifo not empty interrupt */
130#define ADC_FNE_INTR_EN_BIT 0x20
124b13b2
FMH		 131#define ADC_CONVERT_REG 0x3
132#define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1))
133#define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1))
134#define ADC_CLEAR_REG 0x8
135#define DMATC_CLEAR_REG 0xa
136#define TIMER_CLEAR_REG 0xc
e41a6f6d
SR		 137/* 1200 boards only */
138#define COMMAND6_REG 0xe
139/* select ground or common-mode reference */
140#define ADC_COMMON_BIT 0x1
141/* adc unipolar */
142#define ADC_UNIP_BIT 0x2
143/* dac unipolar */
144#define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1))
145/* enable fifo half full interrupt */
146#define ADC_FHF_INTR_EN_BIT 0x20
147/* enable interrupt on end of hardware count */
148#define A1_INTR_EN_BIT 0x40
149/* scan up from channel zero instead of down to zero */
150#define ADC_SCAN_UP_BIT 0x80
124b13b2 151#define COMMAND4_REG 0xf
e41a6f6d
SR		 152/* enables 'interval' scanning */
153#define INTERVAL_SCAN_EN_BIT 0x1
154/* enables external signal on counter b1 output to trigger scan */
155#define EXT_SCAN_EN_BIT 0x2
156/* chooses direction (output or input) for EXTCONV* line */
157#define EXT_CONVERT_OUT_BIT 0x4
158/* chooses differential inputs for adc (in conjunction with board jumper) */
159#define ADC_DIFF_BIT 0x8
124b13b2 160#define EXT_CONVERT_DISABLE_BIT 0x10
e41a6f6d
SR		 161/* 1200 boards only, calibration stuff */
162#define COMMAND5_REG 0x1c
163/* enable eeprom for write */
164#define EEPROM_WRITE_UNPROTECT_BIT 0x4
165/* enable dithering */
166#define DITHER_EN_BIT 0x8
167/* load calibration dac */
168#define CALDAC_LOAD_BIT 0x10
169/* serial clock - rising edge writes, falling edge reads */
170#define SCLOCK_BIT 0x20
171/* serial data bit for writing to eeprom or calibration dacs */
172#define SDATA_BIT 0x40
173/* enable eeprom for read/write */
174#define EEPROM_EN_BIT 0x80
124b13b2
FMH		 175#define INTERVAL_COUNT_REG 0x1e
176#define INTERVAL_LOAD_REG 0x1f
177#define INTERVAL_LOAD_BITS 0x1
178
f6b49620 179/* read-only registers */
124b13b2 180#define STATUS1_REG 0x0
e41a6f6d
SR		 181/* data is available in fifo */
182#define DATA_AVAIL_BIT 0x1
183/* overrun has occurred */
184#define OVERRUN_BIT 0x2
185/* fifo overflow */
186#define OVERFLOW_BIT 0x4
25985edc 187/* timer interrupt has occurred */
e41a6f6d 188#define TIMER_BIT 0x8
25985edc 189/* dma terminal count has occurred */
e41a6f6d 190#define DMATC_BIT 0x10
25985edc 191/* external trigger has occurred */
e41a6f6d
SR		 192#define EXT_TRIG_BIT 0x40
193/* 1200 boards only */
194#define STATUS2_REG 0x1d
195/* programmable eeprom serial output */
196#define EEPROM_OUT_BIT 0x1
197/* counter A1 terminal count */
198#define A1_TC_BIT 0x2
199/* fifo not half full */
200#define FNHF_BIT 0x4
124b13b2
FMH		 201#define ADC_FIFO_REG 0xa
202
203#define DIO_BASE_REG 0x10
204#define COUNTER_A_BASE_REG 0x14
205#define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3)
e41a6f6d
SR		 206/* check modes put conversion pacer output in harmless state (a0 mode 2) */
207#define INIT_A0_BITS 0x14
208/* put hardware conversion counter output in harmless state (a1 mode 0) */
209#define INIT_A1_BITS 0x70
124b13b2
FMH		 210#define COUNTER_B_BASE_REG 0x18
211
814900c9
BP		 212static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it);
213static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s);
70265d24 214static irqreturn_t labpc_interrupt(int irq, void *d);
814900c9
BP		 215static int labpc_drain_fifo(struct comedi_device *dev);
216static void labpc_drain_dma(struct comedi_device *dev);
217static void handle_isa_dma(struct comedi_device *dev);
218static void labpc_drain_dregs(struct comedi_device *dev);
0a85b6f0
MT		 219static int labpc_ai_cmdtest(struct comedi_device *dev,
220 struct comedi_subdevice *s, struct comedi_cmd *cmd);
814900c9
BP		 221static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
222static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 223 struct comedi_insn *insn, unsigned int *data);
814900c9 224static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 225 struct comedi_insn *insn, unsigned int *data);
814900c9 226static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 227 struct comedi_insn *insn, unsigned int *data);
228static int labpc_calib_read_insn(struct comedi_device *dev,
229 struct comedi_subdevice *s,
230 struct comedi_insn *insn, unsigned int *data);
231static int labpc_calib_write_insn(struct comedi_device *dev,
232 struct comedi_subdevice *s,
233 struct comedi_insn *insn, unsigned int *data);
234static int labpc_eeprom_read_insn(struct comedi_device *dev,
235 struct comedi_subdevice *s,
236 struct comedi_insn *insn, unsigned int *data);
237static int labpc_eeprom_write_insn(struct comedi_device *dev,
238 struct comedi_subdevice *s,
239 struct comedi_insn *insn,
240 unsigned int *data);
ea6d0d4c 241static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd);
814900c9 242static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd);
124b13b2 243#ifdef CONFIG_COMEDI_PCI
71b5f4f1 244static int labpc_find_device(struct comedi_device *dev, int bus, int slot);
124b13b2
FMH		 245#endif
246static int labpc_dio_mem_callback(int dir, int port, int data,
0a85b6f0 247 unsigned long arg);
814900c9 248static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
0a85b6f0 249 unsigned int num_bits);
814900c9
BP		 250static unsigned int labpc_serial_in(struct comedi_device *dev);
251static unsigned int labpc_eeprom_read(struct comedi_device *dev,
0a85b6f0 252 unsigned int address);
814900c9 253static unsigned int labpc_eeprom_read_status(struct comedi_device *dev);
d6269644 254static int labpc_eeprom_write(struct comedi_device *dev,
0a85b6f0
MT		 255 unsigned int address,
256 unsigned int value);
814900c9 257static void write_caldac(struct comedi_device *dev, unsigned int channel,
0a85b6f0 258 unsigned int value);
124b13b2
FMH		 259
260enum scan_mode {
261 MODE_SINGLE_CHAN,
262 MODE_SINGLE_CHAN_INTERVAL,
263 MODE_MULT_CHAN_UP,
264 MODE_MULT_CHAN_DOWN,
265};
266
f6b49620 267/* analog input ranges */
124b13b2 268#define NUM_LABPC_PLUS_AI_RANGES 16
f6b49620 269/* indicates unipolar ranges */
124b13b2
FMH		 270static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = {
271 0,
272 0,
273 0,
274 0,
275 0,
276 0,
277 0,
278 0,
279 1,
280 1,
281 1,
282 1,
283 1,
284 1,
285 1,
286 1,
287};
288
f6b49620 289/* map range index to gain bits */
124b13b2
FMH		 290static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = {
291 0x00,
292 0x10,
293 0x20,
294 0x30,
295 0x40,
296 0x50,
297 0x60,
298 0x70,
299 0x00,
300 0x10,
301 0x20,
302 0x30,
303 0x40,
304 0x50,
305 0x60,
306 0x70,
307};
0a85b6f0 308
9ced1de6 309static const struct comedi_lrange range_labpc_plus_ai = {
124b13b2
FMH		 310 NUM_LABPC_PLUS_AI_RANGES,
311 {
0a85b6f0
MT		 312 BIP_RANGE(5),
313 BIP_RANGE(4),
314 BIP_RANGE(2.5),
315 BIP_RANGE(1),
316 BIP_RANGE(0.5),
317 BIP_RANGE(0.25),
318 BIP_RANGE(0.1),
319 BIP_RANGE(0.05),
320 UNI_RANGE(10),
321 UNI_RANGE(8),
322 UNI_RANGE(5),
323 UNI_RANGE(2),
324 UNI_RANGE(1),
325 UNI_RANGE(0.5),
326 UNI_RANGE(0.2),
327 UNI_RANGE(0.1),
328 }
124b13b2
FMH		 329};
330
331#define NUM_LABPC_1200_AI_RANGES 14
f6b49620 332/* indicates unipolar ranges */
124b13b2
FMH		 333const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = {
334 0,
335 0,
336 0,
337 0,
338 0,
339 0,
340 0,
341 1,
342 1,
343 1,
344 1,
345 1,
346 1,
347 1,
348};
0656bb35 349EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar);
124b13b2 350
f6b49620 351/* map range index to gain bits */
124b13b2
FMH		 352const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = {
353 0x00,
354 0x20,
355 0x30,
356 0x40,
357 0x50,
358 0x60,
359 0x70,
360 0x00,
361 0x20,
362 0x30,
363 0x40,
364 0x50,
365 0x60,
366 0x70,
367};
0656bb35 368EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits);
0a85b6f0 369
9ced1de6 370const struct comedi_lrange range_labpc_1200_ai = {
124b13b2
FMH		 371 NUM_LABPC_1200_AI_RANGES,
372 {
0a85b6f0
MT		 373 BIP_RANGE(5),
374 BIP_RANGE(2.5),
375 BIP_RANGE(1),
376 BIP_RANGE(0.5),
377 BIP_RANGE(0.25),
378 BIP_RANGE(0.1),
379 BIP_RANGE(0.05),
380 UNI_RANGE(10),
381 UNI_RANGE(5),
382 UNI_RANGE(2),
383 UNI_RANGE(1),
384 UNI_RANGE(0.5),
385 UNI_RANGE(0.2),
386 UNI_RANGE(0.1),
387 }
124b13b2 388};
0656bb35 389EXPORT_SYMBOL_GPL(range_labpc_1200_ai);
124b13b2 390
f6b49620 391/* analog output ranges */
124b13b2 392#define AO_RANGE_IS_UNIPOLAR 0x1
9ced1de6 393static const struct comedi_lrange range_labpc_ao = {
124b13b2
FMH		 394 2,
395 {
0a85b6f0
MT		 396 BIP_RANGE(5),
397 UNI_RANGE(10),
398 }
124b13b2
FMH		 399};
400
401/* functions that do inb/outb and readb/writeb so we can use
402 * function pointers to decide which to use */
403static inline unsigned int labpc_inb(unsigned long address)
404{
405 return inb(address);
406}
0a85b6f0 407
124b13b2
FMH		 408static inline void labpc_outb(unsigned int byte, unsigned long address)
409{
410 outb(byte, address);
411}
0a85b6f0 412
124b13b2
FMH		 413static inline unsigned int labpc_readb(unsigned long address)
414{
415 return readb((void *)address);
416}
0a85b6f0 417
124b13b2
FMH		 418static inline void labpc_writeb(unsigned int byte, unsigned long address)
419{
420 writeb(byte, (void *)address);
421}
422
9ad00740 423static const struct labpc_board_struct labpc_boards[] = {
124b13b2 424 {
0a85b6f0
MT		 425 .name = "lab-pc-1200",
426 .ai_speed = 10000,
427 .bustype = isa_bustype,
428 .register_layout = labpc_1200_layout,
429 .has_ao = 1,
430 .ai_range_table = &range_labpc_1200_ai,
431 .ai_range_code = labpc_1200_ai_gain_bits,
432 .ai_range_is_unipolar = labpc_1200_is_unipolar,
433 .ai_scan_up = 1,
434 .memory_mapped_io = 0,
435 },
124b13b2 436 {
0a85b6f0
MT		 437 .name = "lab-pc-1200ai",
438 .ai_speed = 10000,
439 .bustype = isa_bustype,
440 .register_layout = labpc_1200_layout,
441 .has_ao = 0,
442 .ai_range_table = &range_labpc_1200_ai,
443 .ai_range_code = labpc_1200_ai_gain_bits,
444 .ai_range_is_unipolar = labpc_1200_is_unipolar,
445 .ai_scan_up = 1,
446 .memory_mapped_io = 0,
447 },
124b13b2 448 {
0a85b6f0
MT		 449 .name = "lab-pc+",
450 .ai_speed = 12000,
451 .bustype = isa_bustype,
452 .register_layout = labpc_plus_layout,
453 .has_ao = 1,
454 .ai_range_table = &range_labpc_plus_ai,
455 .ai_range_code = labpc_plus_ai_gain_bits,
456 .ai_range_is_unipolar = labpc_plus_is_unipolar,
457 .ai_scan_up = 0,
458 .memory_mapped_io = 0,
459 },
124b13b2
FMH		 460#ifdef CONFIG_COMEDI_PCI
461 {
0a85b6f0
MT		 462 .name = "pci-1200",
463 .device_id = 0x161,
464 .ai_speed = 10000,
465 .bustype = pci_bustype,
466 .register_layout = labpc_1200_layout,
467 .has_ao = 1,
468 .ai_range_table = &range_labpc_1200_ai,
469 .ai_range_code = labpc_1200_ai_gain_bits,
470 .ai_range_is_unipolar = labpc_1200_is_unipolar,
471 .ai_scan_up = 1,
472 .memory_mapped_io = 1,
473 },
e41a6f6d 474/* dummy entry so pci board works when comedi_config is passed driver name */
124b13b2 475 {
0a85b6f0
MT		 476 .name = DRV_NAME,
477 .bustype = pci_bustype,
478 },
124b13b2
FMH		 479#endif
480};
481
482/*
483 * Useful for shorthand access to the particular board structure
484 */
9ad00740 485#define thisboard ((struct labpc_board_struct *)dev->board_ptr)
124b13b2 486
e41a6f6d
SR		 487/* size in bytes of dma buffer */
488static const int dma_buffer_size = 0xff00;
489/* 2 bytes per sample */
490static const int sample_size = 2;
124b13b2 491
0a4eb4b6 492#define devpriv ((struct labpc_private *)dev->private)
124b13b2 493
139dfbdf 494static struct comedi_driver driver_labpc = {
124b13b2
FMH		 495 .driver_name = DRV_NAME,
496 .module = THIS_MODULE,
497 .attach = labpc_attach,
498 .detach = labpc_common_detach,
8629efa4 499 .num_names = ARRAY_SIZE(labpc_boards),
124b13b2 500 .board_name = &labpc_boards[0].name,
9ad00740 501 .offset = sizeof(struct labpc_board_struct),
124b13b2
FMH		 502};
503
504#ifdef CONFIG_COMEDI_PCI
505static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = {
4e40cee9
GKH		 506 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)},
507 {0}
124b13b2
FMH		 508};
509
510MODULE_DEVICE_TABLE(pci, labpc_pci_table);
511#endif /* CONFIG_COMEDI_PCI */
512
da91b269 513static inline int labpc_counter_load(struct comedi_device *dev,
0a85b6f0
MT		 514 unsigned long base_address,
515 unsigned int counter_number,
516 unsigned int count, unsigned int mode)
124b13b2
FMH		 517{
518 if (thisboard->memory_mapped_io)
519 return i8254_mm_load((void *)base_address, 0, counter_number,
0a85b6f0 520 count, mode);
124b13b2
FMH		 521 else
522 return i8254_load(base_address, 0, counter_number, count, mode);
523}
524
da91b269 525int labpc_common_attach(struct comedi_device *dev, unsigned long iobase,
0a85b6f0 526 unsigned int irq, unsigned int dma_chan)
124b13b2 527{
34c43922 528 struct comedi_subdevice *s;
124b13b2
FMH		 529 int i;
530 unsigned long dma_flags, isr_flags;
531 short lsb, msb;
532
88d8ed4b
MD		 533 printk(KERN_ERR "comedi%d: ni_labpc: %s, io 0x%lx", dev->minor,
534 thisboard->name,
0a85b6f0 535 iobase);
412bd046 536 if (irq)
124b13b2 537 printk(", irq %u", irq);
412bd046 538 if (dma_chan)
124b13b2 539 printk(", dma %u", dma_chan);
124b13b2
FMH		 540 printk("\n");
541
542 if (iobase == 0) {
177d4282 543 printk(KERN_ERR "io base address is zero!\n");
124b13b2
FMH		 544 return -EINVAL;
545 }
f6b49620 546 /* request io regions for isa boards */
124b13b2
FMH		 547 if (thisboard->bustype == isa_bustype) {
548 /* check if io addresses are available */
549 if (!request_region(iobase, LABPC_SIZE,
0a85b6f0 550 driver_labpc.driver_name)) {
88d8ed4b 551 printk(KERN_ERR "I/O port conflict\n");
124b13b2
FMH		 552 return -EIO;
553 }
554 }
555 dev->iobase = iobase;
556
557 if (thisboard->memory_mapped_io) {
558 devpriv->read_byte = labpc_readb;
559 devpriv->write_byte = labpc_writeb;
560 } else {
561 devpriv->read_byte = labpc_inb;
562 devpriv->write_byte = labpc_outb;
563 }
e41a6f6d 564 /* initialize board's command registers */
124b13b2
FMH		 565 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
566 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
567 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
568 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
569 if (thisboard->register_layout == labpc_1200_layout) {
570 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 571 dev->iobase + COMMAND5_REG);
124b13b2 572 devpriv->write_byte(devpriv->command6_bits,
0a85b6f0 573 dev->iobase + COMMAND6_REG);
124b13b2
FMH		 574 }
575
576 /* grab our IRQ */
577 if (irq) {
578 isr_flags = 0;
d1ce3184
IA		 579 if (thisboard->bustype == pci_bustype
580 || thisboard->bustype == pcmcia_bustype)
124b13b2 581 isr_flags |= IRQF_SHARED;
5f74ea14 582 if (request_irq(irq, labpc_interrupt, isr_flags,
124b13b2 583 driver_labpc.driver_name, dev)) {
88d8ed4b 584 printk(KERN_ERR "unable to allocate irq %u\n", irq);
124b13b2
FMH		 585 return -EINVAL;
586 }
587 }
588 dev->irq = irq;
589
e41a6f6d 590 /* grab dma channel */
124b13b2 591 if (dma_chan > 3) {
88d8ed4b 592 printk(KERN_ERR " invalid dma channel %u\n", dma_chan);
124b13b2
FMH		 593 return -EINVAL;
594 } else if (dma_chan) {
e41a6f6d 595 /* allocate dma buffer */
124b13b2 596 devpriv->dma_buffer =
0a85b6f0 597 kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA);
124b13b2 598 if (devpriv->dma_buffer == NULL) {
88d8ed4b 599 printk(KERN_ERR " failed to allocate dma buffer\n");
124b13b2
FMH		 600 return -ENOMEM;
601 }
602 if (request_dma(dma_chan, driver_labpc.driver_name)) {
88d8ed4b 603 printk(KERN_ERR " failed to allocate dma channel %u\n",
0a85b6f0 604 dma_chan);
124b13b2
FMH		 605 return -EINVAL;
606 }
607 devpriv->dma_chan = dma_chan;
608 dma_flags = claim_dma_lock();
609 disable_dma(devpriv->dma_chan);
610 set_dma_mode(devpriv->dma_chan, DMA_MODE_READ);
611 release_dma_lock(dma_flags);
612 }
613
614 dev->board_name = thisboard->name;
615
616 if (alloc_subdevices(dev, 5) < 0)
617 return -ENOMEM;
618
619 /* analog input subdevice */
620 s = dev->subdevices + 0;
621 dev->read_subdev = s;
622 s->type = COMEDI_SUBD_AI;
623 s->subdev_flags =
0a85b6f0 624 SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ;
124b13b2
FMH		 625 s->n_chan = 8;
626 s->len_chanlist = 8;
e41a6f6d 627 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
124b13b2
FMH		 628 s->range_table = thisboard->ai_range_table;
629 s->do_cmd = labpc_ai_cmd;
630 s->do_cmdtest = labpc_ai_cmdtest;
631 s->insn_read = labpc_ai_rinsn;
632 s->cancel = labpc_cancel;
633
634 /* analog output */
635 s = dev->subdevices + 1;
636 if (thisboard->has_ao) {
639b9f1e
SR		 637 /*
638 * Could provide command support, except it only has a
412bd046 639 * one sample hardware buffer for analog output and no
639b9f1e
SR		 640 * underrun flag.
641 */
124b13b2
FMH		 642 s->type = COMEDI_SUBD_AO;
643 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND;
644 s->n_chan = NUM_AO_CHAN;
f6b49620 645 s->maxdata = (1 << 12) - 1; /* 12 bit resolution */
124b13b2
FMH		 646 s->range_table = &range_labpc_ao;
647 s->insn_read = labpc_ao_rinsn;
648 s->insn_write = labpc_ao_winsn;
649 /* initialize analog outputs to a known value */
650 for (i = 0; i < s->n_chan; i++) {
651 devpriv->ao_value[i] = s->maxdata / 2;
652 lsb = devpriv->ao_value[i] & 0xff;
653 msb = (devpriv->ao_value[i] >> 8) & 0xff;
654 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i));
655 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i));
656 }
657 } else {
658 s->type = COMEDI_SUBD_UNUSED;
659 }
660
661 /* 8255 dio */
662 s = dev->subdevices + 2;
412bd046 663 /* if board uses io memory we have to give a custom callback
664 * function to the 8255 driver */
124b13b2
FMH		 665 if (thisboard->memory_mapped_io)
666 subdev_8255_init(dev, s, labpc_dio_mem_callback,
0a85b6f0 667 (unsigned long)(dev->iobase + DIO_BASE_REG));
124b13b2
FMH		 668 else
669 subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG);
670
f6b49620 671 /* calibration subdevices for boards that have one */
124b13b2
FMH		 672 s = dev->subdevices + 3;
673 if (thisboard->register_layout == labpc_1200_layout) {
674 s->type = COMEDI_SUBD_CALIB;
675 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
676 s->n_chan = 16;
677 s->maxdata = 0xff;
678 s->insn_read = labpc_calib_read_insn;
679 s->insn_write = labpc_calib_write_insn;
680
681 for (i = 0; i < s->n_chan; i++)
682 write_caldac(dev, i, s->maxdata / 2);
683 } else
684 s->type = COMEDI_SUBD_UNUSED;
685
686 /* EEPROM */
687 s = dev->subdevices + 4;
688 if (thisboard->register_layout == labpc_1200_layout) {
689 s->type = COMEDI_SUBD_MEMORY;
690 s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL;
691 s->n_chan = EEPROM_SIZE;
692 s->maxdata = 0xff;
693 s->insn_read = labpc_eeprom_read_insn;
694 s->insn_write = labpc_eeprom_write_insn;
695
412bd046 696 for (i = 0; i < EEPROM_SIZE; i++)
124b13b2 697 devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i);
124b13b2 698#ifdef LABPC_DEBUG
88d8ed4b 699 printk(KERN_ERR " eeprom:");
412bd046 700 for (i = 0; i < EEPROM_SIZE; i++)
124b13b2 701 printk(" %i:0x%x ", i, devpriv->eeprom_data[i]);
124b13b2
FMH		 702 printk("\n");
703#endif
704 } else
705 s->type = COMEDI_SUBD_UNUSED;
706
707 return 0;
708}
0656bb35 709EXPORT_SYMBOL_GPL(labpc_common_attach);
124b13b2 710
da91b269 711static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it)
124b13b2
FMH		 712{
713 unsigned long iobase = 0;
714 unsigned int irq = 0;
715 unsigned int dma_chan = 0;
716#ifdef CONFIG_COMEDI_PCI
717 int retval;
718#endif
719
720 /* allocate and initialize dev->private */
0a4eb4b6 721 if (alloc_private(dev, sizeof(struct labpc_private)) < 0)
124b13b2
FMH		 722 return -ENOMEM;
723
e41a6f6d 724 /* get base address, irq etc. based on bustype */
124b13b2
FMH		 725 switch (thisboard->bustype) {
726 case isa_bustype:
727 iobase = it->options[0];
728 irq = it->options[1];
729 dma_chan = it->options[2];
730 break;
731 case pci_bustype:
732#ifdef CONFIG_COMEDI_PCI
733 retval = labpc_find_device(dev, it->options[0], it->options[1]);
412bd046 734 if (retval < 0)
124b13b2 735 return retval;
124b13b2
FMH		 736 retval = mite_setup(devpriv->mite);
737 if (retval < 0)
738 return retval;
739 iobase = (unsigned long)devpriv->mite->daq_io_addr;
740 irq = mite_irq(devpriv->mite);
741#else
88d8ed4b
MD		 742 printk(KERN_ERR " this driver has not been built with PCI "
743 "support.\n");
124b13b2
FMH		 744 return -EINVAL;
745#endif
746 break;
747 case pcmcia_bustype:
0a85b6f0
MT		 748 printk
749 (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n");
124b13b2
FMH		 750 return -EINVAL;
751 break;
752 default:
88d8ed4b 753 printk(KERN_ERR "bug! couldn't determine board type\n");
124b13b2
FMH		 754 return -EINVAL;
755 break;
756 }
757
758 return labpc_common_attach(dev, iobase, irq, dma_chan);
759}
760
f6b49620 761/* adapted from ni_pcimio for finding mite based boards (pc-1200) */
124b13b2 762#ifdef CONFIG_COMEDI_PCI
71b5f4f1 763static int labpc_find_device(struct comedi_device *dev, int bus, int slot)
124b13b2
FMH		 764{
765 struct mite_struct *mite;
766 int i;
767 for (mite = mite_devices; mite; mite = mite->next) {
768 if (mite->used)
769 continue;
e41a6f6d 770/* if bus/slot are specified then make sure we have the right bus/slot */
124b13b2
FMH		 771 if (bus || slot) {
772 if (bus != mite->pcidev->bus->number
0a85b6f0 773 || slot != PCI_SLOT(mite->pcidev->devfn))
124b13b2
FMH		 774 continue;
775 }
776 for (i = 0; i < driver_labpc.num_names; i++) {
777 if (labpc_boards[i].bustype != pci_bustype)
778 continue;
779 if (mite_device_id(mite) == labpc_boards[i].device_id) {
780 devpriv->mite = mite;
e41a6f6d 781/* fixup board pointer, in case we were using the dummy "ni_labpc" entry */
124b13b2
FMH		 782 dev->board_ptr = &labpc_boards[i];
783 return 0;
784 }
785 }
786 }
88d8ed4b 787 printk(KERN_ERR "no device found\n");
124b13b2
FMH		 788 mite_list_devices();
789 return -EIO;
790}
791#endif
792
da91b269 793int labpc_common_detach(struct comedi_device *dev)
124b13b2 794{
88d8ed4b 795 printk(KERN_ERR "comedi%d: ni_labpc: detach\n", dev->minor);
124b13b2
FMH		 796
797 if (dev->subdevices)
798 subdev_8255_cleanup(dev, dev->subdevices + 2);
799
800 /* only free stuff if it has been allocated by _attach */
e4e1f289 801 kfree(devpriv->dma_buffer);
124b13b2
FMH		 802 if (devpriv->dma_chan)
803 free_dma(devpriv->dma_chan);
804 if (dev->irq)
5f74ea14 805 free_irq(dev->irq, dev);
124b13b2
FMH		 806 if (thisboard->bustype == isa_bustype && dev->iobase)
807 release_region(dev->iobase, LABPC_SIZE);
808#ifdef CONFIG_COMEDI_PCI
809 if (devpriv->mite)
810 mite_unsetup(devpriv->mite);
811#endif
812
813 return 0;
814};
0656bb35 815EXPORT_SYMBOL_GPL(labpc_common_detach);
124b13b2 816
da91b269 817static void labpc_clear_adc_fifo(const struct comedi_device *dev)
124b13b2
FMH		 818{
819 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
820 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
821 devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
822}
823
da91b269 824static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
124b13b2
FMH		 825{
826 unsigned long flags;
827
5f74ea14 828 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 829 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
830 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 831 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2
FMH		 832
833 devpriv->command3_bits = 0;
834 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
835
836 return 0;
837}
838
da91b269 839static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd)
124b13b2
FMH		 840{
841 if (cmd->chanlist_len == 1)
842 return MODE_SINGLE_CHAN;
843
844 /* chanlist may be NULL during cmdtest. */
845 if (cmd->chanlist == NULL)
846 return MODE_MULT_CHAN_UP;
847
848 if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1]))
849 return MODE_SINGLE_CHAN_INTERVAL;
850
851 if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1]))
852 return MODE_MULT_CHAN_UP;
853
854 if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1]))
855 return MODE_MULT_CHAN_DOWN;
856
88d8ed4b 857 printk(KERN_ERR "ni_labpc: bug! this should never happen\n");
124b13b2
FMH		 858
859 return 0;
860}
861
da91b269 862static int labpc_ai_chanlist_invalid(const struct comedi_device *dev,
0a85b6f0 863 const struct comedi_cmd *cmd)
124b13b2
FMH		 864{
865 int mode, channel, range, aref, i;
866
867 if (cmd->chanlist == NULL)
868 return 0;
869
870 mode = labpc_ai_scan_mode(cmd);
871
872 if (mode == MODE_SINGLE_CHAN)
873 return 0;
874
875 if (mode == MODE_SINGLE_CHAN_INTERVAL) {
876 if (cmd->chanlist_len > 0xff) {
877 comedi_error(dev,
0a85b6f0 878 "ni_labpc: chanlist too long for single channel interval mode\n");
124b13b2
FMH		 879 return 1;
880 }
881 }
882
883 channel = CR_CHAN(cmd->chanlist[0]);
884 range = CR_RANGE(cmd->chanlist[0]);
885 aref = CR_AREF(cmd->chanlist[0]);
886
887 for (i = 0; i < cmd->chanlist_len; i++) {
888
889 switch (mode) {
890 case MODE_SINGLE_CHAN_INTERVAL:
891 if (CR_CHAN(cmd->chanlist[i]) != channel) {
892 comedi_error(dev,
0a85b6f0 893 "channel scanning order specified in chanlist is not supported by hardware.\n");
124b13b2
FMH		 894 return 1;
895 }
896 break;
897 case MODE_MULT_CHAN_UP:
898 if (CR_CHAN(cmd->chanlist[i]) != i) {
899 comedi_error(dev,
0a85b6f0 900 "channel scanning order specified in chanlist is not supported by hardware.\n");
124b13b2
FMH		 901 return 1;
902 }
903 break;
904 case MODE_MULT_CHAN_DOWN:
905 if (CR_CHAN(cmd->chanlist[i]) !=
0a85b6f0 906 cmd->chanlist_len - i - 1) {
124b13b2 907 comedi_error(dev,
0a85b6f0 908 "channel scanning order specified in chanlist is not supported by hardware.\n");
124b13b2
FMH		 909 return 1;
910 }
911 break;
912 default:
88d8ed4b 913 printk(KERN_ERR "ni_labpc: bug! in chanlist check\n");
124b13b2
FMH		 914 return 1;
915 break;
916 }
917
918 if (CR_RANGE(cmd->chanlist[i]) != range) {
919 comedi_error(dev,
0a85b6f0 920 "entries in chanlist must all have the same range\n");
124b13b2
FMH		 921 return 1;
922 }
923
924 if (CR_AREF(cmd->chanlist[i]) != aref) {
925 comedi_error(dev,
0a85b6f0 926 "entries in chanlist must all have the same reference\n");
124b13b2
FMH		 927 return 1;
928 }
929 }
930
931 return 0;
932}
933
da91b269 934static int labpc_use_continuous_mode(const struct comedi_cmd *cmd)
124b13b2
FMH		 935{
936 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN)
937 return 1;
938
939 if (cmd->scan_begin_src == TRIG_FOLLOW)
940 return 1;
941
942 return 0;
943}
944
da91b269 945static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd)
124b13b2
FMH		 946{
947 if (cmd->convert_src != TRIG_TIMER)
948 return 0;
949
950 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
0a85b6f0 951 cmd->scan_begin_src == TRIG_TIMER)
124b13b2
FMH		 952 return cmd->scan_begin_arg;
953
954 return cmd->convert_arg;
955}
956
da91b269 957static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns)
124b13b2
FMH		 958{
959 if (cmd->convert_src != TRIG_TIMER)
960 return;
961
962 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
0a85b6f0 963 cmd->scan_begin_src == TRIG_TIMER) {
124b13b2
FMH		 964 cmd->scan_begin_arg = ns;
965 if (cmd->convert_arg > cmd->scan_begin_arg)
966 cmd->convert_arg = cmd->scan_begin_arg;
967 } else
968 cmd->convert_arg = ns;
969}
970
da91b269 971static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd)
124b13b2
FMH		 972{
973 if (cmd->scan_begin_src != TRIG_TIMER)
974 return 0;
975
976 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
0a85b6f0 977 cmd->convert_src == TRIG_TIMER)
124b13b2
FMH		 978 return 0;
979
980 return cmd->scan_begin_arg;
981}
982
da91b269 983static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns)
124b13b2
FMH		 984{
985 if (cmd->scan_begin_src != TRIG_TIMER)
986 return;
987
988 if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN &&
0a85b6f0 989 cmd->convert_src == TRIG_TIMER)
124b13b2
FMH		 990 return;
991
992 cmd->scan_begin_arg = ns;
993}
994
0a85b6f0
MT		 995static int labpc_ai_cmdtest(struct comedi_device *dev,
996 struct comedi_subdevice *s, struct comedi_cmd *cmd)
124b13b2
FMH		 997{
998 int err = 0;
999 int tmp, tmp2;
1000 int stop_mask;
1001
1002 /* step 1: make sure trigger sources are trivially valid */
1003
1004 tmp = cmd->start_src;
1005 cmd->start_src &= TRIG_NOW | TRIG_EXT;
1006 if (!cmd->start_src || tmp != cmd->start_src)
1007 err++;
1008
1009 tmp = cmd->scan_begin_src;
1010 cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT;
1011 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1012 err++;
1013
1014 tmp = cmd->convert_src;
1015 cmd->convert_src &= TRIG_TIMER | TRIG_EXT;
1016 if (!cmd->convert_src || tmp != cmd->convert_src)
1017 err++;
1018
1019 tmp = cmd->scan_end_src;
1020 cmd->scan_end_src &= TRIG_COUNT;
1021 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1022 err++;
1023
1024 tmp = cmd->stop_src;
1025 stop_mask = TRIG_COUNT | TRIG_NONE;
1026 if (thisboard->register_layout == labpc_1200_layout)
1027 stop_mask |= TRIG_EXT;
1028 cmd->stop_src &= stop_mask;
1029 if (!cmd->stop_src || tmp != cmd->stop_src)
1030 err++;
1031
1032 if (err)
1033 return 1;
1034
1035 /* step 2: make sure trigger sources are unique and mutually compatible */
1036
1037 if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT)
1038 err++;
1039 if (cmd->scan_begin_src != TRIG_TIMER &&
0a85b6f0
MT		 1040 cmd->scan_begin_src != TRIG_FOLLOW &&
1041 cmd->scan_begin_src != TRIG_EXT)
124b13b2
FMH		 1042 err++;
1043 if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT)
1044 err++;
1045 if (cmd->stop_src != TRIG_COUNT &&
0a85b6f0 1046 cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE)
124b13b2
FMH		 1047 err++;
1048
e41a6f6d 1049 /* can't have external stop and start triggers at once */
124b13b2
FMH		 1050 if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT)
1051 err++;
1052
1053 if (err)
1054 return 2;
1055
1056 /* step 3: make sure arguments are trivially compatible */
1057
1058 if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) {
1059 cmd->start_arg = 0;
1060 err++;
1061 }
1062
412bd046 1063 if (!cmd->chanlist_len)
124b13b2 1064 err++;
412bd046 1065
124b13b2
FMH		 1066 if (cmd->scan_end_arg != cmd->chanlist_len) {
1067 cmd->scan_end_arg = cmd->chanlist_len;
1068 err++;
1069 }
1070
1071 if (cmd->convert_src == TRIG_TIMER) {
1072 if (cmd->convert_arg < thisboard->ai_speed) {
1073 cmd->convert_arg = thisboard->ai_speed;
1074 err++;
1075 }
1076 }
e41a6f6d 1077 /* make sure scan timing is not too fast */
124b13b2
FMH		 1078 if (cmd->scan_begin_src == TRIG_TIMER) {
1079 if (cmd->convert_src == TRIG_TIMER &&
0a85b6f0
MT		 1080 cmd->scan_begin_arg <
1081 cmd->convert_arg * cmd->chanlist_len) {
124b13b2 1082 cmd->scan_begin_arg =
0a85b6f0 1083 cmd->convert_arg * cmd->chanlist_len;
124b13b2
FMH		 1084 err++;
1085 }
1086 if (cmd->scan_begin_arg <
0a85b6f0 1087 thisboard->ai_speed * cmd->chanlist_len) {
124b13b2 1088 cmd->scan_begin_arg =
0a85b6f0 1089 thisboard->ai_speed * cmd->chanlist_len;
124b13b2
FMH		 1090 err++;
1091 }
1092 }
e41a6f6d 1093 /* stop source */
124b13b2
FMH		 1094 switch (cmd->stop_src) {
1095 case TRIG_COUNT:
1096 if (!cmd->stop_arg) {
1097 cmd->stop_arg = 1;
1098 err++;
1099 }
1100 break;
1101 case TRIG_NONE:
1102 if (cmd->stop_arg != 0) {
1103 cmd->stop_arg = 0;
1104 err++;
1105 }
1106 break;
1309e617
MD		 1107 /*
1108 * TRIG_EXT doesn't care since it doesn't
1109 * trigger off a numbered channel
1110 */
124b13b2
FMH		 1111 default:
1112 break;
1113 }
1114
1115 if (err)
1116 return 3;
1117
1118 /* step 4: fix up any arguments */
1119
1120 tmp = cmd->convert_arg;
1121 tmp2 = cmd->scan_begin_arg;
1122 labpc_adc_timing(dev, cmd);
1123 if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg)
1124 err++;
1125
1126 if (err)
1127 return 4;
1128
1129 if (labpc_ai_chanlist_invalid(dev, cmd))
1130 return 5;
1131
1132 return 0;
1133}
1134
da91b269 1135static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
124b13b2
FMH		 1136{
1137 int channel, range, aref;
1138 unsigned long irq_flags;
1139 int ret;
d163679c 1140 struct comedi_async *async = s->async;
ea6d0d4c 1141 struct comedi_cmd *cmd = &async->cmd;
124b13b2
FMH		 1142 enum transfer_type xfer;
1143 unsigned long flags;
1144
1145 if (!dev->irq) {
1146 comedi_error(dev, "no irq assigned, cannot perform command");
1147 return -1;
1148 }
1149
1150 range = CR_RANGE(cmd->chanlist[0]);
1151 aref = CR_AREF(cmd->chanlist[0]);
1152
25985edc 1153 /* make sure board is disabled before setting up acquisition */
5f74ea14 1154 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 1155 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1156 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 1157 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2
FMH		 1158
1159 devpriv->command3_bits = 0;
1160 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1161
f6b49620 1162 /* initialize software conversion count */
412bd046 1163 if (cmd->stop_src == TRIG_COUNT)
124b13b2 1164 devpriv->count = cmd->stop_arg * cmd->chanlist_len;
65d6d26c 1165
f6b49620 1166 /* setup hardware conversion counter */
124b13b2 1167 if (cmd->stop_src == TRIG_EXT) {
1309e617
MD		 1168 /*
1169 * load counter a1 with count of 3
1170 * (pc+ manual says this is minimum allowed) using mode 0
1171 */
124b13b2 1172 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
0a85b6f0 1173 1, 3, 0);
124b13b2
FMH		 1174 if (ret < 0) {
1175 comedi_error(dev, "error loading counter a1");
1176 return -1;
1177 }
1309e617
MD		 1178 } else /*
1179 * otherwise, just put a1 in mode 0
1180 * with no count to set its output low
1181 */
124b13b2 1182 devpriv->write_byte(INIT_A1_BITS,
0a85b6f0 1183 dev->iobase + COUNTER_A_CONTROL_REG);
124b13b2 1184
f6b49620
BP		 1185 /* figure out what method we will use to transfer data */
1186 if (devpriv->dma_chan && /* need a dma channel allocated */
1309e617
MD		 1187 /*
1188 * dma unsafe at RT priority,
1189 * and too much setup time for TRIG_WAKE_EOS for
1190 */
0a85b6f0
MT		 1191 (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 &&
1192 /* only available on the isa boards */
1193 thisboard->bustype == isa_bustype) {
124b13b2 1194 xfer = isa_dma_transfer;
1309e617
MD		 1195 /* pc-plus has no fifo-half full interrupt */
1196 } else if (thisboard->register_layout == labpc_1200_layout &&
0a85b6f0
MT		 1197 /* wake-end-of-scan should interrupt on fifo not empty */
1198 (cmd->flags & TRIG_WAKE_EOS) == 0 &&
1199 /* make sure we are taking more than just a few points */
1200 (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) {
124b13b2
FMH		 1201 xfer = fifo_half_full_transfer;
1202 } else
1203 xfer = fifo_not_empty_transfer;
1204 devpriv->current_transfer = xfer;
1205
f6b49620 1206 /* setup command6 register for 1200 boards */
124b13b2 1207 if (thisboard->register_layout == labpc_1200_layout) {
f6b49620 1208 /* reference inputs to ground or common? */
124b13b2
FMH		 1209 if (aref != AREF_GROUND)
1210 devpriv->command6_bits |= ADC_COMMON_BIT;
1211 else
1212 devpriv->command6_bits &= ~ADC_COMMON_BIT;
f6b49620 1213 /* bipolar or unipolar range? */
124b13b2
FMH		 1214 if (thisboard->ai_range_is_unipolar[range])
1215 devpriv->command6_bits |= ADC_UNIP_BIT;
1216 else
1217 devpriv->command6_bits &= ~ADC_UNIP_BIT;
f6b49620 1218 /* interrupt on fifo half full? */
124b13b2
FMH		 1219 if (xfer == fifo_half_full_transfer)
1220 devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT;
1221 else
1222 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
f6b49620 1223 /* enable interrupt on counter a1 terminal count? */
124b13b2
FMH		 1224 if (cmd->stop_src == TRIG_EXT)
1225 devpriv->command6_bits |= A1_INTR_EN_BIT;
1226 else
1227 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
f6b49620 1228 /* are we scanning up or down through channels? */
124b13b2
FMH		 1229 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1230 devpriv->command6_bits |= ADC_SCAN_UP_BIT;
1231 else
1232 devpriv->command6_bits &= ~ADC_SCAN_UP_BIT;
f6b49620 1233 /* write to register */
124b13b2 1234 devpriv->write_byte(devpriv->command6_bits,
0a85b6f0 1235 dev->iobase + COMMAND6_REG);
124b13b2
FMH		 1236 }
1237
1238 /* setup channel list, etc (command1 register) */
1239 devpriv->command1_bits = 0;
1240 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP)
1241 channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]);
1242 else
1243 channel = CR_CHAN(cmd->chanlist[0]);
e41a6f6d 1244 /* munge channel bits for differential / scan disabled mode */
124b13b2
FMH		 1245 if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF)
1246 channel *= 2;
1247 devpriv->command1_bits |= ADC_CHAN_BITS(channel);
1248 devpriv->command1_bits |= thisboard->ai_range_code[range];
1249 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
e41a6f6d 1250 /* manual says to set scan enable bit on second pass */
124b13b2 1251 if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP ||
0a85b6f0 1252 labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) {
124b13b2 1253 devpriv->command1_bits |= ADC_SCAN_EN_BIT;
e41a6f6d
SR		 1254 /* need a brief delay before enabling scan, or scan
1255 * list will get screwed when you switch
124b13b2 1256 * between scan up to scan down mode - dunno why */
5f74ea14 1257 udelay(1);
124b13b2 1258 devpriv->write_byte(devpriv->command1_bits,
0a85b6f0 1259 dev->iobase + COMMAND1_REG);
124b13b2 1260 }
f6b49620 1261 /* setup any external triggering/pacing (command4 register) */
124b13b2
FMH		 1262 devpriv->command4_bits = 0;
1263 if (cmd->convert_src != TRIG_EXT)
1264 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
1265 /* XXX should discard first scan when using interval scanning
1266 * since manual says it is not synced with scan clock */
1267 if (labpc_use_continuous_mode(cmd) == 0) {
1268 devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT;
1269 if (cmd->scan_begin_src == TRIG_EXT)
1270 devpriv->command4_bits |= EXT_SCAN_EN_BIT;
1271 }
f6b49620 1272 /* single-ended/differential */
124b13b2
FMH		 1273 if (aref == AREF_DIFF)
1274 devpriv->command4_bits |= ADC_DIFF_BIT;
1275 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1276
1277 devpriv->write_byte(cmd->chanlist_len,
0a85b6f0 1278 dev->iobase + INTERVAL_COUNT_REG);
f6b49620 1279 /* load count */
124b13b2 1280 devpriv->write_byte(INTERVAL_LOAD_BITS,
0a85b6f0 1281 dev->iobase + INTERVAL_LOAD_REG);
124b13b2
FMH		 1282
1283 if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) {
f6b49620 1284 /* set up pacing */
124b13b2 1285 labpc_adc_timing(dev, cmd);
f6b49620 1286 /* load counter b0 in mode 3 */
124b13b2 1287 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
0a85b6f0 1288 0, devpriv->divisor_b0, 3);
124b13b2
FMH		 1289 if (ret < 0) {
1290 comedi_error(dev, "error loading counter b0");
1291 return -1;
1292 }
1293 }
f6b49620 1294 /* set up conversion pacing */
124b13b2 1295 if (labpc_ai_convert_period(cmd)) {
f6b49620 1296 /* load counter a0 in mode 2 */
124b13b2 1297 ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG,
0a85b6f0 1298 0, devpriv->divisor_a0, 2);
124b13b2
FMH		 1299 if (ret < 0) {
1300 comedi_error(dev, "error loading counter a0");
1301 return -1;
1302 }
1303 } else
1304 devpriv->write_byte(INIT_A0_BITS,
0a85b6f0 1305 dev->iobase + COUNTER_A_CONTROL_REG);
124b13b2 1306
f6b49620 1307 /* set up scan pacing */
124b13b2 1308 if (labpc_ai_scan_period(cmd)) {
f6b49620 1309 /* load counter b1 in mode 2 */
124b13b2 1310 ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG,
0a85b6f0 1311 1, devpriv->divisor_b1, 2);
124b13b2
FMH		 1312 if (ret < 0) {
1313 comedi_error(dev, "error loading counter b1");
1314 return -1;
1315 }
1316 }
1317
1318 labpc_clear_adc_fifo(dev);
1319
f6b49620 1320 /* set up dma transfer */
124b13b2
FMH		 1321 if (xfer == isa_dma_transfer) {
1322 irq_flags = claim_dma_lock();
1323 disable_dma(devpriv->dma_chan);
1324 /* clear flip-flop to make sure 2-byte registers for
1325 * count and address get set correctly */
1326 clear_dma_ff(devpriv->dma_chan);
1327 set_dma_addr(devpriv->dma_chan,
0a85b6f0 1328 virt_to_bus(devpriv->dma_buffer));
f6b49620 1329 /* set appropriate size of transfer */
124b13b2
FMH		 1330 devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd);
1331 if (cmd->stop_src == TRIG_COUNT &&
0a85b6f0 1332 devpriv->count * sample_size < devpriv->dma_transfer_size) {
124b13b2 1333 devpriv->dma_transfer_size =
0a85b6f0 1334 devpriv->count * sample_size;
124b13b2
FMH		 1335 }
1336 set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size);
1337 enable_dma(devpriv->dma_chan);
1338 release_dma_lock(irq_flags);
f6b49620 1339 /* enable board's dma */
124b13b2
FMH		 1340 devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT;
1341 } else
1342 devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT;
1343
f6b49620 1344 /* enable error interrupts */
124b13b2 1345 devpriv->command3_bits |= ERR_INTR_EN_BIT;
f6b49620 1346 /* enable fifo not empty interrupt? */
124b13b2
FMH		 1347 if (xfer == fifo_not_empty_transfer)
1348 devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT;
1349 else
1350 devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT;
1351 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1352
25985edc 1353 /* startup acquisition */
124b13b2 1354
f6b49620
BP		 1355 /* command2 reg */
1356 /* use 2 cascaded counters for pacing */
5f74ea14 1357 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 1358 devpriv->command2_bits |= CASCADE_BIT;
1359 switch (cmd->start_src) {
1360 case TRIG_EXT:
1361 devpriv->command2_bits |= HWTRIG_BIT;
1362 devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT;
1363 break;
1364 case TRIG_NOW:
1365 devpriv->command2_bits |= SWTRIG_BIT;
1366 devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT;
1367 break;
1368 default:
1369 comedi_error(dev, "bug with start_src");
1370 return -1;
1371 break;
1372 }
1373 switch (cmd->stop_src) {
1374 case TRIG_EXT:
1375 devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT;
1376 break;
1377 case TRIG_COUNT:
1378 case TRIG_NONE:
1379 break;
1380 default:
1381 comedi_error(dev, "bug with stop_src");
1382 return -1;
1383 }
1384 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 1385 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2
FMH		 1386
1387 return 0;
1388}
1389
1390/* interrupt service routine */
70265d24 1391static irqreturn_t labpc_interrupt(int irq, void *d)
124b13b2 1392{
71b5f4f1 1393 struct comedi_device *dev = d;
34c43922 1394 struct comedi_subdevice *s = dev->read_subdev;
d163679c 1395 struct comedi_async *async;
ea6d0d4c 1396 struct comedi_cmd *cmd;
124b13b2
FMH		 1397
1398 if (dev->attached == 0) {
1399 comedi_error(dev, "premature interrupt");
1400 return IRQ_HANDLED;
1401 }
1402
1403 async = s->async;
1404 cmd = &async->cmd;
1405 async->events = 0;
1406
e41a6f6d 1407 /* read board status */
124b13b2
FMH		 1408 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1409 if (thisboard->register_layout == labpc_1200_layout)
1410 devpriv->status2_bits =
0a85b6f0 1411 devpriv->read_byte(dev->iobase + STATUS2_REG);
124b13b2
FMH		 1412
1413 if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT |
0a85b6f0
MT		 1414 OVERRUN_BIT | DATA_AVAIL_BIT)) == 0
1415 && (devpriv->status2_bits & A1_TC_BIT) == 0
1416 && (devpriv->status2_bits & FNHF_BIT)) {
124b13b2
FMH		 1417 return IRQ_NONE;
1418 }
1419
1420 if (devpriv->status1_bits & OVERRUN_BIT) {
e41a6f6d 1421 /* clear error interrupt */
124b13b2
FMH		 1422 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1423 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1424 comedi_event(dev, s);
1425 comedi_error(dev, "overrun");
1426 return IRQ_HANDLED;
1427 }
1428
1429 if (devpriv->current_transfer == isa_dma_transfer) {
639b9f1e
SR		 1430 /*
1431 * if a dma terminal count of external stop trigger
1432 * has occurred
1433 */
124b13b2 1434 if (devpriv->status1_bits & DMATC_BIT ||
0a85b6f0
MT		 1435 (thisboard->register_layout == labpc_1200_layout
1436 && devpriv->status2_bits & A1_TC_BIT)) {
124b13b2
FMH		 1437 handle_isa_dma(dev);
1438 }
1439 } else
1440 labpc_drain_fifo(dev);
1441
1442 if (devpriv->status1_bits & TIMER_BIT) {
1443 comedi_error(dev, "handled timer interrupt?");
f6b49620 1444 /* clear it */
124b13b2
FMH		 1445 devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG);
1446 }
1447
1448 if (devpriv->status1_bits & OVERFLOW_BIT) {
f6b49620 1449 /* clear error interrupt */
124b13b2
FMH		 1450 devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG);
1451 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1452 comedi_event(dev, s);
1453 comedi_error(dev, "overflow");
1454 return IRQ_HANDLED;
1455 }
f6b49620 1456 /* handle external stop trigger */
124b13b2
FMH		 1457 if (cmd->stop_src == TRIG_EXT) {
1458 if (devpriv->status2_bits & A1_TC_BIT) {
1459 labpc_drain_dregs(dev);
1460 labpc_cancel(dev, s);
1461 async->events |= COMEDI_CB_EOA;
1462 }
1463 }
1464
1465 /* TRIG_COUNT end of acquisition */
1466 if (cmd->stop_src == TRIG_COUNT) {
1467 if (devpriv->count == 0) {
1468 labpc_cancel(dev, s);
1469 async->events |= COMEDI_CB_EOA;
1470 }
1471 }
1472
1473 comedi_event(dev, s);
1474 return IRQ_HANDLED;
1475}
1476
f6b49620 1477/* read all available samples from ai fifo */
da91b269 1478static int labpc_drain_fifo(struct comedi_device *dev)
124b13b2
FMH		 1479{
1480 unsigned int lsb, msb;
790c5541 1481 short data;
d163679c 1482 struct comedi_async *async = dev->read_subdev->async;
124b13b2
FMH		 1483 const int timeout = 10000;
1484 unsigned int i;
1485
1486 devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG);
1487
1488 for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout;
0a85b6f0 1489 i++) {
f6b49620 1490 /* quit if we have all the data we want */
124b13b2
FMH		 1491 if (async->cmd.stop_src == TRIG_COUNT) {
1492 if (devpriv->count == 0)
1493 break;
1494 devpriv->count--;
1495 }
1496 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1497 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1498 data = (msb << 8) | lsb;
1499 cfc_write_to_buffer(dev->read_subdev, data);
1500 devpriv->status1_bits =
0a85b6f0 1501 devpriv->read_byte(dev->iobase + STATUS1_REG);
124b13b2
FMH		 1502 }
1503 if (i == timeout) {
1504 comedi_error(dev, "ai timeout, fifo never empties");
1505 async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA;
1506 return -1;
1507 }
1508
1509 return 0;
1510}
1511
da91b269 1512static void labpc_drain_dma(struct comedi_device *dev)
124b13b2 1513{
34c43922 1514 struct comedi_subdevice *s = dev->read_subdev;
d163679c 1515 struct comedi_async *async = s->async;
124b13b2
FMH		 1516 int status;
1517 unsigned long flags;
1518 unsigned int max_points, num_points, residue, leftover;
1519 int i;
1520
1521 status = devpriv->status1_bits;
1522
1523 flags = claim_dma_lock();
1524 disable_dma(devpriv->dma_chan);
1525 /* clear flip-flop to make sure 2-byte registers for
1526 * count and address get set correctly */
1527 clear_dma_ff(devpriv->dma_chan);
1528
f6b49620 1529 /* figure out how many points to read */
124b13b2
FMH		 1530 max_points = devpriv->dma_transfer_size / sample_size;
1531 /* residue is the number of points left to be done on the dma
1532 * transfer. It should always be zero at this point unless
1533 * the stop_src is set to external triggering.
1534 */
1535 residue = get_dma_residue(devpriv->dma_chan) / sample_size;
1536 num_points = max_points - residue;
1537 if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT)
1538 num_points = devpriv->count;
1539
f6b49620 1540 /* figure out how many points will be stored next time */
124b13b2
FMH		 1541 leftover = 0;
1542 if (async->cmd.stop_src != TRIG_COUNT) {
1543 leftover = devpriv->dma_transfer_size / sample_size;
1544 } else if (devpriv->count > num_points) {
1545 leftover = devpriv->count - num_points;
1546 if (leftover > max_points)
1547 leftover = max_points;
1548 }
1549
1550 /* write data to comedi buffer */
412bd046 1551 for (i = 0; i < num_points; i++)
124b13b2 1552 cfc_write_to_buffer(s, devpriv->dma_buffer[i]);
65d6d26c 1553
124b13b2
FMH		 1554 if (async->cmd.stop_src == TRIG_COUNT)
1555 devpriv->count -= num_points;
1556
f6b49620 1557 /* set address and count for next transfer */
124b13b2
FMH		 1558 set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer));
1559 set_dma_count(devpriv->dma_chan, leftover * sample_size);
1560 release_dma_lock(flags);
1561
1562 async->events |= COMEDI_CB_BLOCK;
1563}
1564
da91b269 1565static void handle_isa_dma(struct comedi_device *dev)
124b13b2
FMH		 1566{
1567 labpc_drain_dma(dev);
1568
1569 enable_dma(devpriv->dma_chan);
1570
f6b49620 1571 /* clear dma tc interrupt */
124b13b2
FMH		 1572 devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG);
1573}
1574
25985edc
LDM		 1575/* makes sure all data acquired by board is transferred to comedi (used
1576 * when acquisition is terminated by stop_src == TRIG_EXT). */
da91b269 1577static void labpc_drain_dregs(struct comedi_device *dev)
124b13b2
FMH		 1578{
1579 if (devpriv->current_transfer == isa_dma_transfer)
1580 labpc_drain_dma(dev);
1581
1582 labpc_drain_fifo(dev);
1583}
1584
da91b269 1585static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 1586 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1587{
1588 int i, n;
1589 int chan, range;
1590 int lsb, msb;
1591 int timeout = 1000;
1592 unsigned long flags;
1593
f6b49620 1594 /* disable timed conversions */
5f74ea14 1595 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 1596 devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT;
1597 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 1598 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2 1599
f6b49620 1600 /* disable interrupt generation and dma */
124b13b2
FMH		 1601 devpriv->command3_bits = 0;
1602 devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG);
1603
1604 /* set gain and channel */
1605 devpriv->command1_bits = 0;
1606 chan = CR_CHAN(insn->chanspec);
1607 range = CR_RANGE(insn->chanspec);
1608 devpriv->command1_bits |= thisboard->ai_range_code[range];
e41a6f6d 1609 /* munge channel bits for differential/scan disabled mode */
124b13b2
FMH		 1610 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1611 chan *= 2;
1612 devpriv->command1_bits |= ADC_CHAN_BITS(chan);
1613 devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG);
1614
e41a6f6d 1615 /* setup command6 register for 1200 boards */
124b13b2 1616 if (thisboard->register_layout == labpc_1200_layout) {
f6b49620 1617 /* reference inputs to ground or common? */
124b13b2
FMH		 1618 if (CR_AREF(insn->chanspec) != AREF_GROUND)
1619 devpriv->command6_bits |= ADC_COMMON_BIT;
1620 else
1621 devpriv->command6_bits &= ~ADC_COMMON_BIT;
e41a6f6d 1622 /* bipolar or unipolar range? */
124b13b2
FMH		 1623 if (thisboard->ai_range_is_unipolar[range])
1624 devpriv->command6_bits |= ADC_UNIP_BIT;
1625 else
1626 devpriv->command6_bits &= ~ADC_UNIP_BIT;
e41a6f6d 1627 /* don't interrupt on fifo half full */
124b13b2 1628 devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT;
e41a6f6d 1629 /* don't enable interrupt on counter a1 terminal count? */
124b13b2 1630 devpriv->command6_bits &= ~A1_INTR_EN_BIT;
e41a6f6d 1631 /* write to register */
124b13b2 1632 devpriv->write_byte(devpriv->command6_bits,
0a85b6f0 1633 dev->iobase + COMMAND6_REG);
124b13b2 1634 }
e41a6f6d 1635 /* setup command4 register */
124b13b2
FMH		 1636 devpriv->command4_bits = 0;
1637 devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT;
e41a6f6d 1638 /* single-ended/differential */
124b13b2
FMH		 1639 if (CR_AREF(insn->chanspec) == AREF_DIFF)
1640 devpriv->command4_bits |= ADC_DIFF_BIT;
1641 devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG);
1642
1309e617
MD		 1643 /*
1644 * initialize pacer counter output to make sure it doesn't
1645 * cause any problems
1646 */
124b13b2
FMH		 1647 devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG);
1648
1649 labpc_clear_adc_fifo(dev);
1650
1651 for (n = 0; n < insn->n; n++) {
1652 /* trigger conversion */
1653 devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG);
1654
1655 for (i = 0; i < timeout; i++) {
1656 if (devpriv->read_byte(dev->iobase +
0a85b6f0 1657 STATUS1_REG) & DATA_AVAIL_BIT)
124b13b2 1658 break;
5f74ea14 1659 udelay(1);
124b13b2
FMH		 1660 }
1661 if (i == timeout) {
1662 comedi_error(dev, "timeout");
1663 return -ETIME;
1664 }
1665 lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1666 msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG);
1667 data[n] = (msb << 8) | lsb;
1668 }
1669
1670 return n;
1671}
1672
f6b49620 1673/* analog output insn */
da91b269 1674static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 1675 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1676{
1677 int channel, range;
1678 unsigned long flags;
1679 int lsb, msb;
1680
1681 channel = CR_CHAN(insn->chanspec);
1682
e41a6f6d 1683 /* turn off pacing of analog output channel */
124b13b2
FMH		 1684 /* note: hardware bug in daqcard-1200 means pacing cannot
1685 * be independently enabled/disabled for its the two channels */
5f74ea14 1686 spin_lock_irqsave(&dev->spinlock, flags);
124b13b2
FMH		 1687 devpriv->command2_bits &= ~DAC_PACED_BIT(channel);
1688 devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG);
5f74ea14 1689 spin_unlock_irqrestore(&dev->spinlock, flags);
124b13b2 1690
e41a6f6d 1691 /* set range */
124b13b2
FMH		 1692 if (thisboard->register_layout == labpc_1200_layout) {
1693 range = CR_RANGE(insn->chanspec);
1694 if (range & AO_RANGE_IS_UNIPOLAR)
1695 devpriv->command6_bits |= DAC_UNIP_BIT(channel);
1696 else
1697 devpriv->command6_bits &= ~DAC_UNIP_BIT(channel);
f6b49620 1698 /* write to register */
124b13b2 1699 devpriv->write_byte(devpriv->command6_bits,
0a85b6f0 1700 dev->iobase + COMMAND6_REG);
124b13b2 1701 }
e41a6f6d 1702 /* send data */
124b13b2
FMH		 1703 lsb = data[0] & 0xff;
1704 msb = (data[0] >> 8) & 0xff;
1705 devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel));
1706 devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel));
1707
e41a6f6d 1708 /* remember value for readback */
124b13b2
FMH		 1709 devpriv->ao_value[channel] = data[0];
1710
1711 return 1;
1712}
1713
f6b49620 1714/* analog output readback insn */
da91b269 1715static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 1716 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1717{
1718 data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)];
1719
1720 return 1;
1721}
1722
0a85b6f0
MT		 1723static int labpc_calib_read_insn(struct comedi_device *dev,
1724 struct comedi_subdevice *s,
1725 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1726{
1727 data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)];
1728
1729 return 1;
1730}
1731
0a85b6f0
MT		 1732static int labpc_calib_write_insn(struct comedi_device *dev,
1733 struct comedi_subdevice *s,
1734 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1735{
1736 int channel = CR_CHAN(insn->chanspec);
1737
1738 write_caldac(dev, channel, data[0]);
1739 return 1;
1740}
1741
0a85b6f0
MT		 1742static int labpc_eeprom_read_insn(struct comedi_device *dev,
1743 struct comedi_subdevice *s,
1744 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1745{
1746 data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)];
1747
1748 return 1;
1749}
1750
0a85b6f0
MT		 1751static int labpc_eeprom_write_insn(struct comedi_device *dev,
1752 struct comedi_subdevice *s,
1753 struct comedi_insn *insn, unsigned int *data)
124b13b2
FMH		 1754{
1755 int channel = CR_CHAN(insn->chanspec);
1756 int ret;
1757
f6b49620 1758 /* only allow writes to user area of eeprom */
124b13b2 1759 if (channel < 16 || channel > 127) {
0a85b6f0
MT		 1760 printk
1761 ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)");
124b13b2
FMH		 1762 return -EINVAL;
1763 }
1764
1765 ret = labpc_eeprom_write(dev, channel, data[0]);
1766 if (ret < 0)
1767 return ret;
1768
1769 return 1;
1770}
1771
f6b49620 1772/* utility function that suggests a dma transfer size in bytes */
ea6d0d4c 1773static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd)
124b13b2
FMH		 1774{
1775 unsigned int size;
1776 unsigned int freq;
1777
1778 if (cmd.convert_src == TRIG_TIMER)
1779 freq = 1000000000 / cmd.convert_arg;
e41a6f6d 1780 /* return some default value */
124b13b2
FMH		 1781 else
1782 freq = 0xffffffff;
1783
e41a6f6d 1784 /* make buffer fill in no more than 1/3 second */
124b13b2
FMH		 1785 size = (freq / 3) * sample_size;
1786
e41a6f6d 1787 /* set a minimum and maximum size allowed */
124b13b2
FMH		 1788 if (size > dma_buffer_size)
1789 size = dma_buffer_size - dma_buffer_size % sample_size;
1790 else if (size < sample_size)
1791 size = sample_size;
1792
1793 return size;
1794}
1795
f6b49620 1796/* figures out what counter values to use based on command */
da91b269 1797static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd)
124b13b2 1798{
e41a6f6d
SR		 1799 /* max value for 16 bit counter in mode 2 */
1800 const int max_counter_value = 0x10000;
1801 /* min value for 16 bit counter in mode 2 */
1802 const int min_counter_value = 2;
124b13b2
FMH		 1803 unsigned int base_period;
1804
e41a6f6d
SR		 1805 /*
1806 * if both convert and scan triggers are TRIG_TIMER, then they
1807 * both rely on counter b0
1808 */
124b13b2 1809 if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) {
e41a6f6d
SR		 1810 /*
1811 * pick the lowest b0 divisor value we can (for maximum input
1812 * clock speed on convert and scan counters)
1813 */
124b13b2 1814 devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) /
0a85b6f0 1815 (LABPC_TIMER_BASE * max_counter_value) + 1;
124b13b2
FMH		 1816 if (devpriv->divisor_b0 < min_counter_value)
1817 devpriv->divisor_b0 = min_counter_value;
1818 if (devpriv->divisor_b0 > max_counter_value)
1819 devpriv->divisor_b0 = max_counter_value;
1820
1821 base_period = LABPC_TIMER_BASE * devpriv->divisor_b0;
1822
f6b49620 1823 /* set a0 for conversion frequency and b1 for scan frequency */
124b13b2
FMH		 1824 switch (cmd->flags & TRIG_ROUND_MASK) {
1825 default:
1826 case TRIG_ROUND_NEAREST:
1827 devpriv->divisor_a0 =
0a85b6f0
MT		 1828 (labpc_ai_convert_period(cmd) +
1829 (base_period / 2)) / base_period;
124b13b2 1830 devpriv->divisor_b1 =
0a85b6f0
MT		 1831 (labpc_ai_scan_period(cmd) +
1832 (base_period / 2)) / base_period;
124b13b2
FMH		 1833 break;
1834 case TRIG_ROUND_UP:
1835 devpriv->divisor_a0 =
0a85b6f0
MT		 1836 (labpc_ai_convert_period(cmd) + (base_period -
1837 1)) / base_period;
124b13b2 1838 devpriv->divisor_b1 =
0a85b6f0
MT		 1839 (labpc_ai_scan_period(cmd) + (base_period -
1840 1)) / base_period;
124b13b2
FMH		 1841 break;
1842 case TRIG_ROUND_DOWN:
1843 devpriv->divisor_a0 =
0a85b6f0 1844 labpc_ai_convert_period(cmd) / base_period;
124b13b2 1845 devpriv->divisor_b1 =
0a85b6f0 1846 labpc_ai_scan_period(cmd) / base_period;
124b13b2
FMH		 1847 break;
1848 }
f6b49620 1849 /* make sure a0 and b1 values are acceptable */
124b13b2
FMH		 1850 if (devpriv->divisor_a0 < min_counter_value)
1851 devpriv->divisor_a0 = min_counter_value;
1852 if (devpriv->divisor_a0 > max_counter_value)
1853 devpriv->divisor_a0 = max_counter_value;
1854 if (devpriv->divisor_b1 < min_counter_value)
1855 devpriv->divisor_b1 = min_counter_value;
1856 if (devpriv->divisor_b1 > max_counter_value)
1857 devpriv->divisor_b1 = max_counter_value;
f6b49620 1858 /* write corrected timings to command */
124b13b2 1859 labpc_set_ai_convert_period(cmd,
0a85b6f0 1860 base_period * devpriv->divisor_a0);
124b13b2 1861 labpc_set_ai_scan_period(cmd,
0a85b6f0 1862 base_period * devpriv->divisor_b1);
e41a6f6d
SR		 1863 /*
1864 * if only one TRIG_TIMER is used, we can employ the generic
1865 * cascaded timing functions
1866 */
124b13b2
FMH		 1867 } else if (labpc_ai_scan_period(cmd)) {
1868 unsigned int scan_period;
1869
1870 scan_period = labpc_ai_scan_period(cmd);
1309e617
MD		 1871 /*
1872 * calculate cascaded counter values
1873 * that give desired scan timing
1874 */
124b13b2 1875 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
0a85b6f0
MT		 1876 &(devpriv->divisor_b1),
1877 &(devpriv->divisor_b0),
1878 &scan_period,
1879 cmd->flags & TRIG_ROUND_MASK);
124b13b2
FMH		 1880 labpc_set_ai_scan_period(cmd, scan_period);
1881 } else if (labpc_ai_convert_period(cmd)) {
1882 unsigned int convert_period;
1883
1884 convert_period = labpc_ai_convert_period(cmd);
1309e617
MD		 1885 /*
1886 * calculate cascaded counter values
1887 * that give desired conversion timing
1888 */
124b13b2 1889 i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE,
0a85b6f0
MT		 1890 &(devpriv->divisor_a0),
1891 &(devpriv->divisor_b0),
1892 &convert_period,
1893 cmd->flags & TRIG_ROUND_MASK);
124b13b2
FMH		 1894 labpc_set_ai_convert_period(cmd, convert_period);
1895 }
1896}
1897
1898static int labpc_dio_mem_callback(int dir, int port, int data,
0a85b6f0 1899 unsigned long iobase)
124b13b2
FMH		 1900{
1901 if (dir) {
1902 writeb(data, (void *)(iobase + port));
1903 return 0;
1904 } else {
1905 return readb((void *)(iobase + port));
1906 }
1907}
1908
f6b49620 1909/* lowlevel write to eeprom/dac */
da91b269 1910static void labpc_serial_out(struct comedi_device *dev, unsigned int value,
0a85b6f0 1911 unsigned int value_width)
124b13b2
FMH		 1912{
1913 int i;
1914
1915 for (i = 1; i <= value_width; i++) {
f6b49620 1916 /* clear serial clock */
124b13b2 1917 devpriv->command5_bits &= ~SCLOCK_BIT;
f6b49620 1918 /* send bits most significant bit first */
124b13b2
FMH		 1919 if (value & (1 << (value_width - i)))
1920 devpriv->command5_bits |= SDATA_BIT;
1921 else
1922 devpriv->command5_bits &= ~SDATA_BIT;
5f74ea14 1923 udelay(1);
124b13b2 1924 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 1925 dev->iobase + COMMAND5_REG);
f6b49620 1926 /* set clock to load bit */
124b13b2 1927 devpriv->command5_bits |= SCLOCK_BIT;
5f74ea14 1928 udelay(1);
124b13b2 1929 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 1930 dev->iobase + COMMAND5_REG);
124b13b2
FMH		 1931 }
1932}
1933
f6b49620 1934/* lowlevel read from eeprom */
da91b269 1935static unsigned int labpc_serial_in(struct comedi_device *dev)
124b13b2
FMH		 1936{
1937 unsigned int value = 0;
1938 int i;
f6b49620 1939 const int value_width = 8; /* number of bits wide values are */
124b13b2
FMH		 1940
1941 for (i = 1; i <= value_width; i++) {
f6b49620 1942 /* set serial clock */
124b13b2 1943 devpriv->command5_bits |= SCLOCK_BIT;
5f74ea14 1944 udelay(1);
124b13b2 1945 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 1946 dev->iobase + COMMAND5_REG);
f6b49620 1947 /* clear clock bit */
124b13b2 1948 devpriv->command5_bits &= ~SCLOCK_BIT;
5f74ea14 1949 udelay(1);
124b13b2 1950 devpriv->write_byte(devpriv->command5_bits,
0a85b6f0 1951 dev->iobase + COMMAND5_REG);
f6b49620 1952 /* read bits most significant bit first */
5f74ea14 1953 udelay(1);
124b13b2 1954 devpriv->status2_bits =
0a85b6f0 1955 devpriv->read_byte(dev->iobase + STATUS2_REG);
412bd046 1956 if (devpriv->status2_bits & EEPROM_OUT_BIT)
124b13b2 1957 value |= 1 << (value_width - i);
124b13b2
FMH		 1958 }
1959
1960 return value;
1961}
1962
0a85b6f0
MT		 1963static unsigned int labpc_eeprom_read(struct comedi_device *dev,
1964 unsigned int address)
124b13b2
FMH		 1965{
1966 unsigned int value;
e41a6f6d
SR		 1967 /* bits to tell eeprom to expect a read */
1968 const int read_instruction = 0x3;
1969 /* 8 bit write lengths to eeprom */
1970 const int write_length = 8;
124b13b2 1971
f6b49620 1972 /* enable read/write to eeprom */
124b13b2 1973 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 1974 udelay(1);
124b13b2
FMH		 1975 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1976 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 1977 udelay(1);
124b13b2
FMH		 1978 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1979
f6b49620 1980 /* send read instruction */
124b13b2 1981 labpc_serial_out(dev, read_instruction, write_length);
f6b49620 1982 /* send 8 bit address to read from */
124b13b2 1983 labpc_serial_out(dev, address, write_length);
f6b49620 1984 /* read result */
124b13b2
FMH		 1985 value = labpc_serial_in(dev);
1986
f6b49620 1987 /* disable read/write to eeprom */
124b13b2 1988 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 1989 udelay(1);
124b13b2
FMH		 1990 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
1991
1992 return value;
1993}
1994
d6269644
JL		 1995static int labpc_eeprom_write(struct comedi_device *dev,
1996 unsigned int address, unsigned int value)
124b13b2
FMH		 1997{
1998 const int write_enable_instruction = 0x6;
1999 const int write_instruction = 0x2;
f6b49620 2000 const int write_length = 8; /* 8 bit write lengths to eeprom */
124b13b2
FMH		 2001 const int write_in_progress_bit = 0x1;
2002 const int timeout = 10000;
2003 int i;
2004
f6b49620 2005 /* make sure there isn't already a write in progress */
124b13b2
FMH		 2006 for (i = 0; i < timeout; i++) {
2007 if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) ==
0a85b6f0 2008 0)
124b13b2
FMH		 2009 break;
2010 }
2011 if (i == timeout) {
2012 comedi_error(dev, "eeprom write timed out");
2013 return -ETIME;
2014 }
f6b49620 2015 /* update software copy of eeprom */
124b13b2
FMH		 2016 devpriv->eeprom_data[address] = value;
2017
f6b49620 2018 /* enable read/write to eeprom */
124b13b2 2019 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 2020 udelay(1);
124b13b2
FMH		 2021 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2022 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2023 udelay(1);
124b13b2
FMH		 2024 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2025
f6b49620 2026 /* send write_enable instruction */
124b13b2
FMH		 2027 labpc_serial_out(dev, write_enable_instruction, write_length);
2028 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 2029 udelay(1);
124b13b2
FMH		 2030 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2031
f6b49620 2032 /* send write instruction */
124b13b2 2033 devpriv->command5_bits |= EEPROM_EN_BIT;
5f74ea14 2034 udelay(1);
124b13b2
FMH		 2035 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2036 labpc_serial_out(dev, write_instruction, write_length);
f6b49620 2037 /* send 8 bit address to write to */
124b13b2 2038 labpc_serial_out(dev, address, write_length);
f6b49620 2039 /* write value */
124b13b2
FMH		 2040 labpc_serial_out(dev, value, write_length);
2041 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 2042 udelay(1);
124b13b2
FMH		 2043 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2044
f6b49620 2045 /* disable read/write to eeprom */
124b13b2 2046 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2047 udelay(1);
124b13b2
FMH		 2048 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2049
2050 return 0;
2051}
2052
da91b269 2053static unsigned int labpc_eeprom_read_status(struct comedi_device *dev)
124b13b2
FMH		 2054{
2055 unsigned int value;
2056 const int read_status_instruction = 0x5;
f6b49620 2057 const int write_length = 8; /* 8 bit write lengths to eeprom */
124b13b2 2058
f6b49620 2059 /* enable read/write to eeprom */
124b13b2 2060 devpriv->command5_bits &= ~EEPROM_EN_BIT;
5f74ea14 2061 udelay(1);
124b13b2
FMH		 2062 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2063 devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2064 udelay(1);
124b13b2
FMH		 2065 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2066
f6b49620 2067 /* send read status instruction */
124b13b2 2068 labpc_serial_out(dev, read_status_instruction, write_length);
f6b49620 2069 /* read result */
124b13b2
FMH		 2070 value = labpc_serial_in(dev);
2071
f6b49620 2072 /* disable read/write to eeprom */
124b13b2 2073 devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2074 udelay(1);
124b13b2
FMH		 2075 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2076
2077 return value;
2078}
2079
f6b49620 2080/* writes to 8 bit calibration dacs */
da91b269 2081static void write_caldac(struct comedi_device *dev, unsigned int channel,
0a85b6f0 2082 unsigned int value)
124b13b2
FMH		 2083{
2084 if (value == devpriv->caldac[channel])
2085 return;
2086 devpriv->caldac[channel] = value;
2087
f6b49620 2088 /* clear caldac load bit and make sure we don't write to eeprom */
124b13b2 2089 devpriv->command5_bits &=
0a85b6f0 2090 ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT;
5f74ea14 2091 udelay(1);
124b13b2
FMH		 2092 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2093
f6b49620 2094 /* write 4 bit channel */
124b13b2 2095 labpc_serial_out(dev, channel, 4);
f6b49620 2096 /* write 8 bit caldac value */
124b13b2
FMH		 2097 labpc_serial_out(dev, value, 8);
2098
f6b49620 2099 /* set and clear caldac bit to load caldac value */
124b13b2 2100 devpriv->command5_bits |= CALDAC_LOAD_BIT;
5f74ea14 2101 udelay(1);
124b13b2
FMH		 2102 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2103 devpriv->command5_bits &= ~CALDAC_LOAD_BIT;
5f74ea14 2104 udelay(1);
124b13b2
FMH		 2105 devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG);
2106}
2107
2108#ifdef CONFIG_COMEDI_PCI
727b286b
AT		 2109static int __devinit driver_labpc_pci_probe(struct pci_dev *dev,
2110 const struct pci_device_id *ent)
2111{
2112 return comedi_pci_auto_config(dev, driver_labpc.driver_name);
2113}
2114
2115static void __devexit driver_labpc_pci_remove(struct pci_dev *dev)
2116{
2117 comedi_pci_auto_unconfig(dev);
2118}
2119
2120static struct pci_driver driver_labpc_pci_driver = {
2121 .id_table = labpc_pci_table,
2122 .probe = &driver_labpc_pci_probe,
2123 .remove = __devexit_p(&driver_labpc_pci_remove)
2124};
2125
2126static int __init driver_labpc_init_module(void)
2127{
2128 int retval;
2129
2130 retval = comedi_driver_register(&driver_labpc);
2131 if (retval < 0)
2132 return retval;
2133
2134 driver_labpc_pci_driver.name = (char *)driver_labpc.driver_name;
2135 return pci_register_driver(&driver_labpc_pci_driver);
2136}
2137
2138static void __exit driver_labpc_cleanup_module(void)
2139{
2140 pci_unregister_driver(&driver_labpc_pci_driver);
2141 comedi_driver_unregister(&driver_labpc);
2142}
2143
2144module_init(driver_labpc_init_module);
2145module_exit(driver_labpc_cleanup_module);
124b13b2 2146#else
7114a280
AT		 2147static int __init driver_labpc_init_module(void)
2148{
2149 return comedi_driver_register(&driver_labpc);
2150}
2151
2152static void __exit driver_labpc_cleanup_module(void)
2153{
2154 comedi_driver_unregister(&driver_labpc);
2155}
2156
2157module_init(driver_labpc_init_module);
2158module_exit(driver_labpc_cleanup_module);
124b13b2
FMH		 2159#endif
2160
90f703d3
AT		 2161
2162MODULE_AUTHOR("Comedi http://www.comedi.org");
2163MODULE_DESCRIPTION("Comedi low-level driver");
2164MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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