Commit | Line | Data |
---|---|---|
124b13b2 FMH |
1 | /* |
2 | comedi/drivers/ni_labpc.c | |
3 | Driver for National Instruments Lab-PC series boards and compatibles | |
4 | Copyright (C) 2001, 2002, 2003 Frank Mori Hess <fmhess@users.sourceforge.net> | |
5 | ||
6 | This program is free software; you can redistribute it and/or modify | |
7 | it under the terms of the GNU General Public License as published by | |
8 | the Free Software Foundation; either version 2 of the License, or | |
9 | (at your option) any later version. | |
10 | ||
11 | This program is distributed in the hope that it will be useful, | |
12 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | GNU General Public License for more details. | |
15 | ||
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | ||
20 | ************************************************************************ | |
21 | */ | |
22 | /* | |
23 | Driver: ni_labpc | |
24 | Description: National Instruments Lab-PC (& compatibles) | |
25 | Author: Frank Mori Hess <fmhess@users.sourceforge.net> | |
26 | Devices: [National Instruments] Lab-PC-1200 (labpc-1200), | |
27 | Lab-PC-1200AI (labpc-1200ai), Lab-PC+ (lab-pc+), PCI-1200 (ni_labpc) | |
28 | Status: works | |
29 | ||
30 | Tested with lab-pc-1200. For the older Lab-PC+, not all input ranges | |
31 | and analog references will work, the available ranges/arefs will | |
32 | depend on how you have configured the jumpers on your board | |
33 | (see your owner's manual). | |
34 | ||
35 | Kernel-level ISA plug-and-play support for the lab-pc-1200 | |
36 | boards has not | |
37 | yet been added to the driver, mainly due to the fact that | |
38 | I don't know the device id numbers. If you have one | |
39 | of these boards, | |
631dd1a8 | 40 | please file a bug report at http://comedi.org/ |
124b13b2 FMH |
41 | so I can get the necessary information from you. |
42 | ||
43 | The 1200 series boards have onboard calibration dacs for correcting | |
44 | analog input/output offsets and gains. The proper settings for these | |
45 | caldacs are stored on the board's eeprom. To read the caldac values | |
46 | from the eeprom and store them into a file that can be then be used by | |
47 | comedilib, use the comedi_calibrate program. | |
48 | ||
49 | Configuration options - ISA boards: | |
50 | [0] - I/O port base address | |
51 | [1] - IRQ (optional, required for timed or externally triggered conversions) | |
52 | [2] - DMA channel (optional) | |
53 | ||
54 | Configuration options - PCI boards: | |
55 | [0] - bus (optional) | |
56 | [1] - slot (optional) | |
57 | ||
58 | The Lab-pc+ has quirky chanlist requirements | |
59 | when scanning multiple channels. Multiple channel scan | |
60 | sequence must start at highest channel, then decrement down to | |
61 | channel 0. The rest of the cards can scan down like lab-pc+ or scan | |
62 | up from channel zero. Chanlists consisting of all one channel | |
63 | are also legal, and allow you to pace conversions in bursts. | |
64 | ||
65 | */ | |
66 | ||
67 | /* | |
68 | ||
69 | NI manuals: | |
70 | 341309a (labpc-1200 register manual) | |
71 | 340914a (pci-1200) | |
72 | 320502b (lab-pc+) | |
73 | ||
74 | */ | |
75 | ||
76 | #undef LABPC_DEBUG | |
f6b49620 | 77 | /* #define LABPC_DEBUG enable debugging messages */ |
124b13b2 | 78 | |
25436dc9 | 79 | #include <linux/interrupt.h> |
5a0e3ad6 | 80 | #include <linux/slab.h> |
845d131e | 81 | #include <linux/io.h> |
124b13b2 FMH |
82 | #include "../comedidev.h" |
83 | ||
84 | #include <linux/delay.h> | |
85 | #include <asm/dma.h> | |
86 | ||
87 | #include "8253.h" | |
88 | #include "8255.h" | |
89 | #include "mite.h" | |
90 | #include "comedi_fc.h" | |
91 | #include "ni_labpc.h" | |
92 | ||
93 | #define DRV_NAME "ni_labpc" | |
94 | ||
e41a6f6d SR |
95 | /* size of io region used by board */ |
96 | #define LABPC_SIZE 32 | |
97 | /* 2 MHz master clock */ | |
98 | #define LABPC_TIMER_BASE 500 | |
124b13b2 FMH |
99 | |
100 | /* Registers for the lab-pc+ */ | |
101 | ||
f6b49620 | 102 | /* write-only registers */ |
124b13b2 FMH |
103 | #define COMMAND1_REG 0x0 |
104 | #define ADC_GAIN_MASK (0x7 << 4) | |
105 | #define ADC_CHAN_BITS(x) ((x) & 0x7) | |
e41a6f6d SR |
106 | /* enables multi channel scans */ |
107 | #define ADC_SCAN_EN_BIT 0x80 | |
124b13b2 | 108 | #define COMMAND2_REG 0x1 |
e41a6f6d SR |
109 | /* enable pretriggering (used in conjunction with SWTRIG) */ |
110 | #define PRETRIG_BIT 0x1 | |
111 | /* enable paced conversions on external trigger */ | |
112 | #define HWTRIG_BIT 0x2 | |
113 | /* enable paced conversions */ | |
114 | #define SWTRIG_BIT 0x4 | |
115 | /* use two cascaded counters for pacing */ | |
116 | #define CASCADE_BIT 0x8 | |
124b13b2 FMH |
117 | #define DAC_PACED_BIT(channel) (0x40 << ((channel) & 0x1)) |
118 | #define COMMAND3_REG 0x2 | |
e41a6f6d SR |
119 | /* enable dma transfers */ |
120 | #define DMA_EN_BIT 0x1 | |
121 | /* enable interrupts for 8255 */ | |
122 | #define DIO_INTR_EN_BIT 0x2 | |
123 | /* enable dma terminal count interrupt */ | |
124 | #define DMATC_INTR_EN_BIT 0x4 | |
125 | /* enable timer interrupt */ | |
126 | #define TIMER_INTR_EN_BIT 0x8 | |
127 | /* enable error interrupt */ | |
128 | #define ERR_INTR_EN_BIT 0x10 | |
129 | /* enable fifo not empty interrupt */ | |
130 | #define ADC_FNE_INTR_EN_BIT 0x20 | |
124b13b2 FMH |
131 | #define ADC_CONVERT_REG 0x3 |
132 | #define DAC_LSB_REG(channel) (0x4 + 2 * ((channel) & 0x1)) | |
133 | #define DAC_MSB_REG(channel) (0x5 + 2 * ((channel) & 0x1)) | |
134 | #define ADC_CLEAR_REG 0x8 | |
135 | #define DMATC_CLEAR_REG 0xa | |
136 | #define TIMER_CLEAR_REG 0xc | |
e41a6f6d SR |
137 | /* 1200 boards only */ |
138 | #define COMMAND6_REG 0xe | |
139 | /* select ground or common-mode reference */ | |
140 | #define ADC_COMMON_BIT 0x1 | |
141 | /* adc unipolar */ | |
142 | #define ADC_UNIP_BIT 0x2 | |
143 | /* dac unipolar */ | |
144 | #define DAC_UNIP_BIT(channel) (0x4 << ((channel) & 0x1)) | |
145 | /* enable fifo half full interrupt */ | |
146 | #define ADC_FHF_INTR_EN_BIT 0x20 | |
147 | /* enable interrupt on end of hardware count */ | |
148 | #define A1_INTR_EN_BIT 0x40 | |
149 | /* scan up from channel zero instead of down to zero */ | |
150 | #define ADC_SCAN_UP_BIT 0x80 | |
124b13b2 | 151 | #define COMMAND4_REG 0xf |
e41a6f6d SR |
152 | /* enables 'interval' scanning */ |
153 | #define INTERVAL_SCAN_EN_BIT 0x1 | |
154 | /* enables external signal on counter b1 output to trigger scan */ | |
155 | #define EXT_SCAN_EN_BIT 0x2 | |
156 | /* chooses direction (output or input) for EXTCONV* line */ | |
157 | #define EXT_CONVERT_OUT_BIT 0x4 | |
158 | /* chooses differential inputs for adc (in conjunction with board jumper) */ | |
159 | #define ADC_DIFF_BIT 0x8 | |
124b13b2 | 160 | #define EXT_CONVERT_DISABLE_BIT 0x10 |
e41a6f6d SR |
161 | /* 1200 boards only, calibration stuff */ |
162 | #define COMMAND5_REG 0x1c | |
163 | /* enable eeprom for write */ | |
164 | #define EEPROM_WRITE_UNPROTECT_BIT 0x4 | |
165 | /* enable dithering */ | |
166 | #define DITHER_EN_BIT 0x8 | |
167 | /* load calibration dac */ | |
168 | #define CALDAC_LOAD_BIT 0x10 | |
169 | /* serial clock - rising edge writes, falling edge reads */ | |
170 | #define SCLOCK_BIT 0x20 | |
171 | /* serial data bit for writing to eeprom or calibration dacs */ | |
172 | #define SDATA_BIT 0x40 | |
173 | /* enable eeprom for read/write */ | |
174 | #define EEPROM_EN_BIT 0x80 | |
124b13b2 FMH |
175 | #define INTERVAL_COUNT_REG 0x1e |
176 | #define INTERVAL_LOAD_REG 0x1f | |
177 | #define INTERVAL_LOAD_BITS 0x1 | |
178 | ||
f6b49620 | 179 | /* read-only registers */ |
124b13b2 | 180 | #define STATUS1_REG 0x0 |
e41a6f6d SR |
181 | /* data is available in fifo */ |
182 | #define DATA_AVAIL_BIT 0x1 | |
183 | /* overrun has occurred */ | |
184 | #define OVERRUN_BIT 0x2 | |
185 | /* fifo overflow */ | |
186 | #define OVERFLOW_BIT 0x4 | |
25985edc | 187 | /* timer interrupt has occurred */ |
e41a6f6d | 188 | #define TIMER_BIT 0x8 |
25985edc | 189 | /* dma terminal count has occurred */ |
e41a6f6d | 190 | #define DMATC_BIT 0x10 |
25985edc | 191 | /* external trigger has occurred */ |
e41a6f6d SR |
192 | #define EXT_TRIG_BIT 0x40 |
193 | /* 1200 boards only */ | |
194 | #define STATUS2_REG 0x1d | |
195 | /* programmable eeprom serial output */ | |
196 | #define EEPROM_OUT_BIT 0x1 | |
197 | /* counter A1 terminal count */ | |
198 | #define A1_TC_BIT 0x2 | |
199 | /* fifo not half full */ | |
200 | #define FNHF_BIT 0x4 | |
124b13b2 FMH |
201 | #define ADC_FIFO_REG 0xa |
202 | ||
203 | #define DIO_BASE_REG 0x10 | |
204 | #define COUNTER_A_BASE_REG 0x14 | |
205 | #define COUNTER_A_CONTROL_REG (COUNTER_A_BASE_REG + 0x3) | |
e41a6f6d SR |
206 | /* check modes put conversion pacer output in harmless state (a0 mode 2) */ |
207 | #define INIT_A0_BITS 0x14 | |
208 | /* put hardware conversion counter output in harmless state (a1 mode 0) */ | |
209 | #define INIT_A1_BITS 0x70 | |
124b13b2 FMH |
210 | #define COUNTER_B_BASE_REG 0x18 |
211 | ||
814900c9 BP |
212 | static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it); |
213 | static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s); | |
70265d24 | 214 | static irqreturn_t labpc_interrupt(int irq, void *d); |
814900c9 | 215 | static int labpc_drain_fifo(struct comedi_device *dev); |
3297d6c7 | 216 | #ifdef CONFIG_ISA_DMA_API |
814900c9 BP |
217 | static void labpc_drain_dma(struct comedi_device *dev); |
218 | static void handle_isa_dma(struct comedi_device *dev); | |
3297d6c7 | 219 | #endif |
814900c9 | 220 | static void labpc_drain_dregs(struct comedi_device *dev); |
0a85b6f0 MT |
221 | static int labpc_ai_cmdtest(struct comedi_device *dev, |
222 | struct comedi_subdevice *s, struct comedi_cmd *cmd); | |
814900c9 BP |
223 | static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s); |
224 | static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, | |
0a85b6f0 | 225 | struct comedi_insn *insn, unsigned int *data); |
814900c9 | 226 | static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 227 | struct comedi_insn *insn, unsigned int *data); |
814900c9 | 228 | static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 MT |
229 | struct comedi_insn *insn, unsigned int *data); |
230 | static int labpc_calib_read_insn(struct comedi_device *dev, | |
231 | struct comedi_subdevice *s, | |
232 | struct comedi_insn *insn, unsigned int *data); | |
233 | static int labpc_calib_write_insn(struct comedi_device *dev, | |
234 | struct comedi_subdevice *s, | |
235 | struct comedi_insn *insn, unsigned int *data); | |
236 | static int labpc_eeprom_read_insn(struct comedi_device *dev, | |
237 | struct comedi_subdevice *s, | |
238 | struct comedi_insn *insn, unsigned int *data); | |
239 | static int labpc_eeprom_write_insn(struct comedi_device *dev, | |
240 | struct comedi_subdevice *s, | |
241 | struct comedi_insn *insn, | |
242 | unsigned int *data); | |
814900c9 | 243 | static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd); |
d6aa8366 | 244 | #ifdef CONFIG_ISA_DMA_API |
3297d6c7 | 245 | static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd); |
d6aa8366 RD |
246 | #endif |
247 | #ifdef CONFIG_COMEDI_PCI_DRIVERS | |
71b5f4f1 | 248 | static int labpc_find_device(struct comedi_device *dev, int bus, int slot); |
124b13b2 FMH |
249 | #endif |
250 | static int labpc_dio_mem_callback(int dir, int port, int data, | |
0a85b6f0 | 251 | unsigned long arg); |
814900c9 | 252 | static void labpc_serial_out(struct comedi_device *dev, unsigned int value, |
0a85b6f0 | 253 | unsigned int num_bits); |
814900c9 BP |
254 | static unsigned int labpc_serial_in(struct comedi_device *dev); |
255 | static unsigned int labpc_eeprom_read(struct comedi_device *dev, | |
0a85b6f0 | 256 | unsigned int address); |
814900c9 | 257 | static unsigned int labpc_eeprom_read_status(struct comedi_device *dev); |
d6269644 | 258 | static int labpc_eeprom_write(struct comedi_device *dev, |
0a85b6f0 MT |
259 | unsigned int address, |
260 | unsigned int value); | |
814900c9 | 261 | static void write_caldac(struct comedi_device *dev, unsigned int channel, |
0a85b6f0 | 262 | unsigned int value); |
124b13b2 FMH |
263 | |
264 | enum scan_mode { | |
265 | MODE_SINGLE_CHAN, | |
266 | MODE_SINGLE_CHAN_INTERVAL, | |
267 | MODE_MULT_CHAN_UP, | |
268 | MODE_MULT_CHAN_DOWN, | |
269 | }; | |
270 | ||
f6b49620 | 271 | /* analog input ranges */ |
124b13b2 | 272 | #define NUM_LABPC_PLUS_AI_RANGES 16 |
f6b49620 | 273 | /* indicates unipolar ranges */ |
124b13b2 FMH |
274 | static const int labpc_plus_is_unipolar[NUM_LABPC_PLUS_AI_RANGES] = { |
275 | 0, | |
276 | 0, | |
277 | 0, | |
278 | 0, | |
279 | 0, | |
280 | 0, | |
281 | 0, | |
282 | 0, | |
283 | 1, | |
284 | 1, | |
285 | 1, | |
286 | 1, | |
287 | 1, | |
288 | 1, | |
289 | 1, | |
290 | 1, | |
291 | }; | |
292 | ||
f6b49620 | 293 | /* map range index to gain bits */ |
124b13b2 FMH |
294 | static const int labpc_plus_ai_gain_bits[NUM_LABPC_PLUS_AI_RANGES] = { |
295 | 0x00, | |
296 | 0x10, | |
297 | 0x20, | |
298 | 0x30, | |
299 | 0x40, | |
300 | 0x50, | |
301 | 0x60, | |
302 | 0x70, | |
303 | 0x00, | |
304 | 0x10, | |
305 | 0x20, | |
306 | 0x30, | |
307 | 0x40, | |
308 | 0x50, | |
309 | 0x60, | |
310 | 0x70, | |
311 | }; | |
0a85b6f0 | 312 | |
9ced1de6 | 313 | static const struct comedi_lrange range_labpc_plus_ai = { |
124b13b2 FMH |
314 | NUM_LABPC_PLUS_AI_RANGES, |
315 | { | |
0a85b6f0 MT |
316 | BIP_RANGE(5), |
317 | BIP_RANGE(4), | |
318 | BIP_RANGE(2.5), | |
319 | BIP_RANGE(1), | |
320 | BIP_RANGE(0.5), | |
321 | BIP_RANGE(0.25), | |
322 | BIP_RANGE(0.1), | |
323 | BIP_RANGE(0.05), | |
324 | UNI_RANGE(10), | |
325 | UNI_RANGE(8), | |
326 | UNI_RANGE(5), | |
327 | UNI_RANGE(2), | |
328 | UNI_RANGE(1), | |
329 | UNI_RANGE(0.5), | |
330 | UNI_RANGE(0.2), | |
331 | UNI_RANGE(0.1), | |
332 | } | |
124b13b2 FMH |
333 | }; |
334 | ||
335 | #define NUM_LABPC_1200_AI_RANGES 14 | |
f6b49620 | 336 | /* indicates unipolar ranges */ |
124b13b2 FMH |
337 | const int labpc_1200_is_unipolar[NUM_LABPC_1200_AI_RANGES] = { |
338 | 0, | |
339 | 0, | |
340 | 0, | |
341 | 0, | |
342 | 0, | |
343 | 0, | |
344 | 0, | |
345 | 1, | |
346 | 1, | |
347 | 1, | |
348 | 1, | |
349 | 1, | |
350 | 1, | |
351 | 1, | |
352 | }; | |
0656bb35 | 353 | EXPORT_SYMBOL_GPL(labpc_1200_is_unipolar); |
124b13b2 | 354 | |
f6b49620 | 355 | /* map range index to gain bits */ |
124b13b2 FMH |
356 | const int labpc_1200_ai_gain_bits[NUM_LABPC_1200_AI_RANGES] = { |
357 | 0x00, | |
358 | 0x20, | |
359 | 0x30, | |
360 | 0x40, | |
361 | 0x50, | |
362 | 0x60, | |
363 | 0x70, | |
364 | 0x00, | |
365 | 0x20, | |
366 | 0x30, | |
367 | 0x40, | |
368 | 0x50, | |
369 | 0x60, | |
370 | 0x70, | |
371 | }; | |
0656bb35 | 372 | EXPORT_SYMBOL_GPL(labpc_1200_ai_gain_bits); |
0a85b6f0 | 373 | |
9ced1de6 | 374 | const struct comedi_lrange range_labpc_1200_ai = { |
124b13b2 FMH |
375 | NUM_LABPC_1200_AI_RANGES, |
376 | { | |
0a85b6f0 MT |
377 | BIP_RANGE(5), |
378 | BIP_RANGE(2.5), | |
379 | BIP_RANGE(1), | |
380 | BIP_RANGE(0.5), | |
381 | BIP_RANGE(0.25), | |
382 | BIP_RANGE(0.1), | |
383 | BIP_RANGE(0.05), | |
384 | UNI_RANGE(10), | |
385 | UNI_RANGE(5), | |
386 | UNI_RANGE(2), | |
387 | UNI_RANGE(1), | |
388 | UNI_RANGE(0.5), | |
389 | UNI_RANGE(0.2), | |
390 | UNI_RANGE(0.1), | |
391 | } | |
124b13b2 | 392 | }; |
0656bb35 | 393 | EXPORT_SYMBOL_GPL(range_labpc_1200_ai); |
124b13b2 | 394 | |
f6b49620 | 395 | /* analog output ranges */ |
124b13b2 | 396 | #define AO_RANGE_IS_UNIPOLAR 0x1 |
9ced1de6 | 397 | static const struct comedi_lrange range_labpc_ao = { |
124b13b2 FMH |
398 | 2, |
399 | { | |
0a85b6f0 MT |
400 | BIP_RANGE(5), |
401 | UNI_RANGE(10), | |
402 | } | |
124b13b2 FMH |
403 | }; |
404 | ||
405 | /* functions that do inb/outb and readb/writeb so we can use | |
406 | * function pointers to decide which to use */ | |
407 | static inline unsigned int labpc_inb(unsigned long address) | |
408 | { | |
409 | return inb(address); | |
410 | } | |
0a85b6f0 | 411 | |
124b13b2 FMH |
412 | static inline void labpc_outb(unsigned int byte, unsigned long address) |
413 | { | |
414 | outb(byte, address); | |
415 | } | |
0a85b6f0 | 416 | |
124b13b2 FMH |
417 | static inline unsigned int labpc_readb(unsigned long address) |
418 | { | |
419 | return readb((void *)address); | |
420 | } | |
0a85b6f0 | 421 | |
124b13b2 FMH |
422 | static inline void labpc_writeb(unsigned int byte, unsigned long address) |
423 | { | |
424 | writeb(byte, (void *)address); | |
425 | } | |
426 | ||
9ad00740 | 427 | static const struct labpc_board_struct labpc_boards[] = { |
124b13b2 | 428 | { |
0a85b6f0 MT |
429 | .name = "lab-pc-1200", |
430 | .ai_speed = 10000, | |
431 | .bustype = isa_bustype, | |
432 | .register_layout = labpc_1200_layout, | |
433 | .has_ao = 1, | |
434 | .ai_range_table = &range_labpc_1200_ai, | |
435 | .ai_range_code = labpc_1200_ai_gain_bits, | |
436 | .ai_range_is_unipolar = labpc_1200_is_unipolar, | |
437 | .ai_scan_up = 1, | |
438 | .memory_mapped_io = 0, | |
439 | }, | |
124b13b2 | 440 | { |
0a85b6f0 MT |
441 | .name = "lab-pc-1200ai", |
442 | .ai_speed = 10000, | |
443 | .bustype = isa_bustype, | |
444 | .register_layout = labpc_1200_layout, | |
445 | .has_ao = 0, | |
446 | .ai_range_table = &range_labpc_1200_ai, | |
447 | .ai_range_code = labpc_1200_ai_gain_bits, | |
448 | .ai_range_is_unipolar = labpc_1200_is_unipolar, | |
449 | .ai_scan_up = 1, | |
450 | .memory_mapped_io = 0, | |
451 | }, | |
124b13b2 | 452 | { |
0a85b6f0 MT |
453 | .name = "lab-pc+", |
454 | .ai_speed = 12000, | |
455 | .bustype = isa_bustype, | |
456 | .register_layout = labpc_plus_layout, | |
457 | .has_ao = 1, | |
458 | .ai_range_table = &range_labpc_plus_ai, | |
459 | .ai_range_code = labpc_plus_ai_gain_bits, | |
460 | .ai_range_is_unipolar = labpc_plus_is_unipolar, | |
461 | .ai_scan_up = 0, | |
462 | .memory_mapped_io = 0, | |
463 | }, | |
d6aa8366 | 464 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
124b13b2 | 465 | { |
0a85b6f0 MT |
466 | .name = "pci-1200", |
467 | .device_id = 0x161, | |
468 | .ai_speed = 10000, | |
469 | .bustype = pci_bustype, | |
470 | .register_layout = labpc_1200_layout, | |
471 | .has_ao = 1, | |
472 | .ai_range_table = &range_labpc_1200_ai, | |
473 | .ai_range_code = labpc_1200_ai_gain_bits, | |
474 | .ai_range_is_unipolar = labpc_1200_is_unipolar, | |
475 | .ai_scan_up = 1, | |
476 | .memory_mapped_io = 1, | |
477 | }, | |
e41a6f6d | 478 | /* dummy entry so pci board works when comedi_config is passed driver name */ |
124b13b2 | 479 | { |
0a85b6f0 MT |
480 | .name = DRV_NAME, |
481 | .bustype = pci_bustype, | |
482 | }, | |
124b13b2 FMH |
483 | #endif |
484 | }; | |
485 | ||
486 | /* | |
487 | * Useful for shorthand access to the particular board structure | |
488 | */ | |
9ad00740 | 489 | #define thisboard ((struct labpc_board_struct *)dev->board_ptr) |
124b13b2 | 490 | |
e41a6f6d SR |
491 | /* size in bytes of dma buffer */ |
492 | static const int dma_buffer_size = 0xff00; | |
493 | /* 2 bytes per sample */ | |
494 | static const int sample_size = 2; | |
124b13b2 | 495 | |
0a4eb4b6 | 496 | #define devpriv ((struct labpc_private *)dev->private) |
124b13b2 | 497 | |
139dfbdf | 498 | static struct comedi_driver driver_labpc = { |
124b13b2 FMH |
499 | .driver_name = DRV_NAME, |
500 | .module = THIS_MODULE, | |
501 | .attach = labpc_attach, | |
502 | .detach = labpc_common_detach, | |
8629efa4 | 503 | .num_names = ARRAY_SIZE(labpc_boards), |
124b13b2 | 504 | .board_name = &labpc_boards[0].name, |
9ad00740 | 505 | .offset = sizeof(struct labpc_board_struct), |
124b13b2 FMH |
506 | }; |
507 | ||
d6aa8366 | 508 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
124b13b2 | 509 | static DEFINE_PCI_DEVICE_TABLE(labpc_pci_table) = { |
4e40cee9 GKH |
510 | {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x161)}, |
511 | {0} | |
124b13b2 FMH |
512 | }; |
513 | ||
514 | MODULE_DEVICE_TABLE(pci, labpc_pci_table); | |
d6aa8366 | 515 | #endif /* CONFIG_COMEDI_PCI_DRIVERS */ |
124b13b2 | 516 | |
da91b269 | 517 | static inline int labpc_counter_load(struct comedi_device *dev, |
0a85b6f0 MT |
518 | unsigned long base_address, |
519 | unsigned int counter_number, | |
520 | unsigned int count, unsigned int mode) | |
124b13b2 FMH |
521 | { |
522 | if (thisboard->memory_mapped_io) | |
523 | return i8254_mm_load((void *)base_address, 0, counter_number, | |
0a85b6f0 | 524 | count, mode); |
124b13b2 FMH |
525 | else |
526 | return i8254_load(base_address, 0, counter_number, count, mode); | |
527 | } | |
528 | ||
da91b269 | 529 | int labpc_common_attach(struct comedi_device *dev, unsigned long iobase, |
0a85b6f0 | 530 | unsigned int irq, unsigned int dma_chan) |
124b13b2 | 531 | { |
34c43922 | 532 | struct comedi_subdevice *s; |
124b13b2 | 533 | int i; |
3297d6c7 RD |
534 | unsigned long isr_flags; |
535 | #ifdef CONFIG_ISA_DMA_API | |
536 | unsigned long dma_flags; | |
537 | #endif | |
124b13b2 | 538 | short lsb, msb; |
8b6c5694 | 539 | int ret; |
124b13b2 | 540 | |
88d8ed4b MD |
541 | printk(KERN_ERR "comedi%d: ni_labpc: %s, io 0x%lx", dev->minor, |
542 | thisboard->name, | |
0a85b6f0 | 543 | iobase); |
412bd046 | 544 | if (irq) |
124b13b2 | 545 | printk(", irq %u", irq); |
412bd046 | 546 | if (dma_chan) |
124b13b2 | 547 | printk(", dma %u", dma_chan); |
124b13b2 FMH |
548 | printk("\n"); |
549 | ||
550 | if (iobase == 0) { | |
177d4282 | 551 | printk(KERN_ERR "io base address is zero!\n"); |
124b13b2 FMH |
552 | return -EINVAL; |
553 | } | |
f6b49620 | 554 | /* request io regions for isa boards */ |
124b13b2 FMH |
555 | if (thisboard->bustype == isa_bustype) { |
556 | /* check if io addresses are available */ | |
557 | if (!request_region(iobase, LABPC_SIZE, | |
0a85b6f0 | 558 | driver_labpc.driver_name)) { |
88d8ed4b | 559 | printk(KERN_ERR "I/O port conflict\n"); |
124b13b2 FMH |
560 | return -EIO; |
561 | } | |
562 | } | |
563 | dev->iobase = iobase; | |
564 | ||
565 | if (thisboard->memory_mapped_io) { | |
566 | devpriv->read_byte = labpc_readb; | |
567 | devpriv->write_byte = labpc_writeb; | |
568 | } else { | |
569 | devpriv->read_byte = labpc_inb; | |
570 | devpriv->write_byte = labpc_outb; | |
571 | } | |
e41a6f6d | 572 | /* initialize board's command registers */ |
124b13b2 FMH |
573 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); |
574 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
575 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
576 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); | |
577 | if (thisboard->register_layout == labpc_1200_layout) { | |
578 | devpriv->write_byte(devpriv->command5_bits, | |
0a85b6f0 | 579 | dev->iobase + COMMAND5_REG); |
124b13b2 | 580 | devpriv->write_byte(devpriv->command6_bits, |
0a85b6f0 | 581 | dev->iobase + COMMAND6_REG); |
124b13b2 FMH |
582 | } |
583 | ||
584 | /* grab our IRQ */ | |
585 | if (irq) { | |
586 | isr_flags = 0; | |
d1ce3184 IA |
587 | if (thisboard->bustype == pci_bustype |
588 | || thisboard->bustype == pcmcia_bustype) | |
124b13b2 | 589 | isr_flags |= IRQF_SHARED; |
5f74ea14 | 590 | if (request_irq(irq, labpc_interrupt, isr_flags, |
124b13b2 | 591 | driver_labpc.driver_name, dev)) { |
88d8ed4b | 592 | printk(KERN_ERR "unable to allocate irq %u\n", irq); |
124b13b2 FMH |
593 | return -EINVAL; |
594 | } | |
595 | } | |
596 | dev->irq = irq; | |
597 | ||
3297d6c7 | 598 | #ifdef CONFIG_ISA_DMA_API |
e41a6f6d | 599 | /* grab dma channel */ |
124b13b2 | 600 | if (dma_chan > 3) { |
88d8ed4b | 601 | printk(KERN_ERR " invalid dma channel %u\n", dma_chan); |
124b13b2 FMH |
602 | return -EINVAL; |
603 | } else if (dma_chan) { | |
e41a6f6d | 604 | /* allocate dma buffer */ |
124b13b2 | 605 | devpriv->dma_buffer = |
0a85b6f0 | 606 | kmalloc(dma_buffer_size, GFP_KERNEL | GFP_DMA); |
124b13b2 | 607 | if (devpriv->dma_buffer == NULL) { |
88d8ed4b | 608 | printk(KERN_ERR " failed to allocate dma buffer\n"); |
124b13b2 FMH |
609 | return -ENOMEM; |
610 | } | |
611 | if (request_dma(dma_chan, driver_labpc.driver_name)) { | |
88d8ed4b | 612 | printk(KERN_ERR " failed to allocate dma channel %u\n", |
0a85b6f0 | 613 | dma_chan); |
124b13b2 FMH |
614 | return -EINVAL; |
615 | } | |
616 | devpriv->dma_chan = dma_chan; | |
617 | dma_flags = claim_dma_lock(); | |
618 | disable_dma(devpriv->dma_chan); | |
619 | set_dma_mode(devpriv->dma_chan, DMA_MODE_READ); | |
620 | release_dma_lock(dma_flags); | |
621 | } | |
3297d6c7 | 622 | #endif |
124b13b2 FMH |
623 | |
624 | dev->board_name = thisboard->name; | |
625 | ||
8b6c5694 HS |
626 | ret = comedi_alloc_subdevices(dev, 5); |
627 | if (ret) | |
628 | return ret; | |
124b13b2 FMH |
629 | |
630 | /* analog input subdevice */ | |
c65e3be1 | 631 | s = &dev->subdevices[0]; |
124b13b2 FMH |
632 | dev->read_subdev = s; |
633 | s->type = COMEDI_SUBD_AI; | |
634 | s->subdev_flags = | |
0a85b6f0 | 635 | SDF_READABLE | SDF_GROUND | SDF_COMMON | SDF_DIFF | SDF_CMD_READ; |
124b13b2 FMH |
636 | s->n_chan = 8; |
637 | s->len_chanlist = 8; | |
e41a6f6d | 638 | s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ |
124b13b2 FMH |
639 | s->range_table = thisboard->ai_range_table; |
640 | s->do_cmd = labpc_ai_cmd; | |
641 | s->do_cmdtest = labpc_ai_cmdtest; | |
642 | s->insn_read = labpc_ai_rinsn; | |
643 | s->cancel = labpc_cancel; | |
644 | ||
645 | /* analog output */ | |
c65e3be1 | 646 | s = &dev->subdevices[1]; |
124b13b2 | 647 | if (thisboard->has_ao) { |
639b9f1e SR |
648 | /* |
649 | * Could provide command support, except it only has a | |
412bd046 | 650 | * one sample hardware buffer for analog output and no |
639b9f1e SR |
651 | * underrun flag. |
652 | */ | |
124b13b2 FMH |
653 | s->type = COMEDI_SUBD_AO; |
654 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_GROUND; | |
655 | s->n_chan = NUM_AO_CHAN; | |
f6b49620 | 656 | s->maxdata = (1 << 12) - 1; /* 12 bit resolution */ |
124b13b2 FMH |
657 | s->range_table = &range_labpc_ao; |
658 | s->insn_read = labpc_ao_rinsn; | |
659 | s->insn_write = labpc_ao_winsn; | |
660 | /* initialize analog outputs to a known value */ | |
661 | for (i = 0; i < s->n_chan; i++) { | |
662 | devpriv->ao_value[i] = s->maxdata / 2; | |
663 | lsb = devpriv->ao_value[i] & 0xff; | |
664 | msb = (devpriv->ao_value[i] >> 8) & 0xff; | |
665 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(i)); | |
666 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(i)); | |
667 | } | |
668 | } else { | |
669 | s->type = COMEDI_SUBD_UNUSED; | |
670 | } | |
671 | ||
672 | /* 8255 dio */ | |
c65e3be1 | 673 | s = &dev->subdevices[2]; |
412bd046 | 674 | /* if board uses io memory we have to give a custom callback |
675 | * function to the 8255 driver */ | |
124b13b2 FMH |
676 | if (thisboard->memory_mapped_io) |
677 | subdev_8255_init(dev, s, labpc_dio_mem_callback, | |
0a85b6f0 | 678 | (unsigned long)(dev->iobase + DIO_BASE_REG)); |
124b13b2 FMH |
679 | else |
680 | subdev_8255_init(dev, s, NULL, dev->iobase + DIO_BASE_REG); | |
681 | ||
f6b49620 | 682 | /* calibration subdevices for boards that have one */ |
c65e3be1 | 683 | s = &dev->subdevices[3]; |
124b13b2 FMH |
684 | if (thisboard->register_layout == labpc_1200_layout) { |
685 | s->type = COMEDI_SUBD_CALIB; | |
686 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; | |
687 | s->n_chan = 16; | |
688 | s->maxdata = 0xff; | |
689 | s->insn_read = labpc_calib_read_insn; | |
690 | s->insn_write = labpc_calib_write_insn; | |
691 | ||
692 | for (i = 0; i < s->n_chan; i++) | |
693 | write_caldac(dev, i, s->maxdata / 2); | |
694 | } else | |
695 | s->type = COMEDI_SUBD_UNUSED; | |
696 | ||
697 | /* EEPROM */ | |
c65e3be1 | 698 | s = &dev->subdevices[4]; |
124b13b2 FMH |
699 | if (thisboard->register_layout == labpc_1200_layout) { |
700 | s->type = COMEDI_SUBD_MEMORY; | |
701 | s->subdev_flags = SDF_READABLE | SDF_WRITABLE | SDF_INTERNAL; | |
702 | s->n_chan = EEPROM_SIZE; | |
703 | s->maxdata = 0xff; | |
704 | s->insn_read = labpc_eeprom_read_insn; | |
705 | s->insn_write = labpc_eeprom_write_insn; | |
706 | ||
412bd046 | 707 | for (i = 0; i < EEPROM_SIZE; i++) |
124b13b2 | 708 | devpriv->eeprom_data[i] = labpc_eeprom_read(dev, i); |
124b13b2 | 709 | #ifdef LABPC_DEBUG |
88d8ed4b | 710 | printk(KERN_ERR " eeprom:"); |
412bd046 | 711 | for (i = 0; i < EEPROM_SIZE; i++) |
124b13b2 | 712 | printk(" %i:0x%x ", i, devpriv->eeprom_data[i]); |
124b13b2 FMH |
713 | printk("\n"); |
714 | #endif | |
715 | } else | |
716 | s->type = COMEDI_SUBD_UNUSED; | |
717 | ||
718 | return 0; | |
719 | } | |
0656bb35 | 720 | EXPORT_SYMBOL_GPL(labpc_common_attach); |
124b13b2 | 721 | |
da91b269 | 722 | static int labpc_attach(struct comedi_device *dev, struct comedi_devconfig *it) |
124b13b2 FMH |
723 | { |
724 | unsigned long iobase = 0; | |
725 | unsigned int irq = 0; | |
726 | unsigned int dma_chan = 0; | |
d6aa8366 | 727 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
124b13b2 FMH |
728 | int retval; |
729 | #endif | |
730 | ||
731 | /* allocate and initialize dev->private */ | |
0a4eb4b6 | 732 | if (alloc_private(dev, sizeof(struct labpc_private)) < 0) |
124b13b2 FMH |
733 | return -ENOMEM; |
734 | ||
e41a6f6d | 735 | /* get base address, irq etc. based on bustype */ |
124b13b2 FMH |
736 | switch (thisboard->bustype) { |
737 | case isa_bustype: | |
3297d6c7 | 738 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 FMH |
739 | iobase = it->options[0]; |
740 | irq = it->options[1]; | |
741 | dma_chan = it->options[2]; | |
3297d6c7 RD |
742 | #else |
743 | printk(KERN_ERR " this driver has not been built with ISA DMA " | |
744 | "support.\n"); | |
745 | return -EINVAL; | |
746 | #endif | |
124b13b2 FMH |
747 | break; |
748 | case pci_bustype: | |
d6aa8366 | 749 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
124b13b2 | 750 | retval = labpc_find_device(dev, it->options[0], it->options[1]); |
412bd046 | 751 | if (retval < 0) |
124b13b2 | 752 | return retval; |
124b13b2 FMH |
753 | retval = mite_setup(devpriv->mite); |
754 | if (retval < 0) | |
755 | return retval; | |
756 | iobase = (unsigned long)devpriv->mite->daq_io_addr; | |
757 | irq = mite_irq(devpriv->mite); | |
758 | #else | |
88d8ed4b MD |
759 | printk(KERN_ERR " this driver has not been built with PCI " |
760 | "support.\n"); | |
124b13b2 FMH |
761 | return -EINVAL; |
762 | #endif | |
763 | break; | |
764 | case pcmcia_bustype: | |
0a85b6f0 MT |
765 | printk |
766 | (" this driver does not support pcmcia cards, use ni_labpc_cs.o\n"); | |
124b13b2 FMH |
767 | return -EINVAL; |
768 | break; | |
769 | default: | |
88d8ed4b | 770 | printk(KERN_ERR "bug! couldn't determine board type\n"); |
124b13b2 FMH |
771 | return -EINVAL; |
772 | break; | |
773 | } | |
774 | ||
775 | return labpc_common_attach(dev, iobase, irq, dma_chan); | |
776 | } | |
777 | ||
f6b49620 | 778 | /* adapted from ni_pcimio for finding mite based boards (pc-1200) */ |
d6aa8366 | 779 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
71b5f4f1 | 780 | static int labpc_find_device(struct comedi_device *dev, int bus, int slot) |
124b13b2 FMH |
781 | { |
782 | struct mite_struct *mite; | |
783 | int i; | |
784 | for (mite = mite_devices; mite; mite = mite->next) { | |
785 | if (mite->used) | |
786 | continue; | |
e41a6f6d | 787 | /* if bus/slot are specified then make sure we have the right bus/slot */ |
124b13b2 FMH |
788 | if (bus || slot) { |
789 | if (bus != mite->pcidev->bus->number | |
0a85b6f0 | 790 | || slot != PCI_SLOT(mite->pcidev->devfn)) |
124b13b2 FMH |
791 | continue; |
792 | } | |
793 | for (i = 0; i < driver_labpc.num_names; i++) { | |
794 | if (labpc_boards[i].bustype != pci_bustype) | |
795 | continue; | |
796 | if (mite_device_id(mite) == labpc_boards[i].device_id) { | |
797 | devpriv->mite = mite; | |
e41a6f6d | 798 | /* fixup board pointer, in case we were using the dummy "ni_labpc" entry */ |
124b13b2 FMH |
799 | dev->board_ptr = &labpc_boards[i]; |
800 | return 0; | |
801 | } | |
802 | } | |
803 | } | |
88d8ed4b | 804 | printk(KERN_ERR "no device found\n"); |
124b13b2 FMH |
805 | mite_list_devices(); |
806 | return -EIO; | |
807 | } | |
808 | #endif | |
809 | ||
484ecc95 | 810 | void labpc_common_detach(struct comedi_device *dev) |
124b13b2 | 811 | { |
c65e3be1 HS |
812 | struct comedi_subdevice *s; |
813 | ||
814 | if (dev->subdevices) { | |
815 | s = &dev->subdevices[2]; | |
816 | subdev_8255_cleanup(dev, s); | |
817 | } | |
3297d6c7 | 818 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 | 819 | /* only free stuff if it has been allocated by _attach */ |
e4e1f289 | 820 | kfree(devpriv->dma_buffer); |
124b13b2 FMH |
821 | if (devpriv->dma_chan) |
822 | free_dma(devpriv->dma_chan); | |
3297d6c7 | 823 | #endif |
124b13b2 | 824 | if (dev->irq) |
5f74ea14 | 825 | free_irq(dev->irq, dev); |
124b13b2 FMH |
826 | if (thisboard->bustype == isa_bustype && dev->iobase) |
827 | release_region(dev->iobase, LABPC_SIZE); | |
d6aa8366 | 828 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
124b13b2 FMH |
829 | if (devpriv->mite) |
830 | mite_unsetup(devpriv->mite); | |
831 | #endif | |
124b13b2 | 832 | }; |
0656bb35 | 833 | EXPORT_SYMBOL_GPL(labpc_common_detach); |
124b13b2 | 834 | |
da91b269 | 835 | static void labpc_clear_adc_fifo(const struct comedi_device *dev) |
124b13b2 FMH |
836 | { |
837 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); | |
838 | devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
839 | devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
840 | } | |
841 | ||
da91b269 | 842 | static int labpc_cancel(struct comedi_device *dev, struct comedi_subdevice *s) |
124b13b2 FMH |
843 | { |
844 | unsigned long flags; | |
845 | ||
5f74ea14 | 846 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
847 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
848 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 849 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
850 | |
851 | devpriv->command3_bits = 0; | |
852 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
853 | ||
854 | return 0; | |
855 | } | |
856 | ||
da91b269 | 857 | static enum scan_mode labpc_ai_scan_mode(const struct comedi_cmd *cmd) |
124b13b2 FMH |
858 | { |
859 | if (cmd->chanlist_len == 1) | |
860 | return MODE_SINGLE_CHAN; | |
861 | ||
862 | /* chanlist may be NULL during cmdtest. */ | |
863 | if (cmd->chanlist == NULL) | |
864 | return MODE_MULT_CHAN_UP; | |
865 | ||
866 | if (CR_CHAN(cmd->chanlist[0]) == CR_CHAN(cmd->chanlist[1])) | |
867 | return MODE_SINGLE_CHAN_INTERVAL; | |
868 | ||
869 | if (CR_CHAN(cmd->chanlist[0]) < CR_CHAN(cmd->chanlist[1])) | |
870 | return MODE_MULT_CHAN_UP; | |
871 | ||
872 | if (CR_CHAN(cmd->chanlist[0]) > CR_CHAN(cmd->chanlist[1])) | |
873 | return MODE_MULT_CHAN_DOWN; | |
874 | ||
88d8ed4b | 875 | printk(KERN_ERR "ni_labpc: bug! this should never happen\n"); |
124b13b2 FMH |
876 | |
877 | return 0; | |
878 | } | |
879 | ||
da91b269 | 880 | static int labpc_ai_chanlist_invalid(const struct comedi_device *dev, |
0a85b6f0 | 881 | const struct comedi_cmd *cmd) |
124b13b2 FMH |
882 | { |
883 | int mode, channel, range, aref, i; | |
884 | ||
885 | if (cmd->chanlist == NULL) | |
886 | return 0; | |
887 | ||
888 | mode = labpc_ai_scan_mode(cmd); | |
889 | ||
890 | if (mode == MODE_SINGLE_CHAN) | |
891 | return 0; | |
892 | ||
893 | if (mode == MODE_SINGLE_CHAN_INTERVAL) { | |
894 | if (cmd->chanlist_len > 0xff) { | |
895 | comedi_error(dev, | |
0a85b6f0 | 896 | "ni_labpc: chanlist too long for single channel interval mode\n"); |
124b13b2 FMH |
897 | return 1; |
898 | } | |
899 | } | |
900 | ||
901 | channel = CR_CHAN(cmd->chanlist[0]); | |
902 | range = CR_RANGE(cmd->chanlist[0]); | |
903 | aref = CR_AREF(cmd->chanlist[0]); | |
904 | ||
905 | for (i = 0; i < cmd->chanlist_len; i++) { | |
906 | ||
907 | switch (mode) { | |
908 | case MODE_SINGLE_CHAN_INTERVAL: | |
909 | if (CR_CHAN(cmd->chanlist[i]) != channel) { | |
910 | comedi_error(dev, | |
0a85b6f0 | 911 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
124b13b2 FMH |
912 | return 1; |
913 | } | |
914 | break; | |
915 | case MODE_MULT_CHAN_UP: | |
916 | if (CR_CHAN(cmd->chanlist[i]) != i) { | |
917 | comedi_error(dev, | |
0a85b6f0 | 918 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
124b13b2 FMH |
919 | return 1; |
920 | } | |
921 | break; | |
922 | case MODE_MULT_CHAN_DOWN: | |
923 | if (CR_CHAN(cmd->chanlist[i]) != | |
0a85b6f0 | 924 | cmd->chanlist_len - i - 1) { |
124b13b2 | 925 | comedi_error(dev, |
0a85b6f0 | 926 | "channel scanning order specified in chanlist is not supported by hardware.\n"); |
124b13b2 FMH |
927 | return 1; |
928 | } | |
929 | break; | |
930 | default: | |
88d8ed4b | 931 | printk(KERN_ERR "ni_labpc: bug! in chanlist check\n"); |
124b13b2 FMH |
932 | return 1; |
933 | break; | |
934 | } | |
935 | ||
936 | if (CR_RANGE(cmd->chanlist[i]) != range) { | |
937 | comedi_error(dev, | |
0a85b6f0 | 938 | "entries in chanlist must all have the same range\n"); |
124b13b2 FMH |
939 | return 1; |
940 | } | |
941 | ||
942 | if (CR_AREF(cmd->chanlist[i]) != aref) { | |
943 | comedi_error(dev, | |
0a85b6f0 | 944 | "entries in chanlist must all have the same reference\n"); |
124b13b2 FMH |
945 | return 1; |
946 | } | |
947 | } | |
948 | ||
949 | return 0; | |
950 | } | |
951 | ||
da91b269 | 952 | static int labpc_use_continuous_mode(const struct comedi_cmd *cmd) |
124b13b2 FMH |
953 | { |
954 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN) | |
955 | return 1; | |
956 | ||
957 | if (cmd->scan_begin_src == TRIG_FOLLOW) | |
958 | return 1; | |
959 | ||
960 | return 0; | |
961 | } | |
962 | ||
da91b269 | 963 | static unsigned int labpc_ai_convert_period(const struct comedi_cmd *cmd) |
124b13b2 FMH |
964 | { |
965 | if (cmd->convert_src != TRIG_TIMER) | |
966 | return 0; | |
967 | ||
968 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && | |
0a85b6f0 | 969 | cmd->scan_begin_src == TRIG_TIMER) |
124b13b2 FMH |
970 | return cmd->scan_begin_arg; |
971 | ||
972 | return cmd->convert_arg; | |
973 | } | |
974 | ||
da91b269 | 975 | static void labpc_set_ai_convert_period(struct comedi_cmd *cmd, unsigned int ns) |
124b13b2 FMH |
976 | { |
977 | if (cmd->convert_src != TRIG_TIMER) | |
978 | return; | |
979 | ||
980 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && | |
0a85b6f0 | 981 | cmd->scan_begin_src == TRIG_TIMER) { |
124b13b2 FMH |
982 | cmd->scan_begin_arg = ns; |
983 | if (cmd->convert_arg > cmd->scan_begin_arg) | |
984 | cmd->convert_arg = cmd->scan_begin_arg; | |
985 | } else | |
986 | cmd->convert_arg = ns; | |
987 | } | |
988 | ||
da91b269 | 989 | static unsigned int labpc_ai_scan_period(const struct comedi_cmd *cmd) |
124b13b2 FMH |
990 | { |
991 | if (cmd->scan_begin_src != TRIG_TIMER) | |
992 | return 0; | |
993 | ||
994 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && | |
0a85b6f0 | 995 | cmd->convert_src == TRIG_TIMER) |
124b13b2 FMH |
996 | return 0; |
997 | ||
998 | return cmd->scan_begin_arg; | |
999 | } | |
1000 | ||
da91b269 | 1001 | static void labpc_set_ai_scan_period(struct comedi_cmd *cmd, unsigned int ns) |
124b13b2 FMH |
1002 | { |
1003 | if (cmd->scan_begin_src != TRIG_TIMER) | |
1004 | return; | |
1005 | ||
1006 | if (labpc_ai_scan_mode(cmd) == MODE_SINGLE_CHAN && | |
0a85b6f0 | 1007 | cmd->convert_src == TRIG_TIMER) |
124b13b2 FMH |
1008 | return; |
1009 | ||
1010 | cmd->scan_begin_arg = ns; | |
1011 | } | |
1012 | ||
0a85b6f0 MT |
1013 | static int labpc_ai_cmdtest(struct comedi_device *dev, |
1014 | struct comedi_subdevice *s, struct comedi_cmd *cmd) | |
124b13b2 FMH |
1015 | { |
1016 | int err = 0; | |
1017 | int tmp, tmp2; | |
1018 | int stop_mask; | |
1019 | ||
1020 | /* step 1: make sure trigger sources are trivially valid */ | |
1021 | ||
1022 | tmp = cmd->start_src; | |
1023 | cmd->start_src &= TRIG_NOW | TRIG_EXT; | |
1024 | if (!cmd->start_src || tmp != cmd->start_src) | |
1025 | err++; | |
1026 | ||
1027 | tmp = cmd->scan_begin_src; | |
1028 | cmd->scan_begin_src &= TRIG_TIMER | TRIG_FOLLOW | TRIG_EXT; | |
1029 | if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src) | |
1030 | err++; | |
1031 | ||
1032 | tmp = cmd->convert_src; | |
1033 | cmd->convert_src &= TRIG_TIMER | TRIG_EXT; | |
1034 | if (!cmd->convert_src || tmp != cmd->convert_src) | |
1035 | err++; | |
1036 | ||
1037 | tmp = cmd->scan_end_src; | |
1038 | cmd->scan_end_src &= TRIG_COUNT; | |
1039 | if (!cmd->scan_end_src || tmp != cmd->scan_end_src) | |
1040 | err++; | |
1041 | ||
1042 | tmp = cmd->stop_src; | |
1043 | stop_mask = TRIG_COUNT | TRIG_NONE; | |
1044 | if (thisboard->register_layout == labpc_1200_layout) | |
1045 | stop_mask |= TRIG_EXT; | |
1046 | cmd->stop_src &= stop_mask; | |
1047 | if (!cmd->stop_src || tmp != cmd->stop_src) | |
1048 | err++; | |
1049 | ||
1050 | if (err) | |
1051 | return 1; | |
1052 | ||
1053 | /* step 2: make sure trigger sources are unique and mutually compatible */ | |
1054 | ||
1055 | if (cmd->start_src != TRIG_NOW && cmd->start_src != TRIG_EXT) | |
1056 | err++; | |
1057 | if (cmd->scan_begin_src != TRIG_TIMER && | |
0a85b6f0 MT |
1058 | cmd->scan_begin_src != TRIG_FOLLOW && |
1059 | cmd->scan_begin_src != TRIG_EXT) | |
124b13b2 FMH |
1060 | err++; |
1061 | if (cmd->convert_src != TRIG_TIMER && cmd->convert_src != TRIG_EXT) | |
1062 | err++; | |
1063 | if (cmd->stop_src != TRIG_COUNT && | |
0a85b6f0 | 1064 | cmd->stop_src != TRIG_EXT && cmd->stop_src != TRIG_NONE) |
124b13b2 FMH |
1065 | err++; |
1066 | ||
e41a6f6d | 1067 | /* can't have external stop and start triggers at once */ |
124b13b2 FMH |
1068 | if (cmd->start_src == TRIG_EXT && cmd->stop_src == TRIG_EXT) |
1069 | err++; | |
1070 | ||
1071 | if (err) | |
1072 | return 2; | |
1073 | ||
1074 | /* step 3: make sure arguments are trivially compatible */ | |
1075 | ||
1076 | if (cmd->start_arg == TRIG_NOW && cmd->start_arg != 0) { | |
1077 | cmd->start_arg = 0; | |
1078 | err++; | |
1079 | } | |
1080 | ||
412bd046 | 1081 | if (!cmd->chanlist_len) |
124b13b2 | 1082 | err++; |
412bd046 | 1083 | |
124b13b2 FMH |
1084 | if (cmd->scan_end_arg != cmd->chanlist_len) { |
1085 | cmd->scan_end_arg = cmd->chanlist_len; | |
1086 | err++; | |
1087 | } | |
1088 | ||
1089 | if (cmd->convert_src == TRIG_TIMER) { | |
1090 | if (cmd->convert_arg < thisboard->ai_speed) { | |
1091 | cmd->convert_arg = thisboard->ai_speed; | |
1092 | err++; | |
1093 | } | |
1094 | } | |
e41a6f6d | 1095 | /* make sure scan timing is not too fast */ |
124b13b2 FMH |
1096 | if (cmd->scan_begin_src == TRIG_TIMER) { |
1097 | if (cmd->convert_src == TRIG_TIMER && | |
0a85b6f0 MT |
1098 | cmd->scan_begin_arg < |
1099 | cmd->convert_arg * cmd->chanlist_len) { | |
124b13b2 | 1100 | cmd->scan_begin_arg = |
0a85b6f0 | 1101 | cmd->convert_arg * cmd->chanlist_len; |
124b13b2 FMH |
1102 | err++; |
1103 | } | |
1104 | if (cmd->scan_begin_arg < | |
0a85b6f0 | 1105 | thisboard->ai_speed * cmd->chanlist_len) { |
124b13b2 | 1106 | cmd->scan_begin_arg = |
0a85b6f0 | 1107 | thisboard->ai_speed * cmd->chanlist_len; |
124b13b2 FMH |
1108 | err++; |
1109 | } | |
1110 | } | |
e41a6f6d | 1111 | /* stop source */ |
124b13b2 FMH |
1112 | switch (cmd->stop_src) { |
1113 | case TRIG_COUNT: | |
1114 | if (!cmd->stop_arg) { | |
1115 | cmd->stop_arg = 1; | |
1116 | err++; | |
1117 | } | |
1118 | break; | |
1119 | case TRIG_NONE: | |
1120 | if (cmd->stop_arg != 0) { | |
1121 | cmd->stop_arg = 0; | |
1122 | err++; | |
1123 | } | |
1124 | break; | |
1309e617 MD |
1125 | /* |
1126 | * TRIG_EXT doesn't care since it doesn't | |
1127 | * trigger off a numbered channel | |
1128 | */ | |
124b13b2 FMH |
1129 | default: |
1130 | break; | |
1131 | } | |
1132 | ||
1133 | if (err) | |
1134 | return 3; | |
1135 | ||
1136 | /* step 4: fix up any arguments */ | |
1137 | ||
1138 | tmp = cmd->convert_arg; | |
1139 | tmp2 = cmd->scan_begin_arg; | |
1140 | labpc_adc_timing(dev, cmd); | |
1141 | if (tmp != cmd->convert_arg || tmp2 != cmd->scan_begin_arg) | |
1142 | err++; | |
1143 | ||
1144 | if (err) | |
1145 | return 4; | |
1146 | ||
1147 | if (labpc_ai_chanlist_invalid(dev, cmd)) | |
1148 | return 5; | |
1149 | ||
1150 | return 0; | |
1151 | } | |
1152 | ||
da91b269 | 1153 | static int labpc_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s) |
124b13b2 FMH |
1154 | { |
1155 | int channel, range, aref; | |
3297d6c7 | 1156 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 | 1157 | unsigned long irq_flags; |
3297d6c7 | 1158 | #endif |
124b13b2 | 1159 | int ret; |
d163679c | 1160 | struct comedi_async *async = s->async; |
ea6d0d4c | 1161 | struct comedi_cmd *cmd = &async->cmd; |
124b13b2 FMH |
1162 | enum transfer_type xfer; |
1163 | unsigned long flags; | |
1164 | ||
1165 | if (!dev->irq) { | |
1166 | comedi_error(dev, "no irq assigned, cannot perform command"); | |
1167 | return -1; | |
1168 | } | |
1169 | ||
1170 | range = CR_RANGE(cmd->chanlist[0]); | |
1171 | aref = CR_AREF(cmd->chanlist[0]); | |
1172 | ||
25985edc | 1173 | /* make sure board is disabled before setting up acquisition */ |
5f74ea14 | 1174 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
1175 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
1176 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 1177 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1178 | |
1179 | devpriv->command3_bits = 0; | |
1180 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
1181 | ||
f6b49620 | 1182 | /* initialize software conversion count */ |
412bd046 | 1183 | if (cmd->stop_src == TRIG_COUNT) |
124b13b2 | 1184 | devpriv->count = cmd->stop_arg * cmd->chanlist_len; |
65d6d26c | 1185 | |
f6b49620 | 1186 | /* setup hardware conversion counter */ |
124b13b2 | 1187 | if (cmd->stop_src == TRIG_EXT) { |
1309e617 MD |
1188 | /* |
1189 | * load counter a1 with count of 3 | |
1190 | * (pc+ manual says this is minimum allowed) using mode 0 | |
1191 | */ | |
124b13b2 | 1192 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
0a85b6f0 | 1193 | 1, 3, 0); |
124b13b2 FMH |
1194 | if (ret < 0) { |
1195 | comedi_error(dev, "error loading counter a1"); | |
1196 | return -1; | |
1197 | } | |
1309e617 MD |
1198 | } else /* |
1199 | * otherwise, just put a1 in mode 0 | |
1200 | * with no count to set its output low | |
1201 | */ | |
124b13b2 | 1202 | devpriv->write_byte(INIT_A1_BITS, |
0a85b6f0 | 1203 | dev->iobase + COUNTER_A_CONTROL_REG); |
124b13b2 | 1204 | |
3297d6c7 | 1205 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 BP |
1206 | /* figure out what method we will use to transfer data */ |
1207 | if (devpriv->dma_chan && /* need a dma channel allocated */ | |
1309e617 MD |
1208 | /* |
1209 | * dma unsafe at RT priority, | |
1210 | * and too much setup time for TRIG_WAKE_EOS for | |
1211 | */ | |
0a85b6f0 MT |
1212 | (cmd->flags & (TRIG_WAKE_EOS | TRIG_RT)) == 0 && |
1213 | /* only available on the isa boards */ | |
1214 | thisboard->bustype == isa_bustype) { | |
124b13b2 | 1215 | xfer = isa_dma_transfer; |
1309e617 | 1216 | /* pc-plus has no fifo-half full interrupt */ |
3297d6c7 RD |
1217 | } else |
1218 | #endif | |
1219 | if (thisboard->register_layout == labpc_1200_layout && | |
0a85b6f0 MT |
1220 | /* wake-end-of-scan should interrupt on fifo not empty */ |
1221 | (cmd->flags & TRIG_WAKE_EOS) == 0 && | |
1222 | /* make sure we are taking more than just a few points */ | |
1223 | (cmd->stop_src != TRIG_COUNT || devpriv->count > 256)) { | |
124b13b2 FMH |
1224 | xfer = fifo_half_full_transfer; |
1225 | } else | |
1226 | xfer = fifo_not_empty_transfer; | |
1227 | devpriv->current_transfer = xfer; | |
1228 | ||
f6b49620 | 1229 | /* setup command6 register for 1200 boards */ |
124b13b2 | 1230 | if (thisboard->register_layout == labpc_1200_layout) { |
f6b49620 | 1231 | /* reference inputs to ground or common? */ |
124b13b2 FMH |
1232 | if (aref != AREF_GROUND) |
1233 | devpriv->command6_bits |= ADC_COMMON_BIT; | |
1234 | else | |
1235 | devpriv->command6_bits &= ~ADC_COMMON_BIT; | |
f6b49620 | 1236 | /* bipolar or unipolar range? */ |
124b13b2 FMH |
1237 | if (thisboard->ai_range_is_unipolar[range]) |
1238 | devpriv->command6_bits |= ADC_UNIP_BIT; | |
1239 | else | |
1240 | devpriv->command6_bits &= ~ADC_UNIP_BIT; | |
f6b49620 | 1241 | /* interrupt on fifo half full? */ |
124b13b2 FMH |
1242 | if (xfer == fifo_half_full_transfer) |
1243 | devpriv->command6_bits |= ADC_FHF_INTR_EN_BIT; | |
1244 | else | |
1245 | devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; | |
f6b49620 | 1246 | /* enable interrupt on counter a1 terminal count? */ |
124b13b2 FMH |
1247 | if (cmd->stop_src == TRIG_EXT) |
1248 | devpriv->command6_bits |= A1_INTR_EN_BIT; | |
1249 | else | |
1250 | devpriv->command6_bits &= ~A1_INTR_EN_BIT; | |
f6b49620 | 1251 | /* are we scanning up or down through channels? */ |
124b13b2 FMH |
1252 | if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) |
1253 | devpriv->command6_bits |= ADC_SCAN_UP_BIT; | |
1254 | else | |
1255 | devpriv->command6_bits &= ~ADC_SCAN_UP_BIT; | |
f6b49620 | 1256 | /* write to register */ |
124b13b2 | 1257 | devpriv->write_byte(devpriv->command6_bits, |
0a85b6f0 | 1258 | dev->iobase + COMMAND6_REG); |
124b13b2 FMH |
1259 | } |
1260 | ||
1261 | /* setup channel list, etc (command1 register) */ | |
1262 | devpriv->command1_bits = 0; | |
1263 | if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP) | |
1264 | channel = CR_CHAN(cmd->chanlist[cmd->chanlist_len - 1]); | |
1265 | else | |
1266 | channel = CR_CHAN(cmd->chanlist[0]); | |
e41a6f6d | 1267 | /* munge channel bits for differential / scan disabled mode */ |
124b13b2 FMH |
1268 | if (labpc_ai_scan_mode(cmd) != MODE_SINGLE_CHAN && aref == AREF_DIFF) |
1269 | channel *= 2; | |
1270 | devpriv->command1_bits |= ADC_CHAN_BITS(channel); | |
1271 | devpriv->command1_bits |= thisboard->ai_range_code[range]; | |
1272 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); | |
e41a6f6d | 1273 | /* manual says to set scan enable bit on second pass */ |
124b13b2 | 1274 | if (labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_UP || |
0a85b6f0 | 1275 | labpc_ai_scan_mode(cmd) == MODE_MULT_CHAN_DOWN) { |
124b13b2 | 1276 | devpriv->command1_bits |= ADC_SCAN_EN_BIT; |
e41a6f6d SR |
1277 | /* need a brief delay before enabling scan, or scan |
1278 | * list will get screwed when you switch | |
124b13b2 | 1279 | * between scan up to scan down mode - dunno why */ |
5f74ea14 | 1280 | udelay(1); |
124b13b2 | 1281 | devpriv->write_byte(devpriv->command1_bits, |
0a85b6f0 | 1282 | dev->iobase + COMMAND1_REG); |
124b13b2 | 1283 | } |
f6b49620 | 1284 | /* setup any external triggering/pacing (command4 register) */ |
124b13b2 FMH |
1285 | devpriv->command4_bits = 0; |
1286 | if (cmd->convert_src != TRIG_EXT) | |
1287 | devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; | |
1288 | /* XXX should discard first scan when using interval scanning | |
1289 | * since manual says it is not synced with scan clock */ | |
1290 | if (labpc_use_continuous_mode(cmd) == 0) { | |
1291 | devpriv->command4_bits |= INTERVAL_SCAN_EN_BIT; | |
1292 | if (cmd->scan_begin_src == TRIG_EXT) | |
1293 | devpriv->command4_bits |= EXT_SCAN_EN_BIT; | |
1294 | } | |
f6b49620 | 1295 | /* single-ended/differential */ |
124b13b2 FMH |
1296 | if (aref == AREF_DIFF) |
1297 | devpriv->command4_bits |= ADC_DIFF_BIT; | |
1298 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); | |
1299 | ||
1300 | devpriv->write_byte(cmd->chanlist_len, | |
0a85b6f0 | 1301 | dev->iobase + INTERVAL_COUNT_REG); |
f6b49620 | 1302 | /* load count */ |
124b13b2 | 1303 | devpriv->write_byte(INTERVAL_LOAD_BITS, |
0a85b6f0 | 1304 | dev->iobase + INTERVAL_LOAD_REG); |
124b13b2 FMH |
1305 | |
1306 | if (cmd->convert_src == TRIG_TIMER || cmd->scan_begin_src == TRIG_TIMER) { | |
f6b49620 | 1307 | /* set up pacing */ |
124b13b2 | 1308 | labpc_adc_timing(dev, cmd); |
f6b49620 | 1309 | /* load counter b0 in mode 3 */ |
124b13b2 | 1310 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
0a85b6f0 | 1311 | 0, devpriv->divisor_b0, 3); |
124b13b2 FMH |
1312 | if (ret < 0) { |
1313 | comedi_error(dev, "error loading counter b0"); | |
1314 | return -1; | |
1315 | } | |
1316 | } | |
f6b49620 | 1317 | /* set up conversion pacing */ |
124b13b2 | 1318 | if (labpc_ai_convert_period(cmd)) { |
f6b49620 | 1319 | /* load counter a0 in mode 2 */ |
124b13b2 | 1320 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_A_BASE_REG, |
0a85b6f0 | 1321 | 0, devpriv->divisor_a0, 2); |
124b13b2 FMH |
1322 | if (ret < 0) { |
1323 | comedi_error(dev, "error loading counter a0"); | |
1324 | return -1; | |
1325 | } | |
1326 | } else | |
1327 | devpriv->write_byte(INIT_A0_BITS, | |
0a85b6f0 | 1328 | dev->iobase + COUNTER_A_CONTROL_REG); |
124b13b2 | 1329 | |
f6b49620 | 1330 | /* set up scan pacing */ |
124b13b2 | 1331 | if (labpc_ai_scan_period(cmd)) { |
f6b49620 | 1332 | /* load counter b1 in mode 2 */ |
124b13b2 | 1333 | ret = labpc_counter_load(dev, dev->iobase + COUNTER_B_BASE_REG, |
0a85b6f0 | 1334 | 1, devpriv->divisor_b1, 2); |
124b13b2 FMH |
1335 | if (ret < 0) { |
1336 | comedi_error(dev, "error loading counter b1"); | |
1337 | return -1; | |
1338 | } | |
1339 | } | |
1340 | ||
1341 | labpc_clear_adc_fifo(dev); | |
1342 | ||
3297d6c7 | 1343 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 | 1344 | /* set up dma transfer */ |
124b13b2 FMH |
1345 | if (xfer == isa_dma_transfer) { |
1346 | irq_flags = claim_dma_lock(); | |
1347 | disable_dma(devpriv->dma_chan); | |
1348 | /* clear flip-flop to make sure 2-byte registers for | |
1349 | * count and address get set correctly */ | |
1350 | clear_dma_ff(devpriv->dma_chan); | |
1351 | set_dma_addr(devpriv->dma_chan, | |
0a85b6f0 | 1352 | virt_to_bus(devpriv->dma_buffer)); |
f6b49620 | 1353 | /* set appropriate size of transfer */ |
124b13b2 FMH |
1354 | devpriv->dma_transfer_size = labpc_suggest_transfer_size(*cmd); |
1355 | if (cmd->stop_src == TRIG_COUNT && | |
0a85b6f0 | 1356 | devpriv->count * sample_size < devpriv->dma_transfer_size) { |
124b13b2 | 1357 | devpriv->dma_transfer_size = |
0a85b6f0 | 1358 | devpriv->count * sample_size; |
124b13b2 FMH |
1359 | } |
1360 | set_dma_count(devpriv->dma_chan, devpriv->dma_transfer_size); | |
1361 | enable_dma(devpriv->dma_chan); | |
1362 | release_dma_lock(irq_flags); | |
f6b49620 | 1363 | /* enable board's dma */ |
124b13b2 FMH |
1364 | devpriv->command3_bits |= DMA_EN_BIT | DMATC_INTR_EN_BIT; |
1365 | } else | |
1366 | devpriv->command3_bits &= ~DMA_EN_BIT & ~DMATC_INTR_EN_BIT; | |
3297d6c7 | 1367 | #endif |
124b13b2 | 1368 | |
f6b49620 | 1369 | /* enable error interrupts */ |
124b13b2 | 1370 | devpriv->command3_bits |= ERR_INTR_EN_BIT; |
f6b49620 | 1371 | /* enable fifo not empty interrupt? */ |
124b13b2 FMH |
1372 | if (xfer == fifo_not_empty_transfer) |
1373 | devpriv->command3_bits |= ADC_FNE_INTR_EN_BIT; | |
1374 | else | |
1375 | devpriv->command3_bits &= ~ADC_FNE_INTR_EN_BIT; | |
1376 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
1377 | ||
25985edc | 1378 | /* startup acquisition */ |
124b13b2 | 1379 | |
f6b49620 BP |
1380 | /* command2 reg */ |
1381 | /* use 2 cascaded counters for pacing */ | |
5f74ea14 | 1382 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
1383 | devpriv->command2_bits |= CASCADE_BIT; |
1384 | switch (cmd->start_src) { | |
1385 | case TRIG_EXT: | |
1386 | devpriv->command2_bits |= HWTRIG_BIT; | |
1387 | devpriv->command2_bits &= ~PRETRIG_BIT & ~SWTRIG_BIT; | |
1388 | break; | |
1389 | case TRIG_NOW: | |
1390 | devpriv->command2_bits |= SWTRIG_BIT; | |
1391 | devpriv->command2_bits &= ~PRETRIG_BIT & ~HWTRIG_BIT; | |
1392 | break; | |
1393 | default: | |
1394 | comedi_error(dev, "bug with start_src"); | |
513e48f9 | 1395 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1396 | return -1; |
1397 | break; | |
1398 | } | |
1399 | switch (cmd->stop_src) { | |
1400 | case TRIG_EXT: | |
1401 | devpriv->command2_bits |= HWTRIG_BIT | PRETRIG_BIT; | |
1402 | break; | |
1403 | case TRIG_COUNT: | |
1404 | case TRIG_NONE: | |
1405 | break; | |
1406 | default: | |
1407 | comedi_error(dev, "bug with stop_src"); | |
513e48f9 | 1408 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1409 | return -1; |
1410 | } | |
1411 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 1412 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 FMH |
1413 | |
1414 | return 0; | |
1415 | } | |
1416 | ||
1417 | /* interrupt service routine */ | |
70265d24 | 1418 | static irqreturn_t labpc_interrupt(int irq, void *d) |
124b13b2 | 1419 | { |
71b5f4f1 | 1420 | struct comedi_device *dev = d; |
34c43922 | 1421 | struct comedi_subdevice *s = dev->read_subdev; |
d163679c | 1422 | struct comedi_async *async; |
ea6d0d4c | 1423 | struct comedi_cmd *cmd; |
124b13b2 FMH |
1424 | |
1425 | if (dev->attached == 0) { | |
1426 | comedi_error(dev, "premature interrupt"); | |
1427 | return IRQ_HANDLED; | |
1428 | } | |
1429 | ||
1430 | async = s->async; | |
1431 | cmd = &async->cmd; | |
1432 | async->events = 0; | |
1433 | ||
e41a6f6d | 1434 | /* read board status */ |
124b13b2 FMH |
1435 | devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); |
1436 | if (thisboard->register_layout == labpc_1200_layout) | |
1437 | devpriv->status2_bits = | |
0a85b6f0 | 1438 | devpriv->read_byte(dev->iobase + STATUS2_REG); |
124b13b2 FMH |
1439 | |
1440 | if ((devpriv->status1_bits & (DMATC_BIT | TIMER_BIT | OVERFLOW_BIT | | |
0a85b6f0 MT |
1441 | OVERRUN_BIT | DATA_AVAIL_BIT)) == 0 |
1442 | && (devpriv->status2_bits & A1_TC_BIT) == 0 | |
1443 | && (devpriv->status2_bits & FNHF_BIT)) { | |
124b13b2 FMH |
1444 | return IRQ_NONE; |
1445 | } | |
1446 | ||
1447 | if (devpriv->status1_bits & OVERRUN_BIT) { | |
e41a6f6d | 1448 | /* clear error interrupt */ |
124b13b2 FMH |
1449 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); |
1450 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
1451 | comedi_event(dev, s); | |
1452 | comedi_error(dev, "overrun"); | |
1453 | return IRQ_HANDLED; | |
1454 | } | |
1455 | ||
3297d6c7 | 1456 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 | 1457 | if (devpriv->current_transfer == isa_dma_transfer) { |
639b9f1e SR |
1458 | /* |
1459 | * if a dma terminal count of external stop trigger | |
1460 | * has occurred | |
1461 | */ | |
124b13b2 | 1462 | if (devpriv->status1_bits & DMATC_BIT || |
0a85b6f0 MT |
1463 | (thisboard->register_layout == labpc_1200_layout |
1464 | && devpriv->status2_bits & A1_TC_BIT)) { | |
124b13b2 FMH |
1465 | handle_isa_dma(dev); |
1466 | } | |
1467 | } else | |
3297d6c7 | 1468 | #endif |
124b13b2 FMH |
1469 | labpc_drain_fifo(dev); |
1470 | ||
1471 | if (devpriv->status1_bits & TIMER_BIT) { | |
1472 | comedi_error(dev, "handled timer interrupt?"); | |
f6b49620 | 1473 | /* clear it */ |
124b13b2 FMH |
1474 | devpriv->write_byte(0x1, dev->iobase + TIMER_CLEAR_REG); |
1475 | } | |
1476 | ||
1477 | if (devpriv->status1_bits & OVERFLOW_BIT) { | |
f6b49620 | 1478 | /* clear error interrupt */ |
124b13b2 FMH |
1479 | devpriv->write_byte(0x1, dev->iobase + ADC_CLEAR_REG); |
1480 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
1481 | comedi_event(dev, s); | |
1482 | comedi_error(dev, "overflow"); | |
1483 | return IRQ_HANDLED; | |
1484 | } | |
f6b49620 | 1485 | /* handle external stop trigger */ |
124b13b2 FMH |
1486 | if (cmd->stop_src == TRIG_EXT) { |
1487 | if (devpriv->status2_bits & A1_TC_BIT) { | |
1488 | labpc_drain_dregs(dev); | |
1489 | labpc_cancel(dev, s); | |
1490 | async->events |= COMEDI_CB_EOA; | |
1491 | } | |
1492 | } | |
1493 | ||
1494 | /* TRIG_COUNT end of acquisition */ | |
1495 | if (cmd->stop_src == TRIG_COUNT) { | |
1496 | if (devpriv->count == 0) { | |
1497 | labpc_cancel(dev, s); | |
1498 | async->events |= COMEDI_CB_EOA; | |
1499 | } | |
1500 | } | |
1501 | ||
1502 | comedi_event(dev, s); | |
1503 | return IRQ_HANDLED; | |
1504 | } | |
1505 | ||
f6b49620 | 1506 | /* read all available samples from ai fifo */ |
da91b269 | 1507 | static int labpc_drain_fifo(struct comedi_device *dev) |
124b13b2 FMH |
1508 | { |
1509 | unsigned int lsb, msb; | |
790c5541 | 1510 | short data; |
d163679c | 1511 | struct comedi_async *async = dev->read_subdev->async; |
124b13b2 FMH |
1512 | const int timeout = 10000; |
1513 | unsigned int i; | |
1514 | ||
1515 | devpriv->status1_bits = devpriv->read_byte(dev->iobase + STATUS1_REG); | |
1516 | ||
1517 | for (i = 0; (devpriv->status1_bits & DATA_AVAIL_BIT) && i < timeout; | |
0a85b6f0 | 1518 | i++) { |
f6b49620 | 1519 | /* quit if we have all the data we want */ |
124b13b2 FMH |
1520 | if (async->cmd.stop_src == TRIG_COUNT) { |
1521 | if (devpriv->count == 0) | |
1522 | break; | |
1523 | devpriv->count--; | |
1524 | } | |
1525 | lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
1526 | msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
1527 | data = (msb << 8) | lsb; | |
1528 | cfc_write_to_buffer(dev->read_subdev, data); | |
1529 | devpriv->status1_bits = | |
0a85b6f0 | 1530 | devpriv->read_byte(dev->iobase + STATUS1_REG); |
124b13b2 FMH |
1531 | } |
1532 | if (i == timeout) { | |
1533 | comedi_error(dev, "ai timeout, fifo never empties"); | |
1534 | async->events |= COMEDI_CB_ERROR | COMEDI_CB_EOA; | |
1535 | return -1; | |
1536 | } | |
1537 | ||
1538 | return 0; | |
1539 | } | |
1540 | ||
3297d6c7 | 1541 | #ifdef CONFIG_ISA_DMA_API |
da91b269 | 1542 | static void labpc_drain_dma(struct comedi_device *dev) |
124b13b2 | 1543 | { |
34c43922 | 1544 | struct comedi_subdevice *s = dev->read_subdev; |
d163679c | 1545 | struct comedi_async *async = s->async; |
124b13b2 FMH |
1546 | int status; |
1547 | unsigned long flags; | |
1548 | unsigned int max_points, num_points, residue, leftover; | |
1549 | int i; | |
1550 | ||
1551 | status = devpriv->status1_bits; | |
1552 | ||
1553 | flags = claim_dma_lock(); | |
1554 | disable_dma(devpriv->dma_chan); | |
1555 | /* clear flip-flop to make sure 2-byte registers for | |
1556 | * count and address get set correctly */ | |
1557 | clear_dma_ff(devpriv->dma_chan); | |
1558 | ||
f6b49620 | 1559 | /* figure out how many points to read */ |
124b13b2 FMH |
1560 | max_points = devpriv->dma_transfer_size / sample_size; |
1561 | /* residue is the number of points left to be done on the dma | |
1562 | * transfer. It should always be zero at this point unless | |
1563 | * the stop_src is set to external triggering. | |
1564 | */ | |
1565 | residue = get_dma_residue(devpriv->dma_chan) / sample_size; | |
1566 | num_points = max_points - residue; | |
1567 | if (devpriv->count < num_points && async->cmd.stop_src == TRIG_COUNT) | |
1568 | num_points = devpriv->count; | |
1569 | ||
f6b49620 | 1570 | /* figure out how many points will be stored next time */ |
124b13b2 FMH |
1571 | leftover = 0; |
1572 | if (async->cmd.stop_src != TRIG_COUNT) { | |
1573 | leftover = devpriv->dma_transfer_size / sample_size; | |
1574 | } else if (devpriv->count > num_points) { | |
1575 | leftover = devpriv->count - num_points; | |
1576 | if (leftover > max_points) | |
1577 | leftover = max_points; | |
1578 | } | |
1579 | ||
1580 | /* write data to comedi buffer */ | |
412bd046 | 1581 | for (i = 0; i < num_points; i++) |
124b13b2 | 1582 | cfc_write_to_buffer(s, devpriv->dma_buffer[i]); |
65d6d26c | 1583 | |
124b13b2 FMH |
1584 | if (async->cmd.stop_src == TRIG_COUNT) |
1585 | devpriv->count -= num_points; | |
1586 | ||
f6b49620 | 1587 | /* set address and count for next transfer */ |
124b13b2 FMH |
1588 | set_dma_addr(devpriv->dma_chan, virt_to_bus(devpriv->dma_buffer)); |
1589 | set_dma_count(devpriv->dma_chan, leftover * sample_size); | |
1590 | release_dma_lock(flags); | |
1591 | ||
1592 | async->events |= COMEDI_CB_BLOCK; | |
1593 | } | |
1594 | ||
da91b269 | 1595 | static void handle_isa_dma(struct comedi_device *dev) |
124b13b2 FMH |
1596 | { |
1597 | labpc_drain_dma(dev); | |
1598 | ||
1599 | enable_dma(devpriv->dma_chan); | |
1600 | ||
f6b49620 | 1601 | /* clear dma tc interrupt */ |
124b13b2 FMH |
1602 | devpriv->write_byte(0x1, dev->iobase + DMATC_CLEAR_REG); |
1603 | } | |
3297d6c7 | 1604 | #endif |
124b13b2 | 1605 | |
25985edc LDM |
1606 | /* makes sure all data acquired by board is transferred to comedi (used |
1607 | * when acquisition is terminated by stop_src == TRIG_EXT). */ | |
da91b269 | 1608 | static void labpc_drain_dregs(struct comedi_device *dev) |
124b13b2 | 1609 | { |
3297d6c7 | 1610 | #ifdef CONFIG_ISA_DMA_API |
124b13b2 FMH |
1611 | if (devpriv->current_transfer == isa_dma_transfer) |
1612 | labpc_drain_dma(dev); | |
3297d6c7 | 1613 | #endif |
124b13b2 FMH |
1614 | |
1615 | labpc_drain_fifo(dev); | |
1616 | } | |
1617 | ||
da91b269 | 1618 | static int labpc_ai_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 1619 | struct comedi_insn *insn, unsigned int *data) |
124b13b2 FMH |
1620 | { |
1621 | int i, n; | |
1622 | int chan, range; | |
1623 | int lsb, msb; | |
1624 | int timeout = 1000; | |
1625 | unsigned long flags; | |
1626 | ||
f6b49620 | 1627 | /* disable timed conversions */ |
5f74ea14 | 1628 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
1629 | devpriv->command2_bits &= ~SWTRIG_BIT & ~HWTRIG_BIT & ~PRETRIG_BIT; |
1630 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 1631 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 | 1632 | |
f6b49620 | 1633 | /* disable interrupt generation and dma */ |
124b13b2 FMH |
1634 | devpriv->command3_bits = 0; |
1635 | devpriv->write_byte(devpriv->command3_bits, dev->iobase + COMMAND3_REG); | |
1636 | ||
1637 | /* set gain and channel */ | |
1638 | devpriv->command1_bits = 0; | |
1639 | chan = CR_CHAN(insn->chanspec); | |
1640 | range = CR_RANGE(insn->chanspec); | |
1641 | devpriv->command1_bits |= thisboard->ai_range_code[range]; | |
e41a6f6d | 1642 | /* munge channel bits for differential/scan disabled mode */ |
124b13b2 FMH |
1643 | if (CR_AREF(insn->chanspec) == AREF_DIFF) |
1644 | chan *= 2; | |
1645 | devpriv->command1_bits |= ADC_CHAN_BITS(chan); | |
1646 | devpriv->write_byte(devpriv->command1_bits, dev->iobase + COMMAND1_REG); | |
1647 | ||
e41a6f6d | 1648 | /* setup command6 register for 1200 boards */ |
124b13b2 | 1649 | if (thisboard->register_layout == labpc_1200_layout) { |
f6b49620 | 1650 | /* reference inputs to ground or common? */ |
124b13b2 FMH |
1651 | if (CR_AREF(insn->chanspec) != AREF_GROUND) |
1652 | devpriv->command6_bits |= ADC_COMMON_BIT; | |
1653 | else | |
1654 | devpriv->command6_bits &= ~ADC_COMMON_BIT; | |
e41a6f6d | 1655 | /* bipolar or unipolar range? */ |
124b13b2 FMH |
1656 | if (thisboard->ai_range_is_unipolar[range]) |
1657 | devpriv->command6_bits |= ADC_UNIP_BIT; | |
1658 | else | |
1659 | devpriv->command6_bits &= ~ADC_UNIP_BIT; | |
e41a6f6d | 1660 | /* don't interrupt on fifo half full */ |
124b13b2 | 1661 | devpriv->command6_bits &= ~ADC_FHF_INTR_EN_BIT; |
e41a6f6d | 1662 | /* don't enable interrupt on counter a1 terminal count? */ |
124b13b2 | 1663 | devpriv->command6_bits &= ~A1_INTR_EN_BIT; |
e41a6f6d | 1664 | /* write to register */ |
124b13b2 | 1665 | devpriv->write_byte(devpriv->command6_bits, |
0a85b6f0 | 1666 | dev->iobase + COMMAND6_REG); |
124b13b2 | 1667 | } |
e41a6f6d | 1668 | /* setup command4 register */ |
124b13b2 FMH |
1669 | devpriv->command4_bits = 0; |
1670 | devpriv->command4_bits |= EXT_CONVERT_DISABLE_BIT; | |
e41a6f6d | 1671 | /* single-ended/differential */ |
124b13b2 FMH |
1672 | if (CR_AREF(insn->chanspec) == AREF_DIFF) |
1673 | devpriv->command4_bits |= ADC_DIFF_BIT; | |
1674 | devpriv->write_byte(devpriv->command4_bits, dev->iobase + COMMAND4_REG); | |
1675 | ||
1309e617 MD |
1676 | /* |
1677 | * initialize pacer counter output to make sure it doesn't | |
1678 | * cause any problems | |
1679 | */ | |
124b13b2 FMH |
1680 | devpriv->write_byte(INIT_A0_BITS, dev->iobase + COUNTER_A_CONTROL_REG); |
1681 | ||
1682 | labpc_clear_adc_fifo(dev); | |
1683 | ||
1684 | for (n = 0; n < insn->n; n++) { | |
1685 | /* trigger conversion */ | |
1686 | devpriv->write_byte(0x1, dev->iobase + ADC_CONVERT_REG); | |
1687 | ||
1688 | for (i = 0; i < timeout; i++) { | |
1689 | if (devpriv->read_byte(dev->iobase + | |
0a85b6f0 | 1690 | STATUS1_REG) & DATA_AVAIL_BIT) |
124b13b2 | 1691 | break; |
5f74ea14 | 1692 | udelay(1); |
124b13b2 FMH |
1693 | } |
1694 | if (i == timeout) { | |
1695 | comedi_error(dev, "timeout"); | |
1696 | return -ETIME; | |
1697 | } | |
1698 | lsb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
1699 | msb = devpriv->read_byte(dev->iobase + ADC_FIFO_REG); | |
1700 | data[n] = (msb << 8) | lsb; | |
1701 | } | |
1702 | ||
1703 | return n; | |
1704 | } | |
1705 | ||
f6b49620 | 1706 | /* analog output insn */ |
da91b269 | 1707 | static int labpc_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 1708 | struct comedi_insn *insn, unsigned int *data) |
124b13b2 FMH |
1709 | { |
1710 | int channel, range; | |
1711 | unsigned long flags; | |
1712 | int lsb, msb; | |
1713 | ||
1714 | channel = CR_CHAN(insn->chanspec); | |
1715 | ||
e41a6f6d | 1716 | /* turn off pacing of analog output channel */ |
124b13b2 FMH |
1717 | /* note: hardware bug in daqcard-1200 means pacing cannot |
1718 | * be independently enabled/disabled for its the two channels */ | |
5f74ea14 | 1719 | spin_lock_irqsave(&dev->spinlock, flags); |
124b13b2 FMH |
1720 | devpriv->command2_bits &= ~DAC_PACED_BIT(channel); |
1721 | devpriv->write_byte(devpriv->command2_bits, dev->iobase + COMMAND2_REG); | |
5f74ea14 | 1722 | spin_unlock_irqrestore(&dev->spinlock, flags); |
124b13b2 | 1723 | |
e41a6f6d | 1724 | /* set range */ |
124b13b2 FMH |
1725 | if (thisboard->register_layout == labpc_1200_layout) { |
1726 | range = CR_RANGE(insn->chanspec); | |
1727 | if (range & AO_RANGE_IS_UNIPOLAR) | |
1728 | devpriv->command6_bits |= DAC_UNIP_BIT(channel); | |
1729 | else | |
1730 | devpriv->command6_bits &= ~DAC_UNIP_BIT(channel); | |
f6b49620 | 1731 | /* write to register */ |
124b13b2 | 1732 | devpriv->write_byte(devpriv->command6_bits, |
0a85b6f0 | 1733 | dev->iobase + COMMAND6_REG); |
124b13b2 | 1734 | } |
e41a6f6d | 1735 | /* send data */ |
124b13b2 FMH |
1736 | lsb = data[0] & 0xff; |
1737 | msb = (data[0] >> 8) & 0xff; | |
1738 | devpriv->write_byte(lsb, dev->iobase + DAC_LSB_REG(channel)); | |
1739 | devpriv->write_byte(msb, dev->iobase + DAC_MSB_REG(channel)); | |
1740 | ||
e41a6f6d | 1741 | /* remember value for readback */ |
124b13b2 FMH |
1742 | devpriv->ao_value[channel] = data[0]; |
1743 | ||
1744 | return 1; | |
1745 | } | |
1746 | ||
f6b49620 | 1747 | /* analog output readback insn */ |
da91b269 | 1748 | static int labpc_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s, |
0a85b6f0 | 1749 | struct comedi_insn *insn, unsigned int *data) |
124b13b2 FMH |
1750 | { |
1751 | data[0] = devpriv->ao_value[CR_CHAN(insn->chanspec)]; | |
1752 | ||
1753 | return 1; | |
1754 | } | |
1755 | ||
0a85b6f0 MT |
1756 | static int labpc_calib_read_insn(struct comedi_device *dev, |
1757 | struct comedi_subdevice *s, | |
1758 | struct comedi_insn *insn, unsigned int *data) | |
124b13b2 FMH |
1759 | { |
1760 | data[0] = devpriv->caldac[CR_CHAN(insn->chanspec)]; | |
1761 | ||
1762 | return 1; | |
1763 | } | |
1764 | ||
0a85b6f0 MT |
1765 | static int labpc_calib_write_insn(struct comedi_device *dev, |
1766 | struct comedi_subdevice *s, | |
1767 | struct comedi_insn *insn, unsigned int *data) | |
124b13b2 FMH |
1768 | { |
1769 | int channel = CR_CHAN(insn->chanspec); | |
1770 | ||
1771 | write_caldac(dev, channel, data[0]); | |
1772 | return 1; | |
1773 | } | |
1774 | ||
0a85b6f0 MT |
1775 | static int labpc_eeprom_read_insn(struct comedi_device *dev, |
1776 | struct comedi_subdevice *s, | |
1777 | struct comedi_insn *insn, unsigned int *data) | |
124b13b2 FMH |
1778 | { |
1779 | data[0] = devpriv->eeprom_data[CR_CHAN(insn->chanspec)]; | |
1780 | ||
1781 | return 1; | |
1782 | } | |
1783 | ||
0a85b6f0 MT |
1784 | static int labpc_eeprom_write_insn(struct comedi_device *dev, |
1785 | struct comedi_subdevice *s, | |
1786 | struct comedi_insn *insn, unsigned int *data) | |
124b13b2 FMH |
1787 | { |
1788 | int channel = CR_CHAN(insn->chanspec); | |
1789 | int ret; | |
1790 | ||
f6b49620 | 1791 | /* only allow writes to user area of eeprom */ |
124b13b2 | 1792 | if (channel < 16 || channel > 127) { |
0a85b6f0 MT |
1793 | printk |
1794 | ("eeprom writes are only allowed to channels 16 through 127 (the pointer and user areas)"); | |
124b13b2 FMH |
1795 | return -EINVAL; |
1796 | } | |
1797 | ||
1798 | ret = labpc_eeprom_write(dev, channel, data[0]); | |
1799 | if (ret < 0) | |
1800 | return ret; | |
1801 | ||
1802 | return 1; | |
1803 | } | |
1804 | ||
3297d6c7 | 1805 | #ifdef CONFIG_ISA_DMA_API |
f6b49620 | 1806 | /* utility function that suggests a dma transfer size in bytes */ |
ea6d0d4c | 1807 | static unsigned int labpc_suggest_transfer_size(struct comedi_cmd cmd) |
124b13b2 FMH |
1808 | { |
1809 | unsigned int size; | |
1810 | unsigned int freq; | |
1811 | ||
1812 | if (cmd.convert_src == TRIG_TIMER) | |
1813 | freq = 1000000000 / cmd.convert_arg; | |
e41a6f6d | 1814 | /* return some default value */ |
124b13b2 FMH |
1815 | else |
1816 | freq = 0xffffffff; | |
1817 | ||
e41a6f6d | 1818 | /* make buffer fill in no more than 1/3 second */ |
124b13b2 FMH |
1819 | size = (freq / 3) * sample_size; |
1820 | ||
e41a6f6d | 1821 | /* set a minimum and maximum size allowed */ |
124b13b2 FMH |
1822 | if (size > dma_buffer_size) |
1823 | size = dma_buffer_size - dma_buffer_size % sample_size; | |
1824 | else if (size < sample_size) | |
1825 | size = sample_size; | |
1826 | ||
1827 | return size; | |
1828 | } | |
3297d6c7 | 1829 | #endif |
124b13b2 | 1830 | |
f6b49620 | 1831 | /* figures out what counter values to use based on command */ |
da91b269 | 1832 | static void labpc_adc_timing(struct comedi_device *dev, struct comedi_cmd *cmd) |
124b13b2 | 1833 | { |
e41a6f6d SR |
1834 | /* max value for 16 bit counter in mode 2 */ |
1835 | const int max_counter_value = 0x10000; | |
1836 | /* min value for 16 bit counter in mode 2 */ | |
1837 | const int min_counter_value = 2; | |
124b13b2 FMH |
1838 | unsigned int base_period; |
1839 | ||
e41a6f6d SR |
1840 | /* |
1841 | * if both convert and scan triggers are TRIG_TIMER, then they | |
1842 | * both rely on counter b0 | |
1843 | */ | |
124b13b2 | 1844 | if (labpc_ai_convert_period(cmd) && labpc_ai_scan_period(cmd)) { |
e41a6f6d SR |
1845 | /* |
1846 | * pick the lowest b0 divisor value we can (for maximum input | |
1847 | * clock speed on convert and scan counters) | |
1848 | */ | |
124b13b2 | 1849 | devpriv->divisor_b0 = (labpc_ai_scan_period(cmd) - 1) / |
0a85b6f0 | 1850 | (LABPC_TIMER_BASE * max_counter_value) + 1; |
124b13b2 FMH |
1851 | if (devpriv->divisor_b0 < min_counter_value) |
1852 | devpriv->divisor_b0 = min_counter_value; | |
1853 | if (devpriv->divisor_b0 > max_counter_value) | |
1854 | devpriv->divisor_b0 = max_counter_value; | |
1855 | ||
1856 | base_period = LABPC_TIMER_BASE * devpriv->divisor_b0; | |
1857 | ||
f6b49620 | 1858 | /* set a0 for conversion frequency and b1 for scan frequency */ |
124b13b2 FMH |
1859 | switch (cmd->flags & TRIG_ROUND_MASK) { |
1860 | default: | |
1861 | case TRIG_ROUND_NEAREST: | |
1862 | devpriv->divisor_a0 = | |
0a85b6f0 MT |
1863 | (labpc_ai_convert_period(cmd) + |
1864 | (base_period / 2)) / base_period; | |
124b13b2 | 1865 | devpriv->divisor_b1 = |
0a85b6f0 MT |
1866 | (labpc_ai_scan_period(cmd) + |
1867 | (base_period / 2)) / base_period; | |
124b13b2 FMH |
1868 | break; |
1869 | case TRIG_ROUND_UP: | |
1870 | devpriv->divisor_a0 = | |
0a85b6f0 MT |
1871 | (labpc_ai_convert_period(cmd) + (base_period - |
1872 | 1)) / base_period; | |
124b13b2 | 1873 | devpriv->divisor_b1 = |
0a85b6f0 MT |
1874 | (labpc_ai_scan_period(cmd) + (base_period - |
1875 | 1)) / base_period; | |
124b13b2 FMH |
1876 | break; |
1877 | case TRIG_ROUND_DOWN: | |
1878 | devpriv->divisor_a0 = | |
0a85b6f0 | 1879 | labpc_ai_convert_period(cmd) / base_period; |
124b13b2 | 1880 | devpriv->divisor_b1 = |
0a85b6f0 | 1881 | labpc_ai_scan_period(cmd) / base_period; |
124b13b2 FMH |
1882 | break; |
1883 | } | |
f6b49620 | 1884 | /* make sure a0 and b1 values are acceptable */ |
124b13b2 FMH |
1885 | if (devpriv->divisor_a0 < min_counter_value) |
1886 | devpriv->divisor_a0 = min_counter_value; | |
1887 | if (devpriv->divisor_a0 > max_counter_value) | |
1888 | devpriv->divisor_a0 = max_counter_value; | |
1889 | if (devpriv->divisor_b1 < min_counter_value) | |
1890 | devpriv->divisor_b1 = min_counter_value; | |
1891 | if (devpriv->divisor_b1 > max_counter_value) | |
1892 | devpriv->divisor_b1 = max_counter_value; | |
f6b49620 | 1893 | /* write corrected timings to command */ |
124b13b2 | 1894 | labpc_set_ai_convert_period(cmd, |
0a85b6f0 | 1895 | base_period * devpriv->divisor_a0); |
124b13b2 | 1896 | labpc_set_ai_scan_period(cmd, |
0a85b6f0 | 1897 | base_period * devpriv->divisor_b1); |
e41a6f6d SR |
1898 | /* |
1899 | * if only one TRIG_TIMER is used, we can employ the generic | |
1900 | * cascaded timing functions | |
1901 | */ | |
124b13b2 FMH |
1902 | } else if (labpc_ai_scan_period(cmd)) { |
1903 | unsigned int scan_period; | |
1904 | ||
1905 | scan_period = labpc_ai_scan_period(cmd); | |
1309e617 MD |
1906 | /* |
1907 | * calculate cascaded counter values | |
1908 | * that give desired scan timing | |
1909 | */ | |
124b13b2 | 1910 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, |
0a85b6f0 MT |
1911 | &(devpriv->divisor_b1), |
1912 | &(devpriv->divisor_b0), | |
1913 | &scan_period, | |
1914 | cmd->flags & TRIG_ROUND_MASK); | |
124b13b2 FMH |
1915 | labpc_set_ai_scan_period(cmd, scan_period); |
1916 | } else if (labpc_ai_convert_period(cmd)) { | |
1917 | unsigned int convert_period; | |
1918 | ||
1919 | convert_period = labpc_ai_convert_period(cmd); | |
1309e617 MD |
1920 | /* |
1921 | * calculate cascaded counter values | |
1922 | * that give desired conversion timing | |
1923 | */ | |
124b13b2 | 1924 | i8253_cascade_ns_to_timer_2div(LABPC_TIMER_BASE, |
0a85b6f0 MT |
1925 | &(devpriv->divisor_a0), |
1926 | &(devpriv->divisor_b0), | |
1927 | &convert_period, | |
1928 | cmd->flags & TRIG_ROUND_MASK); | |
124b13b2 FMH |
1929 | labpc_set_ai_convert_period(cmd, convert_period); |
1930 | } | |
1931 | } | |
1932 | ||
1933 | static int labpc_dio_mem_callback(int dir, int port, int data, | |
0a85b6f0 | 1934 | unsigned long iobase) |
124b13b2 FMH |
1935 | { |
1936 | if (dir) { | |
1937 | writeb(data, (void *)(iobase + port)); | |
1938 | return 0; | |
1939 | } else { | |
1940 | return readb((void *)(iobase + port)); | |
1941 | } | |
1942 | } | |
1943 | ||
f6b49620 | 1944 | /* lowlevel write to eeprom/dac */ |
da91b269 | 1945 | static void labpc_serial_out(struct comedi_device *dev, unsigned int value, |
0a85b6f0 | 1946 | unsigned int value_width) |
124b13b2 FMH |
1947 | { |
1948 | int i; | |
1949 | ||
1950 | for (i = 1; i <= value_width; i++) { | |
f6b49620 | 1951 | /* clear serial clock */ |
124b13b2 | 1952 | devpriv->command5_bits &= ~SCLOCK_BIT; |
f6b49620 | 1953 | /* send bits most significant bit first */ |
124b13b2 FMH |
1954 | if (value & (1 << (value_width - i))) |
1955 | devpriv->command5_bits |= SDATA_BIT; | |
1956 | else | |
1957 | devpriv->command5_bits &= ~SDATA_BIT; | |
5f74ea14 | 1958 | udelay(1); |
124b13b2 | 1959 | devpriv->write_byte(devpriv->command5_bits, |
0a85b6f0 | 1960 | dev->iobase + COMMAND5_REG); |
f6b49620 | 1961 | /* set clock to load bit */ |
124b13b2 | 1962 | devpriv->command5_bits |= SCLOCK_BIT; |
5f74ea14 | 1963 | udelay(1); |
124b13b2 | 1964 | devpriv->write_byte(devpriv->command5_bits, |
0a85b6f0 | 1965 | dev->iobase + COMMAND5_REG); |
124b13b2 FMH |
1966 | } |
1967 | } | |
1968 | ||
f6b49620 | 1969 | /* lowlevel read from eeprom */ |
da91b269 | 1970 | static unsigned int labpc_serial_in(struct comedi_device *dev) |
124b13b2 FMH |
1971 | { |
1972 | unsigned int value = 0; | |
1973 | int i; | |
f6b49620 | 1974 | const int value_width = 8; /* number of bits wide values are */ |
124b13b2 FMH |
1975 | |
1976 | for (i = 1; i <= value_width; i++) { | |
f6b49620 | 1977 | /* set serial clock */ |
124b13b2 | 1978 | devpriv->command5_bits |= SCLOCK_BIT; |
5f74ea14 | 1979 | udelay(1); |
124b13b2 | 1980 | devpriv->write_byte(devpriv->command5_bits, |
0a85b6f0 | 1981 | dev->iobase + COMMAND5_REG); |
f6b49620 | 1982 | /* clear clock bit */ |
124b13b2 | 1983 | devpriv->command5_bits &= ~SCLOCK_BIT; |
5f74ea14 | 1984 | udelay(1); |
124b13b2 | 1985 | devpriv->write_byte(devpriv->command5_bits, |
0a85b6f0 | 1986 | dev->iobase + COMMAND5_REG); |
f6b49620 | 1987 | /* read bits most significant bit first */ |
5f74ea14 | 1988 | udelay(1); |
124b13b2 | 1989 | devpriv->status2_bits = |
0a85b6f0 | 1990 | devpriv->read_byte(dev->iobase + STATUS2_REG); |
412bd046 | 1991 | if (devpriv->status2_bits & EEPROM_OUT_BIT) |
124b13b2 | 1992 | value |= 1 << (value_width - i); |
124b13b2 FMH |
1993 | } |
1994 | ||
1995 | return value; | |
1996 | } | |
1997 | ||
0a85b6f0 MT |
1998 | static unsigned int labpc_eeprom_read(struct comedi_device *dev, |
1999 | unsigned int address) | |
124b13b2 FMH |
2000 | { |
2001 | unsigned int value; | |
e41a6f6d SR |
2002 | /* bits to tell eeprom to expect a read */ |
2003 | const int read_instruction = 0x3; | |
2004 | /* 8 bit write lengths to eeprom */ | |
2005 | const int write_length = 8; | |
124b13b2 | 2006 | |
f6b49620 | 2007 | /* enable read/write to eeprom */ |
124b13b2 | 2008 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
5f74ea14 | 2009 | udelay(1); |
124b13b2 FMH |
2010 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2011 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; | |
5f74ea14 | 2012 | udelay(1); |
124b13b2 FMH |
2013 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2014 | ||
f6b49620 | 2015 | /* send read instruction */ |
124b13b2 | 2016 | labpc_serial_out(dev, read_instruction, write_length); |
f6b49620 | 2017 | /* send 8 bit address to read from */ |
124b13b2 | 2018 | labpc_serial_out(dev, address, write_length); |
f6b49620 | 2019 | /* read result */ |
124b13b2 FMH |
2020 | value = labpc_serial_in(dev); |
2021 | ||
f6b49620 | 2022 | /* disable read/write to eeprom */ |
124b13b2 | 2023 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
5f74ea14 | 2024 | udelay(1); |
124b13b2 FMH |
2025 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2026 | ||
2027 | return value; | |
2028 | } | |
2029 | ||
d6269644 JL |
2030 | static int labpc_eeprom_write(struct comedi_device *dev, |
2031 | unsigned int address, unsigned int value) | |
124b13b2 FMH |
2032 | { |
2033 | const int write_enable_instruction = 0x6; | |
2034 | const int write_instruction = 0x2; | |
f6b49620 | 2035 | const int write_length = 8; /* 8 bit write lengths to eeprom */ |
124b13b2 FMH |
2036 | const int write_in_progress_bit = 0x1; |
2037 | const int timeout = 10000; | |
2038 | int i; | |
2039 | ||
f6b49620 | 2040 | /* make sure there isn't already a write in progress */ |
124b13b2 FMH |
2041 | for (i = 0; i < timeout; i++) { |
2042 | if ((labpc_eeprom_read_status(dev) & write_in_progress_bit) == | |
0a85b6f0 | 2043 | 0) |
124b13b2 FMH |
2044 | break; |
2045 | } | |
2046 | if (i == timeout) { | |
2047 | comedi_error(dev, "eeprom write timed out"); | |
2048 | return -ETIME; | |
2049 | } | |
f6b49620 | 2050 | /* update software copy of eeprom */ |
124b13b2 FMH |
2051 | devpriv->eeprom_data[address] = value; |
2052 | ||
f6b49620 | 2053 | /* enable read/write to eeprom */ |
124b13b2 | 2054 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
5f74ea14 | 2055 | udelay(1); |
124b13b2 FMH |
2056 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2057 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; | |
5f74ea14 | 2058 | udelay(1); |
124b13b2 FMH |
2059 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2060 | ||
f6b49620 | 2061 | /* send write_enable instruction */ |
124b13b2 FMH |
2062 | labpc_serial_out(dev, write_enable_instruction, write_length); |
2063 | devpriv->command5_bits &= ~EEPROM_EN_BIT; | |
5f74ea14 | 2064 | udelay(1); |
124b13b2 FMH |
2065 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2066 | ||
f6b49620 | 2067 | /* send write instruction */ |
124b13b2 | 2068 | devpriv->command5_bits |= EEPROM_EN_BIT; |
5f74ea14 | 2069 | udelay(1); |
124b13b2 FMH |
2070 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2071 | labpc_serial_out(dev, write_instruction, write_length); | |
f6b49620 | 2072 | /* send 8 bit address to write to */ |
124b13b2 | 2073 | labpc_serial_out(dev, address, write_length); |
f6b49620 | 2074 | /* write value */ |
124b13b2 FMH |
2075 | labpc_serial_out(dev, value, write_length); |
2076 | devpriv->command5_bits &= ~EEPROM_EN_BIT; | |
5f74ea14 | 2077 | udelay(1); |
124b13b2 FMH |
2078 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2079 | ||
f6b49620 | 2080 | /* disable read/write to eeprom */ |
124b13b2 | 2081 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
5f74ea14 | 2082 | udelay(1); |
124b13b2 FMH |
2083 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2084 | ||
2085 | return 0; | |
2086 | } | |
2087 | ||
da91b269 | 2088 | static unsigned int labpc_eeprom_read_status(struct comedi_device *dev) |
124b13b2 FMH |
2089 | { |
2090 | unsigned int value; | |
2091 | const int read_status_instruction = 0x5; | |
f6b49620 | 2092 | const int write_length = 8; /* 8 bit write lengths to eeprom */ |
124b13b2 | 2093 | |
f6b49620 | 2094 | /* enable read/write to eeprom */ |
124b13b2 | 2095 | devpriv->command5_bits &= ~EEPROM_EN_BIT; |
5f74ea14 | 2096 | udelay(1); |
124b13b2 FMH |
2097 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2098 | devpriv->command5_bits |= EEPROM_EN_BIT | EEPROM_WRITE_UNPROTECT_BIT; | |
5f74ea14 | 2099 | udelay(1); |
124b13b2 FMH |
2100 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2101 | ||
f6b49620 | 2102 | /* send read status instruction */ |
124b13b2 | 2103 | labpc_serial_out(dev, read_status_instruction, write_length); |
f6b49620 | 2104 | /* read result */ |
124b13b2 FMH |
2105 | value = labpc_serial_in(dev); |
2106 | ||
f6b49620 | 2107 | /* disable read/write to eeprom */ |
124b13b2 | 2108 | devpriv->command5_bits &= ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
5f74ea14 | 2109 | udelay(1); |
124b13b2 FMH |
2110 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2111 | ||
2112 | return value; | |
2113 | } | |
2114 | ||
f6b49620 | 2115 | /* writes to 8 bit calibration dacs */ |
da91b269 | 2116 | static void write_caldac(struct comedi_device *dev, unsigned int channel, |
0a85b6f0 | 2117 | unsigned int value) |
124b13b2 FMH |
2118 | { |
2119 | if (value == devpriv->caldac[channel]) | |
2120 | return; | |
2121 | devpriv->caldac[channel] = value; | |
2122 | ||
f6b49620 | 2123 | /* clear caldac load bit and make sure we don't write to eeprom */ |
124b13b2 | 2124 | devpriv->command5_bits &= |
0a85b6f0 | 2125 | ~CALDAC_LOAD_BIT & ~EEPROM_EN_BIT & ~EEPROM_WRITE_UNPROTECT_BIT; |
5f74ea14 | 2126 | udelay(1); |
124b13b2 FMH |
2127 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2128 | ||
f6b49620 | 2129 | /* write 4 bit channel */ |
124b13b2 | 2130 | labpc_serial_out(dev, channel, 4); |
f6b49620 | 2131 | /* write 8 bit caldac value */ |
124b13b2 FMH |
2132 | labpc_serial_out(dev, value, 8); |
2133 | ||
f6b49620 | 2134 | /* set and clear caldac bit to load caldac value */ |
124b13b2 | 2135 | devpriv->command5_bits |= CALDAC_LOAD_BIT; |
5f74ea14 | 2136 | udelay(1); |
124b13b2 FMH |
2137 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2138 | devpriv->command5_bits &= ~CALDAC_LOAD_BIT; | |
5f74ea14 | 2139 | udelay(1); |
124b13b2 FMH |
2140 | devpriv->write_byte(devpriv->command5_bits, dev->iobase + COMMAND5_REG); |
2141 | } | |
2142 | ||
d6aa8366 | 2143 | #ifdef CONFIG_COMEDI_PCI_DRIVERS |
727b286b AT |
2144 | static int __devinit driver_labpc_pci_probe(struct pci_dev *dev, |
2145 | const struct pci_device_id *ent) | |
2146 | { | |
4c093a6d | 2147 | return comedi_pci_auto_config(dev, &driver_labpc); |
727b286b AT |
2148 | } |
2149 | ||
2150 | static void __devexit driver_labpc_pci_remove(struct pci_dev *dev) | |
2151 | { | |
2152 | comedi_pci_auto_unconfig(dev); | |
2153 | } | |
2154 | ||
2155 | static struct pci_driver driver_labpc_pci_driver = { | |
2156 | .id_table = labpc_pci_table, | |
2157 | .probe = &driver_labpc_pci_probe, | |
2158 | .remove = __devexit_p(&driver_labpc_pci_remove) | |
2159 | }; | |
2160 | ||
2161 | static int __init driver_labpc_init_module(void) | |
2162 | { | |
2163 | int retval; | |
2164 | ||
2165 | retval = comedi_driver_register(&driver_labpc); | |
2166 | if (retval < 0) | |
2167 | return retval; | |
2168 | ||
2169 | driver_labpc_pci_driver.name = (char *)driver_labpc.driver_name; | |
2170 | return pci_register_driver(&driver_labpc_pci_driver); | |
2171 | } | |
2172 | ||
2173 | static void __exit driver_labpc_cleanup_module(void) | |
2174 | { | |
2175 | pci_unregister_driver(&driver_labpc_pci_driver); | |
2176 | comedi_driver_unregister(&driver_labpc); | |
2177 | } | |
2178 | ||
2179 | module_init(driver_labpc_init_module); | |
2180 | module_exit(driver_labpc_cleanup_module); | |
124b13b2 | 2181 | #else |
7114a280 AT |
2182 | static int __init driver_labpc_init_module(void) |
2183 | { | |
2184 | return comedi_driver_register(&driver_labpc); | |
2185 | } | |
2186 | ||
2187 | static void __exit driver_labpc_cleanup_module(void) | |
2188 | { | |
2189 | comedi_driver_unregister(&driver_labpc); | |
2190 | } | |
2191 | ||
2192 | module_init(driver_labpc_init_module); | |
2193 | module_exit(driver_labpc_cleanup_module); | |
124b13b2 FMH |
2194 | #endif |
2195 | ||
90f703d3 AT |
2196 | |
2197 | MODULE_AUTHOR("Comedi http://www.comedi.org"); | |
2198 | MODULE_DESCRIPTION("Comedi low-level driver"); | |
2199 | MODULE_LICENSE("GPL"); |