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Staging: comedi: Remove COMEDI_PCI_INITCLEANUP macro
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_pcimio.c
CommitLineData
c4beb34e
DS		 1/*
2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22/*
23Driver: ni_pcimio
24Description: National Instruments PCI-MIO-E series and M series (all boards)
25Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
27Status: works
28Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
ecb8486d 32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PXI-6224, PCI-6225, PXI-6225,
51e290fd 33 PCI-6229, PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
c4beb34e
DS		 34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
35 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
36 PXI-6071E, PCI-6070E, PXI-6070E,
37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
38 PCI-6143, PXI-6143
51e290fd 39Updated: Wed, 03 Dec 2008 10:51:47 +0000
c4beb34e
DS		 40
41These boards are almost identical to the AT-MIO E series, except that
42they use the PCI bus instead of ISA (i.e., AT). See the notes for
43the ni_atmio.o driver for additional information about these boards.
44
45Autocalibration is supported on many of the devices, using the
46comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
47M-Series boards do analog input and analog output calibration entirely
48in software. The software calibration corrects
49the analog input for offset, gain and
50nonlinearity. The analog outputs are corrected for offset and gain.
51See the comedilib documentation on comedi_get_softcal_converter() for
52more information.
53
54By default, the driver uses DMA to transfer analog input data to
55memory. When DMA is enabled, not all triggering features are
56supported.
57
58Digital I/O may not work on 673x.
59
60Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
61With this board all of the convertors perform one simultaineous sample during
62a scan interval. The period for a scan is used for the convert time in a
63Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
64
65The RTSI trigger bus is supported on these cards on
66subdevice 10. See the comedilib documentation for details.
67
68Information (number of channels, bits, etc.) for some devices may be
69incorrect. Please check this and submit a bug if there are problems
70for your device.
71
72SCXI is probably broken for m-series boards.
73
74Bugs:
75 - When DMA is enabled, COMEDI_EV_CONVERT does
76 not work correctly.
77
78*/
79/*
80 The PCI-MIO E series driver was originally written by
81 Tomasz Motylewski <...>, and ported to comedi by ds.
82
83 References:
84
85 341079b.pdf PCI E Series Register-Level Programmer Manual
86 340934b.pdf DAQ-STC reference manual
87
88 322080b.pdf 6711/6713/6715 User Manual
89
90 320945c.pdf PCI E Series User Manual
91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
92
93 ISSUES:
94
95 need to deal with external reference for DAC, and other DAC
96 properties in board properties
97
98 deal with at-mio-16de-10 revision D to N changes, etc.
99
100 need to add other CALDAC type
101
102 need to slow down DAC loading. I don't trust NI's claim that
103 two writes to the PCI bus slows IO enough. I would prefer to
5f74ea14 104 use udelay(). Timing specs: (clock)
c4beb34e
DS		 105 AD8522 30ns
106 DAC8043 120ns
107 DAC8800 60ns
108 MB88341 ?
109
110*/
111
112#include "../comedidev.h"
113
f8db88ef 114#include <asm/byteorder.h>
c4beb34e
DS		 115#include <linux/delay.h>
116
117#include "ni_stc.h"
118#include "mite.h"
119
2696fb57 120/* #define PCI_DEBUG */
c4beb34e
DS		 121
122#define PCIDMA
123
124#define PCIMIO 1
125#undef ATMIO
126
127#define MAX_N_CALDACS (16+16+2)
128
129#define DRV_NAME "ni_pcimio"
130
131/* The following two tables must be in the same order */
132static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = {
4e40cee9
GKH		 133 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x0162)},
134 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1170)},
135 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1180)},
136 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1190)},
137 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11b0)},
138 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11c0)},
139 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x11d0)},
140 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1270)},
141 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1330)},
142 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1340)},
143 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1350)},
144 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14e0)},
145 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x14f0)},
146 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1580)},
147 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x15b0)},
148 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1880)},
149 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x1870)},
150 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18b0)},
151 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x18c0)},
152 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2410)},
153 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2420)},
154 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2430)},
155 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2890)},
156 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x28c0)},
157 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a60)},
158 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a70)},
159 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2a80)},
160 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ab0)},
161 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b80)},
162 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2b90)},
163 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2c80)},
164 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x2ca0)},
165 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70aa)},
166 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ab)},
167 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70ac)},
168 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70af)},
169 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b0)},
170 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b4)},
171 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b6)},
172 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b7)},
173 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70b8)},
174 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bc)},
175 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bd)},
176 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70bf)},
177 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70c0)},
178 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x70f2)},
179 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x710d)},
180 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716c)},
181 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x716d)},
182 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717f)},
183 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x71bc)},
184 {PCI_DEVICE(PCI_VENDOR_ID_NI, 0x717d)},
185 {0}
c4beb34e
DS		 186};
187
188MODULE_DEVICE_TABLE(pci, ni_pci_table);
189
190/* These are not all the possible ao ranges for 628x boards.
191 They can do OFFSET +- REFERENCE where OFFSET can be
192 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
193 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
194 63 different possibilities. An AO channel
195 can not act as it's own OFFSET or REFERENCE.
196*/
9ced1de6 197static const struct comedi_lrange range_ni_M_628x_ao = { 8, {
0a85b6f0
MT		 198 RANGE(-10, 10),
199 RANGE(-5, 5),
200 RANGE(-2, 2),
201 RANGE(-1, 1),
202 RANGE(-5, 15),
203 RANGE(0, 10),
204 RANGE(3, 7),
205 RANGE(4, 6),
206 RANGE_ext(-1, 1)
207 }
c4beb34e 208};
0a85b6f0 209
9ced1de6 210static const struct comedi_lrange range_ni_M_625x_ao = { 3, {
0a85b6f0
MT		 211 RANGE(-10, 10),
212 RANGE(-5, 5),
213 RANGE_ext(-1, 1)
214 }
c4beb34e 215};
0a85b6f0 216
9ced1de6 217static const struct comedi_lrange range_ni_M_622x_ao = { 1, {
0a85b6f0
MT		 218 RANGE(-10, 10),
219 }
c4beb34e
DS		 220};
221
8ab41df0 222static const struct ni_board_struct ni_boards[] = {
c4beb34e 223 {
0a85b6f0
MT		 224 .device_id = 0x0162, /* NI also says 0x1620. typo? */
225 .name = "pci-mio-16xe-50",
226 .n_adchan = 16,
227 .adbits = 16,
228 .ai_fifo_depth = 2048,
229 .alwaysdither = 1,
230 .gainlkup = ai_gain_8,
231 .ai_speed = 50000,
232 .n_aochan = 2,
233 .aobits = 12,
234 .ao_fifo_depth = 0,
235 .ao_range_table = &range_bipolar10,
236 .ao_unipolar = 0,
237 .ao_speed = 50000,
238 .num_p0_dio_channels = 8,
239 .caldac = {dac8800, dac8043},
240 .has_8255 = 0,
241 },
c4beb34e 242 {
0a85b6f0
MT		 243 .device_id = 0x1170,
244 .name = "pci-mio-16xe-10", /* aka pci-6030E */
245 .n_adchan = 16,
246 .adbits = 16,
247 .ai_fifo_depth = 512,
248 .alwaysdither = 1,
249 .gainlkup = ai_gain_14,
250 .ai_speed = 10000,
251 .n_aochan = 2,
252 .aobits = 16,
253 .ao_fifo_depth = 2048,
254 .ao_range_table = &range_ni_E_ao_ext,
255 .ao_unipolar = 1,
256 .ao_speed = 10000,
257 .num_p0_dio_channels = 8,
258 .caldac = {dac8800, dac8043, ad8522},
259 .has_8255 = 0,
260 },
c4beb34e 261 {
0a85b6f0
MT		 262 .device_id = 0x28c0,
263 .name = "pci-6014",
264 .n_adchan = 16,
265 .adbits = 16,
266 .ai_fifo_depth = 512,
267 .alwaysdither = 1,
268 .gainlkup = ai_gain_4,
269 .ai_speed = 5000,
270 .n_aochan = 2,
271 .aobits = 16,
272 .ao_fifo_depth = 0,
273 .ao_range_table = &range_bipolar10,
274 .ao_unipolar = 0,
275 .ao_speed = 100000,
276 .num_p0_dio_channels = 8,
277 .caldac = {ad8804_debug},
278 .has_8255 = 0,
279 },
c4beb34e 280 {
0a85b6f0
MT		 281 .device_id = 0x11d0,
282 .name = "pxi-6030e",
283 .n_adchan = 16,
284 .adbits = 16,
285 .ai_fifo_depth = 512,
286 .alwaysdither = 1,
287 .gainlkup = ai_gain_14,
288 .ai_speed = 10000,
289 .n_aochan = 2,
290 .aobits = 16,
291 .ao_fifo_depth = 2048,
292 .ao_range_table = &range_ni_E_ao_ext,
293 .ao_unipolar = 1,
294 .ao_speed = 10000,
295 .num_p0_dio_channels = 8,
296 .caldac = {dac8800, dac8043, ad8522},
297 .has_8255 = 0,
298 },
c4beb34e 299 {
0a85b6f0
MT		 300 .device_id = 0x1180,
301 .name = "pci-mio-16e-1", /* aka pci-6070e */
302 .n_adchan = 16,
303 .adbits = 12,
304 .ai_fifo_depth = 512,
305 .alwaysdither = 0,
306 .gainlkup = ai_gain_16,
307 .ai_speed = 800,
308 .n_aochan = 2,
309 .aobits = 12,
310 .ao_fifo_depth = 2048,
311 .ao_range_table = &range_ni_E_ao_ext,
312 .ao_unipolar = 1,
313 .ao_speed = 1000,
314 .num_p0_dio_channels = 8,
315 .caldac = {mb88341},
316 .has_8255 = 0,
317 },
c4beb34e 318 {
0a85b6f0
MT		 319 .device_id = 0x1190,
320 .name = "pci-mio-16e-4", /* aka pci-6040e */
321 .n_adchan = 16,
322 .adbits = 12,
323 .ai_fifo_depth = 512,
324 .alwaysdither = 0,
325 .gainlkup = ai_gain_16,
326 /* .Note = there have been reported problems with full speed
327 * on this board */
328 .ai_speed = 2000,
329 .n_aochan = 2,
330 .aobits = 12,
331 .ao_fifo_depth = 512,
332 .ao_range_table = &range_ni_E_ao_ext,
333 .ao_unipolar = 1,
334 .ao_speed = 1000,
335 .num_p0_dio_channels = 8,
336 .caldac = {ad8804_debug}, /* doc says mb88341 */
337 .has_8255 = 0,
338 },
c4beb34e 339 {
0a85b6f0
MT		 340 .device_id = 0x11c0,
341 .name = "pxi-6040e",
342 .n_adchan = 16,
343 .adbits = 12,
344 .ai_fifo_depth = 512,
345 .alwaysdither = 0,
346 .gainlkup = ai_gain_16,
347 .ai_speed = 2000,
348 .n_aochan = 2,
349 .aobits = 12,
350 .ao_fifo_depth = 512,
351 .ao_range_table = &range_ni_E_ao_ext,
352 .ao_unipolar = 1,
353 .ao_speed = 1000,
354 .num_p0_dio_channels = 8,
355 .caldac = {mb88341},
356 .has_8255 = 0,
357 },
c4beb34e
DS		 358
359 {
0a85b6f0
MT		 360 .device_id = 0x1330,
361 .name = "pci-6031e",
362 .n_adchan = 64,
363 .adbits = 16,
364 .ai_fifo_depth = 512,
365 .alwaysdither = 1,
366 .gainlkup = ai_gain_14,
367 .ai_speed = 10000,
368 .n_aochan = 2,
369 .aobits = 16,
370 .ao_fifo_depth = 2048,
371 .ao_range_table = &range_ni_E_ao_ext,
372 .ao_unipolar = 1,
373 .ao_speed = 10000,
374 .num_p0_dio_channels = 8,
375 .caldac = {dac8800, dac8043, ad8522},
376 .has_8255 = 0,
377 },
c4beb34e 378 {
0a85b6f0
MT		 379 .device_id = 0x1270,
380 .name = "pci-6032e",
381 .n_adchan = 16,
382 .adbits = 16,
383 .ai_fifo_depth = 512,
384 .alwaysdither = 1,
385 .gainlkup = ai_gain_14,
386 .ai_speed = 10000,
387 .n_aochan = 0,
388 .aobits = 0,
389 .ao_fifo_depth = 0,
390 .ao_unipolar = 0,
391 .num_p0_dio_channels = 8,
392 .caldac = {dac8800, dac8043, ad8522},
393 .has_8255 = 0,
394 },
c4beb34e 395 {
0a85b6f0
MT		 396 .device_id = 0x1340,
397 .name = "pci-6033e",
398 .n_adchan = 64,
399 .adbits = 16,
400 .ai_fifo_depth = 512,
401 .alwaysdither = 1,
402 .gainlkup = ai_gain_14,
403 .ai_speed = 10000,
404 .n_aochan = 0,
405 .aobits = 0,
406 .ao_fifo_depth = 0,
407 .ao_unipolar = 0,
408 .num_p0_dio_channels = 8,
409 .caldac = {dac8800, dac8043, ad8522},
410 .has_8255 = 0,
411 },
c4beb34e 412 {
0a85b6f0
MT		 413 .device_id = 0x1350,
414 .name = "pci-6071e",
415 .n_adchan = 64,
416 .adbits = 12,
417 .ai_fifo_depth = 512,
418 .alwaysdither = 1,
419 .gainlkup = ai_gain_16,
420 .ai_speed = 800,
421 .n_aochan = 2,
422 .aobits = 12,
423 .ao_fifo_depth = 2048,
424 .ao_range_table = &range_ni_E_ao_ext,
425 .ao_unipolar = 1,
426 .ao_speed = 1000,
427 .num_p0_dio_channels = 8,
428 .caldac = {ad8804_debug},
429 .has_8255 = 0,
430 },
c4beb34e 431 {
0a85b6f0
MT		 432 .device_id = 0x2a60,
433 .name = "pci-6023e",
434 .n_adchan = 16,
435 .adbits = 12,
436 .ai_fifo_depth = 512,
437 .alwaysdither = 0,
438 .gainlkup = ai_gain_4,
439 .ai_speed = 5000,
440 .n_aochan = 0,
441 .aobits = 0,
442 .ao_unipolar = 0,
443 .num_p0_dio_channels = 8,
444 .caldac = {ad8804_debug}, /* manual is wrong */
445 .has_8255 = 0,
446 },
c4beb34e 447 {
0a85b6f0
MT		 448 .device_id = 0x2a70,
449 .name = "pci-6024e",
450 .n_adchan = 16,
451 .adbits = 12,
452 .ai_fifo_depth = 512,
453 .alwaysdither = 0,
454 .gainlkup = ai_gain_4,
455 .ai_speed = 5000,
456 .n_aochan = 2,
457 .aobits = 12,
458 .ao_fifo_depth = 0,
459 .ao_range_table = &range_bipolar10,
460 .ao_unipolar = 0,
461 .ao_speed = 100000,
462 .num_p0_dio_channels = 8,
463 .caldac = {ad8804_debug}, /* manual is wrong */
464 .has_8255 = 0,
465 },
c4beb34e 466 {
0a85b6f0
MT		 467 .device_id = 0x2a80,
468 .name = "pci-6025e",
469 .n_adchan = 16,
470 .adbits = 12,
471 .ai_fifo_depth = 512,
472 .alwaysdither = 0,
473 .gainlkup = ai_gain_4,
474 .ai_speed = 5000,
475 .n_aochan = 2,
476 .aobits = 12,
477 .ao_fifo_depth = 0,
478 .ao_range_table = &range_bipolar10,
479 .ao_unipolar = 0,
480 .ao_speed = 100000,
481 .num_p0_dio_channels = 8,
482 .caldac = {ad8804_debug}, /* manual is wrong */
483 .has_8255 = 1,
484 },
c4beb34e 485 {
0a85b6f0
MT		 486 .device_id = 0x2ab0,
487 .name = "pxi-6025e",
488 .n_adchan = 16,
489 .adbits = 12,
490 .ai_fifo_depth = 512,
491 .alwaysdither = 0,
492 .gainlkup = ai_gain_4,
493 .ai_speed = 5000,
494 .n_aochan = 2,
495 .aobits = 12,
496 .ao_fifo_depth = 0,
497 .ao_range_table = &range_ni_E_ao_ext,
498 .ao_unipolar = 1,
499 .ao_speed = 100000,
500 .num_p0_dio_channels = 8,
501 .caldac = {ad8804_debug}, /* manual is wrong */
502 .has_8255 = 1,
503 },
c4beb34e
DS		 504
505 {
0a85b6f0
MT		 506 .device_id = 0x2ca0,
507 .name = "pci-6034e",
508 .n_adchan = 16,
509 .adbits = 16,
510 .ai_fifo_depth = 512,
511 .alwaysdither = 1,
512 .gainlkup = ai_gain_4,
513 .ai_speed = 5000,
514 .n_aochan = 0,
515 .aobits = 0,
516 .ao_fifo_depth = 0,
517 .ao_unipolar = 0,
518 .num_p0_dio_channels = 8,
519 .caldac = {ad8804_debug},
520 .has_8255 = 0,
521 },
c4beb34e 522 {
0a85b6f0
MT		 523 .device_id = 0x2c80,
524 .name = "pci-6035e",
525 .n_adchan = 16,
526 .adbits = 16,
527 .ai_fifo_depth = 512,
528 .alwaysdither = 1,
529 .gainlkup = ai_gain_4,
530 .ai_speed = 5000,
531 .n_aochan = 2,
532 .aobits = 12,
533 .ao_fifo_depth = 0,
534 .ao_range_table = &range_bipolar10,
535 .ao_unipolar = 0,
536 .ao_speed = 100000,
537 .num_p0_dio_channels = 8,
538 .caldac = {ad8804_debug},
539 .has_8255 = 0,
540 },
c4beb34e 541 {
0a85b6f0
MT		 542 .device_id = 0x18b0,
543 .name = "pci-6052e",
544 .n_adchan = 16,
545 .adbits = 16,
546 .ai_fifo_depth = 512,
547 .alwaysdither = 1,
548 .gainlkup = ai_gain_16,
549 .ai_speed = 3000,
550 .n_aochan = 2,
551 .aobits = 16,
552 .ao_unipolar = 1,
553 .ao_fifo_depth = 2048,
554 .ao_range_table = &range_ni_E_ao_ext,
555 .ao_speed = 3000,
556 .num_p0_dio_channels = 8,
557 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */
558 },
c4beb34e 559 {.device_id = 0x14e0,
0a85b6f0
MT		 560 .name = "pci-6110",
561 .n_adchan = 4,
562 .adbits = 12,
563 .ai_fifo_depth = 8192,
564 .alwaysdither = 0,
565 .gainlkup = ai_gain_611x,
566 .ai_speed = 200,
567 .n_aochan = 2,
568 .aobits = 16,
569 .reg_type = ni_reg_611x,
570 .ao_range_table = &range_bipolar10,
571 .ao_unipolar = 0,
572 .ao_fifo_depth = 2048,
573 .ao_speed = 250,
574 .num_p0_dio_channels = 8,
575 .caldac = {ad8804, ad8804},
576 },
c4beb34e 577 {
0a85b6f0
MT		 578 .device_id = 0x14f0,
579 .name = "pci-6111",
580 .n_adchan = 2,
581 .adbits = 12,
582 .ai_fifo_depth = 8192,
583 .alwaysdither = 0,
584 .gainlkup = ai_gain_611x,
585 .ai_speed = 200,
586 .n_aochan = 2,
587 .aobits = 16,
588 .reg_type = ni_reg_611x,
589 .ao_range_table = &range_bipolar10,
590 .ao_unipolar = 0,
591 .ao_fifo_depth = 2048,
592 .ao_speed = 250,
593 .num_p0_dio_channels = 8,
594 .caldac = {ad8804, ad8804},
595 },
c4beb34e
DS		 596#if 0
597 /* The 6115 boards probably need their own driver */
598 {
0a85b6f0
MT		 599 .device_id = 0x2ed0,
600 .name = "pci-6115",
601 .n_adchan = 4,
602 .adbits = 12,
603 .ai_fifo_depth = 8192,
604 .alwaysdither = 0,
605 .gainlkup = ai_gain_611x,
606 .ai_speed = 100,
607 .n_aochan = 2,
608 .aobits = 16,
609 .ao_671x = 1,
610 .ao_unipolar = 0,
611 .ao_fifo_depth = 2048,
612 .ao_speed = 250,
613 .num_p0_dio_channels = 8,
614 .reg_611x = 1,
615 .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
616 },
c4beb34e
DS		 617#endif
618#if 0
619 {
0a85b6f0
MT		 620 .device_id = 0x0000,
621 .name = "pxi-6115",
622 .n_adchan = 4,
623 .adbits = 12,
624 .ai_fifo_depth = 8192,
625 .alwaysdither = 0,
626 .gainlkup = ai_gain_611x,
627 .ai_speed = 100,
628 .n_aochan = 2,
629 .aobits = 16,
630 .ao_671x = 1,
631 .ao_unipolar = 0,
632 .ao_fifo_depth = 2048,
633 .ao_speed = 250,
634 .reg_611x = 1,
635 .num_p0_dio_channels = 8,
636 caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
637 },
c4beb34e
DS		 638#endif
639 {
0a85b6f0
MT		 640 .device_id = 0x1880,
641 .name = "pci-6711",
642 .n_adchan = 0, /* no analog input */
643 .n_aochan = 4,
644 .aobits = 12,
645 .ao_unipolar = 0,
646 .ao_fifo_depth = 16384,
647 /* data sheet says 8192, but fifo really holds 16384 samples */
648 .ao_range_table = &range_bipolar10,
649 .ao_speed = 1000,
650 .num_p0_dio_channels = 8,
651 .reg_type = ni_reg_6711,
652 .caldac = {ad8804_debug},
653 },
c4beb34e 654 {
0a85b6f0
MT		 655 .device_id = 0x2b90,
656 .name = "pxi-6711",
657 .n_adchan = 0, /* no analog input */
658 .n_aochan = 4,
659 .aobits = 12,
660 .ao_unipolar = 0,
661 .ao_fifo_depth = 16384,
662 .ao_range_table = &range_bipolar10,
663 .ao_speed = 1000,
664 .num_p0_dio_channels = 8,
665 .reg_type = ni_reg_6711,
666 .caldac = {ad8804_debug},
667 },
c4beb34e 668 {
0a85b6f0
MT		 669 .device_id = 0x1870,
670 .name = "pci-6713",
671 .n_adchan = 0, /* no analog input */
672 .n_aochan = 8,
673 .aobits = 12,
674 .ao_unipolar = 0,
675 .ao_fifo_depth = 16384,
676 .ao_range_table = &range_bipolar10,
677 .ao_speed = 1000,
678 .num_p0_dio_channels = 8,
679 .reg_type = ni_reg_6713,
680 .caldac = {ad8804_debug, ad8804_debug},
681 },
c4beb34e 682 {
0a85b6f0
MT		 683 .device_id = 0x2b80,
684 .name = "pxi-6713",
685 .n_adchan = 0, /* no analog input */
686 .n_aochan = 8,
687 .aobits = 12,
688 .ao_unipolar = 0,
689 .ao_fifo_depth = 16384,
690 .ao_range_table = &range_bipolar10,
691 .ao_speed = 1000,
692 .num_p0_dio_channels = 8,
693 .reg_type = ni_reg_6713,
694 .caldac = {ad8804_debug, ad8804_debug},
695 },
c4beb34e 696 {
0a85b6f0
MT		 697 .device_id = 0x2430,
698 .name = "pci-6731",
699 .n_adchan = 0, /* no analog input */
700 .n_aochan = 4,
701 .aobits = 16,
702 .ao_unipolar = 0,
703 .ao_fifo_depth = 8192,
704 .ao_range_table = &range_bipolar10,
705 .ao_speed = 1000,
706 .num_p0_dio_channels = 8,
707 .reg_type = ni_reg_6711,
708 .caldac = {ad8804_debug},
709 },
c4beb34e
DS		 710#if 0 /* need device ids */
711 {
0a85b6f0
MT		 712 .device_id = 0x0,
713 .name = "pxi-6731",
714 .n_adchan = 0, /* no analog input */
715 .n_aochan = 4,
716 .aobits = 16,
717 .ao_unipolar = 0,
718 .ao_fifo_depth = 8192,
719 .ao_range_table = &range_bipolar10,
720 .num_p0_dio_channels = 8,
721 .reg_type = ni_reg_6711,
722 .caldac = {ad8804_debug},
723 },
c4beb34e
DS		 724#endif
725 {
0a85b6f0
MT		 726 .device_id = 0x2410,
727 .name = "pci-6733",
728 .n_adchan = 0, /* no analog input */
729 .n_aochan = 8,
730 .aobits = 16,
731 .ao_unipolar = 0,
732 .ao_fifo_depth = 16384,
733 .ao_range_table = &range_bipolar10,
734 .ao_speed = 1000,
735 .num_p0_dio_channels = 8,
736 .reg_type = ni_reg_6713,
737 .caldac = {ad8804_debug, ad8804_debug},
738 },
c4beb34e 739 {
0a85b6f0
MT		 740 .device_id = 0x2420,
741 .name = "pxi-6733",
742 .n_adchan = 0, /* no analog input */
743 .n_aochan = 8,
744 .aobits = 16,
745 .ao_unipolar = 0,
746 .ao_fifo_depth = 16384,
747 .ao_range_table = &range_bipolar10,
748 .ao_speed = 1000,
749 .num_p0_dio_channels = 8,
750 .reg_type = ni_reg_6713,
751 .caldac = {ad8804_debug, ad8804_debug},
752 },
c4beb34e 753 {
0a85b6f0
MT		 754 .device_id = 0x15b0,
755 .name = "pxi-6071e",
756 .n_adchan = 64,
757 .adbits = 12,
758 .ai_fifo_depth = 512,
759 .alwaysdither = 1,
760 .gainlkup = ai_gain_16,
761 .ai_speed = 800,
762 .n_aochan = 2,
763 .aobits = 12,
764 .ao_fifo_depth = 2048,
765 .ao_range_table = &range_ni_E_ao_ext,
766 .ao_unipolar = 1,
767 .ao_speed = 1000,
768 .num_p0_dio_channels = 8,
769 .caldac = {ad8804_debug},
770 .has_8255 = 0,
771 },
c4beb34e 772 {
0a85b6f0
MT		 773 .device_id = 0x11b0,
774 .name = "pxi-6070e",
775 .n_adchan = 16,
776 .adbits = 12,
777 .ai_fifo_depth = 512,
778 .alwaysdither = 1,
779 .gainlkup = ai_gain_16,
780 .ai_speed = 800,
781 .n_aochan = 2,
782 .aobits = 12,
783 .ao_fifo_depth = 2048,
784 .ao_range_table = &range_ni_E_ao_ext,
785 .ao_unipolar = 1,
786 .ao_speed = 1000,
787 .num_p0_dio_channels = 8,
788 .caldac = {ad8804_debug},
789 .has_8255 = 0,
790 },
c4beb34e 791 {
0a85b6f0
MT		 792 .device_id = 0x18c0,
793 .name = "pxi-6052e",
794 .n_adchan = 16,
795 .adbits = 16,
796 .ai_fifo_depth = 512,
797 .alwaysdither = 1,
798 .gainlkup = ai_gain_16,
799 .ai_speed = 3000,
800 .n_aochan = 2,
801 .aobits = 16,
802 .ao_unipolar = 1,
803 .ao_fifo_depth = 2048,
804 .ao_range_table = &range_ni_E_ao_ext,
805 .ao_speed = 3000,
806 .num_p0_dio_channels = 8,
807 .caldac = {mb88341, mb88341, ad8522},
808 },
c4beb34e 809 {
0a85b6f0
MT		 810 .device_id = 0x1580,
811 .name = "pxi-6031e",
812 .n_adchan = 64,
813 .adbits = 16,
814 .ai_fifo_depth = 512,
815 .alwaysdither = 1,
816 .gainlkup = ai_gain_14,
817 .ai_speed = 10000,
818 .n_aochan = 2,
819 .aobits = 16,
820 .ao_fifo_depth = 2048,
821 .ao_range_table = &range_ni_E_ao_ext,
822 .ao_unipolar = 1,
823 .ao_speed = 10000,
824 .num_p0_dio_channels = 8,
825 .caldac = {dac8800, dac8043, ad8522},
826 },
c4beb34e 827 {
0a85b6f0
MT		 828 .device_id = 0x2890,
829 .name = "pci-6036e",
830 .n_adchan = 16,
831 .adbits = 16,
832 .ai_fifo_depth = 512,
833 .alwaysdither = 1,
834 .gainlkup = ai_gain_4,
835 .ai_speed = 5000,
836 .n_aochan = 2,
837 .aobits = 16,
838 .ao_fifo_depth = 0,
839 .ao_range_table = &range_bipolar10,
840 .ao_unipolar = 0,
841 .ao_speed = 100000,
842 .num_p0_dio_channels = 8,
843 .caldac = {ad8804_debug},
844 .has_8255 = 0,
845 },
c4beb34e 846 {
0a85b6f0
MT		 847 .device_id = 0x70b0,
848 .name = "pci-6220",
849 .n_adchan = 16,
850 .adbits = 16,
851 .ai_fifo_depth = 512,
852 /* .FIXME = guess */
853 .gainlkup = ai_gain_622x,
854 .ai_speed = 4000,
855 .n_aochan = 0,
856 .aobits = 0,
857 .ao_fifo_depth = 0,
858 .num_p0_dio_channels = 8,
859 .reg_type = ni_reg_622x,
860 .ao_unipolar = 0,
861 .caldac = {caldac_none},
862 .has_8255 = 0,
863 },
c4beb34e 864 {
0a85b6f0
MT		 865 .device_id = 0x70af,
866 .name = "pci-6221",
867 .n_adchan = 16,
868 .adbits = 16,
869 .ai_fifo_depth = 4095,
870 .gainlkup = ai_gain_622x,
871 .ai_speed = 4000,
872 .n_aochan = 2,
873 .aobits = 16,
874 .ao_fifo_depth = 8191,
875 .ao_range_table = &range_ni_M_622x_ao,
876 .reg_type = ni_reg_622x,
877 .ao_unipolar = 0,
878 .ao_speed = 1200,
879 .num_p0_dio_channels = 8,
880 .caldac = {caldac_none},
881 .has_8255 = 0,
882 },
c4beb34e 883 {
0a85b6f0
MT		 884 .device_id = 0x71bc,
885 .name = "pci-6221_37pin",
886 .n_adchan = 16,
887 .adbits = 16,
888 .ai_fifo_depth = 4095,
889 .gainlkup = ai_gain_622x,
890 .ai_speed = 4000,
891 .n_aochan = 2,
892 .aobits = 16,
893 .ao_fifo_depth = 8191,
894 .ao_range_table = &range_ni_M_622x_ao,
895 .reg_type = ni_reg_622x,
896 .ao_unipolar = 0,
897 .ao_speed = 1200,
898 .num_p0_dio_channels = 8,
899 .caldac = {caldac_none},
900 .has_8255 = 0,
901 },
c4beb34e 902 {
0a85b6f0
MT		 903 .device_id = 0x70f2,
904 .name = "pci-6224",
905 .n_adchan = 32,
906 .adbits = 16,
907 .ai_fifo_depth = 4095,
908 .gainlkup = ai_gain_622x,
909 .ai_speed = 4000,
910 .n_aochan = 0,
911 .aobits = 0,
912 .ao_fifo_depth = 0,
913 .reg_type = ni_reg_622x,
914 .ao_unipolar = 0,
915 .num_p0_dio_channels = 32,
916 .caldac = {caldac_none},
917 .has_8255 = 0,
918 },
51e290fd 919 {
0a85b6f0
MT		 920 .device_id = 0x70f3,
921 .name = "pxi-6224",
922 .n_adchan = 32,
923 .adbits = 16,
924 .ai_fifo_depth = 4095,
925 .gainlkup = ai_gain_622x,
926 .ai_speed = 4000,
927 .n_aochan = 0,
928 .aobits = 0,
929 .ao_fifo_depth = 0,
930 .reg_type = ni_reg_622x,
931 .ao_unipolar = 0,
932 .num_p0_dio_channels = 32,
933 .caldac = {caldac_none},
934 .has_8255 = 0,
935 },
c4beb34e 936 {
0a85b6f0
MT		 937 .device_id = 0x716c,
938 .name = "pci-6225",
939 .n_adchan = 80,
940 .adbits = 16,
941 .ai_fifo_depth = 4095,
942 .gainlkup = ai_gain_622x,
943 .ai_speed = 4000,
944 .n_aochan = 2,
945 .aobits = 16,
946 .ao_fifo_depth = 8191,
947 .ao_range_table = &range_ni_M_622x_ao,
948 .reg_type = ni_reg_622x,
949 .ao_unipolar = 0,
950 .ao_speed = 1200,
951 .num_p0_dio_channels = 32,
952 .caldac = {caldac_none},
953 .has_8255 = 0,
954 },
ecb8486d
FMH		 955 {
956 .device_id = 0x716d,
957 .name = "pxi-6225",
958 .n_adchan = 80,
959 .adbits = 16,
960 .ai_fifo_depth = 4095,
961 .gainlkup = ai_gain_622x,
962 .ai_speed = 4000,
963 .n_aochan = 2,
964 .aobits = 16,
965 .ao_fifo_depth = 8191,
966 .ao_range_table = &range_ni_M_622x_ao,
967 .reg_type = ni_reg_622x,
968 .ao_unipolar = 0,
969 .ao_speed = 1200,
970 .num_p0_dio_channels = 32,
971 .caldac = {caldac_none},
972 .has_8255 = 0,
973 },
c4beb34e 974 {
0a85b6f0
MT		 975 .device_id = 0x70aa,
976 .name = "pci-6229",
977 .n_adchan = 32,
978 .adbits = 16,
979 .ai_fifo_depth = 4095,
980 .gainlkup = ai_gain_622x,
981 .ai_speed = 4000,
982 .n_aochan = 4,
983 .aobits = 16,
984 .ao_fifo_depth = 8191,
985 .ao_range_table = &range_ni_M_622x_ao,
986 .reg_type = ni_reg_622x,
987 .ao_unipolar = 0,
988 .ao_speed = 1200,
989 .num_p0_dio_channels = 32,
990 .caldac = {caldac_none},
991 .has_8255 = 0,
992 },
c4beb34e 993 {
0a85b6f0
MT		 994 .device_id = 0x70b4,
995 .name = "pci-6250",
996 .n_adchan = 16,
997 .adbits = 16,
998 .ai_fifo_depth = 4095,
999 .gainlkup = ai_gain_628x,
1000 .ai_speed = 800,
1001 .n_aochan = 0,
1002 .aobits = 0,
1003 .ao_fifo_depth = 0,
1004 .reg_type = ni_reg_625x,
1005 .ao_unipolar = 0,
1006 .num_p0_dio_channels = 8,
1007 .caldac = {caldac_none},
1008 .has_8255 = 0,
1009 },
c4beb34e 1010 {
0a85b6f0
MT		 1011 .device_id = 0x70b8,
1012 .name = "pci-6251",
1013 .n_adchan = 16,
1014 .adbits = 16,
1015 .ai_fifo_depth = 4095,
1016 .gainlkup = ai_gain_628x,
1017 .ai_speed = 800,
1018 .n_aochan = 2,
1019 .aobits = 16,
1020 .ao_fifo_depth = 8191,
1021 .ao_range_table = &range_ni_M_625x_ao,
1022 .reg_type = ni_reg_625x,
1023 .ao_unipolar = 0,
1024 .ao_speed = 357,
1025 .num_p0_dio_channels = 8,
1026 .caldac = {caldac_none},
1027 .has_8255 = 0,
1028 },
c4beb34e 1029 {
0a85b6f0
MT		 1030 .device_id = 0x717d,
1031 .name = "pcie-6251",
1032 .n_adchan = 16,
1033 .adbits = 16,
1034 .ai_fifo_depth = 4095,
1035 .gainlkup = ai_gain_628x,
1036 .ai_speed = 800,
1037 .n_aochan = 2,
1038 .aobits = 16,
1039 .ao_fifo_depth = 8191,
1040 .ao_range_table = &range_ni_M_625x_ao,
1041 .reg_type = ni_reg_625x,
1042 .ao_unipolar = 0,
1043 .ao_speed = 357,
1044 .num_p0_dio_channels = 8,
1045 .caldac = {caldac_none},
1046 .has_8255 = 0,
1047 },
c4beb34e 1048 {
0a85b6f0
MT		 1049 .device_id = 0x70b7,
1050 .name = "pci-6254",
1051 .n_adchan = 32,
1052 .adbits = 16,
1053 .ai_fifo_depth = 4095,
1054 .gainlkup = ai_gain_628x,
1055 .ai_speed = 800,
1056 .n_aochan = 0,
1057 .aobits = 0,
1058 .ao_fifo_depth = 0,
1059 .reg_type = ni_reg_625x,
1060 .ao_unipolar = 0,
1061 .num_p0_dio_channels = 32,
1062 .caldac = {caldac_none},
1063 .has_8255 = 0,
1064 },
c4beb34e 1065 {
0a85b6f0
MT		 1066 .device_id = 0x70ab,
1067 .name = "pci-6259",
1068 .n_adchan = 32,
1069 .adbits = 16,
1070 .ai_fifo_depth = 4095,
1071 .gainlkup = ai_gain_628x,
1072 .ai_speed = 800,
1073 .n_aochan = 4,
1074 .aobits = 16,
1075 .ao_fifo_depth = 8191,
1076 .ao_range_table = &range_ni_M_625x_ao,
1077 .reg_type = ni_reg_625x,
1078 .ao_unipolar = 0,
1079 .ao_speed = 357,
1080 .num_p0_dio_channels = 32,
1081 .caldac = {caldac_none},
1082 .has_8255 = 0,
1083 },
c4beb34e 1084 {
0a85b6f0
MT		 1085 .device_id = 0x717f,
1086 .name = "pcie-6259",
1087 .n_adchan = 32,
1088 .adbits = 16,
1089 .ai_fifo_depth = 4095,
1090 .gainlkup = ai_gain_628x,
1091 .ai_speed = 800,
1092 .n_aochan = 4,
1093 .aobits = 16,
1094 .ao_fifo_depth = 8191,
1095 .ao_range_table = &range_ni_M_625x_ao,
1096 .reg_type = ni_reg_625x,
1097 .ao_unipolar = 0,
1098 .ao_speed = 357,
1099 .num_p0_dio_channels = 32,
1100 .caldac = {caldac_none},
1101 .has_8255 = 0,
1102 },
c4beb34e 1103 {
0a85b6f0
MT		 1104 .device_id = 0x70b6,
1105 .name = "pci-6280",
1106 .n_adchan = 16,
1107 .adbits = 18,
1108 .ai_fifo_depth = 2047,
1109 .gainlkup = ai_gain_628x,
1110 .ai_speed = 1600,
1111 .n_aochan = 0,
1112 .aobits = 0,
1113 .ao_fifo_depth = 8191,
1114 .reg_type = ni_reg_628x,
1115 .ao_unipolar = 0,
1116 .num_p0_dio_channels = 8,
1117 .caldac = {caldac_none},
1118 .has_8255 = 0,
1119 },
c4beb34e 1120 {
0a85b6f0
MT		 1121 .device_id = 0x70bd,
1122 .name = "pci-6281",
1123 .n_adchan = 16,
1124 .adbits = 18,
1125 .ai_fifo_depth = 2047,
1126 .gainlkup = ai_gain_628x,
1127 .ai_speed = 1600,
1128 .n_aochan = 2,
1129 .aobits = 16,
1130 .ao_fifo_depth = 8191,
1131 .ao_range_table = &range_ni_M_628x_ao,
1132 .reg_type = ni_reg_628x,
1133 .ao_unipolar = 1,
1134 .ao_speed = 357,
1135 .num_p0_dio_channels = 8,
1136 .caldac = {caldac_none},
1137 .has_8255 = 0,
1138 },
c4beb34e 1139 {
0a85b6f0
MT		 1140 .device_id = 0x70bf,
1141 .name = "pxi-6281",
1142 .n_adchan = 16,
1143 .adbits = 18,
1144 .ai_fifo_depth = 2047,
1145 .gainlkup = ai_gain_628x,
1146 .ai_speed = 1600,
1147 .n_aochan = 2,
1148 .aobits = 16,
1149 .ao_fifo_depth = 8191,
1150 .ao_range_table = &range_ni_M_628x_ao,
1151 .reg_type = ni_reg_628x,
1152 .ao_unipolar = 1,
1153 .ao_speed = 357,
1154 .num_p0_dio_channels = 8,
1155 .caldac = {caldac_none},
1156 .has_8255 = 0,
1157 },
c4beb34e 1158 {
0a85b6f0
MT		 1159 .device_id = 0x70bc,
1160 .name = "pci-6284",
1161 .n_adchan = 32,
1162 .adbits = 18,
1163 .ai_fifo_depth = 2047,
1164 .gainlkup = ai_gain_628x,
1165 .ai_speed = 1600,
1166 .n_aochan = 0,
1167 .aobits = 0,
1168 .ao_fifo_depth = 0,
1169 .reg_type = ni_reg_628x,
1170 .ao_unipolar = 0,
1171 .num_p0_dio_channels = 32,
1172 .caldac = {caldac_none},
1173 .has_8255 = 0,
1174 },
c4beb34e 1175 {
0a85b6f0
MT		 1176 .device_id = 0x70ac,
1177 .name = "pci-6289",
1178 .n_adchan = 32,
1179 .adbits = 18,
1180 .ai_fifo_depth = 2047,
1181 .gainlkup = ai_gain_628x,
1182 .ai_speed = 1600,
1183 .n_aochan = 4,
1184 .aobits = 16,
1185 .ao_fifo_depth = 8191,
1186 .ao_range_table = &range_ni_M_628x_ao,
1187 .reg_type = ni_reg_628x,
1188 .ao_unipolar = 1,
1189 .ao_speed = 357,
1190 .num_p0_dio_channels = 32,
1191 .caldac = {caldac_none},
1192 .has_8255 = 0,
1193 },
c4beb34e 1194 {
0a85b6f0
MT		 1195 .device_id = 0x70C0,
1196 .name = "pci-6143",
1197 .n_adchan = 8,
1198 .adbits = 16,
1199 .ai_fifo_depth = 1024,
1200 .alwaysdither = 0,
1201 .gainlkup = ai_gain_6143,
1202 .ai_speed = 4000,
1203 .n_aochan = 0,
1204 .aobits = 0,
1205 .reg_type = ni_reg_6143,
1206 .ao_unipolar = 0,
1207 .ao_fifo_depth = 0,
1208 .num_p0_dio_channels = 8,
1209 .caldac = {ad8804_debug, ad8804_debug},
1210 },
c4beb34e 1211 {
0a85b6f0
MT		 1212 .device_id = 0x710D,
1213 .name = "pxi-6143",
1214 .n_adchan = 8,
1215 .adbits = 16,
1216 .ai_fifo_depth = 1024,
1217 .alwaysdither = 0,
1218 .gainlkup = ai_gain_6143,
1219 .ai_speed = 4000,
1220 .n_aochan = 0,
1221 .aobits = 0,
1222 .reg_type = ni_reg_6143,
1223 .ao_unipolar = 0,
1224 .ao_fifo_depth = 0,
1225 .num_p0_dio_channels = 8,
1226 .caldac = {ad8804_debug, ad8804_debug},
1227 },
c4beb34e
DS		 1228};
1229
b6ac1613 1230#define n_pcimio_boards ARRAY_SIZE(ni_boards)
c4beb34e 1231
0a85b6f0
MT		 1232static int pcimio_attach(struct comedi_device *dev,
1233 struct comedi_devconfig *it);
da91b269 1234static int pcimio_detach(struct comedi_device *dev);
139dfbdf 1235static struct comedi_driver driver_pcimio = {
68c3dbff
BP		 1236 .driver_name = DRV_NAME,
1237 .module = THIS_MODULE,
1238 .attach = pcimio_attach,
1239 .detach = pcimio_detach,
c4beb34e
DS		 1240};
1241
727b286b
AT		 1242static int __devinit driver_pcimio_pci_probe(struct pci_dev *dev,
1243 const struct pci_device_id *ent)
1244{
1245 return comedi_pci_auto_config(dev, driver_pcimio.driver_name);
1246}
1247
1248static void __devexit driver_pcimio_pci_remove(struct pci_dev *dev)
1249{
1250 comedi_pci_auto_unconfig(dev);
1251}
1252
1253static struct pci_driver driver_pcimio_pci_driver = {
1254 .id_table = ni_pci_table,
1255 .probe = &driver_pcimio_pci_probe,
1256 .remove = __devexit_p(&driver_pcimio_pci_remove)
1257};
1258
1259static int __init driver_pcimio_init_module(void)
1260{
1261 int retval;
1262
1263 retval = comedi_driver_register(&driver_pcimio);
1264 if (retval < 0)
1265 return retval;
1266
1267 driver_pcimio_pci_driver.name = (char *)driver_pcimio.driver_name;
1268 return pci_register_driver(&driver_pcimio_pci_driver);
1269}
1270
1271static void __exit driver_pcimio_cleanup_module(void)
1272{
1273 pci_unregister_driver(&driver_pcimio_pci_driver);
1274 comedi_driver_unregister(&driver_pcimio);
1275}
1276
1277module_init(driver_pcimio_init_module);
1278module_exit(driver_pcimio_cleanup_module);
c4beb34e 1279
3301cc76 1280struct ni_private {
0a85b6f0 1281NI_PRIVATE_COMMON};
3301cc76 1282#define devpriv ((struct ni_private *)dev->private)
c4beb34e
DS		 1283
1284/* How we access registers */
1285
f7cbd7aa 1286#define ni_writel(a, b) (writel((a), devpriv->mite->daq_io_addr + (b)))
c4beb34e 1287#define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
f7cbd7aa 1288#define ni_writew(a, b) (writew((a), devpriv->mite->daq_io_addr + (b)))
c4beb34e 1289#define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
f7cbd7aa 1290#define ni_writeb(a, b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
c4beb34e
DS		 1291#define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1292
1293/* How we access STC registers */
1294
1295/* We automatically take advantage of STC registers that can be
1296 * read/written directly in the I/O space of the board. Most
1297 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1298 * The 611x devices map the write registers to iobase+addr*2, and
1299 * the read registers to iobase+(addr-1)*2. */
1300/* However, the 611x boards still aren't working, so I'm disabling
1301 * non-windowed STC access temporarily */
1302
da91b269 1303static void e_series_win_out(struct comedi_device *dev, uint16_t data, int reg)
c4beb34e
DS		 1304{
1305 unsigned long flags;
1306
5f74ea14 1307 spin_lock_irqsave(&devpriv->window_lock, flags);
c4beb34e
DS		 1308 ni_writew(reg, Window_Address);
1309 ni_writew(data, Window_Data);
5f74ea14 1310 spin_unlock_irqrestore(&devpriv->window_lock, flags);
c4beb34e
DS		 1311}
1312
da91b269 1313static uint16_t e_series_win_in(struct comedi_device *dev, int reg)
c4beb34e
DS		 1314{
1315 unsigned long flags;
1316 uint16_t ret;
1317
5f74ea14 1318 spin_lock_irqsave(&devpriv->window_lock, flags);
c4beb34e
DS		 1319 ni_writew(reg, Window_Address);
1320 ret = ni_readw(Window_Data);
5f74ea14 1321 spin_unlock_irqrestore(&devpriv->window_lock, flags);
c4beb34e
DS		 1322
1323 return ret;
1324}
1325
0a85b6f0
MT		 1326static void m_series_stc_writew(struct comedi_device *dev, uint16_t data,
1327 int reg)
c4beb34e
DS		 1328{
1329 unsigned offset;
1330 switch (reg) {
1331 case ADC_FIFO_Clear:
1332 offset = M_Offset_AI_FIFO_Clear;
1333 break;
1334 case AI_Command_1_Register:
1335 offset = M_Offset_AI_Command_1;
1336 break;
1337 case AI_Command_2_Register:
1338 offset = M_Offset_AI_Command_2;
1339 break;
1340 case AI_Mode_1_Register:
1341 offset = M_Offset_AI_Mode_1;
1342 break;
1343 case AI_Mode_2_Register:
1344 offset = M_Offset_AI_Mode_2;
1345 break;
1346 case AI_Mode_3_Register:
1347 offset = M_Offset_AI_Mode_3;
1348 break;
1349 case AI_Output_Control_Register:
1350 offset = M_Offset_AI_Output_Control;
1351 break;
1352 case AI_Personal_Register:
1353 offset = M_Offset_AI_Personal;
1354 break;
1355 case AI_SI2_Load_A_Register:
2696fb57 1356 /* this is actually a 32 bit register on m series boards */
c4beb34e
DS		 1357 ni_writel(data, M_Offset_AI_SI2_Load_A);
1358 return;
1359 break;
1360 case AI_SI2_Load_B_Register:
2696fb57 1361 /* this is actually a 32 bit register on m series boards */
c4beb34e
DS		 1362 ni_writel(data, M_Offset_AI_SI2_Load_B);
1363 return;
1364 break;
1365 case AI_START_STOP_Select_Register:
1366 offset = M_Offset_AI_START_STOP_Select;
1367 break;
1368 case AI_Trigger_Select_Register:
1369 offset = M_Offset_AI_Trigger_Select;
1370 break;
1371 case Analog_Trigger_Etc_Register:
1372 offset = M_Offset_Analog_Trigger_Etc;
1373 break;
1374 case AO_Command_1_Register:
1375 offset = M_Offset_AO_Command_1;
1376 break;
1377 case AO_Command_2_Register:
1378 offset = M_Offset_AO_Command_2;
1379 break;
1380 case AO_Mode_1_Register:
1381 offset = M_Offset_AO_Mode_1;
1382 break;
1383 case AO_Mode_2_Register:
1384 offset = M_Offset_AO_Mode_2;
1385 break;
1386 case AO_Mode_3_Register:
1387 offset = M_Offset_AO_Mode_3;
1388 break;
1389 case AO_Output_Control_Register:
1390 offset = M_Offset_AO_Output_Control;
1391 break;
1392 case AO_Personal_Register:
1393 offset = M_Offset_AO_Personal;
1394 break;
1395 case AO_Start_Select_Register:
1396 offset = M_Offset_AO_Start_Select;
1397 break;
1398 case AO_Trigger_Select_Register:
1399 offset = M_Offset_AO_Trigger_Select;
1400 break;
1401 case Clock_and_FOUT_Register:
1402 offset = M_Offset_Clock_and_FOUT;
1403 break;
1404 case Configuration_Memory_Clear:
1405 offset = M_Offset_Configuration_Memory_Clear;
1406 break;
1407 case DAC_FIFO_Clear:
1408 offset = M_Offset_AO_FIFO_Clear;
1409 break;
1410 case DIO_Control_Register:
5f74ea14 1411 printk
0a85b6f0
MT		 1412 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1413 __func__, reg);
c4beb34e
DS		 1414 return;
1415 break;
1416 case G_Autoincrement_Register(0):
1417 offset = M_Offset_G0_Autoincrement;
1418 break;
1419 case G_Autoincrement_Register(1):
1420 offset = M_Offset_G1_Autoincrement;
1421 break;
1422 case G_Command_Register(0):
1423 offset = M_Offset_G0_Command;
1424 break;
1425 case G_Command_Register(1):
1426 offset = M_Offset_G1_Command;
1427 break;
1428 case G_Input_Select_Register(0):
1429 offset = M_Offset_G0_Input_Select;
1430 break;
1431 case G_Input_Select_Register(1):
1432 offset = M_Offset_G1_Input_Select;
1433 break;
1434 case G_Mode_Register(0):
1435 offset = M_Offset_G0_Mode;
1436 break;
1437 case G_Mode_Register(1):
1438 offset = M_Offset_G1_Mode;
1439 break;
1440 case Interrupt_A_Ack_Register:
1441 offset = M_Offset_Interrupt_A_Ack;
1442 break;
1443 case Interrupt_A_Enable_Register:
1444 offset = M_Offset_Interrupt_A_Enable;
1445 break;
1446 case Interrupt_B_Ack_Register:
1447 offset = M_Offset_Interrupt_B_Ack;
1448 break;
1449 case Interrupt_B_Enable_Register:
1450 offset = M_Offset_Interrupt_B_Enable;
1451 break;
1452 case Interrupt_Control_Register:
1453 offset = M_Offset_Interrupt_Control;
1454 break;
1455 case IO_Bidirection_Pin_Register:
1456 offset = M_Offset_IO_Bidirection_Pin;
1457 break;
1458 case Joint_Reset_Register:
1459 offset = M_Offset_Joint_Reset;
1460 break;
1461 case RTSI_Trig_A_Output_Register:
1462 offset = M_Offset_RTSI_Trig_A_Output;
1463 break;
1464 case RTSI_Trig_B_Output_Register:
1465 offset = M_Offset_RTSI_Trig_B_Output;
1466 break;
1467 case RTSI_Trig_Direction_Register:
1468 offset = M_Offset_RTSI_Trig_Direction;
1469 break;
1470 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1471 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1472 default:
5f74ea14 1473 printk("%s: bug! unhandled register=0x%x in switch.\n",
0a85b6f0 1474 __func__, reg);
c4beb34e
DS		 1475 BUG();
1476 return;
1477 break;
1478 }
1479 ni_writew(data, offset);
1480}
1481
da91b269 1482static uint16_t m_series_stc_readw(struct comedi_device *dev, int reg)
c4beb34e
DS		 1483{
1484 unsigned offset;
1485 switch (reg) {
1486 case AI_Status_1_Register:
1487 offset = M_Offset_AI_Status_1;
1488 break;
1489 case AO_Status_1_Register:
1490 offset = M_Offset_AO_Status_1;
1491 break;
1492 case AO_Status_2_Register:
1493 offset = M_Offset_AO_Status_2;
1494 break;
1495 case DIO_Serial_Input_Register:
1496 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1497 break;
1498 case Joint_Status_1_Register:
1499 offset = M_Offset_Joint_Status_1;
1500 break;
1501 case Joint_Status_2_Register:
1502 offset = M_Offset_Joint_Status_2;
1503 break;
1504 case G_Status_Register:
1505 offset = M_Offset_G01_Status;
1506 break;
1507 default:
5f74ea14 1508 printk("%s: bug! unhandled register=0x%x in switch.\n",
0a85b6f0 1509 __func__, reg);
c4beb34e
DS		 1510 BUG();
1511 return 0;
1512 break;
1513 }
1514 return ni_readw(offset);
1515}
1516
0a85b6f0
MT		 1517static void m_series_stc_writel(struct comedi_device *dev, uint32_t data,
1518 int reg)
c4beb34e
DS		 1519{
1520 unsigned offset;
1521 switch (reg) {
1522 case AI_SC_Load_A_Registers:
1523 offset = M_Offset_AI_SC_Load_A;
1524 break;
1525 case AI_SI_Load_A_Registers:
1526 offset = M_Offset_AI_SI_Load_A;
1527 break;
1528 case AO_BC_Load_A_Register:
1529 offset = M_Offset_AO_BC_Load_A;
1530 break;
1531 case AO_UC_Load_A_Register:
1532 offset = M_Offset_AO_UC_Load_A;
1533 break;
1534 case AO_UI_Load_A_Register:
1535 offset = M_Offset_AO_UI_Load_A;
1536 break;
1537 case G_Load_A_Register(0):
1538 offset = M_Offset_G0_Load_A;
1539 break;
1540 case G_Load_A_Register(1):
1541 offset = M_Offset_G1_Load_A;
1542 break;
1543 case G_Load_B_Register(0):
1544 offset = M_Offset_G0_Load_B;
1545 break;
1546 case G_Load_B_Register(1):
1547 offset = M_Offset_G1_Load_B;
1548 break;
1549 default:
5f74ea14 1550 printk("%s: bug! unhandled register=0x%x in switch.\n",
0a85b6f0 1551 __func__, reg);
c4beb34e
DS		 1552 BUG();
1553 return;
1554 break;
1555 }
1556 ni_writel(data, offset);
1557}
1558
da91b269 1559static uint32_t m_series_stc_readl(struct comedi_device *dev, int reg)
c4beb34e
DS		 1560{
1561 unsigned offset;
1562 switch (reg) {
1563 case G_HW_Save_Register(0):
1564 offset = M_Offset_G0_HW_Save;
1565 break;
1566 case G_HW_Save_Register(1):
1567 offset = M_Offset_G1_HW_Save;
1568 break;
1569 case G_Save_Register(0):
1570 offset = M_Offset_G0_Save;
1571 break;
1572 case G_Save_Register(1):
1573 offset = M_Offset_G1_Save;
1574 break;
1575 default:
5f74ea14 1576 printk("%s: bug! unhandled register=0x%x in switch.\n",
0a85b6f0 1577 __func__, reg);
c4beb34e
DS		 1578 BUG();
1579 return 0;
1580 break;
1581 }
1582 return ni_readl(offset);
1583}
1584
1585#define interrupt_pin(a) 0
1586#define IRQ_POLARITY 1
1587
1588#define NI_E_IRQ_FLAGS IRQF_SHARED
1589
1590#include "ni_mio_common.c"
1591
da91b269 1592static int pcimio_find_device(struct comedi_device *dev, int bus, int slot);
0a85b6f0
MT		 1593static int pcimio_ai_change(struct comedi_device *dev,
1594 struct comedi_subdevice *s, unsigned long new_size);
1595static int pcimio_ao_change(struct comedi_device *dev,
1596 struct comedi_subdevice *s, unsigned long new_size);
1597static int pcimio_gpct0_change(struct comedi_device *dev,
1598 struct comedi_subdevice *s,
1599 unsigned long new_size);
1600static int pcimio_gpct1_change(struct comedi_device *dev,
1601 struct comedi_subdevice *s,
1602 unsigned long new_size);
1603static int pcimio_dio_change(struct comedi_device *dev,
1604 struct comedi_subdevice *s,
1605 unsigned long new_size);
c4beb34e 1606
da91b269 1607static void m_series_init_eeprom_buffer(struct comedi_device *dev)
c4beb34e
DS		 1608{
1609 static const int Start_Cal_EEPROM = 0x400;
1610 static const unsigned window_size = 10;
f8db88ef
FMH		 1611 static const int serial_number_eeprom_offset = 0x4;
1612 static const int serial_number_eeprom_length = 0x4;
c4beb34e
DS		 1613 unsigned old_iodwbsr_bits;
1614 unsigned old_iodwbsr1_bits;
1615 unsigned old_iodwcr1_bits;
1616 int i;
1617
1618 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1619 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1620 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1621 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1622 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
0a85b6f0
MT		 1623 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1624 writel(0x1 | old_iodwcr1_bits,
1625 devpriv->mite->mite_io_addr + MITE_IODWCR_1);
c4beb34e
DS		 1626 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1627
f8db88ef
FMH		 1628 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1629 for (i = 0; i < serial_number_eeprom_length; ++i) {
0a85b6f0 1630 char *byte_ptr = (char *)&devpriv->serial_number + i;
f8db88ef
FMH		 1631 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1632 }
1633 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1634
c4beb34e
DS		 1635 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) {
1636 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1637 }
1638
1639 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1640 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1641 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1642 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1643}
1644
da91b269 1645static void init_6143(struct comedi_device *dev)
c4beb34e 1646{
2696fb57 1647 /* Disable interrupts */
c4beb34e
DS		 1648 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1649
2696fb57
BP		 1650 /* Initialise 6143 AI specific bits */
1651 ni_writeb(0x00, Magic_6143); /* Set G0,G1 DMA mode to E series version */
1652 ni_writeb(0x80, PipelineDelay_6143); /* Set EOCMode, ADCMode and pipelinedelay */
1653 ni_writeb(0x00, EOC_Set_6143); /* Set EOC Delay */
c4beb34e 1654
2696fb57 1655 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); /* Set the FIFO half full level */
c4beb34e 1656
2696fb57 1657 /* Strobe Relay disable bit */
c4beb34e
DS		 1658 devpriv->ai_calib_source_enabled = 0;
1659 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
0a85b6f0 1660 Calibration_Channel_6143);
c4beb34e
DS		 1661 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1662}
1663
1664/* cleans up allocated resources */
da91b269 1665static int pcimio_detach(struct comedi_device *dev)
c4beb34e
DS		 1666{
1667 mio_common_detach(dev);
1668 if (dev->irq) {
5f74ea14 1669 free_irq(dev->irq, dev);
c4beb34e
DS		 1670 }
1671 if (dev->private) {
1672 mite_free_ring(devpriv->ai_mite_ring);
1673 mite_free_ring(devpriv->ao_mite_ring);
1674 mite_free_ring(devpriv->cdo_mite_ring);
1675 mite_free_ring(devpriv->gpct_mite_ring[0]);
1676 mite_free_ring(devpriv->gpct_mite_ring[1]);
1677 if (devpriv->mite)
1678 mite_unsetup(devpriv->mite);
1679 }
1680
1681 return 0;
1682}
1683
da91b269 1684static int pcimio_attach(struct comedi_device *dev, struct comedi_devconfig *it)
c4beb34e
DS		 1685{
1686 int ret;
1687
1688 printk("comedi%d: ni_pcimio:", dev->minor);
1689
1690 ret = ni_alloc_private(dev);
1691 if (ret < 0)
1692 return ret;
1693
1694 ret = pcimio_find_device(dev, it->options[0], it->options[1]);
1695 if (ret < 0)
1696 return ret;
1697
1698 printk(" %s", boardtype.name);
1699 dev->board_name = boardtype.name;
1700
1701 if (boardtype.reg_type & ni_reg_m_series_mask) {
1702 devpriv->stc_writew = &m_series_stc_writew;
1703 devpriv->stc_readw = &m_series_stc_readw;
1704 devpriv->stc_writel = &m_series_stc_writel;
1705 devpriv->stc_readl = &m_series_stc_readl;
1706 } else {
1707 devpriv->stc_writew = &e_series_win_out;
1708 devpriv->stc_readw = &e_series_win_in;
1709 devpriv->stc_writel = &win_out2;
1710 devpriv->stc_readl = &win_in2;
1711 }
1712
1713 ret = mite_setup(devpriv->mite);
1714 if (ret < 0) {
1715 printk(" error setting up mite\n");
1716 return ret;
1717 }
1718 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1719 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1720 if (devpriv->ai_mite_ring == NULL)
1721 return -ENOMEM;
1722 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1723 if (devpriv->ao_mite_ring == NULL)
1724 return -ENOMEM;
1725 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1726 if (devpriv->cdo_mite_ring == NULL)
1727 return -ENOMEM;
1728 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1729 if (devpriv->gpct_mite_ring[0] == NULL)
1730 return -ENOMEM;
1731 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1732 if (devpriv->gpct_mite_ring[1] == NULL)
1733 return -ENOMEM;
1734
1735 if (boardtype.reg_type & ni_reg_m_series_mask)
1736 m_series_init_eeprom_buffer(dev);
1737 if (boardtype.reg_type == ni_reg_6143)
1738 init_6143(dev);
1739
1740 dev->irq = mite_irq(devpriv->mite);
1741
1742 if (dev->irq == 0) {
1743 printk(" unknown irq (bad)\n");
1744 } else {
1745 printk(" ( irq = %u )", dev->irq);
5f74ea14
GKH		 1746 ret = request_irq(dev->irq, ni_E_interrupt, NI_E_IRQ_FLAGS,
1747 DRV_NAME, dev);
c3744138 1748 if (ret < 0) {
c4beb34e
DS		 1749 printk(" irq not available\n");
1750 dev->irq = 0;
1751 }
1752 }
1753
1754 ret = ni_E_init(dev, it);
1755 if (ret < 0)
1756 return ret;
1757
1758 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1759 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1760 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1761 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1762 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1763
1764 return ret;
1765}
1766
da91b269 1767static int pcimio_find_device(struct comedi_device *dev, int bus, int slot)
c4beb34e
DS		 1768{
1769 struct mite_struct *mite;
1770 int i;
1771
1772 for (mite = mite_devices; mite; mite = mite->next) {
1773 if (mite->used)
1774 continue;
1775 if (bus || slot) {
1776 if (bus != mite->pcidev->bus->number ||
0a85b6f0 1777 slot != PCI_SLOT(mite->pcidev->devfn))
c4beb34e
DS		 1778 continue;
1779 }
1780
1781 for (i = 0; i < n_pcimio_boards; i++) {
1782 if (mite_device_id(mite) == ni_boards[i].device_id) {
1783 dev->board_ptr = ni_boards + i;
1784 devpriv->mite = mite;
1785
1786 return 0;
1787 }
1788 }
1789 }
1790 printk("no device found\n");
1791 mite_list_devices();
1792 return -EIO;
1793}
1794
0a85b6f0
MT		 1795static int pcimio_ai_change(struct comedi_device *dev,
1796 struct comedi_subdevice *s, unsigned long new_size)
c4beb34e
DS		 1797{
1798 int ret;
1799
1800 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1801 if (ret < 0)
1802 return ret;
1803
1804 return 0;
1805}
1806
0a85b6f0
MT		 1807static int pcimio_ao_change(struct comedi_device *dev,
1808 struct comedi_subdevice *s, unsigned long new_size)
c4beb34e
DS		 1809{
1810 int ret;
1811
1812 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1813 if (ret < 0)
1814 return ret;
1815
1816 return 0;
1817}
1818
0a85b6f0
MT		 1819static int pcimio_gpct0_change(struct comedi_device *dev,
1820 struct comedi_subdevice *s,
1821 unsigned long new_size)
c4beb34e
DS		 1822{
1823 int ret;
1824
1825 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1826 if (ret < 0)
1827 return ret;
1828
1829 return 0;
1830}
1831
0a85b6f0
MT		 1832static int pcimio_gpct1_change(struct comedi_device *dev,
1833 struct comedi_subdevice *s,
1834 unsigned long new_size)
c4beb34e
DS		 1835{
1836 int ret;
1837
1838 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1839 if (ret < 0)
1840 return ret;
1841
1842 return 0;
1843}
1844
0a85b6f0
MT		 1845static int pcimio_dio_change(struct comedi_device *dev,
1846 struct comedi_subdevice *s, unsigned long new_size)
c4beb34e
DS		 1847{
1848 int ret;
1849
1850 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1851 if (ret < 0)
1852 return ret;
1853
1854 return 0;
1855}
Linux kernel - Deliverables
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