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Staging: comedi: Added reading of board serial number from eeprom for m-series boards
[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_pcimio.c
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c4beb34e
DS		 1/*
2 comedi/drivers/ni_pcimio.c
3 Hardware driver for NI PCI-MIO E series cards
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 1997-8 David A. Schleef <ds@schleef.org>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, write to the Free Software
20 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21*/
22/*
23Driver: ni_pcimio
24Description: National Instruments PCI-MIO-E series and M series (all boards)
25Author: ds, John Hallen, Frank Mori Hess, Rolf Mueller, Herbert Peremans,
26 Herman Bruyninckx, Terry Barnaby
27Status: works
28Devices: [National Instruments] PCI-MIO-16XE-50 (ni_pcimio),
29 PCI-MIO-16XE-10, PXI-6030E, PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-6014, PCI-6040E,
30 PXI-6040E, PCI-6030E, PCI-6031E, PCI-6032E, PCI-6033E, PCI-6071E, PCI-6023E,
31 PCI-6024E, PCI-6025E, PXI-6025E, PCI-6034E, PCI-6035E, PCI-6052E,
32 PCI-6110, PCI-6111, PCI-6220, PCI-6221, PCI-6224, PCI-6225, PCI-6229,
33 PCI-6250, PCI-6251, PCIe-6251, PCI-6254, PCI-6259, PCIe-6259,
34 PCI-6280, PCI-6281, PXI-6281, PCI-6284, PCI-6289,
35 PCI-6711, PXI-6711, PCI-6713, PXI-6713,
36 PXI-6071E, PCI-6070E, PXI-6070E,
37 PXI-6052E, PCI-6036E, PCI-6731, PCI-6733, PXI-6733,
38 PCI-6143, PXI-6143
39Updated: Wed Nov 29 10:30:36 EST 2006
40
41These boards are almost identical to the AT-MIO E series, except that
42they use the PCI bus instead of ISA (i.e., AT). See the notes for
43the ni_atmio.o driver for additional information about these boards.
44
45Autocalibration is supported on many of the devices, using the
46comedi_calibrate (or comedi_soft_calibrate for m-series) utility.
47M-Series boards do analog input and analog output calibration entirely
48in software. The software calibration corrects
49the analog input for offset, gain and
50nonlinearity. The analog outputs are corrected for offset and gain.
51See the comedilib documentation on comedi_get_softcal_converter() for
52more information.
53
54By default, the driver uses DMA to transfer analog input data to
55memory. When DMA is enabled, not all triggering features are
56supported.
57
58Digital I/O may not work on 673x.
59
60Note that the PCI-6143 is a simultaineous sampling device with 8 convertors.
61With this board all of the convertors perform one simultaineous sample during
62a scan interval. The period for a scan is used for the convert time in a
63Comedi cmd. The convert trigger source is normally set to TRIG_NOW by default.
64
65The RTSI trigger bus is supported on these cards on
66subdevice 10. See the comedilib documentation for details.
67
68Information (number of channels, bits, etc.) for some devices may be
69incorrect. Please check this and submit a bug if there are problems
70for your device.
71
72SCXI is probably broken for m-series boards.
73
74Bugs:
75 - When DMA is enabled, COMEDI_EV_CONVERT does
76 not work correctly.
77
78*/
79/*
80 The PCI-MIO E series driver was originally written by
81 Tomasz Motylewski <...>, and ported to comedi by ds.
82
83 References:
84
85 341079b.pdf PCI E Series Register-Level Programmer Manual
86 340934b.pdf DAQ-STC reference manual
87
88 322080b.pdf 6711/6713/6715 User Manual
89
90 320945c.pdf PCI E Series User Manual
91 322138a.pdf PCI-6052E and DAQPad-6052E User Manual
92
93 ISSUES:
94
95 need to deal with external reference for DAC, and other DAC
96 properties in board properties
97
98 deal with at-mio-16de-10 revision D to N changes, etc.
99
100 need to add other CALDAC type
101
102 need to slow down DAC loading. I don't trust NI's claim that
103 two writes to the PCI bus slows IO enough. I would prefer to
104 use comedi_udelay(). Timing specs: (clock)
105 AD8522 30ns
106 DAC8043 120ns
107 DAC8800 60ns
108 MB88341 ?
109
110*/
111
112#include "../comedidev.h"
113
f8db88ef 114#include <asm/byteorder.h>
c4beb34e
DS		 115#include <linux/delay.h>
116
117#include "ni_stc.h"
118#include "mite.h"
119
120//#define PCI_DEBUG
121
122#define PCIDMA
123
124#define PCIMIO 1
125#undef ATMIO
126
127#define MAX_N_CALDACS (16+16+2)
128
129#define DRV_NAME "ni_pcimio"
130
131/* The following two tables must be in the same order */
132static DEFINE_PCI_DEVICE_TABLE(ni_pci_table) = {
133 {PCI_VENDOR_ID_NATINST, 0x0162, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
134 {PCI_VENDOR_ID_NATINST, 0x1170, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NATINST, 0x1180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
136 {PCI_VENDOR_ID_NATINST, 0x1190, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NATINST, 0x11b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
138 {PCI_VENDOR_ID_NATINST, 0x11c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NATINST, 0x11d0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
140 {PCI_VENDOR_ID_NATINST, 0x1270, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NATINST, 0x1330, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
142 {PCI_VENDOR_ID_NATINST, 0x1340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NATINST, 0x1350, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
144 {PCI_VENDOR_ID_NATINST, 0x14e0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NATINST, 0x14f0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
146 {PCI_VENDOR_ID_NATINST, 0x1580, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NATINST, 0x15b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
148 {PCI_VENDOR_ID_NATINST, 0x1880, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NATINST, 0x1870, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
150 {PCI_VENDOR_ID_NATINST, 0x18b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NATINST, 0x18c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
152 {PCI_VENDOR_ID_NATINST, 0x2410, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NATINST, 0x2420, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
154 {PCI_VENDOR_ID_NATINST, 0x2430, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NATINST, 0x2890, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
156 {PCI_VENDOR_ID_NATINST, 0x28c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NATINST, 0x2a60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
158 {PCI_VENDOR_ID_NATINST, 0x2a70, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NATINST, 0x2a80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
160 {PCI_VENDOR_ID_NATINST, 0x2ab0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NATINST, 0x2b80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
162 {PCI_VENDOR_ID_NATINST, 0x2b90, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NATINST, 0x2c80, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
164 {PCI_VENDOR_ID_NATINST, 0x2ca0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NATINST, 0x70aa, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
166 {PCI_VENDOR_ID_NATINST, 0x70ab, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NATINST, 0x70ac, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
168 {PCI_VENDOR_ID_NATINST, 0x70af, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NATINST, 0x70b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
170 {PCI_VENDOR_ID_NATINST, 0x70b4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NATINST, 0x70b6, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
172 {PCI_VENDOR_ID_NATINST, 0x70b7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NATINST, 0x70b8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
174 {PCI_VENDOR_ID_NATINST, 0x70bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NATINST, 0x70bd, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
176 {PCI_VENDOR_ID_NATINST, 0x70bf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NATINST, 0x70c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
178 {PCI_VENDOR_ID_NATINST, 0x70f2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NATINST, 0x710d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
180 {PCI_VENDOR_ID_NATINST, 0x716c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NATINST, 0x717f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
182 {PCI_VENDOR_ID_NATINST, 0x71bc, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NATINST, 0x717d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
184 {0}
185};
186
187MODULE_DEVICE_TABLE(pci, ni_pci_table);
188
189/* These are not all the possible ao ranges for 628x boards.
190 They can do OFFSET +- REFERENCE where OFFSET can be
191 0V, 5V, APFI<0,1>, or AO<0...3> and RANGE can
192 be 10V, 5V, 2V, 1V, APFI<0,1>, AO<0...3>. That's
193 63 different possibilities. An AO channel
194 can not act as it's own OFFSET or REFERENCE.
195*/
196static const comedi_lrange range_ni_M_628x_ao = { 8, {
197 RANGE(-10, 10),
198 RANGE(-5, 5),
199 RANGE(-2, 2),
200 RANGE(-1, 1),
201 RANGE(-5, 15),
202 RANGE(0, 10),
203 RANGE(3, 7),
204 RANGE(4, 6),
205 RANGE_ext(-1, 1)
206 }
207};
208static const comedi_lrange range_ni_M_625x_ao = { 3, {
209 RANGE(-10, 10),
210 RANGE(-5, 5),
211 RANGE_ext(-1, 1)
212 }
213};
214static const comedi_lrange range_ni_M_622x_ao = { 1, {
215 RANGE(-10, 10),
216 }
217};
218
219static const ni_board ni_boards[] = {
220 {
221 .device_id = 0x0162, // NI also says 0x1620. typo?
222 .name = "pci-mio-16xe-50",
223 .n_adchan = 16,
224 .adbits = 16,
225 .ai_fifo_depth = 2048,
226 .alwaysdither = 1,
227 .gainlkup = ai_gain_8,
228 .ai_speed = 50000,
229 .n_aochan = 2,
230 .aobits = 12,
231 .ao_fifo_depth = 0,
232 .ao_range_table = &range_bipolar10,
233 .ao_unipolar = 0,
234 .ao_speed = 50000,
235 .num_p0_dio_channels = 8,
236 .caldac = {dac8800, dac8043},
237 .has_8255 = 0,
238 },
239 {
240 .device_id = 0x1170,
241 .name = "pci-mio-16xe-10", // aka pci-6030E
242 .n_adchan = 16,
243 .adbits = 16,
244 .ai_fifo_depth = 512,
245 .alwaysdither = 1,
246 .gainlkup = ai_gain_14,
247 .ai_speed = 10000,
248 .n_aochan = 2,
249 .aobits = 16,
250 .ao_fifo_depth = 2048,
251 .ao_range_table = &range_ni_E_ao_ext,
252 .ao_unipolar = 1,
253 .ao_speed = 10000,
254 .num_p0_dio_channels = 8,
255 .caldac = {dac8800, dac8043, ad8522},
256 .has_8255 = 0,
257 },
258 {
259 .device_id = 0x28c0,
260 .name = "pci-6014",
261 .n_adchan = 16,
262 .adbits = 16,
263 .ai_fifo_depth = 512,
264 .alwaysdither = 1,
265 .gainlkup = ai_gain_4,
266 .ai_speed = 5000,
267 .n_aochan = 2,
268 .aobits = 16,
269 .ao_fifo_depth = 0,
270 .ao_range_table = &range_bipolar10,
271 .ao_unipolar = 0,
272 .ao_speed = 100000,
273 .num_p0_dio_channels = 8,
274 .caldac = {ad8804_debug},
275 .has_8255 = 0,
276 },
277 {
278 .device_id = 0x11d0,
279 .name = "pxi-6030e",
280 .n_adchan = 16,
281 .adbits = 16,
282 .ai_fifo_depth = 512,
283 .alwaysdither = 1,
284 .gainlkup = ai_gain_14,
285 .ai_speed = 10000,
286 .n_aochan = 2,
287 .aobits = 16,
288 .ao_fifo_depth = 2048,
289 .ao_range_table = &range_ni_E_ao_ext,
290 .ao_unipolar = 1,
291 .ao_speed = 10000,
292 .num_p0_dio_channels = 8,
293 .caldac = {dac8800, dac8043, ad8522},
294 .has_8255 = 0,
295 },
296 {
297 .device_id = 0x1180,
298 .name = "pci-mio-16e-1", /* aka pci-6070e */
299 .n_adchan = 16,
300 .adbits = 12,
301 .ai_fifo_depth = 512,
302 .alwaysdither = 0,
303 .gainlkup = ai_gain_16,
304 .ai_speed = 800,
305 .n_aochan = 2,
306 .aobits = 12,
307 .ao_fifo_depth = 2048,
308 .ao_range_table = &range_ni_E_ao_ext,
309 .ao_unipolar = 1,
310 .ao_speed = 1000,
311 .num_p0_dio_channels = 8,
312 .caldac = {mb88341},
313 .has_8255 = 0,
314 },
315 {
316 .device_id = 0x1190,
317 .name = "pci-mio-16e-4", /* aka pci-6040e */
318 .n_adchan = 16,
319 .adbits = 12,
320 .ai_fifo_depth = 512,
321 .alwaysdither = 0,
322 .gainlkup = ai_gain_16,
323 /* Note: there have been reported problems with full speed
324 * on this board */
325 .ai_speed = 2000,
326 .n_aochan = 2,
327 .aobits = 12,
328 .ao_fifo_depth = 512,
329 .ao_range_table = &range_ni_E_ao_ext,
330 .ao_unipolar = 1,
331 .ao_speed = 1000,
332 .num_p0_dio_channels = 8,
333 .caldac = {ad8804_debug}, // doc says mb88341
334 .has_8255 = 0,
335 },
336 {
337 .device_id = 0x11c0,
338 .name = "pxi-6040e",
339 .n_adchan = 16,
340 .adbits = 12,
341 .ai_fifo_depth = 512,
342 .alwaysdither = 0,
343 .gainlkup = ai_gain_16,
344 .ai_speed = 2000,
345 .n_aochan = 2,
346 .aobits = 12,
347 .ao_fifo_depth = 512,
348 .ao_range_table = &range_ni_E_ao_ext,
349 .ao_unipolar = 1,
350 .ao_speed = 1000,
351 .num_p0_dio_channels = 8,
352 .caldac = {mb88341},
353 .has_8255 = 0,
354 },
355
356 {
357 .device_id = 0x1330,
358 .name = "pci-6031e",
359 .n_adchan = 64,
360 .adbits = 16,
361 .ai_fifo_depth = 512,
362 .alwaysdither = 1,
363 .gainlkup = ai_gain_14,
364 .ai_speed = 10000,
365 .n_aochan = 2,
366 .aobits = 16,
367 .ao_fifo_depth = 2048,
368 .ao_range_table = &range_ni_E_ao_ext,
369 .ao_unipolar = 1,
370 .ao_speed = 10000,
371 .num_p0_dio_channels = 8,
372 .caldac = {dac8800, dac8043, ad8522},
373 .has_8255 = 0,
374 },
375 {
376 .device_id = 0x1270,
377 .name = "pci-6032e",
378 .n_adchan = 16,
379 .adbits = 16,
380 .ai_fifo_depth = 512,
381 .alwaysdither = 1,
382 .gainlkup = ai_gain_14,
383 .ai_speed = 10000,
384 .n_aochan = 0,
385 .aobits = 0,
386 .ao_fifo_depth = 0,
387 .ao_unipolar = 0,
388 .num_p0_dio_channels = 8,
389 .caldac = {dac8800, dac8043, ad8522},
390 .has_8255 = 0,
391 },
392 {
393 .device_id = 0x1340,
394 .name = "pci-6033e",
395 .n_adchan = 64,
396 .adbits = 16,
397 .ai_fifo_depth = 512,
398 .alwaysdither = 1,
399 .gainlkup = ai_gain_14,
400 .ai_speed = 10000,
401 .n_aochan = 0,
402 .aobits = 0,
403 .ao_fifo_depth = 0,
404 .ao_unipolar = 0,
405 .num_p0_dio_channels = 8,
406 .caldac = {dac8800, dac8043, ad8522},
407 .has_8255 = 0,
408 },
409 {
410 .device_id = 0x1350,
411 .name = "pci-6071e",
412 .n_adchan = 64,
413 .adbits = 12,
414 .ai_fifo_depth = 512,
415 .alwaysdither = 1,
416 .gainlkup = ai_gain_16,
417 .ai_speed = 800,
418 .n_aochan = 2,
419 .aobits = 12,
420 .ao_fifo_depth = 2048,
421 .ao_range_table = &range_ni_E_ao_ext,
422 .ao_unipolar = 1,
423 .ao_speed = 1000,
424 .num_p0_dio_channels = 8,
425 .caldac = {ad8804_debug},
426 .has_8255 = 0,
427 },
428 {
429 .device_id = 0x2a60,
430 .name = "pci-6023e",
431 .n_adchan = 16,
432 .adbits = 12,
433 .ai_fifo_depth = 512,
434 .alwaysdither = 0,
435 .gainlkup = ai_gain_4,
436 .ai_speed = 5000,
437 .n_aochan = 0,
438 .aobits = 0,
439 .ao_unipolar = 0,
440 .num_p0_dio_channels = 8,
441 .caldac = {ad8804_debug}, /* manual is wrong */
442 .has_8255 = 0,
443 },
444 {
445 .device_id = 0x2a70,
446 .name = "pci-6024e",
447 .n_adchan = 16,
448 .adbits = 12,
449 .ai_fifo_depth = 512,
450 .alwaysdither = 0,
451 .gainlkup = ai_gain_4,
452 .ai_speed = 5000,
453 .n_aochan = 2,
454 .aobits = 12,
455 .ao_fifo_depth = 0,
456 .ao_range_table = &range_bipolar10,
457 .ao_unipolar = 0,
458 .ao_speed = 100000,
459 .num_p0_dio_channels = 8,
460 .caldac = {ad8804_debug}, /* manual is wrong */
461 .has_8255 = 0,
462 },
463 {
464 .device_id = 0x2a80,
465 .name = "pci-6025e",
466 .n_adchan = 16,
467 .adbits = 12,
468 .ai_fifo_depth = 512,
469 .alwaysdither = 0,
470 .gainlkup = ai_gain_4,
471 .ai_speed = 5000,
472 .n_aochan = 2,
473 .aobits = 12,
474 .ao_fifo_depth = 0,
475 .ao_range_table = &range_bipolar10,
476 .ao_unipolar = 0,
477 .ao_speed = 100000,
478 .num_p0_dio_channels = 8,
479 .caldac = {ad8804_debug}, /* manual is wrong */
480 .has_8255 = 1,
481 },
482 {
483 .device_id = 0x2ab0,
484 .name = "pxi-6025e",
485 .n_adchan = 16,
486 .adbits = 12,
487 .ai_fifo_depth = 512,
488 .alwaysdither = 0,
489 .gainlkup = ai_gain_4,
490 .ai_speed = 5000,
491 .n_aochan = 2,
492 .aobits = 12,
493 .ao_fifo_depth = 0,
494 .ao_range_table = &range_ni_E_ao_ext,
495 .ao_unipolar = 1,
496 .ao_speed = 100000,
497 .num_p0_dio_channels = 8,
498 .caldac = {ad8804_debug}, /* manual is wrong */
499 .has_8255 = 1,
500 },
501
502 {
503 .device_id = 0x2ca0,
504 .name = "pci-6034e",
505 .n_adchan = 16,
506 .adbits = 16,
507 .ai_fifo_depth = 512,
508 .alwaysdither = 1,
509 .gainlkup = ai_gain_4,
510 .ai_speed = 5000,
511 .n_aochan = 0,
512 .aobits = 0,
513 .ao_fifo_depth = 0,
514 .ao_unipolar = 0,
515 .num_p0_dio_channels = 8,
516 .caldac = {ad8804_debug},
517 .has_8255 = 0,
518 },
519 {
520 .device_id = 0x2c80,
521 .name = "pci-6035e",
522 .n_adchan = 16,
523 .adbits = 16,
524 .ai_fifo_depth = 512,
525 .alwaysdither = 1,
526 .gainlkup = ai_gain_4,
527 .ai_speed = 5000,
528 .n_aochan = 2,
529 .aobits = 12,
530 .ao_fifo_depth = 0,
531 .ao_range_table = &range_bipolar10,
532 .ao_unipolar = 0,
533 .ao_speed = 100000,
534 .num_p0_dio_channels = 8,
535 .caldac = {ad8804_debug},
536 .has_8255 = 0,
537 },
538 {
539 .device_id = 0x18b0,
540 .name = "pci-6052e",
541 .n_adchan = 16,
542 .adbits = 16,
543 .ai_fifo_depth = 512,
544 .alwaysdither = 1,
545 .gainlkup = ai_gain_16,
546 .ai_speed = 3000,
547 .n_aochan = 2,
548 .aobits = 16,
549 .ao_unipolar = 1,
550 .ao_fifo_depth = 2048,
551 .ao_range_table = &range_ni_E_ao_ext,
552 .ao_speed = 3000,
553 .num_p0_dio_channels = 8,
554 .caldac = {ad8804_debug, ad8804_debug, ad8522}, /* manual is wrong */
555 },
556 {.device_id = 0x14e0,
557 .name = "pci-6110",
558 .n_adchan = 4,
559 .adbits = 12,
560 .ai_fifo_depth = 8192,
561 .alwaysdither = 0,
562 .gainlkup = ai_gain_611x,
563 .ai_speed = 200,
564 .n_aochan = 2,
565 .aobits = 16,
566 .reg_type = ni_reg_611x,
567 .ao_range_table = &range_bipolar10,
568 .ao_unipolar = 0,
569 .ao_fifo_depth = 2048,
570 .ao_speed = 250,
571 .num_p0_dio_channels = 8,
572 .caldac = {ad8804, ad8804},
573 },
574 {
575 .device_id = 0x14f0,
576 .name = "pci-6111",
577 .n_adchan = 2,
578 .adbits = 12,
579 .ai_fifo_depth = 8192,
580 .alwaysdither = 0,
581 .gainlkup = ai_gain_611x,
582 .ai_speed = 200,
583 .n_aochan = 2,
584 .aobits = 16,
585 .reg_type = ni_reg_611x,
586 .ao_range_table = &range_bipolar10,
587 .ao_unipolar = 0,
588 .ao_fifo_depth = 2048,
589 .ao_speed = 250,
590 .num_p0_dio_channels = 8,
591 .caldac = {ad8804, ad8804},
592 },
593#if 0
594 /* The 6115 boards probably need their own driver */
595 {
596 .device_id = 0x2ed0,
597 .name = "pci-6115",
598 .n_adchan = 4,
599 .adbits = 12,
600 .ai_fifo_depth = 8192,
601 .alwaysdither = 0,
602 .gainlkup = ai_gain_611x,
603 .ai_speed = 100,
604 .n_aochan = 2,
605 .aobits = 16,
606 .ao_671x = 1,
607 .ao_unipolar = 0,
608 .ao_fifo_depth = 2048,
609 .ao_speed = 250,
610 .num_p0_dio_channels = 8,
611 .reg_611x = 1,
612 .caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
613 },
614#endif
615#if 0
616 {
617 .device_id = 0x0000,
618 .name = "pxi-6115",
619 .n_adchan = 4,
620 .adbits = 12,
621 .ai_fifo_depth = 8192,
622 .alwaysdither = 0,
623 .gainlkup = ai_gain_611x,
624 .ai_speed = 100,
625 .n_aochan = 2,
626 .aobits = 16,
627 .ao_671x = 1,
628 .ao_unipolar = 0,
629 .ao_fifo_depth = 2048,
630 .ao_speed = 250,
631 .reg_611x = 1,
632 .num_p0_dio_channels = 8,
633 caldac = {ad8804_debug, ad8804_debug, ad8804_debug}, /* XXX */
634 },
635#endif
636 {
637 .device_id = 0x1880,
638 .name = "pci-6711",
639 .n_adchan = 0, /* no analog input */
640 .n_aochan = 4,
641 .aobits = 12,
642 .ao_unipolar = 0,
643 .ao_fifo_depth = 16384,
644 /* data sheet says 8192, but fifo really holds 16384 samples */
645 .ao_range_table = &range_bipolar10,
646 .ao_speed = 1000,
647 .num_p0_dio_channels = 8,
648 .reg_type = ni_reg_6711,
649 .caldac = {ad8804_debug},
650 },
651 {
652 .device_id = 0x2b90,
653 .name = "pxi-6711",
654 .n_adchan = 0, /* no analog input */
655 .n_aochan = 4,
656 .aobits = 12,
657 .ao_unipolar = 0,
658 .ao_fifo_depth = 16384,
659 .ao_range_table = &range_bipolar10,
660 .ao_speed = 1000,
661 .num_p0_dio_channels = 8,
662 .reg_type = ni_reg_6711,
663 .caldac = {ad8804_debug},
664 },
665 {
666 .device_id = 0x1870,
667 .name = "pci-6713",
668 .n_adchan = 0, /* no analog input */
669 .n_aochan = 8,
670 .aobits = 12,
671 .ao_unipolar = 0,
672 .ao_fifo_depth = 16384,
673 .ao_range_table = &range_bipolar10,
674 .ao_speed = 1000,
675 .num_p0_dio_channels = 8,
676 .reg_type = ni_reg_6713,
677 .caldac = {ad8804_debug, ad8804_debug},
678 },
679 {
680 .device_id = 0x2b80,
681 .name = "pxi-6713",
682 .n_adchan = 0, /* no analog input */
683 .n_aochan = 8,
684 .aobits = 12,
685 .ao_unipolar = 0,
686 .ao_fifo_depth = 16384,
687 .ao_range_table = &range_bipolar10,
688 .ao_speed = 1000,
689 .num_p0_dio_channels = 8,
690 .reg_type = ni_reg_6713,
691 .caldac = {ad8804_debug, ad8804_debug},
692 },
693 {
694 .device_id = 0x2430,
695 .name = "pci-6731",
696 .n_adchan = 0, /* no analog input */
697 .n_aochan = 4,
698 .aobits = 16,
699 .ao_unipolar = 0,
700 .ao_fifo_depth = 8192,
701 .ao_range_table = &range_bipolar10,
702 .ao_speed = 1000,
703 .num_p0_dio_channels = 8,
704 .reg_type = ni_reg_6711,
705 .caldac = {ad8804_debug},
706 },
707#if 0 /* need device ids */
708 {
709 .device_id = 0x0,
710 .name = "pxi-6731",
711 .n_adchan = 0, /* no analog input */
712 .n_aochan = 4,
713 .aobits = 16,
714 .ao_unipolar = 0,
715 .ao_fifo_depth = 8192,
716 .ao_range_table = &range_bipolar10,
717 .num_p0_dio_channels = 8,
718 .reg_type = ni_reg_6711,
719 .caldac = {ad8804_debug},
720 },
721#endif
722 {
723 .device_id = 0x2410,
724 .name = "pci-6733",
725 .n_adchan = 0, /* no analog input */
726 .n_aochan = 8,
727 .aobits = 16,
728 .ao_unipolar = 0,
729 .ao_fifo_depth = 16384,
730 .ao_range_table = &range_bipolar10,
731 .ao_speed = 1000,
732 .num_p0_dio_channels = 8,
733 .reg_type = ni_reg_6713,
734 .caldac = {ad8804_debug, ad8804_debug},
735 },
736 {
737 .device_id = 0x2420,
738 .name = "pxi-6733",
739 .n_adchan = 0, /* no analog input */
740 .n_aochan = 8,
741 .aobits = 16,
742 .ao_unipolar = 0,
743 .ao_fifo_depth = 16384,
744 .ao_range_table = &range_bipolar10,
745 .ao_speed = 1000,
746 .num_p0_dio_channels = 8,
747 .reg_type = ni_reg_6713,
748 .caldac = {ad8804_debug, ad8804_debug},
749 },
750 {
751 .device_id = 0x15b0,
752 .name = "pxi-6071e",
753 .n_adchan = 64,
754 .adbits = 12,
755 .ai_fifo_depth = 512,
756 .alwaysdither = 1,
757 .gainlkup = ai_gain_16,
758 .ai_speed = 800,
759 .n_aochan = 2,
760 .aobits = 12,
761 .ao_fifo_depth = 2048,
762 .ao_range_table = &range_ni_E_ao_ext,
763 .ao_unipolar = 1,
764 .ao_speed = 1000,
765 .num_p0_dio_channels = 8,
766 .caldac = {ad8804_debug},
767 .has_8255 = 0,
768 },
769 {
770 .device_id = 0x11b0,
771 .name = "pxi-6070e",
772 .n_adchan = 16,
773 .adbits = 12,
774 .ai_fifo_depth = 512,
775 .alwaysdither = 1,
776 .gainlkup = ai_gain_16,
777 .ai_speed = 800,
778 .n_aochan = 2,
779 .aobits = 12,
780 .ao_fifo_depth = 2048,
781 .ao_range_table = &range_ni_E_ao_ext,
782 .ao_unipolar = 1,
783 .ao_speed = 1000,
784 .num_p0_dio_channels = 8,
785 .caldac = {ad8804_debug},
786 .has_8255 = 0,
787 },
788 {
789 .device_id = 0x18c0,
790 .name = "pxi-6052e",
791 .n_adchan = 16,
792 .adbits = 16,
793 .ai_fifo_depth = 512,
794 .alwaysdither = 1,
795 .gainlkup = ai_gain_16,
796 .ai_speed = 3000,
797 .n_aochan = 2,
798 .aobits = 16,
799 .ao_unipolar = 1,
800 .ao_fifo_depth = 2048,
801 .ao_range_table = &range_ni_E_ao_ext,
802 .ao_speed = 3000,
803 .num_p0_dio_channels = 8,
804 .caldac = {mb88341, mb88341, ad8522},
805 },
806 {
807 .device_id = 0x1580,
808 .name = "pxi-6031e",
809 .n_adchan = 64,
810 .adbits = 16,
811 .ai_fifo_depth = 512,
812 .alwaysdither = 1,
813 .gainlkup = ai_gain_14,
814 .ai_speed = 10000,
815 .n_aochan = 2,
816 .aobits = 16,
817 .ao_fifo_depth = 2048,
818 .ao_range_table = &range_ni_E_ao_ext,
819 .ao_unipolar = 1,
820 .ao_speed = 10000,
821 .num_p0_dio_channels = 8,
822 .caldac = {dac8800, dac8043, ad8522},
823 },
824 {
825 .device_id = 0x2890,
826 .name = "pci-6036e",
827 .n_adchan = 16,
828 .adbits = 16,
829 .ai_fifo_depth = 512,
830 .alwaysdither = 1,
831 .gainlkup = ai_gain_4,
832 .ai_speed = 5000,
833 .n_aochan = 2,
834 .aobits = 16,
835 .ao_fifo_depth = 0,
836 .ao_range_table = &range_bipolar10,
837 .ao_unipolar = 0,
838 .ao_speed = 100000,
839 .num_p0_dio_channels = 8,
840 .caldac = {ad8804_debug},
841 .has_8255 = 0,
842 },
843 {
844 .device_id = 0x70b0,
845 .name = "pci-6220",
846 .n_adchan = 16,
847 .adbits = 16,
848 .ai_fifo_depth = 512,
849 //FIXME: guess
850 .gainlkup = ai_gain_622x,
851 .ai_speed = 4000,
852 .n_aochan = 0,
853 .aobits = 0,
854 .ao_fifo_depth = 0,
855 .num_p0_dio_channels = 8,
856 .reg_type = ni_reg_622x,
857 .ao_unipolar = 0,
858 .caldac = {caldac_none},
859 .has_8255 = 0,
860 },
861 {
862 .device_id = 0x70af,
863 .name = "pci-6221",
864 .n_adchan = 16,
865 .adbits = 16,
866 .ai_fifo_depth = 4095,
867 .gainlkup = ai_gain_622x,
868 .ai_speed = 4000,
869 .n_aochan = 2,
870 .aobits = 16,
871 .ao_fifo_depth = 8191,
872 .ao_range_table = &range_ni_M_622x_ao,
873 .reg_type = ni_reg_622x,
874 .ao_unipolar = 0,
875 .ao_speed = 1200,
876 .num_p0_dio_channels = 8,
877 .caldac = {caldac_none},
878 .has_8255 = 0,
879 },
880 {
881 .device_id = 0x71bc,
882 .name = "pci-6221_37pin",
883 .n_adchan = 16,
884 .adbits = 16,
885 .ai_fifo_depth = 4095,
886 .gainlkup = ai_gain_622x,
887 .ai_speed = 4000,
888 .n_aochan = 2,
889 .aobits = 16,
890 .ao_fifo_depth = 8191,
891 .ao_range_table = &range_ni_M_622x_ao,
892 .reg_type = ni_reg_622x,
893 .ao_unipolar = 0,
894 .ao_speed = 1200,
895 .num_p0_dio_channels = 8,
896 .caldac = {caldac_none},
897 .has_8255 = 0,
898 },
899 {
900 .device_id = 0x70f2,
901 .name = "pci-6224",
902 .n_adchan = 32,
903 .adbits = 16,
904 .ai_fifo_depth = 4095,
905 .gainlkup = ai_gain_622x,
906 .ai_speed = 4000,
907 .n_aochan = 0,
908 .aobits = 0,
909 .ao_fifo_depth = 0,
910 .reg_type = ni_reg_622x,
911 .ao_unipolar = 0,
912 .num_p0_dio_channels = 32,
913 .caldac = {caldac_none},
914 .has_8255 = 0,
915 },
916 {
917 .device_id = 0x716c,
918 .name = "pci-6225",
919 .n_adchan = 80,
920 .adbits = 16,
921 .ai_fifo_depth = 4095,
922 .gainlkup = ai_gain_622x,
923 .ai_speed = 4000,
924 .n_aochan = 2,
925 .aobits = 16,
926 .ao_fifo_depth = 8191,
927 .ao_range_table = &range_ni_M_622x_ao,
928 .reg_type = ni_reg_622x,
929 .ao_unipolar = 0,
930 .ao_speed = 1200,
931 .num_p0_dio_channels = 32,
932 .caldac = {caldac_none},
933 .has_8255 = 0,
934 },
935 {
936 .device_id = 0x70aa,
937 .name = "pci-6229",
938 .n_adchan = 32,
939 .adbits = 16,
940 .ai_fifo_depth = 4095,
941 .gainlkup = ai_gain_622x,
942 .ai_speed = 4000,
943 .n_aochan = 4,
944 .aobits = 16,
945 .ao_fifo_depth = 8191,
946 .ao_range_table = &range_ni_M_622x_ao,
947 .reg_type = ni_reg_622x,
948 .ao_unipolar = 0,
949 .ao_speed = 1200,
950 .num_p0_dio_channels = 32,
951 .caldac = {caldac_none},
952 .has_8255 = 0,
953 },
954 {
955 .device_id = 0x70b4,
956 .name = "pci-6250",
957 .n_adchan = 16,
958 .adbits = 16,
959 .ai_fifo_depth = 4095,
960 .gainlkup = ai_gain_628x,
961 .ai_speed = 800,
962 .n_aochan = 0,
963 .aobits = 0,
964 .ao_fifo_depth = 0,
965 .reg_type = ni_reg_625x,
966 .ao_unipolar = 0,
967 .num_p0_dio_channels = 8,
968 .caldac = {caldac_none},
969 .has_8255 = 0,
970 },
971 {
972 .device_id = 0x70b8,
973 .name = "pci-6251",
974 .n_adchan = 16,
975 .adbits = 16,
976 .ai_fifo_depth = 4095,
977 .gainlkup = ai_gain_628x,
978 .ai_speed = 800,
979 .n_aochan = 2,
980 .aobits = 16,
981 .ao_fifo_depth = 8191,
982 .ao_range_table = &range_ni_M_625x_ao,
983 .reg_type = ni_reg_625x,
984 .ao_unipolar = 0,
985 .ao_speed = 357,
986 .num_p0_dio_channels = 8,
987 .caldac = {caldac_none},
988 .has_8255 = 0,
989 },
990 {
991 .device_id = 0x717d,
992 .name = "pcie-6251",
993 .n_adchan = 16,
994 .adbits = 16,
995 .ai_fifo_depth = 4095,
996 .gainlkup = ai_gain_628x,
997 .ai_speed = 800,
998 .n_aochan = 2,
999 .aobits = 16,
1000 .ao_fifo_depth = 8191,
1001 .ao_range_table = &range_ni_M_625x_ao,
1002 .reg_type = ni_reg_625x,
1003 .ao_unipolar = 0,
1004 .ao_speed = 357,
1005 .num_p0_dio_channels = 8,
1006 .caldac = {caldac_none},
1007 .has_8255 = 0,
1008 },
1009 {
1010 .device_id = 0x70b7,
1011 .name = "pci-6254",
1012 .n_adchan = 32,
1013 .adbits = 16,
1014 .ai_fifo_depth = 4095,
1015 .gainlkup = ai_gain_628x,
1016 .ai_speed = 800,
1017 .n_aochan = 0,
1018 .aobits = 0,
1019 .ao_fifo_depth = 0,
1020 .reg_type = ni_reg_625x,
1021 .ao_unipolar = 0,
1022 .num_p0_dio_channels = 32,
1023 .caldac = {caldac_none},
1024 .has_8255 = 0,
1025 },
1026 {
1027 .device_id = 0x70ab,
1028 .name = "pci-6259",
1029 .n_adchan = 32,
1030 .adbits = 16,
1031 .ai_fifo_depth = 4095,
1032 .gainlkup = ai_gain_628x,
1033 .ai_speed = 800,
1034 .n_aochan = 4,
1035 .aobits = 16,
1036 .ao_fifo_depth = 8191,
1037 .ao_range_table = &range_ni_M_625x_ao,
1038 .reg_type = ni_reg_625x,
1039 .ao_unipolar = 0,
1040 .ao_speed = 357,
1041 .num_p0_dio_channels = 32,
1042 .caldac = {caldac_none},
1043 .has_8255 = 0,
1044 },
1045 {
1046 .device_id = 0x717f,
1047 .name = "pcie-6259",
1048 .n_adchan = 32,
1049 .adbits = 16,
1050 .ai_fifo_depth = 4095,
1051 .gainlkup = ai_gain_628x,
1052 .ai_speed = 800,
1053 .n_aochan = 4,
1054 .aobits = 16,
1055 .ao_fifo_depth = 8191,
1056 .ao_range_table = &range_ni_M_625x_ao,
1057 .reg_type = ni_reg_625x,
1058 .ao_unipolar = 0,
1059 .ao_speed = 357,
1060 .num_p0_dio_channels = 32,
1061 .caldac = {caldac_none},
1062 .has_8255 = 0,
1063 },
1064 {
1065 .device_id = 0x70b6,
1066 .name = "pci-6280",
1067 .n_adchan = 16,
1068 .adbits = 18,
1069 .ai_fifo_depth = 2047,
1070 .gainlkup = ai_gain_628x,
1071 .ai_speed = 1600,
1072 .n_aochan = 0,
1073 .aobits = 0,
1074 .ao_fifo_depth = 8191,
1075 .reg_type = ni_reg_628x,
1076 .ao_unipolar = 0,
1077 .num_p0_dio_channels = 8,
1078 .caldac = {caldac_none},
1079 .has_8255 = 0,
1080 },
1081 {
1082 .device_id = 0x70bd,
1083 .name = "pci-6281",
1084 .n_adchan = 16,
1085 .adbits = 18,
1086 .ai_fifo_depth = 2047,
1087 .gainlkup = ai_gain_628x,
1088 .ai_speed = 1600,
1089 .n_aochan = 2,
1090 .aobits = 16,
1091 .ao_fifo_depth = 8191,
1092 .ao_range_table = &range_ni_M_628x_ao,
1093 .reg_type = ni_reg_628x,
1094 .ao_unipolar = 1,
1095 .ao_speed = 357,
1096 .num_p0_dio_channels = 8,
1097 .caldac = {caldac_none},
1098 .has_8255 = 0,
1099 },
1100 {
1101 .device_id = 0x70bf,
1102 .name = "pxi-6281",
1103 .n_adchan = 16,
1104 .adbits = 18,
1105 .ai_fifo_depth = 2047,
1106 .gainlkup = ai_gain_628x,
1107 .ai_speed = 1600,
1108 .n_aochan = 2,
1109 .aobits = 16,
1110 .ao_fifo_depth = 8191,
1111 .ao_range_table = &range_ni_M_628x_ao,
1112 .reg_type = ni_reg_628x,
1113 .ao_unipolar = 1,
1114 .ao_speed = 357,
1115 .num_p0_dio_channels = 8,
1116 .caldac = {caldac_none},
1117 .has_8255 = 0,
1118 },
1119 {
1120 .device_id = 0x70bc,
1121 .name = "pci-6284",
1122 .n_adchan = 32,
1123 .adbits = 18,
1124 .ai_fifo_depth = 2047,
1125 .gainlkup = ai_gain_628x,
1126 .ai_speed = 1600,
1127 .n_aochan = 0,
1128 .aobits = 0,
1129 .ao_fifo_depth = 0,
1130 .reg_type = ni_reg_628x,
1131 .ao_unipolar = 0,
1132 .num_p0_dio_channels = 32,
1133 .caldac = {caldac_none},
1134 .has_8255 = 0,
1135 },
1136 {
1137 .device_id = 0x70ac,
1138 .name = "pci-6289",
1139 .n_adchan = 32,
1140 .adbits = 18,
1141 .ai_fifo_depth = 2047,
1142 .gainlkup = ai_gain_628x,
1143 .ai_speed = 1600,
1144 .n_aochan = 4,
1145 .aobits = 16,
1146 .ao_fifo_depth = 8191,
1147 .ao_range_table = &range_ni_M_628x_ao,
1148 .reg_type = ni_reg_628x,
1149 .ao_unipolar = 1,
1150 .ao_speed = 357,
1151 .num_p0_dio_channels = 32,
1152 .caldac = {caldac_none},
1153 .has_8255 = 0,
1154 },
1155 {
1156 .device_id = 0x70C0,
1157 .name = "pci-6143",
1158 .n_adchan = 8,
1159 .adbits = 16,
1160 .ai_fifo_depth = 1024,
1161 .alwaysdither = 0,
1162 .gainlkup = ai_gain_6143,
1163 .ai_speed = 4000,
1164 .n_aochan = 0,
1165 .aobits = 0,
1166 .reg_type = ni_reg_6143,
1167 .ao_unipolar = 0,
1168 .ao_fifo_depth = 0,
1169 .num_p0_dio_channels = 8,
1170 .caldac = {ad8804_debug, ad8804_debug},
1171 },
1172 {
1173 .device_id = 0x710D,
1174 .name = "pxi-6143",
1175 .n_adchan = 8,
1176 .adbits = 16,
1177 .ai_fifo_depth = 1024,
1178 .alwaysdither = 0,
1179 .gainlkup = ai_gain_6143,
1180 .ai_speed = 4000,
1181 .n_aochan = 0,
1182 .aobits = 0,
1183 .reg_type = ni_reg_6143,
1184 .ao_unipolar = 0,
1185 .ao_fifo_depth = 0,
1186 .num_p0_dio_channels = 8,
1187 .caldac = {ad8804_debug, ad8804_debug},
1188 },
1189};
1190
1191#define n_pcimio_boards ((sizeof(ni_boards)/sizeof(ni_boards[0])))
1192
1193static int pcimio_attach(comedi_device * dev, comedi_devconfig * it);
1194static int pcimio_detach(comedi_device * dev);
1195static comedi_driver driver_pcimio = {
1196 driver_name: DRV_NAME,
1197 module:THIS_MODULE,
1198 attach:pcimio_attach,
1199 detach:pcimio_detach,
1200};
1201
1202COMEDI_PCI_INITCLEANUP(driver_pcimio, ni_pci_table)
1203
1204typedef struct {
1205NI_PRIVATE_COMMON} ni_private;
1206#define devpriv ((ni_private *)dev->private)
1207
1208/* How we access registers */
1209
1210#define ni_writel(a,b) (writel((a), devpriv->mite->daq_io_addr + (b)))
1211#define ni_readl(a) (readl(devpriv->mite->daq_io_addr + (a)))
1212#define ni_writew(a,b) (writew((a), devpriv->mite->daq_io_addr + (b)))
1213#define ni_readw(a) (readw(devpriv->mite->daq_io_addr + (a)))
1214#define ni_writeb(a,b) (writeb((a), devpriv->mite->daq_io_addr + (b)))
1215#define ni_readb(a) (readb(devpriv->mite->daq_io_addr + (a)))
1216
1217/* How we access STC registers */
1218
1219/* We automatically take advantage of STC registers that can be
1220 * read/written directly in the I/O space of the board. Most
1221 * PCIMIO devices map the low 8 STC registers to iobase+addr*2.
1222 * The 611x devices map the write registers to iobase+addr*2, and
1223 * the read registers to iobase+(addr-1)*2. */
1224/* However, the 611x boards still aren't working, so I'm disabling
1225 * non-windowed STC access temporarily */
1226
1227static void e_series_win_out(comedi_device * dev, uint16_t data, int reg)
1228{
1229 unsigned long flags;
1230
1231 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
1232 ni_writew(reg, Window_Address);
1233 ni_writew(data, Window_Data);
1234 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
1235}
1236
1237static uint16_t e_series_win_in(comedi_device * dev, int reg)
1238{
1239 unsigned long flags;
1240 uint16_t ret;
1241
1242 comedi_spin_lock_irqsave(&devpriv->window_lock, flags);
1243 ni_writew(reg, Window_Address);
1244 ret = ni_readw(Window_Data);
1245 comedi_spin_unlock_irqrestore(&devpriv->window_lock, flags);
1246
1247 return ret;
1248}
1249
1250static void m_series_stc_writew(comedi_device * dev, uint16_t data, int reg)
1251{
1252 unsigned offset;
1253 switch (reg) {
1254 case ADC_FIFO_Clear:
1255 offset = M_Offset_AI_FIFO_Clear;
1256 break;
1257 case AI_Command_1_Register:
1258 offset = M_Offset_AI_Command_1;
1259 break;
1260 case AI_Command_2_Register:
1261 offset = M_Offset_AI_Command_2;
1262 break;
1263 case AI_Mode_1_Register:
1264 offset = M_Offset_AI_Mode_1;
1265 break;
1266 case AI_Mode_2_Register:
1267 offset = M_Offset_AI_Mode_2;
1268 break;
1269 case AI_Mode_3_Register:
1270 offset = M_Offset_AI_Mode_3;
1271 break;
1272 case AI_Output_Control_Register:
1273 offset = M_Offset_AI_Output_Control;
1274 break;
1275 case AI_Personal_Register:
1276 offset = M_Offset_AI_Personal;
1277 break;
1278 case AI_SI2_Load_A_Register:
1279 // this is actually a 32 bit register on m series boards
1280 ni_writel(data, M_Offset_AI_SI2_Load_A);
1281 return;
1282 break;
1283 case AI_SI2_Load_B_Register:
1284 // this is actually a 32 bit register on m series boards
1285 ni_writel(data, M_Offset_AI_SI2_Load_B);
1286 return;
1287 break;
1288 case AI_START_STOP_Select_Register:
1289 offset = M_Offset_AI_START_STOP_Select;
1290 break;
1291 case AI_Trigger_Select_Register:
1292 offset = M_Offset_AI_Trigger_Select;
1293 break;
1294 case Analog_Trigger_Etc_Register:
1295 offset = M_Offset_Analog_Trigger_Etc;
1296 break;
1297 case AO_Command_1_Register:
1298 offset = M_Offset_AO_Command_1;
1299 break;
1300 case AO_Command_2_Register:
1301 offset = M_Offset_AO_Command_2;
1302 break;
1303 case AO_Mode_1_Register:
1304 offset = M_Offset_AO_Mode_1;
1305 break;
1306 case AO_Mode_2_Register:
1307 offset = M_Offset_AO_Mode_2;
1308 break;
1309 case AO_Mode_3_Register:
1310 offset = M_Offset_AO_Mode_3;
1311 break;
1312 case AO_Output_Control_Register:
1313 offset = M_Offset_AO_Output_Control;
1314 break;
1315 case AO_Personal_Register:
1316 offset = M_Offset_AO_Personal;
1317 break;
1318 case AO_Start_Select_Register:
1319 offset = M_Offset_AO_Start_Select;
1320 break;
1321 case AO_Trigger_Select_Register:
1322 offset = M_Offset_AO_Trigger_Select;
1323 break;
1324 case Clock_and_FOUT_Register:
1325 offset = M_Offset_Clock_and_FOUT;
1326 break;
1327 case Configuration_Memory_Clear:
1328 offset = M_Offset_Configuration_Memory_Clear;
1329 break;
1330 case DAC_FIFO_Clear:
1331 offset = M_Offset_AO_FIFO_Clear;
1332 break;
1333 case DIO_Control_Register:
1334 rt_printk
1335 ("%s: FIXME: register 0x%x does not map cleanly on to m-series boards.\n",
1336 __FUNCTION__, reg);
1337 return;
1338 break;
1339 case G_Autoincrement_Register(0):
1340 offset = M_Offset_G0_Autoincrement;
1341 break;
1342 case G_Autoincrement_Register(1):
1343 offset = M_Offset_G1_Autoincrement;
1344 break;
1345 case G_Command_Register(0):
1346 offset = M_Offset_G0_Command;
1347 break;
1348 case G_Command_Register(1):
1349 offset = M_Offset_G1_Command;
1350 break;
1351 case G_Input_Select_Register(0):
1352 offset = M_Offset_G0_Input_Select;
1353 break;
1354 case G_Input_Select_Register(1):
1355 offset = M_Offset_G1_Input_Select;
1356 break;
1357 case G_Mode_Register(0):
1358 offset = M_Offset_G0_Mode;
1359 break;
1360 case G_Mode_Register(1):
1361 offset = M_Offset_G1_Mode;
1362 break;
1363 case Interrupt_A_Ack_Register:
1364 offset = M_Offset_Interrupt_A_Ack;
1365 break;
1366 case Interrupt_A_Enable_Register:
1367 offset = M_Offset_Interrupt_A_Enable;
1368 break;
1369 case Interrupt_B_Ack_Register:
1370 offset = M_Offset_Interrupt_B_Ack;
1371 break;
1372 case Interrupt_B_Enable_Register:
1373 offset = M_Offset_Interrupt_B_Enable;
1374 break;
1375 case Interrupt_Control_Register:
1376 offset = M_Offset_Interrupt_Control;
1377 break;
1378 case IO_Bidirection_Pin_Register:
1379 offset = M_Offset_IO_Bidirection_Pin;
1380 break;
1381 case Joint_Reset_Register:
1382 offset = M_Offset_Joint_Reset;
1383 break;
1384 case RTSI_Trig_A_Output_Register:
1385 offset = M_Offset_RTSI_Trig_A_Output;
1386 break;
1387 case RTSI_Trig_B_Output_Register:
1388 offset = M_Offset_RTSI_Trig_B_Output;
1389 break;
1390 case RTSI_Trig_Direction_Register:
1391 offset = M_Offset_RTSI_Trig_Direction;
1392 break;
1393 /* FIXME: DIO_Output_Register (16 bit reg) is replaced by M_Offset_Static_Digital_Output (32 bit)
1394 and M_Offset_SCXI_Serial_Data_Out (8 bit) */
1395 default:
1396 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1397 __FUNCTION__, reg);
1398 BUG();
1399 return;
1400 break;
1401 }
1402 ni_writew(data, offset);
1403}
1404
1405static uint16_t m_series_stc_readw(comedi_device * dev, int reg)
1406{
1407 unsigned offset;
1408 switch (reg) {
1409 case AI_Status_1_Register:
1410 offset = M_Offset_AI_Status_1;
1411 break;
1412 case AO_Status_1_Register:
1413 offset = M_Offset_AO_Status_1;
1414 break;
1415 case AO_Status_2_Register:
1416 offset = M_Offset_AO_Status_2;
1417 break;
1418 case DIO_Serial_Input_Register:
1419 return ni_readb(M_Offset_SCXI_Serial_Data_In);
1420 break;
1421 case Joint_Status_1_Register:
1422 offset = M_Offset_Joint_Status_1;
1423 break;
1424 case Joint_Status_2_Register:
1425 offset = M_Offset_Joint_Status_2;
1426 break;
1427 case G_Status_Register:
1428 offset = M_Offset_G01_Status;
1429 break;
1430 default:
1431 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1432 __FUNCTION__, reg);
1433 BUG();
1434 return 0;
1435 break;
1436 }
1437 return ni_readw(offset);
1438}
1439
1440static void m_series_stc_writel(comedi_device * dev, uint32_t data, int reg)
1441{
1442 unsigned offset;
1443 switch (reg) {
1444 case AI_SC_Load_A_Registers:
1445 offset = M_Offset_AI_SC_Load_A;
1446 break;
1447 case AI_SI_Load_A_Registers:
1448 offset = M_Offset_AI_SI_Load_A;
1449 break;
1450 case AO_BC_Load_A_Register:
1451 offset = M_Offset_AO_BC_Load_A;
1452 break;
1453 case AO_UC_Load_A_Register:
1454 offset = M_Offset_AO_UC_Load_A;
1455 break;
1456 case AO_UI_Load_A_Register:
1457 offset = M_Offset_AO_UI_Load_A;
1458 break;
1459 case G_Load_A_Register(0):
1460 offset = M_Offset_G0_Load_A;
1461 break;
1462 case G_Load_A_Register(1):
1463 offset = M_Offset_G1_Load_A;
1464 break;
1465 case G_Load_B_Register(0):
1466 offset = M_Offset_G0_Load_B;
1467 break;
1468 case G_Load_B_Register(1):
1469 offset = M_Offset_G1_Load_B;
1470 break;
1471 default:
1472 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1473 __FUNCTION__, reg);
1474 BUG();
1475 return;
1476 break;
1477 }
1478 ni_writel(data, offset);
1479}
1480
1481static uint32_t m_series_stc_readl(comedi_device * dev, int reg)
1482{
1483 unsigned offset;
1484 switch (reg) {
1485 case G_HW_Save_Register(0):
1486 offset = M_Offset_G0_HW_Save;
1487 break;
1488 case G_HW_Save_Register(1):
1489 offset = M_Offset_G1_HW_Save;
1490 break;
1491 case G_Save_Register(0):
1492 offset = M_Offset_G0_Save;
1493 break;
1494 case G_Save_Register(1):
1495 offset = M_Offset_G1_Save;
1496 break;
1497 default:
1498 rt_printk("%s: bug! unhandled register=0x%x in switch.\n",
1499 __FUNCTION__, reg);
1500 BUG();
1501 return 0;
1502 break;
1503 }
1504 return ni_readl(offset);
1505}
1506
1507#define interrupt_pin(a) 0
1508#define IRQ_POLARITY 1
1509
1510#define NI_E_IRQ_FLAGS IRQF_SHARED
1511
1512#include "ni_mio_common.c"
1513
1514static int pcimio_find_device(comedi_device * dev, int bus, int slot);
1515static int pcimio_ai_change(comedi_device * dev, comedi_subdevice * s,
1516 unsigned long new_size);
1517static int pcimio_ao_change(comedi_device * dev, comedi_subdevice * s,
1518 unsigned long new_size);
1519static int pcimio_gpct0_change(comedi_device * dev, comedi_subdevice * s,
1520 unsigned long new_size);
1521static int pcimio_gpct1_change(comedi_device * dev, comedi_subdevice * s,
1522 unsigned long new_size);
1523static int pcimio_dio_change(comedi_device * dev, comedi_subdevice * s,
1524 unsigned long new_size);
1525
1526static void m_series_init_eeprom_buffer(comedi_device * dev)
1527{
1528 static const int Start_Cal_EEPROM = 0x400;
1529 static const unsigned window_size = 10;
f8db88ef
FMH		 1530 static const int serial_number_eeprom_offset = 0x4;
1531 static const int serial_number_eeprom_length = 0x4;
c4beb34e
DS		 1532 unsigned old_iodwbsr_bits;
1533 unsigned old_iodwbsr1_bits;
1534 unsigned old_iodwcr1_bits;
1535 int i;
1536
1537 old_iodwbsr_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR);
1538 old_iodwbsr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1539 old_iodwcr1_bits = readl(devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1540 writel(0x0, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1541 writel(((0x80 | window_size) | devpriv->mite->daq_phys_addr),
1542 devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
f8db88ef 1543 writel(0x1 | old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
c4beb34e
DS		 1544 writel(0xf, devpriv->mite->mite_io_addr + 0x30);
1545
f8db88ef
FMH		 1546 BUG_ON(serial_number_eeprom_length > sizeof(devpriv->serial_number));
1547 for (i = 0; i < serial_number_eeprom_length; ++i) {
1548 char *byte_ptr = (char*)&devpriv->serial_number + i;
1549 *byte_ptr = ni_readb(serial_number_eeprom_offset + i);
1550 }
1551 devpriv->serial_number = be32_to_cpu(devpriv->serial_number);
1552
c4beb34e
DS		 1553 for (i = 0; i < M_SERIES_EEPROM_SIZE; ++i) {
1554 devpriv->eeprom_buffer[i] = ni_readb(Start_Cal_EEPROM + i);
1555 }
1556
1557 writel(old_iodwbsr1_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR_1);
1558 writel(old_iodwbsr_bits, devpriv->mite->mite_io_addr + MITE_IODWBSR);
1559 writel(old_iodwcr1_bits, devpriv->mite->mite_io_addr + MITE_IODWCR_1);
1560 writel(0x0, devpriv->mite->mite_io_addr + 0x30);
1561}
1562
1563static void init_6143(comedi_device * dev)
1564{
1565 // Disable interrupts
1566 devpriv->stc_writew(dev, 0, Interrupt_Control_Register);
1567
1568 // Initialise 6143 AI specific bits
1569 ni_writeb(0x00, Magic_6143); // Set G0,G1 DMA mode to E series version
1570 ni_writeb(0x80, PipelineDelay_6143); // Set EOCMode, ADCMode and pipelinedelay
1571 ni_writeb(0x00, EOC_Set_6143); // Set EOC Delay
1572
1573 ni_writel(boardtype.ai_fifo_depth / 2, AIFIFO_Flag_6143); // Set the FIFO half full level
1574
1575 // Strobe Relay disable bit
1576 devpriv->ai_calib_source_enabled = 0;
1577 ni_writew(devpriv->ai_calib_source | Calibration_Channel_6143_RelayOff,
1578 Calibration_Channel_6143);
1579 ni_writew(devpriv->ai_calib_source, Calibration_Channel_6143);
1580}
1581
1582/* cleans up allocated resources */
1583static int pcimio_detach(comedi_device * dev)
1584{
1585 mio_common_detach(dev);
1586 if (dev->irq) {
1587 comedi_free_irq(dev->irq, dev);
1588 }
1589 if (dev->private) {
1590 mite_free_ring(devpriv->ai_mite_ring);
1591 mite_free_ring(devpriv->ao_mite_ring);
1592 mite_free_ring(devpriv->cdo_mite_ring);
1593 mite_free_ring(devpriv->gpct_mite_ring[0]);
1594 mite_free_ring(devpriv->gpct_mite_ring[1]);
1595 if (devpriv->mite)
1596 mite_unsetup(devpriv->mite);
1597 }
1598
1599 return 0;
1600}
1601
1602static int pcimio_attach(comedi_device * dev, comedi_devconfig * it)
1603{
1604 int ret;
1605
1606 printk("comedi%d: ni_pcimio:", dev->minor);
1607
1608 ret = ni_alloc_private(dev);
1609 if (ret < 0)
1610 return ret;
1611
1612 ret = pcimio_find_device(dev, it->options[0], it->options[1]);
1613 if (ret < 0)
1614 return ret;
1615
1616 printk(" %s", boardtype.name);
1617 dev->board_name = boardtype.name;
1618
1619 if (boardtype.reg_type & ni_reg_m_series_mask) {
1620 devpriv->stc_writew = &m_series_stc_writew;
1621 devpriv->stc_readw = &m_series_stc_readw;
1622 devpriv->stc_writel = &m_series_stc_writel;
1623 devpriv->stc_readl = &m_series_stc_readl;
1624 } else {
1625 devpriv->stc_writew = &e_series_win_out;
1626 devpriv->stc_readw = &e_series_win_in;
1627 devpriv->stc_writel = &win_out2;
1628 devpriv->stc_readl = &win_in2;
1629 }
1630
1631 ret = mite_setup(devpriv->mite);
1632 if (ret < 0) {
1633 printk(" error setting up mite\n");
1634 return ret;
1635 }
1636 comedi_set_hw_dev(dev, &devpriv->mite->pcidev->dev);
1637 devpriv->ai_mite_ring = mite_alloc_ring(devpriv->mite);
1638 if (devpriv->ai_mite_ring == NULL)
1639 return -ENOMEM;
1640 devpriv->ao_mite_ring = mite_alloc_ring(devpriv->mite);
1641 if (devpriv->ao_mite_ring == NULL)
1642 return -ENOMEM;
1643 devpriv->cdo_mite_ring = mite_alloc_ring(devpriv->mite);
1644 if (devpriv->cdo_mite_ring == NULL)
1645 return -ENOMEM;
1646 devpriv->gpct_mite_ring[0] = mite_alloc_ring(devpriv->mite);
1647 if (devpriv->gpct_mite_ring[0] == NULL)
1648 return -ENOMEM;
1649 devpriv->gpct_mite_ring[1] = mite_alloc_ring(devpriv->mite);
1650 if (devpriv->gpct_mite_ring[1] == NULL)
1651 return -ENOMEM;
1652
1653 if (boardtype.reg_type & ni_reg_m_series_mask)
1654 m_series_init_eeprom_buffer(dev);
1655 if (boardtype.reg_type == ni_reg_6143)
1656 init_6143(dev);
1657
1658 dev->irq = mite_irq(devpriv->mite);
1659
1660 if (dev->irq == 0) {
1661 printk(" unknown irq (bad)\n");
1662 } else {
1663 printk(" ( irq = %u )", dev->irq);
1664 if ((ret = comedi_request_irq(dev->irq, ni_E_interrupt,
1665 NI_E_IRQ_FLAGS, DRV_NAME,
1666 dev)) < 0) {
1667 printk(" irq not available\n");
1668 dev->irq = 0;
1669 }
1670 }
1671
1672 ret = ni_E_init(dev, it);
1673 if (ret < 0)
1674 return ret;
1675
1676 dev->subdevices[NI_AI_SUBDEV].buf_change = &pcimio_ai_change;
1677 dev->subdevices[NI_AO_SUBDEV].buf_change = &pcimio_ao_change;
1678 dev->subdevices[NI_GPCT_SUBDEV(0)].buf_change = &pcimio_gpct0_change;
1679 dev->subdevices[NI_GPCT_SUBDEV(1)].buf_change = &pcimio_gpct1_change;
1680 dev->subdevices[NI_DIO_SUBDEV].buf_change = &pcimio_dio_change;
1681
1682 return ret;
1683}
1684
1685static int pcimio_find_device(comedi_device * dev, int bus, int slot)
1686{
1687 struct mite_struct *mite;
1688 int i;
1689
1690 for (mite = mite_devices; mite; mite = mite->next) {
1691 if (mite->used)
1692 continue;
1693 if (bus || slot) {
1694 if (bus != mite->pcidev->bus->number ||
1695 slot != PCI_SLOT(mite->pcidev->devfn))
1696 continue;
1697 }
1698
1699 for (i = 0; i < n_pcimio_boards; i++) {
1700 if (mite_device_id(mite) == ni_boards[i].device_id) {
1701 dev->board_ptr = ni_boards + i;
1702 devpriv->mite = mite;
1703
1704 return 0;
1705 }
1706 }
1707 }
1708 printk("no device found\n");
1709 mite_list_devices();
1710 return -EIO;
1711}
1712
1713static int pcimio_ai_change(comedi_device * dev, comedi_subdevice * s,
1714 unsigned long new_size)
1715{
1716 int ret;
1717
1718 ret = mite_buf_change(devpriv->ai_mite_ring, s->async);
1719 if (ret < 0)
1720 return ret;
1721
1722 return 0;
1723}
1724
1725static int pcimio_ao_change(comedi_device * dev, comedi_subdevice * s,
1726 unsigned long new_size)
1727{
1728 int ret;
1729
1730 ret = mite_buf_change(devpriv->ao_mite_ring, s->async);
1731 if (ret < 0)
1732 return ret;
1733
1734 return 0;
1735}
1736
1737static int pcimio_gpct0_change(comedi_device * dev, comedi_subdevice * s,
1738 unsigned long new_size)
1739{
1740 int ret;
1741
1742 ret = mite_buf_change(devpriv->gpct_mite_ring[0], s->async);
1743 if (ret < 0)
1744 return ret;
1745
1746 return 0;
1747}
1748
1749static int pcimio_gpct1_change(comedi_device * dev, comedi_subdevice * s,
1750 unsigned long new_size)
1751{
1752 int ret;
1753
1754 ret = mite_buf_change(devpriv->gpct_mite_ring[1], s->async);
1755 if (ret < 0)
1756 return ret;
1757
1758 return 0;
1759}
1760
1761static int pcimio_dio_change(comedi_device * dev, comedi_subdevice * s,
1762 unsigned long new_size)
1763{
1764 int ret;
1765
1766 ret = mite_buf_change(devpriv->cdo_mite_ring, s->async);
1767 if (ret < 0)
1768 return ret;
1769
1770 return 0;
1771}
Linux kernel - Deliverables
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