[deliverable/linux.git] / drivers / staging / comedi / drivers / ni_tio_internal.h

/*
    drivers/ni_tio_internal.h
    Header file for NI general purpose counter support code (ni_tio.c and
    ni_tiocmd.c)

    COMEDI - Linux Control and Measurement Device Interface

    This program is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 2 of the License, or
    (at your option) any later version.

    This program is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.
*/

#ifndef _COMEDI_NI_TIO_INTERNAL_H
#define _COMEDI_NI_TIO_INTERNAL_H

#include "ni_tio.h"

static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
							       counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Autoincrement_Reg;
		break;
	case 1:
		return NITIO_G1_Autoincrement_Reg;
		break;
	case 2:
		return NITIO_G2_Autoincrement_Reg;
		break;
	case 3:
		return NITIO_G3_Autoincrement_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Command_Reg;
		break;
	case 1:
		return NITIO_G1_Command_Reg;
		break;
	case 2:
		return NITIO_G2_Command_Reg;
		break;
	case 3:
		return NITIO_G3_Command_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
							       counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Counting_Mode_Reg;
		break;
	case 1:
		return NITIO_G1_Counting_Mode_Reg;
		break;
	case 2:
		return NITIO_G2_Counting_Mode_Reg;
		break;
	case 3:
		return NITIO_G3_Counting_Mode_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
							      counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Input_Select_Reg;
		break;
	case 1:
		return NITIO_G1_Input_Select_Reg;
		break;
	case 2:
		return NITIO_G2_Input_Select_Reg;
		break;
	case 3:
		return NITIO_G3_Input_Select_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
							      counter_index)
{
	switch (counter_index) {
	case 0:
	case 1:
		return NITIO_G01_Joint_Reset_Reg;
		break;
	case 2:
	case 3:
		return NITIO_G23_Joint_Reset_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
								counter_index)
{
	switch (counter_index) {
	case 0:
	case 1:
		return NITIO_G01_Joint_Status1_Reg;
		break;
	case 2:
	case 3:
		return NITIO_G23_Joint_Status1_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
								counter_index)
{
	switch (counter_index) {
	case 0:
	case 1:
		return NITIO_G01_Joint_Status2_Reg;
		break;
	case 2:
	case 3:
		return NITIO_G23_Joint_Status2_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
{
	switch (counter_index) {
	case 0:
	case 1:
		return NITIO_G01_Status_Reg;
		break;
	case 2:
	case 3:
		return NITIO_G23_Status_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_LoadA_Reg;
		break;
	case 1:
		return NITIO_G1_LoadA_Reg;
		break;
	case 2:
		return NITIO_G2_LoadA_Reg;
		break;
	case 3:
		return NITIO_G3_LoadA_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_LoadB_Reg;
		break;
	case 1:
		return NITIO_G1_LoadB_Reg;
		break;
	case 2:
		return NITIO_G2_LoadB_Reg;
		break;
	case 3:
		return NITIO_G3_LoadB_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Mode_Reg;
		break;
	case 1:
		return NITIO_G1_Mode_Reg;
		break;
	case 2:
		return NITIO_G2_Mode_Reg;
		break;
	case 3:
		return NITIO_G3_Mode_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_SW_Save_Reg;
		break;
	case 1:
		return NITIO_G1_SW_Save_Reg;
		break;
	case 2:
		return NITIO_G2_SW_Save_Reg;
		break;
	case 3:
		return NITIO_G3_SW_Save_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Second_Gate_Reg;
		break;
	case 1:
		return NITIO_G1_Second_Gate_Reg;
		break;
	case 2:
		return NITIO_G2_Second_Gate_Reg;
		break;
	case 3:
		return NITIO_G3_Second_Gate_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_DMA_Config_Reg;
		break;
	case 1:
		return NITIO_G1_DMA_Config_Reg;
		break;
	case 2:
		return NITIO_G2_DMA_Config_Reg;
		break;
	case 3:
		return NITIO_G3_DMA_Config_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_DMA_Status_Reg;
		break;
	case 1:
		return NITIO_G1_DMA_Status_Reg;
		break;
	case 2:
		return NITIO_G2_DMA_Status_Reg;
		break;
	case 3:
		return NITIO_G3_DMA_Status_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_ABZ_Reg;
		break;
	case 1:
		return NITIO_G1_ABZ_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(
	int counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Interrupt_Acknowledge_Reg;
		break;
	case 1:
		return NITIO_G1_Interrupt_Acknowledge_Reg;
		break;
	case 2:
		return NITIO_G2_Interrupt_Acknowledge_Reg;
		break;
	case 3:
		return NITIO_G3_Interrupt_Acknowledge_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Status_Reg;
		break;
	case 1:
		return NITIO_G1_Status_Reg;
		break;
	case 2:
		return NITIO_G2_Status_Reg;
		break;
	case 3:
		return NITIO_G3_Status_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(
	int counter_index)
{
	switch (counter_index) {
	case 0:
		return NITIO_G0_Interrupt_Enable_Reg;
		break;
	case 1:
		return NITIO_G1_Interrupt_Enable_Reg;
		break;
	case 2:
		return NITIO_G2_Interrupt_Enable_Reg;
		break;
	case 3:
		return NITIO_G3_Interrupt_Enable_Reg;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

enum Gi_Auto_Increment_Reg_Bits {
	Gi_Auto_Increment_Mask = 0xff
};

#define Gi_Up_Down_Shift 5
enum Gi_Command_Reg_Bits {
	Gi_Arm_Bit = 0x1,
	Gi_Save_Trace_Bit = 0x2,
	Gi_Load_Bit = 0x4,
	Gi_Disarm_Bit = 0x10,
	Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
	Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
	Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
	Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
	Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
	Gi_Write_Switch_Bit = 0x80,
	Gi_Synchronize_Gate_Bit = 0x100,
	Gi_Little_Big_Endian_Bit = 0x200,
	Gi_Bank_Switch_Start_Bit = 0x400,
	Gi_Bank_Switch_Mode_Bit = 0x800,
	Gi_Bank_Switch_Enable_Bit = 0x1000,
	Gi_Arm_Copy_Bit = 0x2000,
	Gi_Save_Trace_Copy_Bit = 0x4000,
	Gi_Disarm_Copy_Bit = 0x8000
};

#define Gi_Index_Phase_Bitshift 5
#define Gi_HW_Arm_Select_Shift 8
enum Gi_Counting_Mode_Reg_Bits {
	Gi_Counting_Mode_Mask = 0x7,
	Gi_Counting_Mode_Normal_Bits = 0x0,
	Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
	Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
	Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
	Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
	Gi_Counting_Mode_Sync_Source_Bits = 0x6,
	Gi_Index_Mode_Bit = 0x10,
	Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
	Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
	Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
	Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
	Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
	/* from m-series example code, not documented in 660x register level
	 * manual */
	Gi_HW_Arm_Enable_Bit = 0x80,
	/* from m-series example code, not documented in 660x register level
	 * manual */
	Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
	Gi_660x_Prescale_X8_Bit = 0x1000,
	Gi_M_Series_Prescale_X8_Bit = 0x2000,
	Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
	/* must be set for clocks over 40MHz, which includes synchronous
	 * counting and quadrature modes */
	Gi_660x_Alternate_Sync_Bit = 0x2000,
	Gi_M_Series_Alternate_Sync_Bit = 0x4000,
	/* from m-series example code, not documented in 660x register level
	 * manual */
	Gi_660x_Prescale_X2_Bit = 0x4000,
	Gi_M_Series_Prescale_X2_Bit = 0x8000,
};

#define Gi_Source_Select_Shift 2
#define Gi_Gate_Select_Shift 7
enum Gi_Input_Select_Bits {
	Gi_Read_Acknowledges_Irq = 0x1,	/*  not present on 660x */
	Gi_Write_Acknowledges_Irq = 0x2,	/*  not present on 660x */
	Gi_Source_Select_Mask = 0x7c,
	Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
	Gi_Gate_Select_Load_Source_Bit = 0x1000,
	Gi_Or_Gate_Bit = 0x2000,
	Gi_Output_Polarity_Bit = 0x4000,	/* set to invert */
	Gi_Source_Polarity_Bit = 0x8000	/* set to invert */
};

enum Gi_Mode_Bits {
	Gi_Gating_Mode_Mask = 0x3,
	Gi_Gating_Disabled_Bits = 0x0,
	Gi_Level_Gating_Bits = 0x1,
	Gi_Rising_Edge_Gating_Bits = 0x2,
	Gi_Falling_Edge_Gating_Bits = 0x3,
	Gi_Gate_On_Both_Edges_Bit = 0x4,	/* used in conjunction with
						 * rising edge gating mode */
	Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
	Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
	Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
	Gi_Edge_Gate_Starts_Bits = 0x10,
	Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
	Gi_Stop_Mode_Mask = 0x60,
	Gi_Stop_on_Gate_Bits = 0x00,
	Gi_Stop_on_Gate_or_TC_Bits = 0x20,
	Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
	Gi_Load_Source_Select_Bit = 0x80,
	Gi_Output_Mode_Mask = 0x300,
	Gi_Output_TC_Pulse_Bits = 0x100,
	Gi_Output_TC_Toggle_Bits = 0x200,
	Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
	Gi_Counting_Once_Mask = 0xc00,
	Gi_No_Hardware_Disarm_Bits = 0x000,
	Gi_Disarm_at_TC_Bits = 0x400,
	Gi_Disarm_at_Gate_Bits = 0x800,
	Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
	Gi_Loading_On_TC_Bit = 0x1000,
	Gi_Gate_Polarity_Bit = 0x2000,
	Gi_Loading_On_Gate_Bit = 0x4000,
	Gi_Reload_Source_Switching_Bit = 0x8000
};

#define Gi_Second_Gate_Select_Shift 7
/*FIXME: m-series has a second gate subselect bit */
/*FIXME: m-series second gate sources are undocumented (by NI)*/
enum Gi_Second_Gate_Bits {
	Gi_Second_Gate_Mode_Bit = 0x1,
	Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
	Gi_Second_Gate_Polarity_Bit = 0x2000,
	Gi_Second_Gate_Subselect_Bit = 0x4000,	/* m-series only */
	Gi_Source_Subselect_Bit = 0x8000	/* m-series only */
};
static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
{
	return (second_gate_select << Gi_Second_Gate_Select_Shift) &
	    Gi_Second_Gate_Select_Mask;
}

enum Gxx_Status_Bits {
	G0_Save_Bit = 0x1,
	G1_Save_Bit = 0x2,
	G0_Counting_Bit = 0x4,
	G1_Counting_Bit = 0x8,
	G0_Next_Load_Source_Bit = 0x10,
	G1_Next_Load_Source_Bit = 0x20,
	G0_Stale_Data_Bit = 0x40,
	G1_Stale_Data_Bit = 0x80,
	G0_Armed_Bit = 0x100,
	G1_Armed_Bit = 0x200,
	G0_No_Load_Between_Gates_Bit = 0x400,
	G1_No_Load_Between_Gates_Bit = 0x800,
	G0_TC_Error_Bit = 0x1000,
	G1_TC_Error_Bit = 0x2000,
	G0_Gate_Error_Bit = 0x4000,
	G1_Gate_Error_Bit = 0x8000
};
static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Counting_Bit;
	return G0_Counting_Bit;
}

static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Armed_Bit;
	return G0_Armed_Bit;
}

static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
							   counter_index)
{
	if (counter_index % 2)
		return G1_Next_Load_Source_Bit;
	return G0_Next_Load_Source_Bit;
}

static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Stale_Data_Bit;
	return G0_Stale_Data_Bit;
}

static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_TC_Error_Bit;
	return G0_TC_Error_Bit;
}

static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Gate_Error_Bit;
	return G0_Gate_Error_Bit;
}

/* joint reset register bits */
static inline unsigned Gi_Reset_Bit(unsigned counter_index)
{
	return 0x1 << (2 + (counter_index % 2));
}

enum Gxx_Joint_Status2_Bits {
	G0_Output_Bit = 0x1,
	G1_Output_Bit = 0x2,
	G0_HW_Save_Bit = 0x1000,
	G1_HW_Save_Bit = 0x2000,
	G0_Permanent_Stale_Bit = 0x4000,
	G1_Permanent_Stale_Bit = 0x8000
};
static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
								 counter_index)
{
	if (counter_index % 2)
		return G1_Permanent_Stale_Bit;
	return G0_Permanent_Stale_Bit;
}

enum Gi_DMA_Config_Reg_Bits {
	Gi_DMA_Enable_Bit = 0x1,
	Gi_DMA_Write_Bit = 0x2,
	Gi_DMA_Int_Bit = 0x4
};

enum Gi_DMA_Status_Reg_Bits {
	Gi_DMA_Readbank_Bit = 0x2000,
	Gi_DRQ_Error_Bit = 0x4000,
	Gi_DRQ_Status_Bit = 0x8000
};

enum G02_Interrupt_Acknowledge_Bits {
	G0_Gate_Error_Confirm_Bit = 0x20,
	G0_TC_Error_Confirm_Bit = 0x40
};
enum G13_Interrupt_Acknowledge_Bits {
	G1_Gate_Error_Confirm_Bit = 0x2,
	G1_TC_Error_Confirm_Bit = 0x4
};
static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_Gate_Error_Confirm_Bit;
	return G0_Gate_Error_Confirm_Bit;
}

static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
{
	if (counter_index % 2)
		return G1_TC_Error_Confirm_Bit;
	return G0_TC_Error_Confirm_Bit;
}

/* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
enum Gxx_Interrupt_Acknowledge_Bits {
	Gi_TC_Interrupt_Ack_Bit = 0x4000,
	Gi_Gate_Interrupt_Ack_Bit = 0x8000
};

enum Gi_Status_Bits {
	Gi_Gate_Interrupt_Bit = 0x4,
	Gi_TC_Bit = 0x8,
	Gi_Interrupt_Bit = 0x8000
};

enum G02_Interrupt_Enable_Bits {
	G0_TC_Interrupt_Enable_Bit = 0x40,
	G0_Gate_Interrupt_Enable_Bit = 0x100
};
enum G13_Interrupt_Enable_Bits {
	G1_TC_Interrupt_Enable_Bit = 0x200,
	G1_Gate_Interrupt_Enable_Bit = 0x400
};
static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
{
	unsigned bit;

	if (counter_index % 2)
		bit = G1_Gate_Interrupt_Enable_Bit;
	else
		bit = G0_Gate_Interrupt_Enable_Bit;
	return bit;
}

static inline void write_register(struct ni_gpct *counter, unsigned bits,
				  enum ni_gpct_register reg)
{
	BUG_ON(reg >= NITIO_Num_Registers);
	counter->counter_dev->write_register(counter, bits, reg);
}

static inline unsigned read_register(struct ni_gpct *counter,
				     enum ni_gpct_register reg)
{
	BUG_ON(reg >= NITIO_Num_Registers);
	return counter->counter_dev->read_register(counter, reg);
}

static inline int ni_tio_counting_mode_registers_present(const struct
							 ni_gpct_device
							 *counter_dev)
{
	switch (counter_dev->variant) {
	case ni_gpct_variant_e_series:
		return 0;
		break;
	case ni_gpct_variant_m_series:
	case ni_gpct_variant_660x:
		return 1;
		break;
	default:
		BUG();
		break;
	}
	return 0;
}

static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
					     enum ni_gpct_register
					     register_index, unsigned bit_mask,
					     unsigned bit_values,
					     unsigned transient_bit_values)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;
	unsigned long flags;

	BUG_ON(register_index >= NITIO_Num_Registers);
	spin_lock_irqsave(&counter_dev->regs_lock, flags);
	counter_dev->regs[register_index] &= ~bit_mask;
	counter_dev->regs[register_index] |= (bit_values & bit_mask);
	write_register(counter,
		       counter_dev->regs[register_index] | transient_bit_values,
		       register_index);
	mmiowb();
	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
}

/* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
 * twiddled in interrupt context, or whose software copy may be read in
 * interrupt context.
 */
static inline void ni_tio_set_bits(struct ni_gpct *counter,
				   enum ni_gpct_register register_index,
				   unsigned bit_mask, unsigned bit_values)
{
	ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
				  0x0);
}

/* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
whose bits might be modified in interrupt context, or whose software copy
might need to be read in interrupt context.
*/
static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
					    enum ni_gpct_register
					    register_index)
{
	struct ni_gpct_device *counter_dev = counter->counter_dev;
	unsigned long flags;
	unsigned value;

	BUG_ON(register_index >= NITIO_Num_Registers);
	spin_lock_irqsave(&counter_dev->regs_lock, flags);
	value = counter_dev->regs[register_index];
	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
	return value;
}

int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
			unsigned int gate_source);

#endif /* _COMEDI_NI_TIO_INTERNAL_H */
Commit	Line	Data
cb7859a9 FMH	1	/*
	2	drivers/ni_tio_internal.h
	3	Header file for NI general purpose counter support code (ni_tio.c and
	4	ni_tiocmd.c)
	5
	6	COMEDI - Linux Control and Measurement Device Interface
	7
	8	This program is free software; you can redistribute it and/or modify
	9	it under the terms of the GNU General Public License as published by
	10	the Free Software Foundation; either version 2 of the License, or
	11	(at your option) any later version.
	12
	13	This program is distributed in the hope that it will be useful,
	14	but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	GNU General Public License for more details.
cb7859a9 FMH	17	*/
	18
	19	#ifndef _COMEDI_NI_TIO_INTERNAL_H
	20	#define _COMEDI_NI_TIO_INTERNAL_H
	21
	22	#include "ni_tio.h"
	23
	24	static inline enum ni_gpct_register NITIO_Gi_Autoincrement_Reg(unsigned
0a85b6f0	25	counter_index)
cb7859a9 FMH	26	{
	27	switch (counter_index) {
	28	case 0:
	29	return NITIO_G0_Autoincrement_Reg;
	30	break;
	31	case 1:
	32	return NITIO_G1_Autoincrement_Reg;
	33	break;
	34	case 2:
	35	return NITIO_G2_Autoincrement_Reg;
	36	break;
	37	case 3:
	38	return NITIO_G3_Autoincrement_Reg;
	39	break;
	40	default:
	41	BUG();
	42	break;
	43	}
	44	return 0;
	45	}
	46
	47	static inline enum ni_gpct_register NITIO_Gi_Command_Reg(unsigned counter_index)
	48	{
	49	switch (counter_index) {
	50	case 0:
	51	return NITIO_G0_Command_Reg;
	52	break;
	53	case 1:
	54	return NITIO_G1_Command_Reg;
	55	break;
	56	case 2:
	57	return NITIO_G2_Command_Reg;
	58	break;
	59	case 3:
	60	return NITIO_G3_Command_Reg;
	61	break;
	62	default:
	63	BUG();
	64	break;
	65	}
	66	return 0;
	67	}
	68
	69	static inline enum ni_gpct_register NITIO_Gi_Counting_Mode_Reg(unsigned
0a85b6f0	70	counter_index)
cb7859a9 FMH	71	{
	72	switch (counter_index) {
	73	case 0:
	74	return NITIO_G0_Counting_Mode_Reg;
	75	break;
	76	case 1:
	77	return NITIO_G1_Counting_Mode_Reg;
	78	break;
	79	case 2:
	80	return NITIO_G2_Counting_Mode_Reg;
	81	break;
	82	case 3:
	83	return NITIO_G3_Counting_Mode_Reg;
	84	break;
	85	default:
	86	BUG();
	87	break;
	88	}
	89	return 0;
	90	}
	91
	92	static inline enum ni_gpct_register NITIO_Gi_Input_Select_Reg(unsigned
0a85b6f0	93	counter_index)
cb7859a9 FMH	94	{
	95	switch (counter_index) {
	96	case 0:
	97	return NITIO_G0_Input_Select_Reg;
	98	break;
	99	case 1:
	100	return NITIO_G1_Input_Select_Reg;
	101	break;
	102	case 2:
	103	return NITIO_G2_Input_Select_Reg;
	104	break;
	105	case 3:
	106	return NITIO_G3_Input_Select_Reg;
	107	break;
	108	default:
	109	BUG();
	110	break;
	111	}
	112	return 0;
	113	}
	114
	115	static inline enum ni_gpct_register NITIO_Gxx_Joint_Reset_Reg(unsigned
0a85b6f0	116	counter_index)
cb7859a9 FMH	117	{
	118	switch (counter_index) {
	119	case 0:
	120	case 1:
	121	return NITIO_G01_Joint_Reset_Reg;
	122	break;
	123	case 2:
	124	case 3:
	125	return NITIO_G23_Joint_Reset_Reg;
	126	break;
	127	default:
	128	BUG();
	129	break;
	130	}
	131	return 0;
	132	}
	133
	134	static inline enum ni_gpct_register NITIO_Gxx_Joint_Status1_Reg(unsigned
0a85b6f0	135	counter_index)
cb7859a9 FMH	136	{
	137	switch (counter_index) {
	138	case 0:
	139	case 1:
	140	return NITIO_G01_Joint_Status1_Reg;
	141	break;
	142	case 2:
	143	case 3:
	144	return NITIO_G23_Joint_Status1_Reg;
	145	break;
	146	default:
	147	BUG();
	148	break;
	149	}
	150	return 0;
	151	}
	152
	153	static inline enum ni_gpct_register NITIO_Gxx_Joint_Status2_Reg(unsigned
0a85b6f0	154	counter_index)
cb7859a9 FMH	155	{
	156	switch (counter_index) {
	157	case 0:
	158	case 1:
	159	return NITIO_G01_Joint_Status2_Reg;
	160	break;
	161	case 2:
	162	case 3:
	163	return NITIO_G23_Joint_Status2_Reg;
	164	break;
	165	default:
	166	BUG();
	167	break;
	168	}
	169	return 0;
	170	}
	171
	172	static inline enum ni_gpct_register NITIO_Gxx_Status_Reg(unsigned counter_index)
	173	{
	174	switch (counter_index) {
	175	case 0:
	176	case 1:
	177	return NITIO_G01_Status_Reg;
	178	break;
	179	case 2:
	180	case 3:
	181	return NITIO_G23_Status_Reg;
	182	break;
	183	default:
	184	BUG();
	185	break;
	186	}
	187	return 0;
	188	}
	189
	190	static inline enum ni_gpct_register NITIO_Gi_LoadA_Reg(unsigned counter_index)
	191	{
	192	switch (counter_index) {
	193	case 0:
	194	return NITIO_G0_LoadA_Reg;
	195	break;
	196	case 1:
	197	return NITIO_G1_LoadA_Reg;
	198	break;
	199	case 2:
	200	return NITIO_G2_LoadA_Reg;
	201	break;
	202	case 3:
	203	return NITIO_G3_LoadA_Reg;
	204	break;
	205	default:
	206	BUG();
	207	break;
	208	}
	209	return 0;
	210	}
	211
	212	static inline enum ni_gpct_register NITIO_Gi_LoadB_Reg(unsigned counter_index)
	213	{
	214	switch (counter_index) {
	215	case 0:
	216	return NITIO_G0_LoadB_Reg;
	217	break;
	218	case 1:
219	return NITIO_G1_LoadB_Reg;
220	break;
221	case 2:
222	return NITIO_G2_LoadB_Reg;
223	break;
224	case 3:
225	return NITIO_G3_LoadB_Reg;
226	break;
227	default:
228	BUG();
229	break;
230	}
231	return 0;
232	}
233
234	static inline enum ni_gpct_register NITIO_Gi_Mode_Reg(unsigned counter_index)
235	{
236	switch (counter_index) {
237	case 0:
238	return NITIO_G0_Mode_Reg;
239	break;
240	case 1:
241	return NITIO_G1_Mode_Reg;
242	break;
243	case 2:
244	return NITIO_G2_Mode_Reg;
245	break;
246	case 3:
247	return NITIO_G3_Mode_Reg;
248	break;
249	default:
250	BUG();
251	break;
252	}
253	return 0;
254	}
255
256	static inline enum ni_gpct_register NITIO_Gi_SW_Save_Reg(int counter_index)
257	{
258	switch (counter_index) {
259	case 0:
260	return NITIO_G0_SW_Save_Reg;
261	break;
262	case 1:
263	return NITIO_G1_SW_Save_Reg;
264	break;
265	case 2:
266	return NITIO_G2_SW_Save_Reg;
267	break;
268	case 3:
269	return NITIO_G3_SW_Save_Reg;
270	break;
271	default:
272	BUG();
273	break;
274	}
275	return 0;
276	}
277
278	static inline enum ni_gpct_register NITIO_Gi_Second_Gate_Reg(int counter_index)
279	{
280	switch (counter_index) {
281	case 0:
282	return NITIO_G0_Second_Gate_Reg;
283	break;
284	case 1:
285	return NITIO_G1_Second_Gate_Reg;
286	break;
287	case 2:
288	return NITIO_G2_Second_Gate_Reg;
289	break;
290	case 3:
291	return NITIO_G3_Second_Gate_Reg;
292	break;
293	default:
294	BUG();
295	break;
296	}
297	return 0;
298	}
299
300	static inline enum ni_gpct_register NITIO_Gi_DMA_Config_Reg(int counter_index)
301	{
302	switch (counter_index) {
303	case 0:
304	return NITIO_G0_DMA_Config_Reg;
305	break;
306	case 1:
307	return NITIO_G1_DMA_Config_Reg;
308	break;
309	case 2:
310	return NITIO_G2_DMA_Config_Reg;
311	break;
312	case 3:
313	return NITIO_G3_DMA_Config_Reg;
314	break;
315	default:
316	BUG();
317	break;
318	}
319	return 0;
320	}
321
322	static inline enum ni_gpct_register NITIO_Gi_DMA_Status_Reg(int counter_index)
323	{
324	switch (counter_index) {
325	case 0:
326	return NITIO_G0_DMA_Status_Reg;
327	break;
328	case 1:
329	return NITIO_G1_DMA_Status_Reg;
330	break;
331	case 2:
332	return NITIO_G2_DMA_Status_Reg;
333	break;
334	case 3:
335	return NITIO_G3_DMA_Status_Reg;
336	break;
337	default:
338	BUG();
339	break;
340	}
341	return 0;
342	}
343
344	static inline enum ni_gpct_register NITIO_Gi_ABZ_Reg(int counter_index)
345	{
346	switch (counter_index) {
347	case 0:
348	return NITIO_G0_ABZ_Reg;
349	break;
350	case 1:
351	return NITIO_G1_ABZ_Reg;
352	break;
353	default:
354	BUG();
355	break;
356	}
357	return 0;
358	}
359
35c81aaa TK	360	static inline enum ni_gpct_register NITIO_Gi_Interrupt_Acknowledge_Reg(
35c81aaa TK	361	int counter_index)
cb7859a9 FMH	362	{
	363	switch (counter_index) {
	364	case 0:
	365	return NITIO_G0_Interrupt_Acknowledge_Reg;
	366	break;
	367	case 1:
	368	return NITIO_G1_Interrupt_Acknowledge_Reg;
	369	break;
	370	case 2:
	371	return NITIO_G2_Interrupt_Acknowledge_Reg;
	372	break;
	373	case 3:
	374	return NITIO_G3_Interrupt_Acknowledge_Reg;
	375	break;
	376	default:
	377	BUG();
	378	break;
	379	}
	380	return 0;
	381	}
	382
	383	static inline enum ni_gpct_register NITIO_Gi_Status_Reg(int counter_index)
	384	{
	385	switch (counter_index) {
	386	case 0:
	387	return NITIO_G0_Status_Reg;
	388	break;
	389	case 1:
	390	return NITIO_G1_Status_Reg;
	391	break;
	392	case 2:
	393	return NITIO_G2_Status_Reg;
	394	break;
	395	case 3:
	396	return NITIO_G3_Status_Reg;
	397	break;
	398	default:
	399	BUG();
	400	break;
	401	}
	402	return 0;
	403	}
	404
35c81aaa TK	405	static inline enum ni_gpct_register NITIO_Gi_Interrupt_Enable_Reg(
35c81aaa TK	406	int counter_index)
cb7859a9 FMH	407	{
	408	switch (counter_index) {
	409	case 0:
	410	return NITIO_G0_Interrupt_Enable_Reg;
	411	break;
	412	case 1:
	413	return NITIO_G1_Interrupt_Enable_Reg;
	414	break;
	415	case 2:
	416	return NITIO_G2_Interrupt_Enable_Reg;
	417	break;
	418	case 3:
	419	return NITIO_G3_Interrupt_Enable_Reg;
	420	break;
	421	default:
	422	BUG();
	423	break;
	424	}
	425	return 0;
	426	}
	427
	428	enum Gi_Auto_Increment_Reg_Bits {
	429	Gi_Auto_Increment_Mask = 0xff
	430	};
	431
	432	#define Gi_Up_Down_Shift 5
	433	enum Gi_Command_Reg_Bits {
	434	Gi_Arm_Bit = 0x1,
	435	Gi_Save_Trace_Bit = 0x2,
	436	Gi_Load_Bit = 0x4,
	437	Gi_Disarm_Bit = 0x10,
	438	Gi_Up_Down_Mask = 0x3 << Gi_Up_Down_Shift,
	439	Gi_Always_Down_Bits = 0x0 << Gi_Up_Down_Shift,
	440	Gi_Always_Up_Bits = 0x1 << Gi_Up_Down_Shift,
	441	Gi_Up_Down_Hardware_IO_Bits = 0x2 << Gi_Up_Down_Shift,
	442	Gi_Up_Down_Hardware_Gate_Bits = 0x3 << Gi_Up_Down_Shift,
	443	Gi_Write_Switch_Bit = 0x80,
	444	Gi_Synchronize_Gate_Bit = 0x100,
	445	Gi_Little_Big_Endian_Bit = 0x200,
	446	Gi_Bank_Switch_Start_Bit = 0x400,
	447	Gi_Bank_Switch_Mode_Bit = 0x800,
	448	Gi_Bank_Switch_Enable_Bit = 0x1000,
	449	Gi_Arm_Copy_Bit = 0x2000,
	450	Gi_Save_Trace_Copy_Bit = 0x4000,
	451	Gi_Disarm_Copy_Bit = 0x8000
	452	};
	453
	454	#define Gi_Index_Phase_Bitshift 5
	455	#define Gi_HW_Arm_Select_Shift 8
	456	enum Gi_Counting_Mode_Reg_Bits {
	457	Gi_Counting_Mode_Mask = 0x7,
	458	Gi_Counting_Mode_Normal_Bits = 0x0,
	459	Gi_Counting_Mode_QuadratureX1_Bits = 0x1,
	460	Gi_Counting_Mode_QuadratureX2_Bits = 0x2,
	461	Gi_Counting_Mode_QuadratureX4_Bits = 0x3,
	462	Gi_Counting_Mode_Two_Pulse_Bits = 0x4,
	463	Gi_Counting_Mode_Sync_Source_Bits = 0x6,
	464	Gi_Index_Mode_Bit = 0x10,
	465	Gi_Index_Phase_Mask = 0x3 << Gi_Index_Phase_Bitshift,
	466	Gi_Index_Phase_LowA_LowB = 0x0 << Gi_Index_Phase_Bitshift,
	467	Gi_Index_Phase_LowA_HighB = 0x1 << Gi_Index_Phase_Bitshift,
	468	Gi_Index_Phase_HighA_LowB = 0x2 << Gi_Index_Phase_Bitshift,
	469	Gi_Index_Phase_HighA_HighB = 0x3 << Gi_Index_Phase_Bitshift,
35c81aaa TK	470	/* from m-series example code, not documented in 660x register level
	471	* manual */
	472	Gi_HW_Arm_Enable_Bit = 0x80,
	473	/* from m-series example code, not documented in 660x register level
	474	* manual */
	475	Gi_660x_HW_Arm_Select_Mask = 0x7 << Gi_HW_Arm_Select_Shift,
cb7859a9 FMH	476	Gi_660x_Prescale_X8_Bit = 0x1000,
	477	Gi_M_Series_Prescale_X8_Bit = 0x2000,
	478	Gi_M_Series_HW_Arm_Select_Mask = 0x1f << Gi_HW_Arm_Select_Shift,
35c81aaa TK	479	/* must be set for clocks over 40MHz, which includes synchronous
35c81aaa TK	480	* counting and quadrature modes */
cb7859a9 FMH	481	Gi_660x_Alternate_Sync_Bit = 0x2000,
cb7859a9 FMH	482	Gi_M_Series_Alternate_Sync_Bit = 0x4000,
35c81aaa TK	483	/* from m-series example code, not documented in 660x register level
	484	* manual */
	485	Gi_660x_Prescale_X2_Bit = 0x4000,
cb7859a9 FMH	486	Gi_M_Series_Prescale_X2_Bit = 0x8000,
	487	};
	488
	489	#define Gi_Source_Select_Shift 2
	490	#define Gi_Gate_Select_Shift 7
	491	enum Gi_Input_Select_Bits {
2696fb57 BP	492	Gi_Read_Acknowledges_Irq = 0x1, /* not present on 660x */
2696fb57 BP	493	Gi_Write_Acknowledges_Irq = 0x2, /* not present on 660x */
cb7859a9 FMH	494	Gi_Source_Select_Mask = 0x7c,
	495	Gi_Gate_Select_Mask = 0x1f << Gi_Gate_Select_Shift,
	496	Gi_Gate_Select_Load_Source_Bit = 0x1000,
	497	Gi_Or_Gate_Bit = 0x2000,
	498	Gi_Output_Polarity_Bit = 0x4000, /* set to invert */
	499	Gi_Source_Polarity_Bit = 0x8000 /* set to invert */
	500	};
	501
	502	enum Gi_Mode_Bits {
	503	Gi_Gating_Mode_Mask = 0x3,
	504	Gi_Gating_Disabled_Bits = 0x0,
	505	Gi_Level_Gating_Bits = 0x1,
	506	Gi_Rising_Edge_Gating_Bits = 0x2,
	507	Gi_Falling_Edge_Gating_Bits = 0x3,
35c81aaa TK	508	Gi_Gate_On_Both_Edges_Bit = 0x4, /* used in conjunction with
35c81aaa TK	509	* rising edge gating mode */
cb7859a9 FMH	510	Gi_Trigger_Mode_for_Edge_Gate_Mask = 0x18,
	511	Gi_Edge_Gate_Starts_Stops_Bits = 0x0,
	512	Gi_Edge_Gate_Stops_Starts_Bits = 0x8,
	513	Gi_Edge_Gate_Starts_Bits = 0x10,
	514	Gi_Edge_Gate_No_Starts_or_Stops_Bits = 0x18,
	515	Gi_Stop_Mode_Mask = 0x60,
	516	Gi_Stop_on_Gate_Bits = 0x00,
	517	Gi_Stop_on_Gate_or_TC_Bits = 0x20,
	518	Gi_Stop_on_Gate_or_Second_TC_Bits = 0x40,
	519	Gi_Load_Source_Select_Bit = 0x80,
	520	Gi_Output_Mode_Mask = 0x300,
	521	Gi_Output_TC_Pulse_Bits = 0x100,
	522	Gi_Output_TC_Toggle_Bits = 0x200,
	523	Gi_Output_TC_or_Gate_Toggle_Bits = 0x300,
	524	Gi_Counting_Once_Mask = 0xc00,
	525	Gi_No_Hardware_Disarm_Bits = 0x000,
	526	Gi_Disarm_at_TC_Bits = 0x400,
	527	Gi_Disarm_at_Gate_Bits = 0x800,
	528	Gi_Disarm_at_TC_or_Gate_Bits = 0xc00,
	529	Gi_Loading_On_TC_Bit = 0x1000,
	530	Gi_Gate_Polarity_Bit = 0x2000,
	531	Gi_Loading_On_Gate_Bit = 0x4000,
	532	Gi_Reload_Source_Switching_Bit = 0x8000
	533	};
	534
	535	#define Gi_Second_Gate_Select_Shift 7
	536	/FIXME: m-series has a second gate subselect bit /
	537	/FIXME: m-series second gate sources are undocumented (by NI)/
	538	enum Gi_Second_Gate_Bits {
	539	Gi_Second_Gate_Mode_Bit = 0x1,
	540	Gi_Second_Gate_Select_Mask = 0x1f << Gi_Second_Gate_Select_Shift,
	541	Gi_Second_Gate_Polarity_Bit = 0x2000,
	542	Gi_Second_Gate_Subselect_Bit = 0x4000, /* m-series only */
	543	Gi_Source_Subselect_Bit = 0x8000 /* m-series only */
	544	};
	545	static inline unsigned Gi_Second_Gate_Select_Bits(unsigned second_gate_select)
	546	{
	547	return (second_gate_select << Gi_Second_Gate_Select_Shift) &
0a85b6f0	548	Gi_Second_Gate_Select_Mask;
cb7859a9 FMH	549	}
	550
	551	enum Gxx_Status_Bits {
	552	G0_Save_Bit = 0x1,
	553	G1_Save_Bit = 0x2,
	554	G0_Counting_Bit = 0x4,
	555	G1_Counting_Bit = 0x8,
	556	G0_Next_Load_Source_Bit = 0x10,
	557	G1_Next_Load_Source_Bit = 0x20,
	558	G0_Stale_Data_Bit = 0x40,
	559	G1_Stale_Data_Bit = 0x80,
	560	G0_Armed_Bit = 0x100,
	561	G1_Armed_Bit = 0x200,
	562	G0_No_Load_Between_Gates_Bit = 0x400,
	563	G1_No_Load_Between_Gates_Bit = 0x800,
	564	G0_TC_Error_Bit = 0x1000,
	565	G1_TC_Error_Bit = 0x2000,
	566	G0_Gate_Error_Bit = 0x4000,
	567	G1_Gate_Error_Bit = 0x8000
	568	};
	569	static inline enum Gxx_Status_Bits Gi_Counting_Bit(unsigned counter_index)
	570	{
	571	if (counter_index % 2)
	572	return G1_Counting_Bit;
	573	return G0_Counting_Bit;
	574	}
0a85b6f0	575
cb7859a9 FMH	576	static inline enum Gxx_Status_Bits Gi_Armed_Bit(unsigned counter_index)
	577	{
	578	if (counter_index % 2)
	579	return G1_Armed_Bit;
	580	return G0_Armed_Bit;
	581	}
0a85b6f0	582
cb7859a9	583	static inline enum Gxx_Status_Bits Gi_Next_Load_Source_Bit(unsigned
0a85b6f0	584	counter_index)
cb7859a9 FMH	585	{
	586	if (counter_index % 2)
	587	return G1_Next_Load_Source_Bit;
	588	return G0_Next_Load_Source_Bit;
	589	}
0a85b6f0	590
cb7859a9 FMH	591	static inline enum Gxx_Status_Bits Gi_Stale_Data_Bit(unsigned counter_index)
	592	{
	593	if (counter_index % 2)
	594	return G1_Stale_Data_Bit;
	595	return G0_Stale_Data_Bit;
	596	}
0a85b6f0	597
cb7859a9 FMH	598	static inline enum Gxx_Status_Bits Gi_TC_Error_Bit(unsigned counter_index)
	599	{
	600	if (counter_index % 2)
	601	return G1_TC_Error_Bit;
	602	return G0_TC_Error_Bit;
	603	}
0a85b6f0	604
cb7859a9 FMH	605	static inline enum Gxx_Status_Bits Gi_Gate_Error_Bit(unsigned counter_index)
	606	{
	607	if (counter_index % 2)
	608	return G1_Gate_Error_Bit;
	609	return G0_Gate_Error_Bit;
	610	}
	611
	612	/* joint reset register bits */
	613	static inline unsigned Gi_Reset_Bit(unsigned counter_index)
	614	{
	615	return 0x1 << (2 + (counter_index % 2));
	616	}
	617
	618	enum Gxx_Joint_Status2_Bits {
	619	G0_Output_Bit = 0x1,
	620	G1_Output_Bit = 0x2,
	621	G0_HW_Save_Bit = 0x1000,
	622	G1_HW_Save_Bit = 0x2000,
	623	G0_Permanent_Stale_Bit = 0x4000,
	624	G1_Permanent_Stale_Bit = 0x8000
	625	};
	626	static inline enum Gxx_Joint_Status2_Bits Gi_Permanent_Stale_Bit(unsigned
0a85b6f0	627	counter_index)
cb7859a9 FMH	628	{
	629	if (counter_index % 2)
	630	return G1_Permanent_Stale_Bit;
	631	return G0_Permanent_Stale_Bit;
	632	}
	633
	634	enum Gi_DMA_Config_Reg_Bits {
	635	Gi_DMA_Enable_Bit = 0x1,
	636	Gi_DMA_Write_Bit = 0x2,
	637	Gi_DMA_Int_Bit = 0x4
	638	};
	639
	640	enum Gi_DMA_Status_Reg_Bits {
	641	Gi_DMA_Readbank_Bit = 0x2000,
	642	Gi_DRQ_Error_Bit = 0x4000,
	643	Gi_DRQ_Status_Bit = 0x8000
	644	};
	645
	646	enum G02_Interrupt_Acknowledge_Bits {
	647	G0_Gate_Error_Confirm_Bit = 0x20,
	648	G0_TC_Error_Confirm_Bit = 0x40
	649	};
	650	enum G13_Interrupt_Acknowledge_Bits {
	651	G1_Gate_Error_Confirm_Bit = 0x2,
	652	G1_TC_Error_Confirm_Bit = 0x4
	653	};
	654	static inline unsigned Gi_Gate_Error_Confirm_Bit(unsigned counter_index)
	655	{
	656	if (counter_index % 2)
	657	return G1_Gate_Error_Confirm_Bit;
	658	return G0_Gate_Error_Confirm_Bit;
	659	}
0a85b6f0	660
cb7859a9 FMH	661	static inline unsigned Gi_TC_Error_Confirm_Bit(unsigned counter_index)
	662	{
	663	if (counter_index % 2)
	664	return G1_TC_Error_Confirm_Bit;
	665	return G0_TC_Error_Confirm_Bit;
	666	}
	667
2696fb57	668	/* bits that are the same in G0/G2 and G1/G3 interrupt acknowledge registers */
cb7859a9 FMH	669	enum Gxx_Interrupt_Acknowledge_Bits {
	670	Gi_TC_Interrupt_Ack_Bit = 0x4000,
	671	Gi_Gate_Interrupt_Ack_Bit = 0x8000
	672	};
	673
	674	enum Gi_Status_Bits {
	675	Gi_Gate_Interrupt_Bit = 0x4,
	676	Gi_TC_Bit = 0x8,
	677	Gi_Interrupt_Bit = 0x8000
	678	};
	679
	680	enum G02_Interrupt_Enable_Bits {
	681	G0_TC_Interrupt_Enable_Bit = 0x40,
	682	G0_Gate_Interrupt_Enable_Bit = 0x100
	683	};
	684	enum G13_Interrupt_Enable_Bits {
	685	G1_TC_Interrupt_Enable_Bit = 0x200,
	686	G1_Gate_Interrupt_Enable_Bit = 0x400
	687	};
	688	static inline unsigned Gi_Gate_Interrupt_Enable_Bit(unsigned counter_index)
	689	{
	690	unsigned bit;
	691
933df659	692	if (counter_index % 2)
cb7859a9	693	bit = G1_Gate_Interrupt_Enable_Bit;
933df659	694	else
cb7859a9	695	bit = G0_Gate_Interrupt_Enable_Bit;
cb7859a9 FMH	696	return bit;
	697	}
	698
	699	static inline void write_register(struct ni_gpct *counter, unsigned bits,
0a85b6f0	700	enum ni_gpct_register reg)
cb7859a9 FMH	701	{
	702	BUG_ON(reg >= NITIO_Num_Registers);
	703	counter->counter_dev->write_register(counter, bits, reg);
	704	}
	705
	706	static inline unsigned read_register(struct ni_gpct *counter,
0a85b6f0	707	enum ni_gpct_register reg)
cb7859a9 FMH	708	{
	709	BUG_ON(reg >= NITIO_Num_Registers);
	710	return counter->counter_dev->read_register(counter, reg);
	711	}
	712
0a85b6f0 MT	713	static inline int ni_tio_counting_mode_registers_present(const struct
	714	ni_gpct_device
	715	*counter_dev)
cb7859a9 FMH	716	{
	717	switch (counter_dev->variant) {
	718	case ni_gpct_variant_e_series:
	719	return 0;
	720	break;
	721	case ni_gpct_variant_m_series:
	722	case ni_gpct_variant_660x:
	723	return 1;
	724	break;
	725	default:
	726	BUG();
	727	break;
	728	}
	729	return 0;
	730	}
	731
	732	static inline void ni_tio_set_bits_transient(struct ni_gpct *counter,
0a85b6f0 MT	733	enum ni_gpct_register
	734	register_index, unsigned bit_mask,
	735	unsigned bit_values,
	736	unsigned transient_bit_values)
cb7859a9 FMH	737	{
	738	struct ni_gpct_device *counter_dev = counter->counter_dev;
	739	unsigned long flags;
	740
	741	BUG_ON(register_index >= NITIO_Num_Registers);
5f74ea14	742	spin_lock_irqsave(&counter_dev->regs_lock, flags);
cb7859a9 FMH	743	counter_dev->regs[register_index] &= ~bit_mask;
	744	counter_dev->regs[register_index] \|= (bit_values & bit_mask);
	745	write_register(counter,
0a85b6f0 MT	746	counter_dev->regs[register_index] \| transient_bit_values,
0a85b6f0 MT	747	register_index);
cb7859a9	748	mmiowb();
5f74ea14	749	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
cb7859a9 FMH	750	}
	751
	752	/* ni_tio_set_bits( ) is for safely writing to registers whose bits may be
35c81aaa TK	753	* twiddled in interrupt context, or whose software copy may be read in
	754	* interrupt context.
	755	*/
cb7859a9	756	static inline void ni_tio_set_bits(struct ni_gpct *counter,
0a85b6f0 MT	757	enum ni_gpct_register register_index,
0a85b6f0 MT	758	unsigned bit_mask, unsigned bit_values)
cb7859a9 FMH	759	{
cb7859a9 FMH	760	ni_tio_set_bits_transient(counter, register_index, bit_mask, bit_values,
0a85b6f0	761	0x0);
cb7859a9 FMH	762	}
	763
	764	/* ni_tio_get_soft_copy( ) is for safely reading the software copy of a register
	765	whose bits might be modified in interrupt context, or whose software copy
	766	might need to be read in interrupt context.
	767	*/
	768	static inline unsigned ni_tio_get_soft_copy(const struct ni_gpct *counter,
0a85b6f0 MT	769	enum ni_gpct_register
0a85b6f0 MT	770	register_index)
cb7859a9 FMH	771	{
	772	struct ni_gpct_device *counter_dev = counter->counter_dev;
	773	unsigned long flags;
	774	unsigned value;
	775
	776	BUG_ON(register_index >= NITIO_Num_Registers);
5f74ea14	777	spin_lock_irqsave(&counter_dev->regs_lock, flags);
cb7859a9	778	value = counter_dev->regs[register_index];
5f74ea14	779	spin_unlock_irqrestore(&counter_dev->regs_lock, flags);
cb7859a9 FMH	780	return value;
	781	}
	782
	783	int ni_tio_arm(struct ni_gpct *counter, int arm, unsigned start_trigger);
	784	int ni_tio_set_gate_src(struct ni_gpct *counter, unsigned gate_index,
0a85b6f0	785	unsigned int gate_source);
cb7859a9 FMH	786
cb7859a9 FMH	787	#endif /* _COMEDI_NI_TIO_INTERNAL_H */