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staging: comedi: propogate error code from comedi_alloc_subdevices
[deliverable/linux.git] / drivers / staging / comedi / drivers / s626.c
CommitLineData
11e865c1
GP		 1/*
2 comedi/drivers/s626.c
3 Sensoray s626 Comedi driver
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25*/
26
27/*
28Driver: s626
29Description: Sensoray 626 driver
30Devices: [Sensoray] 626 (s626)
31Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32Updated: Fri, 15 Feb 2008 10:28:42 +0000
33Status: experimental
34
35Configuration options:
36 [0] - PCI bus of device (optional)
37 [1] - PCI slot of device (optional)
38 If bus/slot is not specified, the first supported
39 PCI device found will be used.
40
41INSN_CONFIG instructions:
42 analog input:
43 none
44
45 analog output:
46 none
47
48 digital channel:
49 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
50 supported configuration options:
51 INSN_CONFIG_DIO_QUERY
52 COMEDI_INPUT
53 COMEDI_OUTPUT
54
55 encoder:
56 Every channel must be configured before reading.
57
58 Example code
59
60 insn.insn=INSN_CONFIG; //configuration instruction
61 insn.n=1; //number of operation (must be 1)
62 insn.data=&initialvalue; //initial value loaded into encoder
add74595 63 //during configuration
11e865c1
GP		 64 insn.subdev=5; //encoder subdevice
65 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
add74595 66 //to configure
11e865c1
GP		 67
68 comedi_do_insn(cf,&insn); //executing configuration
69*/
70
25436dc9 71#include <linux/interrupt.h>
11e865c1
GP		 72#include <linux/kernel.h>
73#include <linux/types.h>
74
75#include "../comedidev.h"
76
11e865c1
GP		 77#include "comedi_fc.h"
78#include "s626.h"
79
e17b8e48
GS		 80#define PCI_VENDOR_ID_S626 0x1131
81#define PCI_DEVICE_ID_S626 0x7146
82#define PCI_SUBVENDOR_ID_S626 0x6000
83#define PCI_SUBDEVICE_ID_S626 0x0272
84
eb5e029e 85struct s626_board {
11e865c1 86 const char *name;
e17b8e48
GS		 87 int vendor_id;
88 int device_id;
89 int subvendor_id;
90 int subdevice_id;
11e865c1
GP		 91 int ai_chans;
92 int ai_bits;
93 int ao_chans;
94 int ao_bits;
95 int dio_chans;
96 int dio_banks;
97 int enc_chans;
eb5e029e 98};
11e865c1 99
eb5e029e 100static const struct s626_board s626_boards[] = {
11e865c1 101 {
0a85b6f0 102 .name = "s626",
e17b8e48
GS		 103 .vendor_id = PCI_VENDOR_ID_S626,
104 .device_id = PCI_DEVICE_ID_S626,
105 .subvendor_id = PCI_SUBVENDOR_ID_S626,
106 .subdevice_id = PCI_SUBDEVICE_ID_S626,
0a85b6f0
MT		 107 .ai_chans = S626_ADC_CHANNELS,
108 .ai_bits = 14,
109 .ao_chans = S626_DAC_CHANNELS,
110 .ao_bits = 13,
111 .dio_chans = S626_DIO_CHANNELS,
112 .dio_banks = S626_DIO_BANKS,
113 .enc_chans = S626_ENCODER_CHANNELS,
114 }
11e865c1
GP		 115};
116
eb5e029e 117#define thisboard ((const struct s626_board *)dev->board_ptr)
11e865c1 118
eb5e029e 119struct s626_private {
11e865c1 120 struct pci_dev *pdev;
42caa910 121 void __iomem *base_addr;
11e865c1
GP		 122 int got_regions;
123 short allocatedBuf;
b6c77757 124 uint8_t ai_cmd_running; /* ai_cmd is running */
25985edc 125 uint8_t ai_continous; /* continous acquisition */
9d220c6b 126 int ai_sample_count; /* number of samples to acquire */
b6c77757
BP		 127 unsigned int ai_sample_timer;
128 /* time between samples in units of the timer */
129 int ai_convert_count; /* conversion counter */
130 unsigned int ai_convert_timer;
131 /* time between conversion in units of the timer */
132 uint16_t CounterIntEnabs;
133 /* Counter interrupt enable mask for MISC2 register. */
134 uint8_t AdcItems; /* Number of items in ADC poll list. */
0a85b6f0 135 struct bufferDMA RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */
4753d235 136 struct bufferDMA ANABuf;
b6c77757
BP		 137 /* DMA buffer used to receive ADC data and hold DAC data. */
138 uint32_t *pDacWBuf;
139 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */
140 uint16_t Dacpol; /* Image of DAC polarity register. */
141 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
142 uint16_t ChargeEnabled; /* Image of MISC2 Battery */
143 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
144 uint16_t WDInterval; /* Image of MISC2 watchdog interval control bits. */
145 uint32_t I2CAdrs;
146 /* I2C device address for onboard EEPROM (board rev dependent). */
147 /* short I2Cards; */
790c5541 148 unsigned int ao_readback[S626_DAC_CHANNELS];
eb5e029e 149};
11e865c1 150
eb5e029e 151struct dio_private {
11e865c1
GP		 152 uint16_t RDDIn;
153 uint16_t WRDOut;
154 uint16_t RDEdgSel;
155 uint16_t WREdgSel;
156 uint16_t RDCapSel;
157 uint16_t WRCapSel;
158 uint16_t RDCapFlg;
159 uint16_t RDIntSel;
160 uint16_t WRIntSel;
eb5e029e 161};
11e865c1 162
eb5e029e 163static struct dio_private dio_private_A = {
b4918808
BP		 164 .RDDIn = LP_RDDINA,
165 .WRDOut = LP_WRDOUTA,
166 .RDEdgSel = LP_RDEDGSELA,
167 .WREdgSel = LP_WREDGSELA,
168 .RDCapSel = LP_RDCAPSELA,
169 .WRCapSel = LP_WRCAPSELA,
170 .RDCapFlg = LP_RDCAPFLGA,
171 .RDIntSel = LP_RDINTSELA,
172 .WRIntSel = LP_WRINTSELA,
11e865c1
GP		 173};
174
eb5e029e 175static struct dio_private dio_private_B = {
b4918808
BP		 176 .RDDIn = LP_RDDINB,
177 .WRDOut = LP_WRDOUTB,
178 .RDEdgSel = LP_RDEDGSELB,
179 .WREdgSel = LP_WREDGSELB,
180 .RDCapSel = LP_RDCAPSELB,
181 .WRCapSel = LP_WRCAPSELB,
182 .RDCapFlg = LP_RDCAPFLGB,
183 .RDIntSel = LP_RDINTSELB,
184 .WRIntSel = LP_WRINTSELB,
11e865c1
GP		 185};
186
eb5e029e 187static struct dio_private dio_private_C = {
b4918808
BP		 188 .RDDIn = LP_RDDINC,
189 .WRDOut = LP_WRDOUTC,
190 .RDEdgSel = LP_RDEDGSELC,
191 .WREdgSel = LP_WREDGSELC,
192 .RDCapSel = LP_RDCAPSELC,
193 .WRCapSel = LP_WRCAPSELC,
194 .RDCapFlg = LP_RDCAPFLGC,
195 .RDIntSel = LP_RDINTSELC,
196 .WRIntSel = LP_WRINTSELC,
11e865c1
GP		 197};
198
199/* to group dio devices (48 bits mask and data are not allowed ???)
eb5e029e 200static struct dio_private *dio_private_word[]={
11e865c1
GP		 201 &dio_private_A,
202 &dio_private_B,
203 &dio_private_C,
204};
205*/
206
eb5e029e
BP		 207#define devpriv ((struct s626_private *)dev->private)
208#define diopriv ((struct dio_private *)s->private)
11e865c1 209
b6c77757 210/* ioctl routines */
0a85b6f0
MT		 211static int s626_ai_insn_config(struct comedi_device *dev,
212 struct comedi_subdevice *s,
213 struct comedi_insn *insn, unsigned int *data);
90035c08 214/* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data); */
0a85b6f0
MT		 215static int s626_ai_insn_read(struct comedi_device *dev,
216 struct comedi_subdevice *s,
217 struct comedi_insn *insn, unsigned int *data);
34c43922 218static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s);
0a85b6f0
MT		 219static int s626_ai_cmdtest(struct comedi_device *dev,
220 struct comedi_subdevice *s, struct comedi_cmd *cmd);
221static int s626_ai_cancel(struct comedi_device *dev,
222 struct comedi_subdevice *s);
34c43922 223static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 224 struct comedi_insn *insn, unsigned int *data);
34c43922 225static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0
MT		 226 struct comedi_insn *insn, unsigned int *data);
227static int s626_dio_insn_bits(struct comedi_device *dev,
228 struct comedi_subdevice *s,
229 struct comedi_insn *insn, unsigned int *data);
230static int s626_dio_insn_config(struct comedi_device *dev,
231 struct comedi_subdevice *s,
232 struct comedi_insn *insn, unsigned int *data);
71b5f4f1
BP		 233static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan);
234static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int gruop,
0a85b6f0 235 unsigned int mask);
71b5f4f1 236static int s626_dio_clear_irq(struct comedi_device *dev);
0a85b6f0
MT		 237static int s626_enc_insn_config(struct comedi_device *dev,
238 struct comedi_subdevice *s,
239 struct comedi_insn *insn, unsigned int *data);
240static int s626_enc_insn_read(struct comedi_device *dev,
241 struct comedi_subdevice *s,
242 struct comedi_insn *insn, unsigned int *data);
243static int s626_enc_insn_write(struct comedi_device *dev,
244 struct comedi_subdevice *s,
245 struct comedi_insn *insn, unsigned int *data);
11e865c1 246static int s626_ns_to_timer(int *nanosec, int round_mode);
add74595 247static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd);
0a85b6f0
MT		 248static int s626_ai_inttrig(struct comedi_device *dev,
249 struct comedi_subdevice *s, unsigned int trignum);
70265d24 250static irqreturn_t s626_irq_handler(int irq, void *d);
790c5541 251static unsigned int s626_ai_reg_to_uint(int data);
34c43922 252/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data); */
11e865c1 253
b6c77757 254/* end ioctl routines */
11e865c1 255
b6c77757 256/* internal routines */
71b5f4f1 257static void s626_dio_init(struct comedi_device *dev);
0a85b6f0 258static void ResetADC(struct comedi_device *dev, uint8_t * ppl);
71b5f4f1
BP		 259static void LoadTrimDACs(struct comedi_device *dev);
260static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
0a85b6f0 261 uint8_t DacData);
71b5f4f1
BP		 262static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr);
263static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val);
264static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata);
265static void SendDAC(struct comedi_device *dev, uint32_t val);
266static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage);
267static void DEBItransfer(struct comedi_device *dev);
268static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr);
269static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata);
270static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
0a85b6f0
MT		 271 uint16_t wdata);
272static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
273 size_t bsize);
11e865c1 274
b6c77757 275/* COUNTER OBJECT ------------------------------------------------ */
eb5e029e 276struct enc_private {
b6c77757 277 /* Pointers to functions that differ for A and B counters: */
add74595
JS		 278 uint16_t(*GetEnable) (struct comedi_device *dev, struct enc_private *); /* Return clock enable. */
279 uint16_t(*GetIntSrc) (struct comedi_device *dev, struct enc_private *); /* Return interrupt source. */
280 uint16_t(*GetLoadTrig) (struct comedi_device *dev, struct enc_private *); /* Return preload trigger source. */
281 uint16_t(*GetMode) (struct comedi_device *dev, struct enc_private *); /* Return standardized operating mode. */
282 void (*PulseIndex) (struct comedi_device *dev, struct enc_private *); /* Generate soft index strobe. */
283 void (*SetEnable) (struct comedi_device *dev, struct enc_private *, uint16_t enab); /* Program clock enable. */
284 void (*SetIntSrc) (struct comedi_device *dev, struct enc_private *, uint16_t IntSource); /* Program interrupt source. */
285 void (*SetLoadTrig) (struct comedi_device *dev, struct enc_private *, uint16_t Trig); /* Program preload trigger source. */
286 void (*SetMode) (struct comedi_device *dev, struct enc_private *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
287 void (*ResetCapFlags) (struct comedi_device *dev, struct enc_private *); /* Reset event capture flags. */
b6c77757
BP		 288
289 uint16_t MyCRA; /* Address of CRA register. */
290 uint16_t MyCRB; /* Address of CRB register. */
291 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */
292 /* register. */
293 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */
eb5e029e 294};
11e865c1 295
eb5e029e 296#define encpriv ((struct enc_private *)(dev->subdevices+5)->private)
11e865c1 297
b6c77757 298/* counters routines */
0a85b6f0
MT		 299static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
300 int tick);
71b5f4f1
BP		 301static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k);
302static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k);
303static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k);
304static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k);
305static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k);
0a85b6f0
MT		 306static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
307 uint16_t Setup, uint16_t DisableIntSrc);
308static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
309 uint16_t Setup, uint16_t DisableIntSrc);
310static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
311 uint16_t enab);
312static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
313 uint16_t enab);
71b5f4f1
BP		 314static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k);
315static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k);
316static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 317 uint16_t value);
71b5f4f1 318/* static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k ); */
0a85b6f0
MT		 319static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
320 uint16_t Trig);
321static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
322 uint16_t Trig);
71b5f4f1
BP		 323static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k);
324static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k);
325static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 326 uint16_t IntSource);
71b5f4f1 327static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 328 uint16_t IntSource);
71b5f4f1
BP		 329static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k);
330static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k);
331/* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) ; */
332/* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) ; */
333/* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ); */
334/* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) ; */
335/* static void SetIndexSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ); */
336/* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ); */
337/* static void SetIndexSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ); */
338/* static uint16_t GetIndexSrc( struct comedi_device *dev,struct enc_private *k ); */
339static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k);
340static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k);
0a85b6f0
MT		 341static void Preload(struct comedi_device *dev, struct enc_private *k,
342 uint32_t value);
71b5f4f1 343static void CountersInit(struct comedi_device *dev);
b6c77757 344/* end internal routines */
11e865c1 345
b6c77757 346/* Counter objects constructor. */
11e865c1 347
b6c77757 348/* Counter overflow/index event flag masks for RDMISC2. */
6a98d36e
BP		 349#define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
350#define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
11e865c1
GP		 351#define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }
352
b6c77757
BP		 353/* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */
354/* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
11e865c1 355
eb5e029e
BP		 356/* struct enc_private; */
357static struct enc_private enc_private_data[] = {
11e865c1 358 {
0a85b6f0
MT		 359 .GetEnable = GetEnable_A,
360 .GetIntSrc = GetIntSrc_A,
361 .GetLoadTrig = GetLoadTrig_A,
362 .GetMode = GetMode_A,
363 .PulseIndex = PulseIndex_A,
364 .SetEnable = SetEnable_A,
365 .SetIntSrc = SetIntSrc_A,
366 .SetLoadTrig = SetLoadTrig_A,
367 .SetMode = SetMode_A,
368 .ResetCapFlags = ResetCapFlags_A,
369 .MyCRA = LP_CR0A,
370 .MyCRB = LP_CR0B,
371 .MyLatchLsw = LP_CNTR0ALSW,
372 .MyEventBits = EVBITS(0),
373 },
11e865c1 374 {
0a85b6f0
MT		 375 .GetEnable = GetEnable_A,
376 .GetIntSrc = GetIntSrc_A,
377 .GetLoadTrig = GetLoadTrig_A,
378 .GetMode = GetMode_A,
379 .PulseIndex = PulseIndex_A,
380 .SetEnable = SetEnable_A,
381 .SetIntSrc = SetIntSrc_A,
382 .SetLoadTrig = SetLoadTrig_A,
383 .SetMode = SetMode_A,
384 .ResetCapFlags = ResetCapFlags_A,
385 .MyCRA = LP_CR1A,
386 .MyCRB = LP_CR1B,
387 .MyLatchLsw = LP_CNTR1ALSW,
388 .MyEventBits = EVBITS(1),
389 },
11e865c1 390 {
0a85b6f0
MT		 391 .GetEnable = GetEnable_A,
392 .GetIntSrc = GetIntSrc_A,
393 .GetLoadTrig = GetLoadTrig_A,
394 .GetMode = GetMode_A,
395 .PulseIndex = PulseIndex_A,
396 .SetEnable = SetEnable_A,
397 .SetIntSrc = SetIntSrc_A,
398 .SetLoadTrig = SetLoadTrig_A,
399 .SetMode = SetMode_A,
400 .ResetCapFlags = ResetCapFlags_A,
401 .MyCRA = LP_CR2A,
402 .MyCRB = LP_CR2B,
403 .MyLatchLsw = LP_CNTR2ALSW,
404 .MyEventBits = EVBITS(2),
405 },
11e865c1 406 {
0a85b6f0
MT		 407 .GetEnable = GetEnable_B,
408 .GetIntSrc = GetIntSrc_B,
409 .GetLoadTrig = GetLoadTrig_B,
410 .GetMode = GetMode_B,
411 .PulseIndex = PulseIndex_B,
412 .SetEnable = SetEnable_B,
413 .SetIntSrc = SetIntSrc_B,
414 .SetLoadTrig = SetLoadTrig_B,
415 .SetMode = SetMode_B,
416 .ResetCapFlags = ResetCapFlags_B,
417 .MyCRA = LP_CR0A,
418 .MyCRB = LP_CR0B,
419 .MyLatchLsw = LP_CNTR0BLSW,
420 .MyEventBits = EVBITS(3),
421 },
11e865c1 422 {
0a85b6f0
MT		 423 .GetEnable = GetEnable_B,
424 .GetIntSrc = GetIntSrc_B,
425 .GetLoadTrig = GetLoadTrig_B,
426 .GetMode = GetMode_B,
427 .PulseIndex = PulseIndex_B,
428 .SetEnable = SetEnable_B,
429 .SetIntSrc = SetIntSrc_B,
430 .SetLoadTrig = SetLoadTrig_B,
431 .SetMode = SetMode_B,
432 .ResetCapFlags = ResetCapFlags_B,
433 .MyCRA = LP_CR1A,
434 .MyCRB = LP_CR1B,
435 .MyLatchLsw = LP_CNTR1BLSW,
436 .MyEventBits = EVBITS(4),
437 },
11e865c1 438 {
0a85b6f0
MT		 439 .GetEnable = GetEnable_B,
440 .GetIntSrc = GetIntSrc_B,
441 .GetLoadTrig = GetLoadTrig_B,
442 .GetMode = GetMode_B,
443 .PulseIndex = PulseIndex_B,
444 .SetEnable = SetEnable_B,
445 .SetIntSrc = SetIntSrc_B,
446 .SetLoadTrig = SetLoadTrig_B,
447 .SetMode = SetMode_B,
448 .ResetCapFlags = ResetCapFlags_B,
449 .MyCRA = LP_CR2A,
450 .MyCRB = LP_CR2B,
451 .MyLatchLsw = LP_CNTR2BLSW,
452 .MyEventBits = EVBITS(5),
453 },
11e865c1
GP		 454};
455
b6c77757
BP		 456/* enab/disable a function or test status bit(s) that are accessed */
457/* through Main Control Registers 1 or 2. */
6a98d36e 458#define MC_ENABLE(REGADRS, CTRLWORD) writel(((uint32_t)(CTRLWORD) << 16) | (uint32_t)(CTRLWORD), devpriv->base_addr+(REGADRS))
11e865c1 459
6a98d36e 460#define MC_DISABLE(REGADRS, CTRLWORD) writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS))
11e865c1 461
6a98d36e 462#define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
11e865c1
GP		 463
464/* #define WR7146(REGARDS,CTRLWORD)
465 writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
8086fff8 466#define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
11e865c1
GP		 467
468/* #define RR7146(REGARDS)
469 readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
470#define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
471
6a98d36e 472#define BUGFIX_STREG(REGADRS) (REGADRS - 4)
11e865c1 473
b6c77757 474/* Write a time slot control record to TSL2. */
6a98d36e
BP		 475#define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
476#define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL))
11e865c1 477
b6c77757 478/* Code macros used for constructing I2C command bytes. */
6a98d36e
BP		 479#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
480#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
481#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
11e865c1 482
9ced1de6 483static const struct comedi_lrange s626_range_table = { 2, {
0a85b6f0
MT		 484 RANGE(-5, 5),
485 RANGE(-10, 10),
486 }
11e865c1
GP		 487};
488
0707bb04 489static int s626_attach(struct comedi_device *dev, struct comedi_devconfig *it)
11e865c1
GP		 490{
491/* uint8_t PollList; */
492/* uint16_t AdcData; */
493/* uint16_t StartVal; */
494/* uint16_t index; */
495/* unsigned int data[16]; */
496 int result;
497 int i;
498 int ret;
499 resource_size_t resourceStart;
500 dma_addr_t appdma;
34c43922 501 struct comedi_subdevice *s;
8231eb56 502 struct pci_dev *pdev = NULL;
11e865c1 503
eb5e029e 504 if (alloc_private(dev, sizeof(struct s626_private)) < 0)
11e865c1
GP		 505 return -ENOMEM;
506
e17b8e48 507 for (i = 0; i < ARRAY_SIZE(s626_boards) && !pdev; i++) {
8231eb56 508 do {
e17b8e48
GS		 509 pdev = pci_get_subsys(s626_boards[i].vendor_id,
510 s626_boards[i].device_id,
511 s626_boards[i].subvendor_id,
512 s626_boards[i].subdevice_id,
0a85b6f0 513 pdev);
8231eb56
HRK		 514
515 if ((it->options[0] || it->options[1]) && pdev) {
11e865c1 516 /* matches requested bus/slot */
8231eb56
HRK		 517 if (pdev->bus->number == it->options[0] &&
518 PCI_SLOT(pdev->devfn) == it->options[1])
519 break;
520 } else
11e865c1 521 break;
8231eb56 522 } while (1);
11e865c1
GP		 523 }
524 devpriv->pdev = pdev;
525
526 if (pdev == NULL) {
daca497d 527 printk(KERN_ERR "s626_attach: Board not present!!!\n");
11e865c1
GP		 528 return -ENODEV;
529 }
530
197c82bf
BP		 531 result = comedi_pci_enable(pdev, "s626");
532 if (result < 0) {
daca497d 533 printk(KERN_ERR "s626_attach: comedi_pci_enable fails\n");
11e865c1
GP		 534 return -ENODEV;
535 }
536 devpriv->got_regions = 1;
537
538 resourceStart = pci_resource_start(devpriv->pdev, 0);
539
540 devpriv->base_addr = ioremap(resourceStart, SIZEOF_ADDRESS_SPACE);
541 if (devpriv->base_addr == NULL) {
daca497d 542 printk(KERN_ERR "s626_attach: IOREMAP failed\n");
11e865c1
GP		 543 return -ENODEV;
544 }
545
546 if (devpriv->base_addr) {
b6c77757 547 /* disable master interrupt */
11e865c1
GP		 548 writel(0, devpriv->base_addr + P_IER);
549
b6c77757 550 /* soft reset */
11e865c1
GP		 551 writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1);
552
b6c77757 553 /* DMA FIXME DMA// */
11e865c1
GP		 554 DEBUG("s626_attach: DMA ALLOCATION\n");
555
b6c77757 556 /* adc buffer allocation */
11e865c1
GP		 557 devpriv->allocatedBuf = 0;
558
197c82bf 559 devpriv->ANABuf.LogicalBase =
0a85b6f0 560 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
197c82bf
BP		 561
562 if (devpriv->ANABuf.LogicalBase == NULL) {
daca497d 563 printk(KERN_ERR "s626_attach: DMA Memory mapping error\n");
11e865c1
GP		 564 return -ENOMEM;
565 }
566
567 devpriv->ANABuf.PhysicalBase = appdma;
568
0a85b6f0
MT		 569 DEBUG
570 ("s626_attach: AllocDMAB ADC Logical=%p, bsize=%d, Physical=0x%x\n",
571 devpriv->ANABuf.LogicalBase, DMABUF_SIZE,
572 (uint32_t) devpriv->ANABuf.PhysicalBase);
11e865c1
GP		 573
574 devpriv->allocatedBuf++;
575
197c82bf 576 devpriv->RPSBuf.LogicalBase =
0a85b6f0 577 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
197c82bf
BP		 578
579 if (devpriv->RPSBuf.LogicalBase == NULL) {
daca497d 580 printk(KERN_ERR "s626_attach: DMA Memory mapping error\n");
11e865c1
GP		 581 return -ENOMEM;
582 }
583
584 devpriv->RPSBuf.PhysicalBase = appdma;
585
0a85b6f0
MT		 586 DEBUG
587 ("s626_attach: AllocDMAB RPS Logical=%p, bsize=%d, Physical=0x%x\n",
588 devpriv->RPSBuf.LogicalBase, DMABUF_SIZE,
589 (uint32_t) devpriv->RPSBuf.PhysicalBase);
11e865c1
GP		 590
591 devpriv->allocatedBuf++;
592
593 }
594
595 dev->board_ptr = s626_boards;
596 dev->board_name = thisboard->name;
597
8b6c5694
HS		 598 ret = comedi_alloc_subdevices(dev, 6);
599 if (ret)
600 return ret;
11e865c1
GP		 601
602 dev->iobase = (unsigned long)devpriv->base_addr;
603 dev->irq = devpriv->pdev->irq;
604
b6c77757 605 /* set up interrupt handler */
11e865c1 606 if (dev->irq == 0) {
daca497d 607 printk(KERN_ERR " unknown irq (bad)\n");
11e865c1 608 } else {
5f74ea14
GKH		 609 ret = request_irq(dev->irq, s626_irq_handler, IRQF_SHARED,
610 "s626", dev);
197c82bf
BP		 611
612 if (ret < 0) {
daca497d 613 printk(KERN_ERR " irq not available\n");
11e865c1
GP		 614 dev->irq = 0;
615 }
616 }
617
daca497d 618 DEBUG("s626_attach: -- it opts %d,%d --\n",
0a85b6f0 619 it->options[0], it->options[1]);
11e865c1
GP		 620
621 s = dev->subdevices + 0;
622 /* analog input subdevice */
623 dev->read_subdev = s;
624 /* we support single-ended (ground) and differential */
625 s->type = COMEDI_SUBD_AI;
626 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
627 s->n_chan = thisboard->ai_chans;
628 s->maxdata = (0xffff >> 2);
629 s->range_table = &s626_range_table;
630 s->len_chanlist = thisboard->ai_chans; /* This is the maximum chanlist
631 length that the board can
632 handle */
633 s->insn_config = s626_ai_insn_config;
634 s->insn_read = s626_ai_insn_read;
635 s->do_cmd = s626_ai_cmd;
636 s->do_cmdtest = s626_ai_cmdtest;
637 s->cancel = s626_ai_cancel;
638
639 s = dev->subdevices + 1;
640 /* analog output subdevice */
641 s->type = COMEDI_SUBD_AO;
642 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
643 s->n_chan = thisboard->ao_chans;
644 s->maxdata = (0x3fff);
645 s->range_table = &range_bipolar10;
646 s->insn_write = s626_ao_winsn;
647 s->insn_read = s626_ao_rinsn;
648
649 s = dev->subdevices + 2;
650 /* digital I/O subdevice */
651 s->type = COMEDI_SUBD_DIO;
652 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
653 s->n_chan = S626_DIO_CHANNELS;
654 s->maxdata = 1;
655 s->io_bits = 0xffff;
656 s->private = &dio_private_A;
657 s->range_table = &range_digital;
658 s->insn_config = s626_dio_insn_config;
659 s->insn_bits = s626_dio_insn_bits;
660
661 s = dev->subdevices + 3;
662 /* digital I/O subdevice */
663 s->type = COMEDI_SUBD_DIO;
664 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
665 s->n_chan = 16;
666 s->maxdata = 1;
667 s->io_bits = 0xffff;
668 s->private = &dio_private_B;
669 s->range_table = &range_digital;
670 s->insn_config = s626_dio_insn_config;
671 s->insn_bits = s626_dio_insn_bits;
672
673 s = dev->subdevices + 4;
674 /* digital I/O subdevice */
675 s->type = COMEDI_SUBD_DIO;
676 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
677 s->n_chan = 16;
678 s->maxdata = 1;
679 s->io_bits = 0xffff;
680 s->private = &dio_private_C;
681 s->range_table = &range_digital;
682 s->insn_config = s626_dio_insn_config;
683 s->insn_bits = s626_dio_insn_bits;
684
685 s = dev->subdevices + 5;
686 /* encoder (counter) subdevice */
687 s->type = COMEDI_SUBD_COUNTER;
688 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
689 s->n_chan = thisboard->enc_chans;
690 s->private = enc_private_data;
691 s->insn_config = s626_enc_insn_config;
692 s->insn_read = s626_enc_insn_read;
693 s->insn_write = s626_enc_insn_write;
694 s->maxdata = 0xffffff;
695 s->range_table = &range_unknown;
696
b6c77757 697 /* stop ai_command */
11e865c1
GP		 698 devpriv->ai_cmd_running = 0;
699
700 if (devpriv->base_addr && (devpriv->allocatedBuf == 2)) {
701 dma_addr_t pPhysBuf;
702 uint16_t chan;
703
b6c77757 704 /* enab DEBI and audio pins, enable I2C interface. */
11e865c1 705 MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
b6c77757
BP		 706 /* Configure DEBI operating mode. */
707 WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
0a85b6f0
MT		 708 /* bits wide. */
709 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT)
710
711 /* Declare DEBI */
712 /* transfer timeout */
713 /* interval. */
714 |DEBI_SWAP /* Set up byte lane */
715 /* steering. */
716 | DEBI_CFG_INTEL); /* Intel-compatible */
b6c77757
BP		 717 /* local bus (DEBI */
718 /* never times out). */
11e865c1 719 DEBUG("s626_attach: %d debi init -- %d\n",
0a85b6f0
MT		 720 DEBI_CFG_SLAVE16 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
721 DEBI_SWAP | DEBI_CFG_INTEL,
722 DEBI_CFG_INTEL | DEBI_CFG_TOQ | DEBI_CFG_INCQ |
723 DEBI_CFG_16Q);
11e865c1 724
b6c77757
BP		 725 /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
726 /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
11e865c1 727
b6c77757
BP		 728 /* Paging is disabled. */
729 WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
11e865c1 730
b6c77757 731 /* Init GPIO so that ADC Start* is negated. */
11e865c1
GP		 732 WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
733
0a85b6f0
MT		 734 /* IsBoardRevA is a boolean that indicates whether the board is RevA.
735 *
736 * VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
737 * EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
738 * is used to access the onboard serial EEPROM. The EEPROM's I2C
739 * DeviceAddress is hardwired to a value that is dependent on the
740 * 626 board revision. On all board revisions, the EEPROM stores
741 * TrimDAC calibration constants for analog I/O. On RevB and
742 * higher boards, the DeviceAddress is hardwired to 0 to enable
743 * the EEPROM to also store the PCI SubVendorID and SubDeviceID;
744 * this is the address at which the SAA7146 expects a
745 * configuration EEPROM to reside. On RevA boards, the EEPROM
746 * device address, which is hardwired to 4, prevents the SAA7146
747 * from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
748 * default values, instead.
749 */
b6c77757
BP		 750
751 /* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
752 /* DeviceType (0xA0) */
753 /* and DeviceAddress<<1. */
754
755 devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */
756 /* eeprom(revb) */
757
758 /* Issue an I2C ABORT command to halt any I2C operation in */
759 /* progress and reset BUSY flag. */
760 WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
761 /* Write I2C control: abort any I2C activity. */
762 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
763 /* Invoke command upload */
add74595 764 while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
ae6eb75c 765 ;
b6c77757
BP		 766 /* and wait for upload to complete. */
767
768 /* Per SAA7146 data sheet, write to STATUS reg twice to
769 * reset all I2C error flags. */
11e865c1 770 for (i = 0; i < 2; i++) {
b6c77757
BP		 771 WR7146(P_I2CSTAT, I2C_CLKSEL);
772 /* Write I2C control: reset error flags. */
773 MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
add74595 774 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
ae6eb75c 775 ;
b6c77757 776 /* and wait for upload to complete. */
11e865c1
GP		 777 }
778
b6c77757
BP		 779 /* Init audio interface functional attributes: set DAC/ADC
780 * serial clock rates, invert DAC serial clock so that
781 * DAC data setup times are satisfied, enable DAC serial
782 * clock out.
783 */
784
11e865c1
GP		 785 WR7146(P_ACON2, ACON2_INIT);
786
b6c77757
BP		 787 /* Set up TSL1 slot list, which is used to control the
788 * accumulation of ADC data: RSD1 = shift data in on SD1.
789 * SIB_A1 = store data uint8_t at next available location in
790 * FB BUFFER1 register. */
791 WR7146(P_TSL1, RSD1 | SIB_A1);
792 /* Fetch ADC high data uint8_t. */
793 WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
794 /* Fetch ADC low data uint8_t; end of TSL1. */
795
796 /* enab TSL1 slot list so that it executes all the time. */
11e865c1
GP		 797 WR7146(P_ACON1, ACON1_ADCSTART);
798
b6c77757 799 /* Initialize RPS registers used for ADC. */
11e865c1 800
b6c77757 801 /* Physical start of RPS program. */
11e865c1
GP		 802 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
803
b6c77757
BP		 804 WR7146(P_RPSPAGE1, 0);
805 /* RPS program performs no explicit mem writes. */
806 WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
11e865c1 807
b6c77757
BP		 808 /* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface
809 * to a known state by invoking ADCs until FB BUFFER 1
810 * register shows that it is correctly receiving ADC data.
811 * This is necessary because the SAA7146 ADC interface does
812 * not start up in a defined state after a PCI reset.
813 */
11e865c1 814
ae6eb75c
JS		 815/* PollList = EOPL; // Create a simple polling */
816/* // list for analog input */
817/* // channel 0. */
11e865c1
GP		 818/* ResetADC( dev, &PollList ); */
819
820/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); //( &AdcData ); // */
ae6eb75c
JS		 821/* //Get initial ADC */
822/* //value. */
11e865c1
GP		 823
824/* StartVal = data[0]; */
825
826/* // VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION. */
827/* // Invoke ADCs until the new ADC value differs from the initial */
828/* // value or a timeout occurs. The timeout protects against the */
829/* // possibility that the driver is restarting and the ADC data is a */
830/* // fixed value resulting from the applied ADC analog input being */
831/* // unusually quiet or at the rail. */
832
833/* for ( index = 0; index < 500; index++ ) */
834/* { */
ae6eb75c
JS		 835/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); */
836/* AdcData = data[0]; //ReadADC( &AdcData ); */
837/* if ( AdcData != StartVal ) */
838/* break; */
11e865c1
GP		 839/* } */
840
b6c77757 841 /* end initADC */
11e865c1 842
b6c77757 843 /* init the DAC interface */
11e865c1 844
b6c77757
BP		 845 /* Init Audio2's output DMAC attributes: burst length = 1
846 * DWORD, threshold = 1 DWORD.
847 */
11e865c1
GP		 848 WR7146(P_PCI_BT_A, 0);
849
b6c77757
BP		 850 /* Init Audio2's output DMA physical addresses. The protection
851 * address is set to 1 DWORD past the base address so that a
852 * single DWORD will be transferred each time a DMA transfer is
853 * enabled. */
11e865c1
GP		 854
855 pPhysBuf =
0a85b6f0
MT		 856 devpriv->ANABuf.PhysicalBase +
857 (DAC_WDMABUF_OS * sizeof(uint32_t));
11e865c1 858
b6c77757
BP		 859 WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
860 WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
11e865c1 861
b6c77757
BP		 862 /* Cache Audio2's output DMA buffer logical address. This is
863 * where DAC data is buffered for A2 output DMA transfers. */
11e865c1 864 devpriv->pDacWBuf =
0a85b6f0 865 (uint32_t *) devpriv->ANABuf.LogicalBase + DAC_WDMABUF_OS;
11e865c1 866
b6c77757
BP		 867 /* Audio2's output channels does not use paging. The protection
868 * violation handling bit is set so that the DMAC will
869 * automatically halt and its PCI address pointer will be reset
870 * when the protection address is reached. */
871
11e865c1
GP		 872 WR7146(P_PAGEA2_OUT, 8);
873
b6c77757
BP		 874 /* Initialize time slot list 2 (TSL2), which is used to control
875 * the clock generation for and serialization of data to be sent
876 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
877 * execution; this permits other slots to be safely modified
878 * without first turning off the TSL sequencer (which is
879 * apparently impossible to do). Also, SD3 (which is driven by a
880 * pull-up resistor) is shifted in and stored to the MSB of
881 * FB_BUFFER2 to be used as evidence that the slot sequence has
882 * not yet finished executing.
883 */
884
885 SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
886 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
887
888 /* Initialize slot 1, which is constant. Slot 1 causes a
889 * DWORD to be transferred from audio channel 2's output FIFO
890 * to the FIFO's output buffer so that it can be serialized
891 * and sent to the DAC during subsequent slots. All remaining
892 * slots are dynamically populated as required by the target
893 * DAC device.
894 */
895 SETVECT(1, LF_A2);
896 /* Slot 1: Fetch DWORD from Audio2's output FIFO. */
897
898 /* Start DAC's audio interface (TSL2) running. */
11e865c1
GP		 899 WR7146(P_ACON1, ACON1_DACSTART);
900
b6c77757 901 /* end init DAC interface */
11e865c1 902
b6c77757
BP		 903 /* Init Trim DACs to calibrated values. Do it twice because the
904 * SAA7146 audio channel does not always reset properly and
905 * sometimes causes the first few TrimDAC writes to malfunction.
906 */
11e865c1
GP		 907
908 LoadTrimDACs(dev);
b6c77757 909 LoadTrimDACs(dev); /* Insurance. */
11e865c1 910
b6c77757
BP		 911 /* Manually init all gate array hardware in case this is a soft
912 * reset (we have no way of determining whether this is a warm
913 * or cold start). This is necessary because the gate array will
914 * reset only in response to a PCI hard reset; there is no soft
915 * reset function. */
11e865c1 916
b6c77757
BP		 917 /* Init all DAC outputs to 0V and init all DAC setpoint and
918 * polarity images.
919 */
11e865c1
GP		 920 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
921 SetDAC(dev, chan, 0);
922
b6c77757
BP		 923 /* Init image of WRMISC2 Battery Charger Enabled control bit.
924 * This image is used when the state of the charger control bit,
925 * which has no direct hardware readback mechanism, is queried.
926 */
11e865c1
GP		 927 devpriv->ChargeEnabled = 0;
928
b6c77757
BP		 929 /* Init image of watchdog timer interval in WRMISC2. This image
930 * maintains the value of the control bits of MISC2 are
931 * continuously reset to zero as long as the WD timer is disabled.
932 */
11e865c1
GP		 933 devpriv->WDInterval = 0;
934
b6c77757
BP		 935 /* Init Counter Interrupt enab mask for RDMISC2. This mask is
936 * applied against MISC2 when testing to determine which timer
937 * events are requesting interrupt service.
938 */
11e865c1
GP		 939 devpriv->CounterIntEnabs = 0;
940
b6c77757 941 /* Init counters. */
11e865c1
GP		 942 CountersInit(dev);
943
b6c77757
BP		 944 /* Without modifying the state of the Battery Backup enab, disable
945 * the watchdog timer, set DIO channels 0-5 to operate in the
946 * standard DIO (vs. counter overflow) mode, disable the battery
947 * charger, and reset the watchdog interval selector to zero.
948 */
11e865c1 949 WriteMISC2(dev, (uint16_t) (DEBIread(dev,
0a85b6f0
MT		 950 LP_RDMISC2) &
951 MISC2_BATT_ENABLE));
11e865c1 952
b6c77757 953 /* Initialize the digital I/O subsystem. */
11e865c1
GP		 954 s626_dio_init(dev);
955
b6c77757
BP		 956 /* enable interrupt test */
957 /* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
11e865c1
GP		 958 }
959
960 DEBUG("s626_attach: comedi%d s626 attached %04x\n", dev->minor,
0a85b6f0 961 (uint32_t) devpriv->base_addr);
11e865c1
GP		 962
963 return 1;
964}
965
790c5541 966static unsigned int s626_ai_reg_to_uint(int data)
11e865c1 967{
790c5541 968 unsigned int tempdata;
11e865c1
GP		 969
970 tempdata = (data >> 18);
971 if (tempdata & 0x2000)
972 tempdata &= 0x1fff;
973 else
974 tempdata += (1 << 13);
975
976 return tempdata;
977}
978
34c43922 979/* static unsigned int s626_uint_to_reg(struct comedi_subdevice *s, int data){ */
11e865c1
GP		 980/* return 0; */
981/* } */
982
70265d24 983static irqreturn_t s626_irq_handler(int irq, void *d)
11e865c1 984{
71b5f4f1 985 struct comedi_device *dev = d;
34c43922 986 struct comedi_subdevice *s;
ea6d0d4c 987 struct comedi_cmd *cmd;
eb5e029e 988 struct enc_private *k;
11e865c1
GP		 989 unsigned long flags;
990 int32_t *readaddr;
991 uint32_t irqtype, irqstatus;
992 int i = 0;
790c5541 993 short tempdata;
11e865c1
GP		 994 uint8_t group;
995 uint16_t irqbit;
996
25985edc 997 DEBUG("s626_irq_handler: interrupt request received!!!\n");
11e865c1
GP		 998
999 if (dev->attached == 0)
1000 return IRQ_NONE;
b6c77757 1001 /* lock to avoid race with comedi_poll */
5f74ea14 1002 spin_lock_irqsave(&dev->spinlock, flags);
11e865c1 1003
b6c77757 1004 /* save interrupt enable register state */
11e865c1
GP		 1005 irqstatus = readl(devpriv->base_addr + P_IER);
1006
b6c77757 1007 /* read interrupt type */
11e865c1
GP		 1008 irqtype = readl(devpriv->base_addr + P_ISR);
1009
b6c77757 1010 /* disable master interrupt */
11e865c1
GP		 1011 writel(0, devpriv->base_addr + P_IER);
1012
b6c77757 1013 /* clear interrupt */
11e865c1
GP		 1014 writel(irqtype, devpriv->base_addr + P_ISR);
1015
b6c77757 1016 /* do somethings */
11e865c1
GP		 1017 DEBUG("s626_irq_handler: interrupt type %d\n", irqtype);
1018
1019 switch (irqtype) {
b6c77757 1020 case IRQ_RPS1: /* end_of_scan occurs */
11e865c1
GP		 1021
1022 DEBUG("s626_irq_handler: RPS1 irq detected\n");
1023
b6c77757 1024 /* manage ai subdevice */
11e865c1
GP		 1025 s = dev->subdevices;
1026 cmd = &(s->async->cmd);
1027
b6c77757
BP		 1028 /* Init ptr to DMA buffer that holds new ADC data. We skip the
1029 * first uint16_t in the buffer because it contains junk data from
1030 * the final ADC of the previous poll list scan.
1031 */
11e865c1
GP		 1032 readaddr = (int32_t *) devpriv->ANABuf.LogicalBase + 1;
1033
b6c77757 1034 /* get the data and hand it over to comedi */
11e865c1 1035 for (i = 0; i < (s->async->cmd.chanlist_len); i++) {
b6c77757
BP		 1036 /* Convert ADC data to 16-bit integer values and copy to application */
1037 /* buffer. */
11e865c1
GP		 1038 tempdata = s626_ai_reg_to_uint((int)*readaddr);
1039 readaddr++;
1040
b6c77757
BP		 1041 /* put data into read buffer */
1042 /* comedi_buf_put(s->async, tempdata); */
11e865c1 1043 if (cfc_write_to_buffer(s, tempdata) == 0)
0a85b6f0
MT		 1044 printk
1045 ("s626_irq_handler: cfc_write_to_buffer error!\n");
11e865c1
GP		 1046
1047 DEBUG("s626_irq_handler: ai channel %d acquired: %d\n",
0a85b6f0 1048 i, tempdata);
11e865c1
GP		 1049 }
1050
b6c77757 1051 /* end of scan occurs */
11e865c1
GP		 1052 s->async->events |= COMEDI_CB_EOS;
1053
1054 if (!(devpriv->ai_continous))
1055 devpriv->ai_sample_count--;
1056 if (devpriv->ai_sample_count <= 0) {
1057 devpriv->ai_cmd_running = 0;
1058
b6c77757 1059 /* Stop RPS program. */
11e865c1
GP		 1060 MC_DISABLE(P_MC1, MC1_ERPS1);
1061
b6c77757 1062 /* send end of acquisition */
11e865c1
GP		 1063 s->async->events |= COMEDI_CB_EOA;
1064
b6c77757 1065 /* disable master interrupt */
11e865c1
GP		 1066 irqstatus = 0;
1067 }
1068
1069 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) {
0a85b6f0
MT		 1070 DEBUG
1071 ("s626_irq_handler: enable interrupt on dio channel %d\n",
1072 cmd->scan_begin_arg);
11e865c1
GP		 1073
1074 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1075
1076 DEBUG("s626_irq_handler: External trigger is set!!!\n");
1077 }
b6c77757 1078 /* tell comedi that data is there */
11e865c1
GP		 1079 DEBUG("s626_irq_handler: events %d\n", s->async->events);
1080 comedi_event(dev, s);
1081 break;
b6c77757 1082 case IRQ_GPIO3: /* check dio and conter interrupt */
11e865c1
GP		 1083
1084 DEBUG("s626_irq_handler: GPIO3 irq detected\n");
1085
b6c77757 1086 /* manage ai subdevice */
11e865c1
GP		 1087 s = dev->subdevices;
1088 cmd = &(s->async->cmd);
1089
b6c77757 1090 /* s626_dio_clear_irq(dev); */
11e865c1
GP		 1091
1092 for (group = 0; group < S626_DIO_BANKS; group++) {
1093 irqbit = 0;
b6c77757 1094 /* read interrupt type */
11e865c1 1095 irqbit = DEBIread(dev,
0a85b6f0
MT		 1096 ((struct dio_private *)(dev->
1097 subdevices +
1098 2 +
1099 group)->
1100 private)->RDCapFlg);
11e865c1 1101
b6c77757 1102 /* check if interrupt is generated from dio channels */
11e865c1
GP		 1103 if (irqbit) {
1104 s626_dio_reset_irq(dev, group, irqbit);
0a85b6f0
MT		 1105 DEBUG
1106 ("s626_irq_handler: check interrupt on dio group %d %d\n",
1107 group, i);
11e865c1 1108 if (devpriv->ai_cmd_running) {
b6c77757 1109 /* check if interrupt is an ai acquisition start trigger */
11e865c1 1110 if ((irqbit >> (cmd->start_arg -
0a85b6f0
MT		 1111 (16 * group)))
1112 == 1 && cmd->start_src == TRIG_EXT) {
1113 DEBUG
25985edc 1114 ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
0a85b6f0 1115 cmd->start_arg);
11e865c1 1116
b6c77757 1117 /* Start executing the RPS program. */
11e865c1
GP		 1118 MC_ENABLE(P_MC1, MC1_ERPS1);
1119
0a85b6f0 1120 DEBUG
25985edc 1121 ("s626_irq_handler: acquisition start triggered!!!\n");
11e865c1
GP		 1122
1123 if (cmd->scan_begin_src ==
0a85b6f0
MT		 1124 TRIG_EXT) {
1125 DEBUG
1126 ("s626_ai_cmd: enable interrupt on dio channel %d\n",
1127 cmd->
1128 scan_begin_arg);
11e865c1
GP		 1129
1130 s626_dio_set_irq(dev,
0a85b6f0 1131 cmd->scan_begin_arg);
11e865c1 1132
0a85b6f0
MT		 1133 DEBUG
1134 ("s626_irq_handler: External scan trigger is set!!!\n");
11e865c1
GP		 1135 }
1136 }
1137 if ((irqbit >> (cmd->scan_begin_arg -
0a85b6f0
MT		 1138 (16 * group)))
1139 == 1
1140 && cmd->scan_begin_src ==
1141 TRIG_EXT) {
1142 DEBUG
25985edc 1143 ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
0a85b6f0 1144 cmd->scan_begin_arg);
11e865c1 1145
b6c77757 1146 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1147 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1148
0a85b6f0
MT		 1149 DEBUG
1150 ("s626_irq_handler: scan triggered!!! %d\n",
1151 devpriv->ai_sample_count);
11e865c1 1152 if (cmd->convert_src ==
0a85b6f0 1153 TRIG_EXT) {
11e865c1 1154
0a85b6f0
MT		 1155 DEBUG
1156 ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n",
1157 cmd->convert_arg -
1158 (16 * group),
1159 group);
11e865c1 1160
0a85b6f0
MT		 1161 devpriv->ai_convert_count
1162 = cmd->chanlist_len;
11e865c1
GP		 1163
1164 s626_dio_set_irq(dev,
0a85b6f0 1165 cmd->convert_arg);
11e865c1 1166
0a85b6f0
MT		 1167 DEBUG
1168 ("s626_irq_handler: External convert trigger is set!!!\n");
11e865c1
GP		 1169 }
1170
1171 if (cmd->convert_src ==
0a85b6f0 1172 TRIG_TIMER) {
11e865c1 1173 k = &encpriv[5];
0a85b6f0
MT		 1174 devpriv->ai_convert_count
1175 = cmd->chanlist_len;
11e865c1 1176 k->SetEnable(dev, k,
0a85b6f0 1177 CLKENAB_ALWAYS);
11e865c1
GP		 1178 }
1179 }
1180 if ((irqbit >> (cmd->convert_arg -
0a85b6f0
MT		 1181 (16 * group)))
1182 == 1
1183 && cmd->convert_src == TRIG_EXT) {
1184 DEBUG
25985edc 1185 ("s626_irq_handler: Edge capture interrupt received from channel %d\n",
0a85b6f0 1186 cmd->convert_arg);
11e865c1 1187
b6c77757 1188 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1189 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1190
0a85b6f0
MT		 1191 DEBUG
1192 ("s626_irq_handler: adc convert triggered!!!\n");
11e865c1
GP		 1193
1194 devpriv->ai_convert_count--;
1195
1196 if (devpriv->ai_convert_count >
0a85b6f0 1197 0) {
11e865c1 1198
0a85b6f0
MT		 1199 DEBUG
1200 ("s626_ai_cmd: enable interrupt on dio channel %d group %d\n",
1201 cmd->convert_arg -
1202 (16 * group),
1203 group);
11e865c1
GP		 1204
1205 s626_dio_set_irq(dev,
0a85b6f0 1206 cmd->convert_arg);
11e865c1 1207
0a85b6f0
MT		 1208 DEBUG
1209 ("s626_irq_handler: External trigger is set!!!\n");
11e865c1
GP		 1210 }
1211 }
1212 }
1213 break;
1214 }
1215 }
1216
b6c77757 1217 /* read interrupt type */
11e865c1
GP		 1218 irqbit = DEBIread(dev, LP_RDMISC2);
1219
b6c77757 1220 /* check interrupt on counters */
11e865c1 1221 DEBUG("s626_irq_handler: check counters interrupt %d\n",
0a85b6f0 1222 irqbit);
11e865c1
GP		 1223
1224 if (irqbit & IRQ_COINT1A) {
0a85b6f0
MT		 1225 DEBUG
1226 ("s626_irq_handler: interrupt on counter 1A overflow\n");
11e865c1
GP		 1227 k = &encpriv[0];
1228
b6c77757 1229 /* clear interrupt capture flag */
11e865c1
GP		 1230 k->ResetCapFlags(dev, k);
1231 }
1232 if (irqbit & IRQ_COINT2A) {
0a85b6f0
MT		 1233 DEBUG
1234 ("s626_irq_handler: interrupt on counter 2A overflow\n");
11e865c1
GP		 1235 k = &encpriv[1];
1236
b6c77757 1237 /* clear interrupt capture flag */
11e865c1
GP		 1238 k->ResetCapFlags(dev, k);
1239 }
1240 if (irqbit & IRQ_COINT3A) {
0a85b6f0
MT		 1241 DEBUG
1242 ("s626_irq_handler: interrupt on counter 3A overflow\n");
11e865c1
GP		 1243 k = &encpriv[2];
1244
b6c77757 1245 /* clear interrupt capture flag */
11e865c1
GP		 1246 k->ResetCapFlags(dev, k);
1247 }
1248 if (irqbit & IRQ_COINT1B) {
0a85b6f0
MT		 1249 DEBUG
1250 ("s626_irq_handler: interrupt on counter 1B overflow\n");
11e865c1
GP		 1251 k = &encpriv[3];
1252
b6c77757 1253 /* clear interrupt capture flag */
11e865c1
GP		 1254 k->ResetCapFlags(dev, k);
1255 }
1256 if (irqbit & IRQ_COINT2B) {
0a85b6f0
MT		 1257 DEBUG
1258 ("s626_irq_handler: interrupt on counter 2B overflow\n");
11e865c1
GP		 1259 k = &encpriv[4];
1260
b6c77757 1261 /* clear interrupt capture flag */
11e865c1
GP		 1262 k->ResetCapFlags(dev, k);
1263
1264 if (devpriv->ai_convert_count > 0) {
1265 devpriv->ai_convert_count--;
1266 if (devpriv->ai_convert_count == 0)
1267 k->SetEnable(dev, k, CLKENAB_INDEX);
1268
1269 if (cmd->convert_src == TRIG_TIMER) {
0a85b6f0
MT		 1270 DEBUG
1271 ("s626_irq_handler: conver timer trigger!!! %d\n",
1272 devpriv->ai_convert_count);
11e865c1 1273
b6c77757 1274 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1275 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1276 }
1277 }
1278 }
1279 if (irqbit & IRQ_COINT3B) {
0a85b6f0
MT		 1280 DEBUG
1281 ("s626_irq_handler: interrupt on counter 3B overflow\n");
11e865c1
GP		 1282 k = &encpriv[5];
1283
b6c77757 1284 /* clear interrupt capture flag */
11e865c1
GP		 1285 k->ResetCapFlags(dev, k);
1286
1287 if (cmd->scan_begin_src == TRIG_TIMER) {
0a85b6f0
MT		 1288 DEBUG
1289 ("s626_irq_handler: scan timer trigger!!!\n");
11e865c1 1290
b6c77757 1291 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1292 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1293 }
1294
1295 if (cmd->convert_src == TRIG_TIMER) {
0a85b6f0
MT		 1296 DEBUG
1297 ("s626_irq_handler: convert timer trigger is set\n");
11e865c1
GP		 1298 k = &encpriv[4];
1299 devpriv->ai_convert_count = cmd->chanlist_len;
1300 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1301 }
1302 }
1303 }
1304
b6c77757 1305 /* enable interrupt */
11e865c1
GP		 1306 writel(irqstatus, devpriv->base_addr + P_IER);
1307
1308 DEBUG("s626_irq_handler: exit interrupt service routine.\n");
1309
5f74ea14 1310 spin_unlock_irqrestore(&dev->spinlock, flags);
11e865c1
GP		 1311 return IRQ_HANDLED;
1312}
1313
484ecc95 1314static void s626_detach(struct comedi_device *dev)
11e865c1
GP		 1315{
1316 if (devpriv) {
b6c77757 1317 /* stop ai_command */
11e865c1
GP		 1318 devpriv->ai_cmd_running = 0;
1319
1320 if (devpriv->base_addr) {
b6c77757
BP		 1321 /* interrupt mask */
1322 WR7146(P_IER, 0); /* Disable master interrupt. */
1323 WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */
11e865c1 1324
b6c77757 1325 /* Disable the watchdog timer and battery charger. */
11e865c1
GP		 1326 WriteMISC2(dev, 0);
1327
b6c77757 1328 /* Close all interfaces on 7146 device. */
11e865c1
GP		 1329 WR7146(P_MC1, MC1_SHUTDOWN);
1330 WR7146(P_ACON1, ACON1_BASE);
1331
1332 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
1333 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
1334 }
1335
82675f35 1336 if (dev->irq)
5f74ea14 1337 free_irq(dev->irq, dev);
82675f35 1338 if (devpriv->base_addr)
11e865c1 1339 iounmap(devpriv->base_addr);
11e865c1 1340 if (devpriv->pdev) {
82675f35 1341 if (devpriv->got_regions)
11e865c1 1342 comedi_pci_disable(devpriv->pdev);
11e865c1
GP		 1343 pci_dev_put(devpriv->pdev);
1344 }
1345 }
11e865c1
GP		 1346}
1347
1348/*
1349 * this functions build the RPS program for hardware driven acquistion
1350 */
0a85b6f0 1351void ResetADC(struct comedi_device *dev, uint8_t * ppl)
11e865c1
GP		 1352{
1353 register uint32_t *pRPS;
1354 uint32_t JmpAdrs;
1355 uint16_t i;
1356 uint16_t n;
1357 uint32_t LocalPPL;
ea6d0d4c 1358 struct comedi_cmd *cmd = &(dev->subdevices->async->cmd);
11e865c1 1359
b6c77757 1360 /* Stop RPS program in case it is currently running. */
11e865c1
GP		 1361 MC_DISABLE(P_MC1, MC1_ERPS1);
1362
b6c77757 1363 /* Set starting logical address to write RPS commands. */
11e865c1
GP		 1364 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
1365
b6c77757 1366 /* Initialize RPS instruction pointer. */
11e865c1
GP		 1367 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
1368
b6c77757 1369 /* Construct RPS program in RPSBuf DMA buffer */
11e865c1
GP		 1370
1371 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1372 DEBUG("ResetADC: scan_begin pause inserted\n");
b6c77757 1373 /* Wait for Start trigger. */
11e865c1
GP		 1374 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1375 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1376 }
b6c77757
BP		 1377
1378 /* SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
1379 * because the first RPS DEBI Write following a non-RPS DEBI write
1380 * seems to always fail. If we don't do this dummy write, the ADC
1381 * gain might not be set to the value required for the first slot in
1382 * the poll list; the ADC gain would instead remain unchanged from
1383 * the previously programmed value.
1384 */
1385 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1386 /* Write DEBI Write command and address to shadow RAM. */
1387
11e865c1 1388 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
b6c77757
BP		 1389 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1390 /* Write DEBI immediate data to shadow RAM: */
1391
1392 *pRPS++ = GSEL_BIPOLAR5V;
1393 /* arbitrary immediate data value. */
1394
1395 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1396 /* Reset "shadow RAM uploaded" flag. */
1397 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1398 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
1399
1400 /* Digitize all slots in the poll list. This is implemented as a
1401 * for loop to limit the slot count to 16 in case the application
1402 * forgot to set the EOPL flag in the final slot.
1403 */
11e865c1 1404 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
0a85b6f0
MT		 1405 /* Convert application's poll list item to private board class
1406 * format. Each app poll list item is an uint8_t with form
1407 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1408 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1409 */
11e865c1 1410 LocalPPL =
0a85b6f0
MT		 1411 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
1412 GSEL_BIPOLAR10V);
11e865c1 1413
b6c77757
BP		 1414 /* Switch ADC analog gain. */
1415 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */
1416 /* and address to */
1417 /* shadow RAM. */
11e865c1 1418 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
b6c77757
BP		 1419 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */
1420 /* immediate data to */
1421 /* shadow RAM. */
11e865c1 1422 *pRPS++ = LocalPPL;
b6c77757
BP		 1423 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */
1424 /* flag. */
1425 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1426 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */
1427 /* finish. */
1428
1429 /* Select ADC analog input channel. */
1430 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1431 /* Write DEBI command and address to shadow RAM. */
11e865c1 1432 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
b6c77757
BP		 1433 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1434 /* Write DEBI immediate data to shadow RAM. */
11e865c1 1435 *pRPS++ = LocalPPL;
b6c77757
BP		 1436 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1437 /* Reset "shadow RAM uploaded" flag. */
1438
1439 *pRPS++ = RPS_UPLOAD | RPS_DEBI;
1440 /* Invoke shadow RAM upload. */
1441
1442 *pRPS++ = RPS_PAUSE | RPS_DEBI;
1443 /* Wait for shadow upload to finish. */
1444
1445 /* Delay at least 10 microseconds for analog input settling.
1446 * Instead of padding with NOPs, we use RPS_JUMP instructions
1447 * here; this allows us to produce a longer delay than is
1448 * possible with NOPs because each RPS_JUMP flushes the RPS'
1449 * instruction prefetch pipeline.
1450 */
11e865c1 1451 JmpAdrs =
0a85b6f0
MT		 1452 (uint32_t) devpriv->RPSBuf.PhysicalBase +
1453 (uint32_t) ((unsigned long)pRPS -
1454 (unsigned long)devpriv->RPSBuf.LogicalBase);
11e865c1 1455 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
b6c77757
BP		 1456 JmpAdrs += 8; /* Repeat to implement time delay: */
1457 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
11e865c1
GP		 1458 *pRPS++ = JmpAdrs;
1459 }
1460
1461 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1462 DEBUG("ResetADC: convert pause inserted\n");
b6c77757 1463 /* Wait for Start trigger. */
11e865c1
GP		 1464 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1465 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1466 }
b6c77757
BP		 1467 /* Start ADC by pulsing GPIO1. */
1468 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
11e865c1
GP		 1469 *pRPS++ = GPIO_BASE | GPIO1_LO;
1470 *pRPS++ = RPS_NOP;
b6c77757
BP		 1471 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1472 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
11e865c1
GP		 1473 *pRPS++ = GPIO_BASE | GPIO1_HI;
1474
b6c77757
BP		 1475 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not
1476 * busy) and for data from previous conversion to shift into FB
1477 * BUFFER 1 register.
1478 */
1479 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1480
b6c77757 1481 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
11e865c1
GP		 1482 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
1483 *pRPS++ =
0a85b6f0
MT		 1484 (uint32_t) devpriv->ANABuf.PhysicalBase +
1485 (devpriv->AdcItems << 2);
11e865c1 1486
b6c77757
BP		 1487 /* If this slot's EndOfPollList flag is set, all channels have */
1488 /* now been processed. */
11e865c1 1489 if (*ppl++ & EOPL) {
b6c77757
BP		 1490 devpriv->AdcItems++; /* Adjust poll list item count. */
1491 break; /* Exit poll list processing loop. */
11e865c1
GP		 1492 }
1493 }
daca497d 1494 DEBUG("ResetADC: ADC items %d\n", devpriv->AdcItems);
11e865c1 1495
b6c77757
BP		 1496 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1497 * ADC to stabilize for 2 microseconds before starting the final
1498 * (dummy) conversion. This delay is necessary to allow sufficient
1499 * time between last conversion finished and the start of the dummy
1500 * conversion. Without this delay, the last conversion's data value
1501 * is sometimes set to the previous conversion's data value.
1502 */
11e865c1
GP		 1503 for (n = 0; n < (2 * RPSCLK_PER_US); n++)
1504 *pRPS++ = RPS_NOP;
1505
b6c77757
BP		 1506 /* Start a dummy conversion to cause the data from the last
1507 * conversion of interest to be shifted in.
1508 */
1509 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
11e865c1
GP		 1510 *pRPS++ = GPIO_BASE | GPIO1_LO;
1511 *pRPS++ = RPS_NOP;
b6c77757
BP		 1512 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1513 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
11e865c1
GP		 1514 *pRPS++ = GPIO_BASE | GPIO1_HI;
1515
b6c77757
BP		 1516 /* Wait for the data from the last conversion of interest to arrive
1517 * in FB BUFFER 1 register.
1518 */
1519 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1520
b6c77757
BP		 1521 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1522 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */
11e865c1 1523 *pRPS++ =
0a85b6f0 1524 (uint32_t) devpriv->ANABuf.PhysicalBase + (devpriv->AdcItems << 2);
11e865c1 1525
b6c77757
BP		 1526 /* Indicate ADC scan loop is finished. */
1527 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */
11e865c1 1528
b6c77757 1529 /* invoke interrupt */
11e865c1
GP		 1530 if (devpriv->ai_cmd_running == 1) {
1531 DEBUG("ResetADC: insert irq in ADC RPS task\n");
1532 *pRPS++ = RPS_IRQ;
1533 }
b6c77757
BP		 1534 /* Restart RPS program at its beginning. */
1535 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
11e865c1
GP		 1536 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase;
1537
b6c77757 1538 /* End of RPS program build */
11e865c1
GP		 1539}
1540
1541/* TO COMPLETE, IF NECESSARY */
0a85b6f0
MT		 1542static int s626_ai_insn_config(struct comedi_device *dev,
1543 struct comedi_subdevice *s,
1544 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 1545{
1546
1547 return -EINVAL;
1548}
1549
90035c08 1550/* static int s626_ai_rinsn(struct comedi_device *dev,struct comedi_subdevice *s,struct comedi_insn *insn,unsigned int *data) */
11e865c1
GP		 1551/* { */
1552/* register uint8_t i; */
1553/* register int32_t *readaddr; */
1554
daca497d 1555/* DEBUG("as626_ai_rinsn: ai_rinsn enter\n"); */
11e865c1 1556
b6c77757 1557/* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1558/* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
1559
b6c77757 1560/* Wait until ADC scan loop is finished (RPS Signal 0 reset). */
11e865c1
GP		 1561/* while ( MC_TEST( P_MC2, MC2_ADC_RPS ) ); */
1562
b6c77757
BP		 1563/* Init ptr to DMA buffer that holds new ADC data. We skip the
1564 * first uint16_t in the buffer because it contains junk data from
1565 * the final ADC of the previous poll list scan.
1566 */
11e865c1
GP		 1567/* readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1; */
1568
b6c77757 1569/* Convert ADC data to 16-bit integer values and copy to application buffer. */
11e865c1
GP		 1570/* for ( i = 0; i < devpriv->AdcItems; i++ ) { */
1571/* *data = s626_ai_reg_to_uint( *readaddr++ ); */
daca497d 1572/* DEBUG("s626_ai_rinsn: data %d\n",*data); */
11e865c1
GP		 1573/* data++; */
1574/* } */
1575
daca497d 1576/* DEBUG("s626_ai_rinsn: ai_rinsn escape\n"); */
11e865c1
GP		 1577/* return i; */
1578/* } */
1579
0a85b6f0
MT		 1580static int s626_ai_insn_read(struct comedi_device *dev,
1581 struct comedi_subdevice *s,
1582 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 1583{
1584 uint16_t chan = CR_CHAN(insn->chanspec);
1585 uint16_t range = CR_RANGE(insn->chanspec);
1586 uint16_t AdcSpec = 0;
1587 uint32_t GpioImage;
1588 int n;
1589
0a85b6f0 1590 /* interrupt call test */
b6c77757
BP		 1591/* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */
1592 /* Writing a logical 1 into any of the RPS_PSR bits causes the
1593 * corresponding interrupt to be generated if enabled
1594 */
11e865c1
GP		 1595
1596 DEBUG("s626_ai_insn_read: entering\n");
1597
b6c77757
BP		 1598 /* Convert application's ADC specification into form
1599 * appropriate for register programming.
1600 */
11e865c1
GP		 1601 if (range == 0)
1602 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
1603 else
1604 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
1605
b6c77757
BP		 1606 /* Switch ADC analog gain. */
1607 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */
11e865c1 1608
b6c77757
BP		 1609 /* Select ADC analog input channel. */
1610 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */
11e865c1
GP		 1611
1612 for (n = 0; n < insn->n; n++) {
1613
b6c77757 1614 /* Delay 10 microseconds for analog input settling. */
5f74ea14 1615 udelay(10);
11e865c1 1616
b6c77757 1617 /* Start ADC by pulsing GPIO1 low. */
11e865c1 1618 GpioImage = RR7146(P_GPIO);
b6c77757 1619 /* Assert ADC Start command */
11e865c1 1620 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1621 /* and stretch it out. */
11e865c1
GP		 1622 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1623 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1624 /* Negate ADC Start command. */
11e865c1
GP		 1625 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1626
b6c77757
BP		 1627 /* Wait for ADC to complete (GPIO2 is asserted high when */
1628 /* ADC not busy) and for data from previous conversion to */
1629 /* shift into FB BUFFER 1 register. */
11e865c1 1630
b6c77757 1631 /* Wait for ADC done. */
add74595 1632 while (!(RR7146(P_PSR) & PSR_GPIO2))
ae6eb75c 1633 ;
11e865c1 1634
b6c77757 1635 /* Fetch ADC data. */
11e865c1
GP		 1636 if (n != 0)
1637 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1638
b6c77757
BP		 1639 /* Allow the ADC to stabilize for 4 microseconds before
1640 * starting the next (final) conversion. This delay is
1641 * necessary to allow sufficient time between last
1642 * conversion finished and the start of the next
1643 * conversion. Without this delay, the last conversion's
1644 * data value is sometimes set to the previous
1645 * conversion's data value.
1646 */
5f74ea14 1647 udelay(4);
11e865c1
GP		 1648 }
1649
b6c77757
BP		 1650 /* Start a dummy conversion to cause the data from the
1651 * previous conversion to be shifted in. */
11e865c1
GP		 1652 GpioImage = RR7146(P_GPIO);
1653
b6c77757 1654 /* Assert ADC Start command */
11e865c1 1655 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1656 /* and stretch it out. */
11e865c1
GP		 1657 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1658 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1659 /* Negate ADC Start command. */
11e865c1
GP		 1660 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1661
b6c77757 1662 /* Wait for the data to arrive in FB BUFFER 1 register. */
11e865c1 1663
b6c77757 1664 /* Wait for ADC done. */
add74595 1665 while (!(RR7146(P_PSR) & PSR_GPIO2))
ae6eb75c 1666 ;
11e865c1 1667
b6c77757 1668 /* Fetch ADC data from audio interface's input shift register. */
11e865c1 1669
b6c77757 1670 /* Fetch ADC data. */
11e865c1
GP		 1671 if (n != 0)
1672 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1673
1674 DEBUG("s626_ai_insn_read: samples %d, data %d\n", n, data[n - 1]);
1675
1676 return n;
1677}
1678
add74595 1679static int s626_ai_load_polllist(uint8_t *ppl, struct comedi_cmd *cmd)
11e865c1
GP		 1680{
1681
1682 int n;
1683
1684 for (n = 0; n < cmd->chanlist_len; n++) {
1685 if (CR_RANGE((cmd->chanlist)[n]) == 0)
1686 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V);
1687 else
1688 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V);
1689 }
4ff863b1
RK		 1690 if (n != 0)
1691 ppl[n - 1] |= EOPL;
11e865c1
GP		 1692
1693 return n;
1694}
1695
0a85b6f0
MT		 1696static int s626_ai_inttrig(struct comedi_device *dev,
1697 struct comedi_subdevice *s, unsigned int trignum)
11e865c1
GP		 1698{
1699 if (trignum != 0)
1700 return -EINVAL;
1701
1702 DEBUG("s626_ai_inttrig: trigger adc start...");
1703
b6c77757 1704 /* Start executing the RPS program. */
11e865c1
GP		 1705 MC_ENABLE(P_MC1, MC1_ERPS1);
1706
1707 s->async->inttrig = NULL;
1708
1709 DEBUG(" done\n");
1710
1711 return 1;
1712}
1713
1714/* TO COMPLETE */
34c43922 1715static int s626_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
11e865c1
GP		 1716{
1717
1718 uint8_t ppl[16];
ea6d0d4c 1719 struct comedi_cmd *cmd = &s->async->cmd;
eb5e029e 1720 struct enc_private *k;
11e865c1
GP		 1721 int tick;
1722
1723 DEBUG("s626_ai_cmd: entering command function\n");
1724
1725 if (devpriv->ai_cmd_running) {
daca497d 1726 printk(KERN_ERR "s626_ai_cmd: Another ai_cmd is running %d\n",
0a85b6f0 1727 dev->minor);
11e865c1
GP		 1728 return -EBUSY;
1729 }
b6c77757 1730 /* disable interrupt */
11e865c1
GP		 1731 writel(0, devpriv->base_addr + P_IER);
1732
b6c77757 1733 /* clear interrupt request */
11e865c1
GP		 1734 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR);
1735
b6c77757 1736 /* clear any pending interrupt */
11e865c1 1737 s626_dio_clear_irq(dev);
b6c77757 1738 /* s626_enc_clear_irq(dev); */
11e865c1 1739
b6c77757 1740 /* reset ai_cmd_running flag */
11e865c1
GP		 1741 devpriv->ai_cmd_running = 0;
1742
b6c77757 1743 /* test if cmd is valid */
11e865c1
GP		 1744 if (cmd == NULL) {
1745 DEBUG("s626_ai_cmd: NULL command\n");
1746 return -EINVAL;
1747 } else {
25985edc 1748 DEBUG("s626_ai_cmd: command received!!!\n");
11e865c1
GP		 1749 }
1750
1751 if (dev->irq == 0) {
1752 comedi_error(dev,
0a85b6f0 1753 "s626_ai_cmd: cannot run command without an irq");
11e865c1
GP		 1754 return -EIO;
1755 }
1756
1757 s626_ai_load_polllist(ppl, cmd);
1758 devpriv->ai_cmd_running = 1;
1759 devpriv->ai_convert_count = 0;
1760
1761 switch (cmd->scan_begin_src) {
1762 case TRIG_FOLLOW:
1763 break;
1764 case TRIG_TIMER:
b6c77757 1765 /* set a conter to generate adc trigger at scan_begin_arg interval */
11e865c1
GP		 1766 k = &encpriv[5];
1767 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
0a85b6f0 1768 cmd->flags & TRIG_ROUND_MASK);
11e865c1 1769
b6c77757 1770 /* load timer value and enable interrupt */
11e865c1
GP		 1771 s626_timer_load(dev, k, tick);
1772 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1773
1774 DEBUG("s626_ai_cmd: scan trigger timer is set with value %d\n",
0a85b6f0 1775 tick);
11e865c1
GP		 1776
1777 break;
1778 case TRIG_EXT:
b6c77757 1779 /* set the digital line and interrupt for scan trigger */
11e865c1
GP		 1780 if (cmd->start_src != TRIG_EXT)
1781 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1782
1783 DEBUG("s626_ai_cmd: External scan trigger is set!!!\n");
1784
1785 break;
1786 }
1787
1788 switch (cmd->convert_src) {
1789 case TRIG_NOW:
1790 break;
1791 case TRIG_TIMER:
b6c77757 1792 /* set a conter to generate adc trigger at convert_arg interval */
11e865c1
GP		 1793 k = &encpriv[4];
1794 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
0a85b6f0 1795 cmd->flags & TRIG_ROUND_MASK);
11e865c1 1796
b6c77757 1797 /* load timer value and enable interrupt */
11e865c1
GP		 1798 s626_timer_load(dev, k, tick);
1799 k->SetEnable(dev, k, CLKENAB_INDEX);
1800
0a85b6f0
MT		 1801 DEBUG
1802 ("s626_ai_cmd: convert trigger timer is set with value %d\n",
1803 tick);
11e865c1
GP		 1804 break;
1805 case TRIG_EXT:
b6c77757 1806 /* set the digital line and interrupt for convert trigger */
11e865c1 1807 if (cmd->scan_begin_src != TRIG_EXT
0a85b6f0 1808 && cmd->start_src == TRIG_EXT)
11e865c1
GP		 1809 s626_dio_set_irq(dev, cmd->convert_arg);
1810
1811 DEBUG("s626_ai_cmd: External convert trigger is set!!!\n");
1812
1813 break;
1814 }
1815
1816 switch (cmd->stop_src) {
1817 case TRIG_COUNT:
b6c77757 1818 /* data arrives as one packet */
11e865c1
GP		 1819 devpriv->ai_sample_count = cmd->stop_arg;
1820 devpriv->ai_continous = 0;
1821 break;
1822 case TRIG_NONE:
25985edc 1823 /* continous acquisition */
11e865c1
GP		 1824 devpriv->ai_continous = 1;
1825 devpriv->ai_sample_count = 0;
1826 break;
1827 }
1828
1829 ResetADC(dev, ppl);
1830
1831 switch (cmd->start_src) {
1832 case TRIG_NOW:
b6c77757
BP		 1833 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1834 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
11e865c1 1835
b6c77757 1836 /* Start executing the RPS program. */
11e865c1
GP		 1837 MC_ENABLE(P_MC1, MC1_ERPS1);
1838
1839 DEBUG("s626_ai_cmd: ADC triggered\n");
1840 s->async->inttrig = NULL;
1841 break;
1842 case TRIG_EXT:
b6c77757 1843 /* configure DIO channel for acquisition trigger */
11e865c1
GP		 1844 s626_dio_set_irq(dev, cmd->start_arg);
1845
1846 DEBUG("s626_ai_cmd: External start trigger is set!!!\n");
1847
1848 s->async->inttrig = NULL;
1849 break;
1850 case TRIG_INT:
1851 s->async->inttrig = s626_ai_inttrig;
1852 break;
1853 }
1854
b6c77757 1855 /* enable interrupt */
11e865c1
GP		 1856 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER);
1857
1858 DEBUG("s626_ai_cmd: command function terminated\n");
1859
1860 return 0;
1861}
1862
0a85b6f0
MT		 1863static int s626_ai_cmdtest(struct comedi_device *dev,
1864 struct comedi_subdevice *s, struct comedi_cmd *cmd)
11e865c1
GP		 1865{
1866 int err = 0;
1867 int tmp;
1868
1869 /* cmdtest tests a particular command to see if it is valid. Using
1870 * the cmdtest ioctl, a user can create a valid cmd and then have it
1871 * executes by the cmd ioctl.
1872 *
1873 * cmdtest returns 1,2,3,4 or 0, depending on which tests the
1874 * command passes. */
1875
1876 /* step 1: make sure trigger sources are trivially valid */
1877
1878 tmp = cmd->start_src;
1879 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
1880 if (!cmd->start_src || tmp != cmd->start_src)
1881 err++;
1882
1883 tmp = cmd->scan_begin_src;
1884 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW;
1885 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1886 err++;
1887
1888 tmp = cmd->convert_src;
1889 cmd->convert_src &= TRIG_TIMER | TRIG_EXT | TRIG_NOW;
1890 if (!cmd->convert_src || tmp != cmd->convert_src)
1891 err++;
1892
1893 tmp = cmd->scan_end_src;
1894 cmd->scan_end_src &= TRIG_COUNT;
1895 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1896 err++;
1897
1898 tmp = cmd->stop_src;
1899 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1900 if (!cmd->stop_src || tmp != cmd->stop_src)
1901 err++;
1902
1903 if (err)
1904 return 1;
1905
1906 /* step 2: make sure trigger sources are unique and mutually
1907 compatible */
1908
828684f9 1909 /* note that mutual compatibility is not an issue here */
11e865c1 1910 if (cmd->scan_begin_src != TRIG_TIMER &&
0a85b6f0
MT		 1911 cmd->scan_begin_src != TRIG_EXT
1912 && cmd->scan_begin_src != TRIG_FOLLOW)
11e865c1
GP		 1913 err++;
1914 if (cmd->convert_src != TRIG_TIMER &&
0a85b6f0 1915 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
11e865c1
GP		 1916 err++;
1917 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1918 err++;
1919
1920 if (err)
1921 return 2;
1922
1923 /* step 3: make sure arguments are trivially compatible */
1924
1925 if (cmd->start_src != TRIG_EXT && cmd->start_arg != 0) {
1926 cmd->start_arg = 0;
1927 err++;
1928 }
1929
11e865c1
GP		 1930 if (cmd->start_src == TRIG_EXT && cmd->start_arg > 39) {
1931 cmd->start_arg = 39;
1932 err++;
1933 }
1934
11e865c1
GP		 1935 if (cmd->scan_begin_src == TRIG_EXT && cmd->scan_begin_arg > 39) {
1936 cmd->scan_begin_arg = 39;
1937 err++;
1938 }
1939
11e865c1
GP		 1940 if (cmd->convert_src == TRIG_EXT && cmd->convert_arg > 39) {
1941 cmd->convert_arg = 39;
1942 err++;
1943 }
1944#define MAX_SPEED 200000 /* in nanoseconds */
1945#define MIN_SPEED 2000000000 /* in nanoseconds */
1946
1947 if (cmd->scan_begin_src == TRIG_TIMER) {
1948 if (cmd->scan_begin_arg < MAX_SPEED) {
1949 cmd->scan_begin_arg = MAX_SPEED;
1950 err++;
1951 }
1952 if (cmd->scan_begin_arg > MIN_SPEED) {
1953 cmd->scan_begin_arg = MIN_SPEED;
1954 err++;
1955 }
1956 } else {
1957 /* external trigger */
1958 /* should be level/edge, hi/lo specification here */
1959 /* should specify multiple external triggers */
1960/* if(cmd->scan_begin_arg>9){ */
1961/* cmd->scan_begin_arg=9; */
1962/* err++; */
1963/* } */
1964 }
1965 if (cmd->convert_src == TRIG_TIMER) {
1966 if (cmd->convert_arg < MAX_SPEED) {
1967 cmd->convert_arg = MAX_SPEED;
1968 err++;
1969 }
1970 if (cmd->convert_arg > MIN_SPEED) {
1971 cmd->convert_arg = MIN_SPEED;
1972 err++;
1973 }
1974 } else {
1975 /* external trigger */
1976 /* see above */
1977/* if(cmd->convert_arg>9){ */
1978/* cmd->convert_arg=9; */
1979/* err++; */
1980/* } */
1981 }
1982
1983 if (cmd->scan_end_arg != cmd->chanlist_len) {
1984 cmd->scan_end_arg = cmd->chanlist_len;
1985 err++;
1986 }
1987 if (cmd->stop_src == TRIG_COUNT) {
1988 if (cmd->stop_arg > 0x00ffffff) {
1989 cmd->stop_arg = 0x00ffffff;
1990 err++;
1991 }
1992 } else {
1993 /* TRIG_NONE */
1994 if (cmd->stop_arg != 0) {
1995 cmd->stop_arg = 0;
1996 err++;
1997 }
1998 }
1999
2000 if (err)
2001 return 3;
2002
2003 /* step 4: fix up any arguments */
2004
2005 if (cmd->scan_begin_src == TRIG_TIMER) {
2006 tmp = cmd->scan_begin_arg;
2007 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
0a85b6f0 2008 cmd->flags & TRIG_ROUND_MASK);
11e865c1
GP		 2009 if (tmp != cmd->scan_begin_arg)
2010 err++;
2011 }
2012 if (cmd->convert_src == TRIG_TIMER) {
2013 tmp = cmd->convert_arg;
2014 s626_ns_to_timer((int *)&cmd->convert_arg,
0a85b6f0 2015 cmd->flags & TRIG_ROUND_MASK);
11e865c1
GP		 2016 if (tmp != cmd->convert_arg)
2017 err++;
2018 if (cmd->scan_begin_src == TRIG_TIMER &&
0a85b6f0
MT		 2019 cmd->scan_begin_arg <
2020 cmd->convert_arg * cmd->scan_end_arg) {
11e865c1 2021 cmd->scan_begin_arg =
0a85b6f0 2022 cmd->convert_arg * cmd->scan_end_arg;
11e865c1
GP		 2023 err++;
2024 }
2025 }
2026
2027 if (err)
2028 return 4;
2029
2030 return 0;
2031}
2032
34c43922 2033static int s626_ai_cancel(struct comedi_device *dev, struct comedi_subdevice *s)
11e865c1 2034{
b6c77757 2035 /* Stop RPS program in case it is currently running. */
11e865c1
GP		 2036 MC_DISABLE(P_MC1, MC1_ERPS1);
2037
b6c77757 2038 /* disable master interrupt */
11e865c1
GP		 2039 writel(0, devpriv->base_addr + P_IER);
2040
2041 devpriv->ai_cmd_running = 0;
2042
2043 return 0;
2044}
2045
2046/* This function doesn't require a particular form, this is just what
2047 * happens to be used in some of the drivers. It should convert ns
2048 * nanoseconds to a counter value suitable for programming the device.
2049 * Also, it should adjust ns so that it cooresponds to the actual time
2050 * that the device will use. */
2051static int s626_ns_to_timer(int *nanosec, int round_mode)
2052{
2053 int divider, base;
2054
b6c77757 2055 base = 500; /* 2MHz internal clock */
11e865c1
GP		 2056
2057 switch (round_mode) {
2058 case TRIG_ROUND_NEAREST:
2059 default:
2060 divider = (*nanosec + base / 2) / base;
2061 break;
2062 case TRIG_ROUND_DOWN:
2063 divider = (*nanosec) / base;
2064 break;
2065 case TRIG_ROUND_UP:
2066 divider = (*nanosec + base - 1) / base;
2067 break;
2068 }
2069
2070 *nanosec = base * divider;
2071 return divider - 1;
2072}
2073
34c43922 2074static int s626_ao_winsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 2075 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2076{
2077
2078 int i;
2079 uint16_t chan = CR_CHAN(insn->chanspec);
2080 int16_t dacdata;
2081
2082 for (i = 0; i < insn->n; i++) {
2083 dacdata = (int16_t) data[i];
2084 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2085 dacdata -= (0x1fff);
2086
2087 SetDAC(dev, chan, dacdata);
2088 }
2089
2090 return i;
2091}
2092
34c43922 2093static int s626_ao_rinsn(struct comedi_device *dev, struct comedi_subdevice *s,
0a85b6f0 2094 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2095{
2096 int i;
2097
82675f35 2098 for (i = 0; i < insn->n; i++)
11e865c1 2099 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
11e865c1
GP		 2100
2101 return i;
2102}
2103
b6c77757
BP		 2104/* *************** DIGITAL I/O FUNCTIONS ***************
2105 * All DIO functions address a group of DIO channels by means of
2106 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
2107 * ports A, B and C, respectively.
2108 */
11e865c1 2109
71b5f4f1 2110static void s626_dio_init(struct comedi_device *dev)
11e865c1
GP		 2111{
2112 uint16_t group;
34c43922 2113 struct comedi_subdevice *s;
11e865c1 2114
b6c77757 2115 /* Prepare to treat writes to WRCapSel as capture disables. */
11e865c1
GP		 2116 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2117
b6c77757 2118 /* For each group of sixteen channels ... */
11e865c1
GP		 2119 for (group = 0; group < S626_DIO_BANKS; group++) {
2120 s = dev->subdevices + 2 + group;
b6c77757
BP		 2121 DEBIwrite(dev, diopriv->WRIntSel, 0); /* Disable all interrupts. */
2122 DEBIwrite(dev, diopriv->WRCapSel, 0xFFFF); /* Disable all event */
2123 /* captures. */
2124 DEBIwrite(dev, diopriv->WREdgSel, 0); /* Init all DIOs to */
2125 /* default edge */
2126 /* polarity. */
2127 DEBIwrite(dev, diopriv->WRDOut, 0); /* Program all outputs */
2128 /* to inactive state. */
11e865c1 2129 }
daca497d 2130 DEBUG("s626_dio_init: DIO initialized\n");
11e865c1
GP		 2131}
2132
2133/* DIO devices are slightly special. Although it is possible to
2134 * implement the insn_read/insn_write interface, it is much more
2135 * useful to applications if you implement the insn_bits interface.
2136 * This allows packed reading/writing of the DIO channels. The comedi
2137 * core can convert between insn_bits and insn_read/write */
2138
0a85b6f0
MT		 2139static int s626_dio_insn_bits(struct comedi_device *dev,
2140 struct comedi_subdevice *s,
2141 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2142{
2143
2144 /* Length of data must be 2 (mask and new data, see below) */
82675f35 2145 if (insn->n == 0)
11e865c1 2146 return 0;
82675f35 2147
11e865c1 2148 if (insn->n != 2) {
0a85b6f0
MT		 2149 printk
2150 ("comedi%d: s626: s626_dio_insn_bits(): Invalid instruction length\n",
2151 dev->minor);
11e865c1
GP		 2152 return -EINVAL;
2153 }
2154
2155 /*
2156 * The insn data consists of a mask in data[0] and the new data in
2157 * data[1]. The mask defines which bits we are concerning about.
2158 * The new data must be anded with the mask. Each channel
2159 * corresponds to a bit.
2160 */
2161 if (data[0]) {
2162 /* Check if requested ports are configured for output */
2163 if ((s->io_bits & data[0]) != data[0])
2164 return -EIO;
2165
2166 s->state &= ~data[0];
2167 s->state |= data[0] & data[1];
2168
2169 /* Write out the new digital output lines */
2170
2171 DEBIwrite(dev, diopriv->WRDOut, s->state);
2172 }
2173 data[1] = DEBIread(dev, diopriv->RDDIn);
2174
2175 return 2;
2176}
2177
0a85b6f0
MT		 2178static int s626_dio_insn_config(struct comedi_device *dev,
2179 struct comedi_subdevice *s,
2180 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2181{
2182
2183 switch (data[0]) {
2184 case INSN_CONFIG_DIO_QUERY:
2185 data[1] =
0a85b6f0
MT		 2186 (s->
2187 io_bits & (1 << CR_CHAN(insn->chanspec))) ? COMEDI_OUTPUT :
2188 COMEDI_INPUT;
11e865c1
GP		 2189 return insn->n;
2190 break;
2191 case COMEDI_INPUT:
2192 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2193 break;
2194 case COMEDI_OUTPUT:
2195 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2196 break;
2197 default:
2198 return -EINVAL;
2199 break;
2200 }
2201 DEBIwrite(dev, diopriv->WRDOut, s->io_bits);
2202
2203 return 1;
2204}
2205
71b5f4f1 2206static int s626_dio_set_irq(struct comedi_device *dev, unsigned int chan)
11e865c1
GP		 2207{
2208 unsigned int group;
2209 unsigned int bitmask;
2210 unsigned int status;
2211
b6c77757 2212 /* select dio bank */
11e865c1
GP		 2213 group = chan / 16;
2214 bitmask = 1 << (chan - (16 * group));
2215 DEBUG("s626_dio_set_irq: enable interrupt on dio channel %d group %d\n",
0a85b6f0 2216 chan - (16 * group), group);
11e865c1 2217
b6c77757 2218 /* set channel to capture positive edge */
11e865c1 2219 status = DEBIread(dev,
0a85b6f0
MT		 2220 ((struct dio_private *)(dev->subdevices + 2 +
2221 group)->private)->RDEdgSel);
11e865c1 2222 DEBIwrite(dev,
0a85b6f0
MT		 2223 ((struct dio_private *)(dev->subdevices + 2 +
2224 group)->private)->WREdgSel,
2225 bitmask | status);
11e865c1 2226
b6c77757 2227 /* enable interrupt on selected channel */
11e865c1 2228 status = DEBIread(dev,
0a85b6f0
MT		 2229 ((struct dio_private *)(dev->subdevices + 2 +
2230 group)->private)->RDIntSel);
11e865c1 2231 DEBIwrite(dev,
0a85b6f0
MT		 2232 ((struct dio_private *)(dev->subdevices + 2 +
2233 group)->private)->WRIntSel,
2234 bitmask | status);
11e865c1 2235
b6c77757 2236 /* enable edge capture write command */
11e865c1
GP		 2237 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);
2238
b6c77757 2239 /* enable edge capture on selected channel */
11e865c1 2240 status = DEBIread(dev,
0a85b6f0
MT		 2241 ((struct dio_private *)(dev->subdevices + 2 +
2242 group)->private)->RDCapSel);
11e865c1 2243 DEBIwrite(dev,
0a85b6f0
MT		 2244 ((struct dio_private *)(dev->subdevices + 2 +
2245 group)->private)->WRCapSel,
2246 bitmask | status);
11e865c1
GP		 2247
2248 return 0;
2249}
2250
71b5f4f1 2251static int s626_dio_reset_irq(struct comedi_device *dev, unsigned int group,
0a85b6f0 2252 unsigned int mask)
11e865c1 2253{
0a85b6f0
MT		 2254 DEBUG
2255 ("s626_dio_reset_irq: disable interrupt on dio channel %d group %d\n",
2256 mask, group);
11e865c1 2257
b6c77757 2258 /* disable edge capture write command */
11e865c1
GP		 2259 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2260
b6c77757 2261 /* enable edge capture on selected channel */
11e865c1 2262 DEBIwrite(dev,
0a85b6f0
MT		 2263 ((struct dio_private *)(dev->subdevices + 2 +
2264 group)->private)->WRCapSel, mask);
11e865c1
GP		 2265
2266 return 0;
2267}
2268
71b5f4f1 2269static int s626_dio_clear_irq(struct comedi_device *dev)
11e865c1
GP		 2270{
2271 unsigned int group;
2272
b6c77757 2273 /* disable edge capture write command */
11e865c1
GP		 2274 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2275
2276 for (group = 0; group < S626_DIO_BANKS; group++) {
b6c77757 2277 /* clear pending events and interrupt */
11e865c1 2278 DEBIwrite(dev,
0a85b6f0
MT		 2279 ((struct dio_private *)(dev->subdevices + 2 +
2280 group)->private)->WRCapSel,
2281 0xffff);
11e865c1
GP		 2282 }
2283
2284 return 0;
2285}
2286
2287/* Now this function initializes the value of the counter (data[0])
2288 and set the subdevice. To complete with trigger and interrupt
2289 configuration */
0a85b6f0
MT		 2290static int s626_enc_insn_config(struct comedi_device *dev,
2291 struct comedi_subdevice *s,
2292 struct comedi_insn *insn, unsigned int *data)
11e865c1 2293{
b6c77757 2294 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
0a85b6f0
MT		 2295 /* index. */
2296 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2297 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
2298 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2299 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */
2300 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2301 (CLKENAB_INDEX << BF_CLKENAB);
11e865c1 2302 /* uint16_t DisableIntSrc=TRUE; */
b6c77757 2303 /* uint32_t Preloadvalue; //Counter initial value */
11e865c1
GP		 2304 uint16_t valueSrclatch = LATCHSRC_AB_READ;
2305 uint16_t enab = CLKENAB_ALWAYS;
eb5e029e 2306 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1
GP		 2307
2308 DEBUG("s626_enc_insn_config: encoder config\n");
2309
b6c77757 2310 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
11e865c1
GP		 2311
2312 k->SetMode(dev, k, Setup, TRUE);
2313 Preload(dev, k, *(insn->data));
2314 k->PulseIndex(dev, k);
2315 SetLatchSource(dev, k, valueSrclatch);
2316 k->SetEnable(dev, k, (uint16_t) (enab != 0));
2317
2318 return insn->n;
2319}
2320
0a85b6f0
MT		 2321static int s626_enc_insn_read(struct comedi_device *dev,
2322 struct comedi_subdevice *s,
2323 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2324{
2325
2326 int n;
eb5e029e 2327 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1 2328
daca497d 2329 DEBUG("s626_enc_insn_read: encoder read channel %d\n",
0a85b6f0 2330 CR_CHAN(insn->chanspec));
11e865c1
GP		 2331
2332 for (n = 0; n < insn->n; n++)
2333 data[n] = ReadLatch(dev, k);
2334
2335 DEBUG("s626_enc_insn_read: encoder sample %d\n", data[n]);
2336
2337 return n;
2338}
2339
0a85b6f0
MT		 2340static int s626_enc_insn_write(struct comedi_device *dev,
2341 struct comedi_subdevice *s,
2342 struct comedi_insn *insn, unsigned int *data)
11e865c1
GP		 2343{
2344
eb5e029e 2345 struct enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
11e865c1 2346
daca497d 2347 DEBUG("s626_enc_insn_write: encoder write channel %d\n",
0a85b6f0 2348 CR_CHAN(insn->chanspec));
11e865c1 2349
b6c77757 2350 /* Set the preload register */
11e865c1
GP		 2351 Preload(dev, k, data[0]);
2352
b6c77757
BP		 2353 /* Software index pulse forces the preload register to load */
2354 /* into the counter */
11e865c1
GP		 2355 k->SetLoadTrig(dev, k, 0);
2356 k->PulseIndex(dev, k);
2357 k->SetLoadTrig(dev, k, 2);
2358
2359 DEBUG("s626_enc_insn_write: End encoder write\n");
2360
2361 return 1;
2362}
2363
0a85b6f0
MT		 2364static void s626_timer_load(struct comedi_device *dev, struct enc_private *k,
2365 int tick)
11e865c1 2366{
b6c77757 2367 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
0a85b6f0
MT		 2368 /* index. */
2369 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2370 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
2371 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2372 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
2373 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
2374 (CLKENAB_INDEX << BF_CLKENAB);
11e865c1 2375 uint16_t valueSrclatch = LATCHSRC_A_INDXA;
b6c77757 2376 /* uint16_t enab=CLKENAB_ALWAYS; */
11e865c1
GP		 2377
2378 k->SetMode(dev, k, Setup, FALSE);
2379
b6c77757 2380 /* Set the preload register */
11e865c1
GP		 2381 Preload(dev, k, tick);
2382
b6c77757
BP		 2383 /* Software index pulse forces the preload register to load */
2384 /* into the counter */
11e865c1
GP		 2385 k->SetLoadTrig(dev, k, 0);
2386 k->PulseIndex(dev, k);
2387
b6c77757 2388 /* set reload on counter overflow */
11e865c1
GP		 2389 k->SetLoadTrig(dev, k, 1);
2390
b6c77757 2391 /* set interrupt on overflow */
11e865c1
GP		 2392 k->SetIntSrc(dev, k, INTSRC_OVER);
2393
2394 SetLatchSource(dev, k, valueSrclatch);
b6c77757 2395 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */
11e865c1
GP		 2396}
2397
b6c77757 2398/* *********** DAC FUNCTIONS *********** */
11e865c1 2399
b6c77757 2400/* Slot 0 base settings. */
6a98d36e 2401#define VECT0 (XSD2 | RSD3 | SIB_A2)
b6c77757 2402/* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */
11e865c1 2403
b6c77757 2404/* TrimDac LogicalChan-to-PhysicalChan mapping table. */
11e865c1
GP		 2405static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
2406
b6c77757 2407/* TrimDac LogicalChan-to-EepromAdrs mapping table. */
add74595 2408static uint8_t trimadrs[] = { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
11e865c1 2409
71b5f4f1 2410static void LoadTrimDACs(struct comedi_device *dev)
11e865c1
GP		 2411{
2412 register uint8_t i;
2413
b6c77757 2414 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
8629efa4 2415 for (i = 0; i < ARRAY_SIZE(trimchan); i++)
11e865c1
GP		 2416 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
2417}
2418
71b5f4f1 2419static void WriteTrimDAC(struct comedi_device *dev, uint8_t LogicalChan,
0a85b6f0 2420 uint8_t DacData)
11e865c1
GP		 2421{
2422 uint32_t chan;
2423
b6c77757 2424 /* Save the new setpoint in case the application needs to read it back later. */
11e865c1
GP		 2425 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;
2426
b6c77757 2427 /* Map logical channel number to physical channel number. */
11e865c1
GP		 2428 chan = (uint32_t) trimchan[LogicalChan];
2429
b6c77757
BP		 2430 /* Set up TSL2 records for TrimDac write operation. All slots shift
2431 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
2432 * can be detected.
2433 */
2434
2435 SETVECT(2, XSD2 | XFIFO_1 | WS3);
2436 /* Slot 2: Send high uint8_t to target TrimDac. */
2437 SETVECT(3, XSD2 | XFIFO_0 | WS3);
2438 /* Slot 3: Send low uint8_t to target TrimDac. */
2439 SETVECT(4, XSD2 | XFIFO_3 | WS1);
2440 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */
2441 SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS);
2442 /* Slot 5: Send NOP low uint8_t to DAC0. */
2443
2444 /* Construct and transmit target DAC's serial packet:
2445 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
2446 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
2447 * WORD value (that writes a channel 0 NOP command to a non-existent
2448 * main DAC channel) that serves to keep the clock running after the
2449 * packet has been sent to the target DAC.
2450 */
11e865c1 2451
b6c77757
BP		 2452 /* Address the DAC channel within the trimdac device. */
2453 SendDAC(dev, ((uint32_t) chan << 8)
2454 | (uint32_t) DacData); /* Include DAC setpoint data. */
2455}
11e865c1 2456
b6c77757
BP		 2457/* ************** EEPROM ACCESS FUNCTIONS ************** */
2458/* Read uint8_t from EEPROM. */
11e865c1 2459
71b5f4f1 2460static uint8_t I2Cread(struct comedi_device *dev, uint8_t addr)
11e865c1
GP		 2461{
2462 uint8_t rtnval;
2463
b6c77757
BP		 2464 /* Send EEPROM target address. */
2465 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
2466 /* Byte2 = I2C command: write to I2C EEPROM device. */
0a85b6f0 2467 | I2C_B1(I2C_ATTRSTOP, addr)
b6c77757 2468 /* Byte1 = EEPROM internal target address. */
0a85b6f0 2469 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
b6c77757 2470 /* Abort function and declare error if handshake failed. */
11e865c1
GP		 2471 DEBUG("I2Cread: error handshake I2Cread a\n");
2472 return 0;
2473 }
b6c77757 2474 /* Execute EEPROM read. */
0a85b6f0
MT		 2475 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR)
2476
2477 /* Byte2 = I2C */
2478 /* command: read */
2479 /* from I2C EEPROM */
2480 /* device. */
2481 |I2C_B1(I2C_ATTRSTOP, 0)
2482
2483 /* Byte1 receives */
2484 /* uint8_t from */
2485 /* EEPROM. */
2486 |I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
f10fe574 2487
b6c77757 2488 /* Abort function and declare error if handshake failed. */
11e865c1
GP		 2489 DEBUG("I2Cread: error handshake I2Cread b\n");
2490 return 0;
2491 }
b6c77757 2492 /* Return copy of EEPROM value. */
11e865c1
GP		 2493 rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16);
2494 return rtnval;
2495}
2496
71b5f4f1 2497static uint32_t I2Chandshake(struct comedi_device *dev, uint32_t val)
11e865c1 2498{
b6c77757 2499 /* Write I2C command to I2C Transfer Control shadow register. */
11e865c1
GP		 2500 WR7146(P_I2CCTRL, val);
2501
b6c77757
BP		 2502 /* Upload I2C shadow registers into working registers and wait for */
2503 /* upload confirmation. */
11e865c1
GP		 2504
2505 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
add74595 2506 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
ae6eb75c 2507 ;
11e865c1 2508
b6c77757 2509 /* Wait until I2C bus transfer is finished or an error occurs. */
add74595 2510 while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
ae6eb75c 2511 ;
11e865c1 2512
25985edc 2513 /* Return non-zero if I2C error occurred. */
11e865c1
GP		 2514 return RR7146(P_I2CCTRL) & I2C_ERR;
2515
2516}
2517
b6c77757 2518/* Private helper function: Write setpoint to an application DAC channel. */
11e865c1 2519
71b5f4f1 2520static void SetDAC(struct comedi_device *dev, uint16_t chan, short dacdata)
11e865c1
GP		 2521{
2522 register uint16_t signmask;
2523 register uint32_t WSImage;
2524
b6c77757
BP		 2525 /* Adjust DAC data polarity and set up Polarity Control Register */
2526 /* image. */
11e865c1
GP		 2527 signmask = 1 << chan;
2528 if (dacdata < 0) {
2529 dacdata = -dacdata;
2530 devpriv->Dacpol |= signmask;
2531 } else
2532 devpriv->Dacpol &= ~signmask;
2533
b6c77757 2534 /* Limit DAC setpoint value to valid range. */
11e865c1
GP		 2535 if ((uint16_t) dacdata > 0x1FFF)
2536 dacdata = 0x1FFF;
2537
b6c77757
BP		 2538 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
2539 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
2540 * data to a non-existent TrimDac channel just to keep the clock
2541 * running after sending data to the target DAC. This is necessary
2542 * to eliminate the clock glitch that would otherwise occur at the
2543 * end of the target DAC's serial data stream. When the sequence
2544 * restarts at V0 (after executing V5), the gate array automatically
2545 * disables gating for the DAC clock and all DAC chip selects.
2546 */
2547
2548 WSImage = (chan & 2) ? WS1 : WS2;
2549 /* Choose DAC chip select to be asserted. */
2550 SETVECT(2, XSD2 | XFIFO_1 | WSImage);
2551 /* Slot 2: Transmit high data byte to target DAC. */
2552 SETVECT(3, XSD2 | XFIFO_0 | WSImage);
2553 /* Slot 3: Transmit low data byte to target DAC. */
2554 SETVECT(4, XSD2 | XFIFO_3 | WS3);
2555 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
2556 SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS);
2557 /* Slot 5: running after writing target DAC's low data byte. */
2558
2559 /* Construct and transmit target DAC's serial packet:
2560 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
2561 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
2562 * to a non-existent TrimDac channel) that serves to keep the clock
2563 * running after the packet has been sent to the target DAC.
2564 */
2565 SendDAC(dev, 0x0F000000
2566 /* Continue clock after target DAC data (write to non-existent trimdac). */
2567 | 0x00004000
2568 /* Address the two main dual-DAC devices (TSL's chip select enables
2569 * target device). */
2570 | ((uint32_t) (chan & 1) << 15)
2571 /* Address the DAC channel within the device. */
2572 | (uint32_t) dacdata); /* Include DAC setpoint data. */
11e865c1
GP		 2573
2574}
2575
b6c77757
BP		 2576/* Private helper function: Transmit serial data to DAC via Audio
2577 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
2578 * Dacpol contains valid target image.
2579 */
11e865c1 2580
71b5f4f1 2581static void SendDAC(struct comedi_device *dev, uint32_t val)
11e865c1
GP		 2582{
2583
b6c77757 2584 /* START THE SERIAL CLOCK RUNNING ------------- */
11e865c1 2585
b6c77757
BP		 2586 /* Assert DAC polarity control and enable gating of DAC serial clock
2587 * and audio bit stream signals. At this point in time we must be
2588 * assured of being in time slot 0. If we are not in slot 0, the
2589 * serial clock and audio stream signals will be disabled; this is
2590 * because the following DEBIwrite statement (which enables signals
2591 * to be passed through the gate array) would execute before the
2592 * trailing edge of WS1/WS3 (which turns off the signals), thus
2593 * causing the signals to be inactive during the DAC write.
2594 */
11e865c1
GP		 2595 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
2596
b6c77757 2597 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
11e865c1 2598
b6c77757 2599 /* Copy DAC setpoint value to DAC's output DMA buffer. */
11e865c1 2600
b6c77757 2601 /* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */
11e865c1
GP		 2602 *devpriv->pDacWBuf = val;
2603
b6c77757
BP		 2604 /* enab the output DMA transfer. This will cause the DMAC to copy
2605 * the DAC's data value to A2's output FIFO. The DMA transfer will
2606 * then immediately terminate because the protection address is
2607 * reached upon transfer of the first DWORD value.
2608 */
11e865c1
GP		 2609 MC_ENABLE(P_MC1, MC1_A2OUT);
2610
b6c77757 2611 /* While the DMA transfer is executing ... */
11e865c1 2612
b6c77757
BP		 2613 /* Reset Audio2 output FIFO's underflow flag (along with any other
2614 * FIFO underflow/overflow flags). When set, this flag will
2615 * indicate that we have emerged from slot 0.
2616 */
11e865c1
GP		 2617 WR7146(P_ISR, ISR_AFOU);
2618
b6c77757
BP		 2619 /* Wait for the DMA transfer to finish so that there will be data
2620 * available in the FIFO when time slot 1 tries to transfer a DWORD
2621 * from the FIFO to the output buffer register. We test for DMA
2622 * Done by polling the DMAC enable flag; this flag is automatically
2623 * cleared when the transfer has finished.
2624 */
add74595 2625 while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
ae6eb75c 2626 ;
11e865c1 2627
b6c77757 2628 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
11e865c1 2629
b6c77757
BP		 2630 /* FIFO data is now available, so we enable execution of time slots
2631 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
2632 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
2633 * detection.
2634 */
11e865c1
GP		 2635 SETVECT(0, XSD2 | RSD3 | SIB_A2);
2636
b6c77757
BP		 2637 /* Wait for slot 1 to execute to ensure that the Packet will be
2638 * transmitted. This is detected by polling the Audio2 output FIFO
2639 * underflow flag, which will be set when slot 1 execution has
2640 * finished transferring the DAC's data DWORD from the output FIFO
2641 * to the output buffer register.
2642 */
add74595 2643 while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
ae6eb75c 2644 ;
11e865c1 2645
b6c77757
BP		 2646 /* Set up to trap execution at slot 0 when the TSL sequencer cycles
2647 * back to slot 0 after executing the EOS in slot 5. Also,
2648 * simultaneously shift out and in the 0x00 that is ALWAYS the value
2649 * stored in the last byte to be shifted out of the FIFO's DWORD
2650 * buffer register.
2651 */
11e865c1
GP		 2652 SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS);
2653
b6c77757
BP		 2654 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
2655
2656 /* Wait for the TSL to finish executing all time slots before
2657 * exiting this function. We must do this so that the next DAC
2658 * write doesn't start, thereby enabling clock/chip select signals:
2659 *
2660 * 1. Before the TSL sequence cycles back to slot 0, which disables
2661 * the clock/cs signal gating and traps slot // list execution.
2662 * we have not yet finished slot 5 then the clock/cs signals are
2663 * still gated and we have not finished transmitting the stream.
2664 *
2665 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
2666 * this case, the slot sequence is currently repeating, but with
2667 * clock/cs signals disabled. We must wait for slot 0 to trap
2668 * execution before setting up the next DAC setpoint DMA transfer
2669 * and enabling the clock/cs signals. To detect the end of slot 5,
2670 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
2671 * the TSL has not yet finished executing slot 5 ...
2672 */
11e865c1 2673 if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) {
b6c77757
BP		 2674 /* The trap was set on time and we are still executing somewhere
2675 * in slots 2-5, so we now wait for slot 0 to execute and trap
2676 * TSL execution. This is detected when FB_BUFFER2 MSB changes
2677 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
2678 * out/in on SD2 the 0x00 that is always referenced by slot 5.
2679 */
add74595 2680 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
ae6eb75c 2681 ;
11e865c1 2682 }
b6c77757
BP		 2683 /* Either (1) we were too late setting the slot 0 trap; the TSL
2684 * sequencer restarted slot 0 before we could set the EOS trap flag,
2685 * or (2) we were not late and execution is now trapped at slot 0.
2686 * In either case, we must now change slot 0 so that it will store
2687 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
2688 * In order to do this, we reprogram slot 0 so that it will shift in
2689 * SD3, which is driven only by a pull-up resistor.
2690 */
11e865c1
GP		 2691 SETVECT(0, RSD3 | SIB_A2 | EOS);
2692
b6c77757
BP		 2693 /* Wait for slot 0 to execute, at which time the TSL is setup for
2694 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
2695 * from 0x00 to 0xFF.
2696 */
add74595 2697 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
ae6eb75c 2698 ;
11e865c1
GP		 2699}
2700
71b5f4f1 2701static void WriteMISC2(struct comedi_device *dev, uint16_t NewImage)
11e865c1 2702{
b6c77757
BP		 2703 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */
2704 /* MISC2 register. */
2705 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
2706 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */
11e865c1
GP		 2707}
2708
b6c77757 2709/* Initialize the DEBI interface for all transfers. */
11e865c1 2710
71b5f4f1 2711static uint16_t DEBIread(struct comedi_device *dev, uint16_t addr)
11e865c1
GP		 2712{
2713 uint16_t retval;
2714
b6c77757 2715 /* Set up DEBI control register value in shadow RAM. */
11e865c1
GP		 2716 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2717
b6c77757 2718 /* Execute the DEBI transfer. */
11e865c1
GP		 2719 DEBItransfer(dev);
2720
b6c77757 2721 /* Fetch target register value. */
11e865c1
GP		 2722 retval = (uint16_t) RR7146(P_DEBIAD);
2723
b6c77757 2724 /* Return register value. */
11e865c1
GP		 2725 return retval;
2726}
2727
b6c77757
BP		 2728/* Execute a DEBI transfer. This must be called from within a */
2729/* critical section. */
71b5f4f1 2730static void DEBItransfer(struct comedi_device *dev)
11e865c1 2731{
b6c77757 2732 /* Initiate upload of shadow RAM to DEBI control register. */
11e865c1
GP		 2733 MC_ENABLE(P_MC2, MC2_UPLD_DEBI);
2734
b6c77757
BP		 2735 /* Wait for completion of upload from shadow RAM to DEBI control */
2736 /* register. */
add74595 2737 while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
ae6eb75c 2738 ;
11e865c1 2739
b6c77757 2740 /* Wait until DEBI transfer is done. */
add74595 2741 while (RR7146(P_PSR) & PSR_DEBI_S)
ae6eb75c 2742 ;
11e865c1
GP		 2743}
2744
b6c77757 2745/* Write a value to a gate array register. */
71b5f4f1 2746static void DEBIwrite(struct comedi_device *dev, uint16_t addr, uint16_t wdata)
11e865c1
GP		 2747{
2748
b6c77757 2749 /* Set up DEBI control register value in shadow RAM. */
11e865c1
GP		 2750 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2751 WR7146(P_DEBIAD, wdata);
2752
b6c77757 2753 /* Execute the DEBI transfer. */
11e865c1
GP		 2754 DEBItransfer(dev);
2755}
2756
b6c77757
BP		 2757/* Replace the specified bits in a gate array register. Imports: mask
2758 * specifies bits that are to be preserved, wdata is new value to be
2759 * or'd with the masked original.
2760 */
71b5f4f1 2761static void DEBIreplace(struct comedi_device *dev, uint16_t addr, uint16_t mask,
0a85b6f0 2762 uint16_t wdata)
11e865c1
GP		 2763{
2764
b6c77757
BP		 2765 /* Copy target gate array register into P_DEBIAD register. */
2766 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2767 /* Set up DEBI control reg value in shadow RAM. */
2768 DEBItransfer(dev); /* Execute the DEBI Read transfer. */
11e865c1 2769
b6c77757
BP		 2770 /* Write back the modified image. */
2771 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2772 /* Set up DEBI control reg value in shadow RAM. */
11e865c1 2773
b6c77757
BP		 2774 WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
2775 /* Modify the register image. */
2776 DEBItransfer(dev); /* Execute the DEBI Write transfer. */
11e865c1
GP		 2777}
2778
0a85b6f0
MT		 2779static void CloseDMAB(struct comedi_device *dev, struct bufferDMA *pdma,
2780 size_t bsize)
11e865c1
GP		 2781{
2782 void *vbptr;
2783 dma_addr_t vpptr;
2784
2785 DEBUG("CloseDMAB: Entering S626DRV_CloseDMAB():\n");
2786 if (pdma == NULL)
2787 return;
b6c77757 2788 /* find the matching allocation from the board struct */
11e865c1
GP		 2789
2790 vbptr = pdma->LogicalBase;
2791 vpptr = pdma->PhysicalBase;
2792 if (vbptr) {
2793 pci_free_consistent(devpriv->pdev, bsize, vbptr, vpptr);
2794 pdma->LogicalBase = 0;
2795 pdma->PhysicalBase = 0;
2796
2797 DEBUG("CloseDMAB(): Logical=%p, bsize=%d, Physical=0x%x\n",
0a85b6f0 2798 vbptr, bsize, (uint32_t) vpptr);
11e865c1
GP		 2799 }
2800}
2801
b6c77757
BP		 2802/* ****** COUNTER FUNCTIONS ******* */
2803/* All counter functions address a specific counter by means of the
2804 * "Counter" argument, which is a logical counter number. The Counter
2805 * argument may have any of the following legal values: 0=0A, 1=1A,
2806 * 2=2A, 3=0B, 4=1B, 5=2B.
2807 */
11e865c1 2808
b6c77757 2809/* Forward declarations for functions that are common to both A and B counters: */
11e865c1 2810
b6c77757 2811/* ****** PRIVATE COUNTER FUNCTIONS ****** */
11e865c1 2812
b6c77757 2813/* Read a counter's output latch. */
11e865c1 2814
71b5f4f1 2815static uint32_t ReadLatch(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2816{
2817 register uint32_t value;
b6c77757 2818 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch enter\n"); */
11e865c1 2819
b6c77757 2820 /* Latch counts and fetch LSW of latched counts value. */
11e865c1
GP		 2821 value = (uint32_t) DEBIread(dev, k->MyLatchLsw);
2822
b6c77757 2823 /* Fetch MSW of latched counts and combine with LSW. */
11e865c1
GP		 2824 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);
2825
b6c77757 2826 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch exit\n"); */
11e865c1 2827
b6c77757 2828 /* Return latched counts. */
11e865c1
GP		 2829 return value;
2830}
2831
b6c77757 2832/* Reset a counter's index and overflow event capture flags. */
11e865c1 2833
71b5f4f1 2834static void ResetCapFlags_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2835{
2836 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
0a85b6f0 2837 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
11e865c1
GP		 2838}
2839
71b5f4f1 2840static void ResetCapFlags_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2841{
2842 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
0a85b6f0 2843 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B);
11e865c1
GP		 2844}
2845
b6c77757
BP		 2846/* Return counter setup in a format (COUNTER_SETUP) that is consistent */
2847/* for both A and B counters. */
11e865c1 2848
71b5f4f1 2849static uint16_t GetMode_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2850{
2851 register uint16_t cra;
2852 register uint16_t crb;
2853 register uint16_t setup;
2854
b6c77757 2855 /* Fetch CRA and CRB register images. */
11e865c1
GP		 2856 cra = DEBIread(dev, k->MyCRA);
2857 crb = DEBIread(dev, k->MyCRB);
2858
b6c77757
BP		 2859 /* Populate the standardized counter setup bit fields. Note: */
2860 /* IndexSrc is restricted to ENC_X or IndxPol. */
2861 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */
0a85b6f0
MT		 2862 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */
2863 |((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */
2864 |((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */
2865 |((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */
2866 |((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */
b6c77757
BP		 2867
2868 /* Adjust mode-dependent parameters. */
2869 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */
2870 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
0a85b6f0
MT		 2871 |((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */
2872 |(MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */
b6c77757
BP		 2873
2874 else /* If Counter mode (ClkSrcA<1> == 0): */
2875 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */
0a85b6f0
MT		 2876 |((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */
2877 |(((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */
2878 (MULT_X1 << STDBIT_CLKMULT) :
2879 ((cra >> (CRABIT_CLKMULT_A -
2880 STDBIT_CLKMULT)) & STDMSK_CLKMULT)));
11e865c1 2881
b6c77757 2882 /* Return adjusted counter setup. */
11e865c1
GP		 2883 return setup;
2884}
2885
71b5f4f1 2886static uint16_t GetMode_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 2887{
2888 register uint16_t cra;
2889 register uint16_t crb;
2890 register uint16_t setup;
2891
b6c77757 2892 /* Fetch CRA and CRB register images. */
11e865c1
GP		 2893 cra = DEBIread(dev, k->MyCRA);
2894 crb = DEBIread(dev, k->MyCRB);
2895
b6c77757
BP		 2896 /* Populate the standardized counter setup bit fields. Note: */
2897 /* IndexSrc is restricted to ENC_X or IndxPol. */
2898 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */
0a85b6f0
MT		 2899 |((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */
2900 |((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */
2901 |((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */
2902 |((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */
2903 |((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */
b6c77757
BP		 2904
2905 /* Adjust mode-dependent parameters. */
2906 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */
2907 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */
0a85b6f0
MT		 2908 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2909 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
b6c77757
BP		 2910
2911 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */
2912 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
0a85b6f0
MT		 2913 |(MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2914 |((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
b6c77757
BP		 2915
2916 else /* If Counter mode (ClkSrcB<1> == 0): */
2917 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */
0a85b6f0
MT		 2918 |((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */
2919 |((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */
b6c77757
BP		 2920
2921 /* Return adjusted counter setup. */
11e865c1
GP		 2922 return setup;
2923}
2924
b6c77757
BP		 2925/*
2926 * Set the operating mode for the specified counter. The setup
2927 * parameter is treated as a COUNTER_SETUP data type. The following
2928 * parameters are programmable (all other parms are ignored): ClkMult,
2929 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
2930 */
11e865c1 2931
0a85b6f0
MT		 2932static void SetMode_A(struct comedi_device *dev, struct enc_private *k,
2933 uint16_t Setup, uint16_t DisableIntSrc)
11e865c1
GP		 2934{
2935 register uint16_t cra;
2936 register uint16_t crb;
b6c77757 2937 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 2938
b6c77757
BP		 2939 /* Initialize CRA and CRB images. */
2940 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */
0a85b6f0 2941 |((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */
11e865c1 2942
b6c77757 2943 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */
0a85b6f0 2944 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */
11e865c1 2945
b6c77757 2946 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
11e865c1
GP		 2947 if (!DisableIntSrc)
2948 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
0a85b6f0 2949 CRABIT_INTSRC_A));
11e865c1 2950
b6c77757 2951 /* Populate all mode-dependent attributes of CRA & CRB images. */
11e865c1 2952 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
b6c77757
BP		 2953 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */
2954 /* (Extender valid only for B counters). */
2955
2956 case CLKSRC_TIMER: /* Timer Mode: */
2957 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */
0a85b6f0
MT		 2958 |((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */
2959 |(1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */
2960 |(MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */
11e865c1
GP		 2961 break;
2962
b6c77757
BP		 2963 default: /* Counter Mode: */
2964 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */
2965 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */
0a85b6f0
MT		 2966 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */
2967 (MULT_X1 << CRABIT_CLKMULT_A) :
2968 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A -
2969 STDBIT_CLKMULT))));
11e865c1
GP		 2970 }
2971
b6c77757
BP		 2972 /* Force positive index polarity if IndxSrc is software-driven only, */
2973 /* otherwise pass it through. */
11e865c1
GP		 2974 if (~setup & STDMSK_INDXSRC)
2975 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A -
0a85b6f0 2976 STDBIT_INDXPOL));
11e865c1 2977
b6c77757
BP		 2978 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
2979 /* enable mask to indicate the counter interrupt is disabled. */
11e865c1
GP		 2980 if (DisableIntSrc)
2981 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
2982
b6c77757
BP		 2983 /* While retaining CounterB and LatchSrc configurations, program the */
2984 /* new counter operating mode. */
11e865c1
GP		 2985 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
2986 DEBIreplace(dev, k->MyCRB,
0a85b6f0 2987 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), crb);
11e865c1
GP		 2988}
2989
0a85b6f0
MT		 2990static void SetMode_B(struct comedi_device *dev, struct enc_private *k,
2991 uint16_t Setup, uint16_t DisableIntSrc)
11e865c1
GP		 2992{
2993 register uint16_t cra;
2994 register uint16_t crb;
b6c77757 2995 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 2996
b6c77757
BP		 2997 /* Initialize CRA and CRB images. */
2998 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */
11e865c1 2999
b6c77757 3000 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */
0a85b6f0
MT		 3001 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */
3002 |((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */
11e865c1 3003
b6c77757 3004 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
11e865c1
GP		 3005 if (!DisableIntSrc)
3006 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
0a85b6f0 3007 CRBBIT_INTSRC_B));
11e865c1 3008
b6c77757 3009 /* Populate all mode-dependent attributes of CRA & CRB images. */
11e865c1 3010 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
b6c77757
BP		 3011 case CLKSRC_TIMER: /* Timer Mode: */
3012 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */
0a85b6f0 3013 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */
b6c77757 3014 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */
0a85b6f0 3015 |(MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */
11e865c1
GP		 3016 break;
3017
b6c77757
BP		 3018 case CLKSRC_EXTENDER: /* Extender Mode: */
3019 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */
0a85b6f0 3020 |((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */
b6c77757 3021 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */
0a85b6f0 3022 |(MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */
11e865c1
GP		 3023 break;
3024
b6c77757
BP		 3025 default: /* Counter Mode: */
3026 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */
3027 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */
0a85b6f0
MT		 3028 |(((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */
3029 (MULT_X1 << CRBBIT_CLKMULT_B) :
3030 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B -
3031 STDBIT_CLKMULT))));
11e865c1
GP		 3032 }
3033
b6c77757
BP		 3034 /* Force positive index polarity if IndxSrc is software-driven only, */
3035 /* otherwise pass it through. */
11e865c1
GP		 3036 if (~setup & STDMSK_INDXSRC)
3037 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL -
0a85b6f0 3038 CRBBIT_INDXPOL_B));
11e865c1 3039
b6c77757
BP		 3040 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
3041 /* enable mask to indicate the counter interrupt is disabled. */
11e865c1
GP		 3042 if (DisableIntSrc)
3043 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
3044
b6c77757
BP		 3045 /* While retaining CounterA and LatchSrc configurations, program the */
3046 /* new counter operating mode. */
11e865c1 3047 DEBIreplace(dev, k->MyCRA,
0a85b6f0 3048 (uint16_t) (~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B)), cra);
11e865c1
GP		 3049 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
3050}
3051
b6c77757 3052/* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */
11e865c1 3053
0a85b6f0
MT		 3054static void SetEnable_A(struct comedi_device *dev, struct enc_private *k,
3055 uint16_t enab)
11e865c1
GP		 3056{
3057 DEBUG("SetEnable_A: SetEnable_A enter 3541\n");
3058 DEBIreplace(dev, k->MyCRB,
0a85b6f0
MT		 3059 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)),
3060 (uint16_t) (enab << CRBBIT_CLKENAB_A));
11e865c1
GP		 3061}
3062
0a85b6f0
MT		 3063static void SetEnable_B(struct comedi_device *dev, struct enc_private *k,
3064 uint16_t enab)
11e865c1
GP		 3065{
3066 DEBIreplace(dev, k->MyCRB,
0a85b6f0
MT		 3067 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B)),
3068 (uint16_t) (enab << CRBBIT_CLKENAB_B));
11e865c1
GP		 3069}
3070
71b5f4f1 3071static uint16_t GetEnable_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3072{
3073 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1;
3074}
3075
71b5f4f1 3076static uint16_t GetEnable_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3077{
3078 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1;
3079}
3080
b6c77757
BP		 3081/* Return/set a counter pair's latch trigger source. 0: On read
3082 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
3083 * latches B.
3084 */
11e865c1 3085
0a85b6f0
MT		 3086static void SetLatchSource(struct comedi_device *dev, struct enc_private *k,
3087 uint16_t value)
11e865c1 3088{
daca497d 3089 DEBUG("SetLatchSource: SetLatchSource enter 3550\n");
11e865c1 3090 DEBIreplace(dev, k->MyCRB,
0a85b6f0
MT		 3091 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC)),
3092 (uint16_t) (value << CRBBIT_LATCHSRC));
11e865c1 3093
daca497d 3094 DEBUG("SetLatchSource: SetLatchSource exit\n");
11e865c1
GP		 3095}
3096
b6c77757 3097/*
71b5f4f1 3098 * static uint16_t GetLatchSource(struct comedi_device *dev, struct enc_private *k )
b6c77757 3099 * {
ae6eb75c 3100 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3;
b6c77757
BP		 3101 * }
3102 */
11e865c1 3103
b6c77757
BP		 3104/*
3105 * Return/set the event that will trigger transfer of the preload
3106 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
3107 * 2=OverflowA (B counters only), 3=disabled.
3108 */
11e865c1 3109
0a85b6f0
MT		 3110static void SetLoadTrig_A(struct comedi_device *dev, struct enc_private *k,
3111 uint16_t Trig)
11e865c1
GP		 3112{
3113 DEBIreplace(dev, k->MyCRA, (uint16_t) (~CRAMSK_LOADSRC_A),
0a85b6f0 3114 (uint16_t) (Trig << CRABIT_LOADSRC_A));
11e865c1
GP		 3115}
3116
0a85b6f0
MT		 3117static void SetLoadTrig_B(struct comedi_device *dev, struct enc_private *k,
3118 uint16_t Trig)
11e865c1
GP		 3119{
3120 DEBIreplace(dev, k->MyCRB,
0a85b6f0
MT		 3121 (uint16_t) (~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL)),
3122 (uint16_t) (Trig << CRBBIT_LOADSRC_B));
11e865c1
GP		 3123}
3124
71b5f4f1 3125static uint16_t GetLoadTrig_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3126{
3127 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3;
3128}
3129
71b5f4f1 3130static uint16_t GetLoadTrig_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3131{
3132 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3;
3133}
3134
b6c77757
BP		 3135/* Return/set counter interrupt source and clear any captured
3136 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
3137 * 2=IndexOnly, 3=IndexAndOverflow.
3138 */
11e865c1 3139
71b5f4f1 3140static void SetIntSrc_A(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 3141 uint16_t IntSource)
11e865c1 3142{
b6c77757 3143 /* Reset any pending counter overflow or index captures. */
11e865c1 3144 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
0a85b6f0 3145 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
11e865c1 3146
b6c77757 3147 /* Program counter interrupt source. */
11e865c1 3148 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A,
0a85b6f0 3149 (uint16_t) (IntSource << CRABIT_INTSRC_A));
11e865c1 3150
b6c77757 3151 /* Update MISC2 interrupt enable mask. */
11e865c1 3152 devpriv->CounterIntEnabs =
0a85b6f0
MT		 3153 (devpriv->CounterIntEnabs & ~k->
3154 MyEventBits[3]) | k->MyEventBits[IntSource];
11e865c1
GP		 3155}
3156
71b5f4f1 3157static void SetIntSrc_B(struct comedi_device *dev, struct enc_private *k,
0a85b6f0 3158 uint16_t IntSource)
11e865c1
GP		 3159{
3160 uint16_t crb;
3161
b6c77757 3162 /* Cache writeable CRB register image. */
11e865c1
GP		 3163 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL;
3164
b6c77757 3165 /* Reset any pending counter overflow or index captures. */
11e865c1 3166 DEBIwrite(dev, k->MyCRB,
0a85b6f0 3167 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B));
11e865c1 3168
b6c77757 3169 /* Program counter interrupt source. */
11e865c1 3170 DEBIwrite(dev, k->MyCRB,
0a85b6f0
MT		 3171 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource <<
3172 CRBBIT_INTSRC_B)));
11e865c1 3173
b6c77757 3174 /* Update MISC2 interrupt enable mask. */
11e865c1 3175 devpriv->CounterIntEnabs =
0a85b6f0
MT		 3176 (devpriv->CounterIntEnabs & ~k->
3177 MyEventBits[3]) | k->MyEventBits[IntSource];
11e865c1
GP		 3178}
3179
71b5f4f1 3180static uint16_t GetIntSrc_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3181{
3182 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3;
3183}
3184
71b5f4f1 3185static uint16_t GetIntSrc_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3186{
3187 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3;
3188}
3189
b6c77757 3190/* Return/set the clock multiplier. */
11e865c1 3191
71b5f4f1 3192/* static void SetClkMult(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3193/* { */
3194/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */
3195/* } */
3196
71b5f4f1 3197/* static uint16_t GetClkMult(struct comedi_device *dev, struct enc_private *k ) */
11e865c1
GP		 3198/* { */
3199/* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */
3200/* } */
3201
b6c77757 3202/* Return/set the clock polarity. */
11e865c1 3203
71b5f4f1 3204/* static void SetClkPol( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3205/* { */
3206/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */
3207/* } */
3208
71b5f4f1 3209/* static uint16_t GetClkPol(struct comedi_device *dev, struct enc_private *k ) */
11e865c1
GP		 3210/* { */
3211/* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */
3212/* } */
3213
b6c77757 3214/* Return/set the clock source. */
11e865c1 3215
71b5f4f1 3216/* static void SetClkSrc( struct comedi_device *dev,struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3217/* { */
3218/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */
3219/* } */
3220
71b5f4f1 3221/* static uint16_t GetClkSrc( struct comedi_device *dev,struct enc_private *k ) */
11e865c1
GP		 3222/* { */
3223/* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */
3224/* } */
3225
b6c77757 3226/* Return/set the index polarity. */
11e865c1 3227
71b5f4f1 3228/* static void SetIndexPol(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3229/* { */
3230/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */
3231/* } */
3232
71b5f4f1 3233/* static uint16_t GetIndexPol(struct comedi_device *dev, struct enc_private *k ) */
11e865c1
GP		 3234/* { */
3235/* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */
3236/* } */
3237
b6c77757 3238/* Return/set the index source. */
11e865c1 3239
71b5f4f1 3240/* static void SetIndexSrc(struct comedi_device *dev, struct enc_private *k, uint16_t value ) */
11e865c1
GP		 3241/* { */
3242/* DEBUG("SetIndexSrc: set index src enter 3700\n"); */
3243/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */
3244/* } */
3245
71b5f4f1 3246/* static uint16_t GetIndexSrc(struct comedi_device *dev, struct enc_private *k ) */
11e865c1
GP		 3247/* { */
3248/* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */
3249/* } */
3250
b6c77757 3251/* Generate an index pulse. */
11e865c1 3252
71b5f4f1 3253static void PulseIndex_A(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3254{
3255 register uint16_t cra;
3256
3257 DEBUG("PulseIndex_A: pulse index enter\n");
3258
b6c77757 3259 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */
11e865c1
GP		 3260 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A));
3261 DEBUG("PulseIndex_A: pulse index step1\n");
3262 DEBIwrite(dev, k->MyCRA, cra);
3263}
3264
71b5f4f1 3265static void PulseIndex_B(struct comedi_device *dev, struct enc_private *k)
11e865c1
GP		 3266{
3267 register uint16_t crb;
3268
b6c77757 3269 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */
11e865c1
GP		 3270 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B));
3271 DEBIwrite(dev, k->MyCRB, crb);
3272}
3273
b6c77757 3274/* Write value into counter preload register. */
11e865c1 3275
0a85b6f0
MT		 3276static void Preload(struct comedi_device *dev, struct enc_private *k,
3277 uint32_t value)
11e865c1
GP		 3278{
3279 DEBUG("Preload: preload enter\n");
b6c77757 3280 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value); /* Write value to preload register. */
11e865c1
GP		 3281 DEBUG("Preload: preload step 1\n");
3282 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
0a85b6f0 3283 (uint16_t) (value >> 16));
11e865c1
GP		 3284}
3285
71b5f4f1 3286static void CountersInit(struct comedi_device *dev)
11e865c1
GP		 3287{
3288 int chan;
eb5e029e 3289 struct enc_private *k;
b6c77757 3290 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
0a85b6f0
MT		 3291 /* index. */
3292 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
3293 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
3294 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
3295 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */
3296 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
3297 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */
b6c77757
BP		 3298
3299 /* Disable all counter interrupts and clear any captured counter events. */
11e865c1
GP		 3300 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
3301 k = &encpriv[chan];
3302 k->SetMode(dev, k, Setup, TRUE);
3303 k->SetIntSrc(dev, k, 0);
3304 k->ResetCapFlags(dev, k);
3305 k->SetEnable(dev, k, CLKENAB_ALWAYS);
3306 }
daca497d 3307 DEBUG("CountersInit: counters initialized\n");
11e865c1
GP		 3308
3309}
7122b76d 3310
75e6301b 3311static struct comedi_driver s626_driver = {
7122b76d
HS		 3312 .driver_name = "s626",
3313 .module = THIS_MODULE,
3314 .attach = s626_attach,
3315 .detach = s626_detach,
3316};
3317
75e6301b
HS		 3318static int __devinit s626_pci_probe(struct pci_dev *dev,
3319 const struct pci_device_id *ent)
7122b76d 3320{
75e6301b 3321 return comedi_pci_auto_config(dev, &s626_driver);
7122b76d
HS		 3322}
3323
75e6301b 3324static void __devexit s626_pci_remove(struct pci_dev *dev)
7122b76d
HS		 3325{
3326 comedi_pci_auto_unconfig(dev);
3327}
3328
3329/*
3330 * For devices with vendor:device id == 0x1131:0x7146 you must specify
3331 * also subvendor:subdevice ids, because otherwise it will conflict with
3332 * Philips SAA7146 media/dvb based cards.
3333 */
3334static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
3335 { PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626,
3336 PCI_SUBVENDOR_ID_S626, PCI_SUBDEVICE_ID_S626, 0, 0, 0 },
3337 { 0 }
3338};
3339MODULE_DEVICE_TABLE(pci, s626_pci_table);
3340
75e6301b
HS		 3341static struct pci_driver s626_pci_driver = {
3342 .name = "s626",
7122b76d 3343 .id_table = s626_pci_table,
75e6301b
HS		 3344 .probe = s626_pci_probe,
3345 .remove = __devexit_p(s626_pci_remove),
7122b76d 3346};
75e6301b 3347module_comedi_pci_driver(s626_driver, s626_pci_driver);
7122b76d
HS		 3348
3349MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
3350MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
3351MODULE_LICENSE("GPL");
Linux kernel - Deliverables
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