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Staging: comedi: Fix cases of open curly on wrong line
[deliverable/linux.git] / drivers / staging / comedi / drivers / s626.c
CommitLineData
11e865c1
GP		 1/*
2 comedi/drivers/s626.c
3 Sensoray s626 Comedi driver
4
5 COMEDI - Linux Control and Measurement Device Interface
6 Copyright (C) 2000 David A. Schleef <ds@schleef.org>
7
8 Based on Sensoray Model 626 Linux driver Version 0.2
9 Copyright (C) 2002-2004 Sensoray Co., Inc.
10
11 This program is free software; you can redistribute it and/or modify
12 it under the terms of the GNU General Public License as published by
13 the Free Software Foundation; either version 2 of the License, or
14 (at your option) any later version.
15
16 This program is distributed in the hope that it will be useful,
17 but WITHOUT ANY WARRANTY; without even the implied warranty of
18 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 GNU General Public License for more details.
20
21 You should have received a copy of the GNU General Public License
22 along with this program; if not, write to the Free Software
23 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24
25*/
26
27/*
28Driver: s626
29Description: Sensoray 626 driver
30Devices: [Sensoray] 626 (s626)
31Authors: Gianluca Palli <gpalli@deis.unibo.it>,
32Updated: Fri, 15 Feb 2008 10:28:42 +0000
33Status: experimental
34
35Configuration options:
36 [0] - PCI bus of device (optional)
37 [1] - PCI slot of device (optional)
38 If bus/slot is not specified, the first supported
39 PCI device found will be used.
40
41INSN_CONFIG instructions:
42 analog input:
43 none
44
45 analog output:
46 none
47
48 digital channel:
49 s626 has 3 dio subdevices (2,3 and 4) each with 16 i/o channels
50 supported configuration options:
51 INSN_CONFIG_DIO_QUERY
52 COMEDI_INPUT
53 COMEDI_OUTPUT
54
55 encoder:
56 Every channel must be configured before reading.
57
58 Example code
59
60 insn.insn=INSN_CONFIG; //configuration instruction
61 insn.n=1; //number of operation (must be 1)
62 insn.data=&initialvalue; //initial value loaded into encoder
63 //during configuration
64 insn.subdev=5; //encoder subdevice
65 insn.chanspec=CR_PACK(encoder_channel,0,AREF_OTHER); //encoder_channel
66 //to configure
67
68 comedi_do_insn(cf,&insn); //executing configuration
69*/
70
71#include <linux/kernel.h>
72#include <linux/types.h>
73
74#include "../comedidev.h"
75
76#include "comedi_pci.h"
77
78#include "comedi_fc.h"
79#include "s626.h"
80
81MODULE_AUTHOR("Gianluca Palli <gpalli@deis.unibo.it>");
82MODULE_DESCRIPTION("Sensoray 626 Comedi driver module");
83MODULE_LICENSE("GPL");
84
85typedef struct s626_board_struct {
86 const char *name;
87 int ai_chans;
88 int ai_bits;
89 int ao_chans;
90 int ao_bits;
91 int dio_chans;
92 int dio_banks;
93 int enc_chans;
94} s626_board;
95
96static const s626_board s626_boards[] = {
97 {
98 name: "s626",
f7266a48 99 ai_chans : S626_ADC_CHANNELS,
11e865c1 100 ai_bits: 14,
f7266a48 101 ao_chans : S626_DAC_CHANNELS,
11e865c1 102 ao_bits: 13,
f7266a48
BP		 103 dio_chans : S626_DIO_CHANNELS,
104 dio_banks : S626_DIO_BANKS,
105 enc_chans : S626_ENCODER_CHANNELS,
11e865c1
GP		 106 }
107};
108
109#define thisboard ((const s626_board *)dev->board_ptr)
110#define PCI_VENDOR_ID_S626 0x1131
111#define PCI_DEVICE_ID_S626 0x7146
112
113static DEFINE_PCI_DEVICE_TABLE(s626_pci_table) = {
114 {PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
115 0},
116 {0}
117};
118
119MODULE_DEVICE_TABLE(pci, s626_pci_table);
120
e473e912
BP		 121static int s626_attach(comedi_device *dev, comedi_devconfig *it);
122static int s626_detach(comedi_device *dev);
11e865c1
GP		 123
124static comedi_driver driver_s626 = {
125 driver_name:"s626",
f7266a48
BP		 126 module : THIS_MODULE,
127 attach : s626_attach,
128 detach : s626_detach,
11e865c1
GP		 129};
130
131typedef struct {
132 struct pci_dev *pdev;
133 void *base_addr;
134 int got_regions;
135 short allocatedBuf;
b6c77757
BP		 136 uint8_t ai_cmd_running; /* ai_cmd is running */
137 uint8_t ai_continous; /* continous aquisition */
138 int ai_sample_count; /* number of samples to aquire */
139 unsigned int ai_sample_timer;
140 /* time between samples in units of the timer */
141 int ai_convert_count; /* conversion counter */
142 unsigned int ai_convert_timer;
143 /* time between conversion in units of the timer */
144 uint16_t CounterIntEnabs;
145 /* Counter interrupt enable mask for MISC2 register. */
146 uint8_t AdcItems; /* Number of items in ADC poll list. */
147 DMABUF RPSBuf; /* DMA buffer used to hold ADC (RPS1) program. */
148 DMABUF ANABuf;
149 /* DMA buffer used to receive ADC data and hold DAC data. */
150 uint32_t *pDacWBuf;
151 /* Pointer to logical adrs of DMA buffer used to hold DAC data. */
152 uint16_t Dacpol; /* Image of DAC polarity register. */
153 uint8_t TrimSetpoint[12]; /* Images of TrimDAC setpoints */
154 uint16_t ChargeEnabled; /* Image of MISC2 Battery */
155 /* Charge Enabled (0 or WRMISC2_CHARGE_ENABLE). */
156 uint16_t WDInterval; /* Image of MISC2 watchdog interval control bits. */
157 uint32_t I2CAdrs;
158 /* I2C device address for onboard EEPROM (board rev dependent). */
159 /* short I2Cards; */
11e865c1
GP		 160 lsampl_t ao_readback[S626_DAC_CHANNELS];
161} s626_private;
162
163typedef struct {
164 uint16_t RDDIn;
165 uint16_t WRDOut;
166 uint16_t RDEdgSel;
167 uint16_t WREdgSel;
168 uint16_t RDCapSel;
169 uint16_t WRCapSel;
170 uint16_t RDCapFlg;
171 uint16_t RDIntSel;
172 uint16_t WRIntSel;
173} dio_private;
174
175static dio_private dio_private_A = {
176 RDDIn:LP_RDDINA,
f7266a48
BP		 177 WRDOut : LP_WRDOUTA,
178 RDEdgSel : LP_RDEDGSELA,
179 WREdgSel : LP_WREDGSELA,
180 RDCapSel : LP_RDCAPSELA,
181 WRCapSel : LP_WRCAPSELA,
182 RDCapFlg : LP_RDCAPFLGA,
183 RDIntSel : LP_RDINTSELA,
184 WRIntSel : LP_WRINTSELA,
11e865c1
GP		 185};
186
187static dio_private dio_private_B = {
188 RDDIn:LP_RDDINB,
f7266a48
BP		 189 WRDOut : LP_WRDOUTB,
190 RDEdgSel : LP_RDEDGSELB,
191 WREdgSel : LP_WREDGSELB,
192 RDCapSel : LP_RDCAPSELB,
193 WRCapSel : LP_WRCAPSELB,
194 RDCapFlg : LP_RDCAPFLGB,
195 RDIntSel : LP_RDINTSELB,
196 WRIntSel : LP_WRINTSELB,
11e865c1
GP		 197};
198
199static dio_private dio_private_C = {
200 RDDIn:LP_RDDINC,
f7266a48
BP		 201 WRDOut : LP_WRDOUTC,
202 RDEdgSel : LP_RDEDGSELC,
203 WREdgSel : LP_WREDGSELC,
204 RDCapSel : LP_RDCAPSELC,
205 WRCapSel : LP_WRCAPSELC,
206 RDCapFlg : LP_RDCAPFLGC,
207 RDIntSel : LP_RDINTSELC,
208 WRIntSel : LP_WRINTSELC,
11e865c1
GP		 209};
210
211/* to group dio devices (48 bits mask and data are not allowed ???)
212static dio_private *dio_private_word[]={
213 &dio_private_A,
214 &dio_private_B,
215 &dio_private_C,
216};
217*/
218
219#define devpriv ((s626_private *)dev->private)
220#define diopriv ((dio_private *)s->private)
221
222COMEDI_PCI_INITCLEANUP_NOMODULE(driver_s626, s626_pci_table);
223
b6c77757 224/* ioctl routines */
e473e912
BP		 225static int s626_ai_insn_config(comedi_device *dev, comedi_subdevice *s,
226 comedi_insn *insn, lsampl_t *data);
11e865c1 227/* static int s626_ai_rinsn(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data); */
e473e912
BP		 228static int s626_ai_insn_read(comedi_device *dev, comedi_subdevice *s,
229 comedi_insn *insn, lsampl_t *data);
230static int s626_ai_cmd(comedi_device *dev, comedi_subdevice *s);
231static int s626_ai_cmdtest(comedi_device *dev, comedi_subdevice *s,
232 comedi_cmd *cmd);
233static int s626_ai_cancel(comedi_device *dev, comedi_subdevice *s);
234static int s626_ao_winsn(comedi_device *dev, comedi_subdevice *s,
235 comedi_insn *insn, lsampl_t *data);
236static int s626_ao_rinsn(comedi_device *dev, comedi_subdevice *s,
237 comedi_insn *insn, lsampl_t *data);
238static int s626_dio_insn_bits(comedi_device *dev, comedi_subdevice *s,
239 comedi_insn *insn, lsampl_t *data);
240static int s626_dio_insn_config(comedi_device *dev, comedi_subdevice *s,
241 comedi_insn *insn, lsampl_t *data);
242static int s626_dio_set_irq(comedi_device *dev, unsigned int chan);
243static int s626_dio_reset_irq(comedi_device *dev, unsigned int gruop,
11e865c1 244 unsigned int mask);
e473e912
BP		 245static int s626_dio_clear_irq(comedi_device *dev);
246static int s626_enc_insn_config(comedi_device *dev, comedi_subdevice *s,
247 comedi_insn *insn, lsampl_t *data);
248static int s626_enc_insn_read(comedi_device *dev, comedi_subdevice *s,
249 comedi_insn *insn, lsampl_t *data);
250static int s626_enc_insn_write(comedi_device *dev, comedi_subdevice *s,
251 comedi_insn *insn, lsampl_t *data);
11e865c1 252static int s626_ns_to_timer(int *nanosec, int round_mode);
e473e912
BP		 253static int s626_ai_load_polllist(uint8_t *ppl, comedi_cmd *cmd);
254static int s626_ai_inttrig(comedi_device *dev, comedi_subdevice *s,
11e865c1
GP		 255 unsigned int trignum);
256static irqreturn_t s626_irq_handler(int irq, void *d PT_REGS_ARG);
257static lsampl_t s626_ai_reg_to_uint(int data);
258/* static lsampl_t s626_uint_to_reg(comedi_subdevice *s, int data); */
259
b6c77757 260/* end ioctl routines */
11e865c1 261
b6c77757 262/* internal routines */
e473e912
BP		 263static void s626_dio_init(comedi_device *dev);
264static void ResetADC(comedi_device *dev, uint8_t *ppl);
265static void LoadTrimDACs(comedi_device *dev);
266static void WriteTrimDAC(comedi_device *dev, uint8_t LogicalChan,
11e865c1 267 uint8_t DacData);
e473e912
BP		 268static uint8_t I2Cread(comedi_device *dev, uint8_t addr);
269static uint32_t I2Chandshake(comedi_device *dev, uint32_t val);
270static void SetDAC(comedi_device *dev, uint16_t chan, short dacdata);
271static void SendDAC(comedi_device *dev, uint32_t val);
272static void WriteMISC2(comedi_device *dev, uint16_t NewImage);
273static void DEBItransfer(comedi_device *dev);
274static uint16_t DEBIread(comedi_device *dev, uint16_t addr);
275static void DEBIwrite(comedi_device *dev, uint16_t addr, uint16_t wdata);
276static void DEBIreplace(comedi_device *dev, uint16_t addr, uint16_t mask,
11e865c1 277 uint16_t wdata);
e473e912 278static void CloseDMAB(comedi_device *dev, DMABUF *pdma, size_t bsize);
11e865c1 279
b6c77757 280/* COUNTER OBJECT ------------------------------------------------ */
11e865c1 281typedef struct enc_private_struct {
b6c77757 282 /* Pointers to functions that differ for A and B counters: */
e473e912
BP		 283 uint16_t(*GetEnable) (comedi_device *dev, struct enc_private_struct *); /* Return clock enable. */
284 uint16_t(*GetIntSrc) (comedi_device *dev, struct enc_private_struct *); /* Return interrupt source. */
285 uint16_t(*GetLoadTrig) (comedi_device *dev, struct enc_private_struct *); /* Return preload trigger source. */
286 uint16_t(*GetMode) (comedi_device *dev, struct enc_private_struct *); /* Return standardized operating mode. */
287 void (*PulseIndex) (comedi_device *dev, struct enc_private_struct *); /* Generate soft index strobe. */
288 void (*SetEnable) (comedi_device *dev, struct enc_private_struct *, uint16_t enab); /* Program clock enable. */
289 void (*SetIntSrc) (comedi_device *dev, struct enc_private_struct *, uint16_t IntSource); /* Program interrupt source. */
290 void (*SetLoadTrig) (comedi_device *dev, struct enc_private_struct *, uint16_t Trig); /* Program preload trigger source. */
291 void (*SetMode) (comedi_device *dev, struct enc_private_struct *, uint16_t Setup, uint16_t DisableIntSrc); /* Program standardized operating mode. */
292 void (*ResetCapFlags) (comedi_device *dev, struct enc_private_struct *); /* Reset event capture flags. */
b6c77757
BP		 293
294 uint16_t MyCRA; /* Address of CRA register. */
295 uint16_t MyCRB; /* Address of CRB register. */
296 uint16_t MyLatchLsw; /* Address of Latch least-significant-word */
297 /* register. */
298 uint16_t MyEventBits[4]; /* Bit translations for IntSrc -->RDMISC2. */
299} enc_private; /* counter object */
11e865c1
GP		 300
301#define encpriv ((enc_private *)(dev->subdevices+5)->private)
302
b6c77757 303/* counters routines */
e473e912
BP		 304static void s626_timer_load(comedi_device *dev, enc_private *k, int tick);
305static uint32_t ReadLatch(comedi_device *dev, enc_private *k);
306static void ResetCapFlags_A(comedi_device *dev, enc_private *k);
307static void ResetCapFlags_B(comedi_device *dev, enc_private *k);
308static uint16_t GetMode_A(comedi_device *dev, enc_private *k);
309static uint16_t GetMode_B(comedi_device *dev, enc_private *k);
310static void SetMode_A(comedi_device *dev, enc_private *k, uint16_t Setup,
11e865c1 311 uint16_t DisableIntSrc);
e473e912 312static void SetMode_B(comedi_device *dev, enc_private *k, uint16_t Setup,
11e865c1 313 uint16_t DisableIntSrc);
e473e912
BP		 314static void SetEnable_A(comedi_device *dev, enc_private *k, uint16_t enab);
315static void SetEnable_B(comedi_device *dev, enc_private *k, uint16_t enab);
316static uint16_t GetEnable_A(comedi_device *dev, enc_private *k);
317static uint16_t GetEnable_B(comedi_device *dev, enc_private *k);
318static void SetLatchSource(comedi_device *dev, enc_private *k,
11e865c1
GP		 319 uint16_t value);
320/* static uint16_t GetLatchSource(comedi_device *dev, enc_private *k ); */
e473e912
BP		 321static void SetLoadTrig_A(comedi_device *dev, enc_private *k, uint16_t Trig);
322static void SetLoadTrig_B(comedi_device *dev, enc_private *k, uint16_t Trig);
323static uint16_t GetLoadTrig_A(comedi_device *dev, enc_private *k);
324static uint16_t GetLoadTrig_B(comedi_device *dev, enc_private *k);
325static void SetIntSrc_B(comedi_device *dev, enc_private *k,
11e865c1 326 uint16_t IntSource);
e473e912 327static void SetIntSrc_A(comedi_device *dev, enc_private *k,
11e865c1 328 uint16_t IntSource);
e473e912
BP		 329static uint16_t GetIntSrc_A(comedi_device *dev, enc_private *k);
330static uint16_t GetIntSrc_B(comedi_device *dev, enc_private *k);
11e865c1
GP		 331/* static void SetClkMult(comedi_device *dev, enc_private *k, uint16_t value ) ; */
332/* static uint16_t GetClkMult(comedi_device *dev, enc_private *k ) ; */
333/* static void SetIndexPol(comedi_device *dev, enc_private *k, uint16_t value ); */
334/* static uint16_t GetClkPol(comedi_device *dev, enc_private *k ) ; */
335/* static void SetIndexSrc( comedi_device *dev,enc_private *k, uint16_t value ); */
336/* static uint16_t GetClkSrc( comedi_device *dev,enc_private *k ); */
337/* static void SetIndexSrc( comedi_device *dev,enc_private *k, uint16_t value ); */
338/* static uint16_t GetIndexSrc( comedi_device *dev,enc_private *k ); */
e473e912
BP		 339static void PulseIndex_A(comedi_device *dev, enc_private *k);
340static void PulseIndex_B(comedi_device *dev, enc_private *k);
341static void Preload(comedi_device *dev, enc_private *k, uint32_t value);
342static void CountersInit(comedi_device *dev);
b6c77757 343/* end internal routines */
11e865c1 344
b6c77757 345/* Counter objects constructor. */
11e865c1 346
b6c77757 347/* Counter overflow/index event flag masks for RDMISC2. */
6a98d36e
BP		 348#define INDXMASK(C) (1 << (((C) > 2) ? ((C) * 2 - 1) : ((C) * 2 + 4)))
349#define OVERMASK(C) (1 << (((C) > 2) ? ((C) * 2 + 5) : ((C) * 2 + 10)))
11e865c1
GP		 350#define EVBITS(C) { 0, OVERMASK(C), INDXMASK(C), OVERMASK(C) | INDXMASK(C) }
351
b6c77757
BP		 352/* Translation table to map IntSrc into equivalent RDMISC2 event flag bits. */
353/* static const uint16_t EventBits[][4] = { EVBITS(0), EVBITS(1), EVBITS(2), EVBITS(3), EVBITS(4), EVBITS(5) }; */
11e865c1
GP		 354
355/* enc_private; */
356static enc_private enc_private_data[] = {
357 {
358 GetEnable:GetEnable_A,
f7266a48
BP		 359 GetIntSrc : GetIntSrc_A,
360 GetLoadTrig : GetLoadTrig_A,
11e865c1 361 GetMode: GetMode_A,
f7266a48
BP		 362 PulseIndex : PulseIndex_A,
363 SetEnable : SetEnable_A,
364 SetIntSrc : SetIntSrc_A,
365 SetLoadTrig : SetLoadTrig_A,
11e865c1 366 SetMode: SetMode_A,
f7266a48 367 ResetCapFlags : ResetCapFlags_A,
11e865c1
GP		 368 MyCRA: LP_CR0A,
369 MyCRB: LP_CR0B,
f7266a48
BP		 370 MyLatchLsw : LP_CNTR0ALSW,
371 MyEventBits : EVBITS(0),
11e865c1
GP		 372 },
373 {
374 GetEnable:GetEnable_A,
f7266a48
BP		 375 GetIntSrc : GetIntSrc_A,
376 GetLoadTrig : GetLoadTrig_A,
11e865c1 377 GetMode: GetMode_A,
f7266a48
BP		 378 PulseIndex : PulseIndex_A,
379 SetEnable : SetEnable_A,
380 SetIntSrc : SetIntSrc_A,
381 SetLoadTrig : SetLoadTrig_A,
11e865c1 382 SetMode: SetMode_A,
f7266a48 383 ResetCapFlags : ResetCapFlags_A,
11e865c1
GP		 384 MyCRA: LP_CR1A,
385 MyCRB: LP_CR1B,
f7266a48
BP		 386 MyLatchLsw : LP_CNTR1ALSW,
387 MyEventBits : EVBITS(1),
11e865c1
GP		 388 },
389 {
390 GetEnable:GetEnable_A,
f7266a48
BP		 391 GetIntSrc : GetIntSrc_A,
392 GetLoadTrig : GetLoadTrig_A,
11e865c1 393 GetMode: GetMode_A,
f7266a48
BP		 394 PulseIndex : PulseIndex_A,
395 SetEnable : SetEnable_A,
396 SetIntSrc : SetIntSrc_A,
397 SetLoadTrig : SetLoadTrig_A,
11e865c1 398 SetMode: SetMode_A,
f7266a48 399 ResetCapFlags : ResetCapFlags_A,
11e865c1
GP		 400 MyCRA: LP_CR2A,
401 MyCRB: LP_CR2B,
f7266a48
BP		 402 MyLatchLsw : LP_CNTR2ALSW,
403 MyEventBits : EVBITS(2),
11e865c1
GP		 404 },
405 {
406 GetEnable:GetEnable_B,
f7266a48
BP		 407 GetIntSrc : GetIntSrc_B,
408 GetLoadTrig : GetLoadTrig_B,
11e865c1 409 GetMode: GetMode_B,
f7266a48
BP		 410 PulseIndex : PulseIndex_B,
411 SetEnable : SetEnable_B,
412 SetIntSrc : SetIntSrc_B,
413 SetLoadTrig : SetLoadTrig_B,
11e865c1 414 SetMode: SetMode_B,
f7266a48 415 ResetCapFlags : ResetCapFlags_B,
11e865c1
GP		 416 MyCRA: LP_CR0A,
417 MyCRB: LP_CR0B,
f7266a48
BP		 418 MyLatchLsw : LP_CNTR0BLSW,
419 MyEventBits : EVBITS(3),
11e865c1
GP		 420 },
421 {
422 GetEnable:GetEnable_B,
f7266a48
BP		 423 GetIntSrc : GetIntSrc_B,
424 GetLoadTrig : GetLoadTrig_B,
11e865c1 425 GetMode: GetMode_B,
f7266a48
BP		 426 PulseIndex : PulseIndex_B,
427 SetEnable : SetEnable_B,
428 SetIntSrc : SetIntSrc_B,
429 SetLoadTrig : SetLoadTrig_B,
11e865c1 430 SetMode: SetMode_B,
f7266a48 431 ResetCapFlags : ResetCapFlags_B,
11e865c1
GP		 432 MyCRA: LP_CR1A,
433 MyCRB: LP_CR1B,
f7266a48
BP		 434 MyLatchLsw : LP_CNTR1BLSW,
435 MyEventBits : EVBITS(4),
11e865c1
GP		 436 },
437 {
438 GetEnable:GetEnable_B,
f7266a48
BP		 439 GetIntSrc : GetIntSrc_B,
440 GetLoadTrig : GetLoadTrig_B,
11e865c1 441 GetMode: GetMode_B,
f7266a48
BP		 442 PulseIndex : PulseIndex_B,
443 SetEnable : SetEnable_B,
444 SetIntSrc : SetIntSrc_B,
445 SetLoadTrig : SetLoadTrig_B,
11e865c1 446 SetMode: SetMode_B,
f7266a48 447 ResetCapFlags : ResetCapFlags_B,
11e865c1
GP		 448 MyCRA: LP_CR2A,
449 MyCRB: LP_CR2B,
f7266a48
BP		 450 MyLatchLsw : LP_CNTR2BLSW,
451 MyEventBits : EVBITS(5),
11e865c1
GP		 452 },
453};
454
b6c77757
BP		 455/* enab/disable a function or test status bit(s) that are accessed */
456/* through Main Control Registers 1 or 2. */
6a98d36e 457#define MC_ENABLE(REGADRS, CTRLWORD) writel(((uint32_t)(CTRLWORD) << 16) | (uint32_t)(CTRLWORD), devpriv->base_addr+(REGADRS))
11e865c1 458
6a98d36e 459#define MC_DISABLE(REGADRS, CTRLWORD) writel((uint32_t)(CTRLWORD) << 16 , devpriv->base_addr+(REGADRS))
11e865c1 460
6a98d36e 461#define MC_TEST(REGADRS, CTRLWORD) ((readl(devpriv->base_addr+(REGADRS)) & CTRLWORD) != 0)
11e865c1
GP		 462
463/* #define WR7146(REGARDS,CTRLWORD)
464 writel(CTRLWORD,(uint32_t)(devpriv->base_addr+(REGARDS))) */
8086fff8 465#define WR7146(REGARDS, CTRLWORD) writel(CTRLWORD, devpriv->base_addr+(REGARDS))
11e865c1
GP		 466
467/* #define RR7146(REGARDS)
468 readl((uint32_t)(devpriv->base_addr+(REGARDS))) */
469#define RR7146(REGARDS) readl(devpriv->base_addr+(REGARDS))
470
6a98d36e 471#define BUGFIX_STREG(REGADRS) (REGADRS - 4)
11e865c1 472
b6c77757 473/* Write a time slot control record to TSL2. */
6a98d36e
BP		 474#define VECTPORT(VECTNUM) (P_TSL2 + ((VECTNUM) << 2))
475#define SETVECT(VECTNUM, VECTVAL) WR7146(VECTPORT(VECTNUM), (VECTVAL))
11e865c1 476
b6c77757 477/* Code macros used for constructing I2C command bytes. */
6a98d36e
BP		 478#define I2C_B2(ATTR, VAL) (((ATTR) << 6) | ((VAL) << 24))
479#define I2C_B1(ATTR, VAL) (((ATTR) << 4) | ((VAL) << 16))
480#define I2C_B0(ATTR, VAL) (((ATTR) << 2) | ((VAL) << 8))
11e865c1
GP		 481
482static const comedi_lrange s626_range_table = { 2, {
483 RANGE(-5, 5),
484 RANGE(-10, 10),
485 }
486};
487
e473e912 488static int s626_attach(comedi_device *dev, comedi_devconfig *it)
11e865c1
GP		 489{
490/* uint8_t PollList; */
491/* uint16_t AdcData; */
492/* uint16_t StartVal; */
493/* uint16_t index; */
494/* unsigned int data[16]; */
495 int result;
496 int i;
497 int ret;
498 resource_size_t resourceStart;
499 dma_addr_t appdma;
500 comedi_subdevice *s;
501 struct pci_dev *pdev;
502
503 if (alloc_private(dev, sizeof(s626_private)) < 0)
504 return -ENOMEM;
505
506 for (pdev = pci_get_device(PCI_VENDOR_ID_S626, PCI_DEVICE_ID_S626,
507 NULL); pdev != NULL;
508 pdev = pci_get_device(PCI_VENDOR_ID_S626,
509 PCI_DEVICE_ID_S626, pdev)) {
510 if (it->options[0] || it->options[1]) {
511 if (pdev->bus->number == it->options[0] &&
512 PCI_SLOT(pdev->devfn) == it->options[1]) {
513 /* matches requested bus/slot */
514 break;
515 }
516 } else {
517 /* no bus/slot specified */
518 break;
519 }
520 }
521 devpriv->pdev = pdev;
522
523 if (pdev == NULL) {
524 printk("s626_attach: Board not present!!!\n");
525 return -ENODEV;
526 }
527
197c82bf
BP		 528 result = comedi_pci_enable(pdev, "s626");
529 if (result < 0) {
11e865c1
GP		 530 printk("s626_attach: comedi_pci_enable fails\n");
531 return -ENODEV;
532 }
533 devpriv->got_regions = 1;
534
535 resourceStart = pci_resource_start(devpriv->pdev, 0);
536
537 devpriv->base_addr = ioremap(resourceStart, SIZEOF_ADDRESS_SPACE);
538 if (devpriv->base_addr == NULL) {
539 printk("s626_attach: IOREMAP failed\n");
540 return -ENODEV;
541 }
542
543 if (devpriv->base_addr) {
b6c77757 544 /* disable master interrupt */
11e865c1
GP		 545 writel(0, devpriv->base_addr + P_IER);
546
b6c77757 547 /* soft reset */
11e865c1
GP		 548 writel(MC1_SOFT_RESET, devpriv->base_addr + P_MC1);
549
b6c77757 550 /* DMA FIXME DMA// */
11e865c1
GP		 551 DEBUG("s626_attach: DMA ALLOCATION\n");
552
b6c77757 553 /* adc buffer allocation */
11e865c1
GP		 554 devpriv->allocatedBuf = 0;
555
197c82bf
BP		 556 devpriv->ANABuf.LogicalBase =
557 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
558
559 if (devpriv->ANABuf.LogicalBase == NULL) {
11e865c1
GP		 560 printk("s626_attach: DMA Memory mapping error\n");
561 return -ENOMEM;
562 }
563
564 devpriv->ANABuf.PhysicalBase = appdma;
565
566 DEBUG("s626_attach: AllocDMAB ADC Logical=%p, bsize=%d, Physical=0x%x\n", devpriv->ANABuf.LogicalBase, DMABUF_SIZE, (uint32_t) devpriv->ANABuf.PhysicalBase);
567
568 devpriv->allocatedBuf++;
569
197c82bf
BP		 570 devpriv->RPSBuf.LogicalBase =
571 pci_alloc_consistent(devpriv->pdev, DMABUF_SIZE, &appdma);
572
573 if (devpriv->RPSBuf.LogicalBase == NULL) {
11e865c1
GP		 574 printk("s626_attach: DMA Memory mapping error\n");
575 return -ENOMEM;
576 }
577
578 devpriv->RPSBuf.PhysicalBase = appdma;
579
580 DEBUG("s626_attach: AllocDMAB RPS Logical=%p, bsize=%d, Physical=0x%x\n", devpriv->RPSBuf.LogicalBase, DMABUF_SIZE, (uint32_t) devpriv->RPSBuf.PhysicalBase);
581
582 devpriv->allocatedBuf++;
583
584 }
585
586 dev->board_ptr = s626_boards;
587 dev->board_name = thisboard->name;
588
589 if (alloc_subdevices(dev, 6) < 0)
590 return -ENOMEM;
591
592 dev->iobase = (unsigned long)devpriv->base_addr;
593 dev->irq = devpriv->pdev->irq;
594
b6c77757 595 /* set up interrupt handler */
11e865c1
GP		 596 if (dev->irq == 0) {
597 printk(" unknown irq (bad)\n");
598 } else {
197c82bf
BP		 599 ret = comedi_request_irq(dev->irq, s626_irq_handler,
600 IRQF_SHARED, "s626", dev);
601
602 if (ret < 0) {
11e865c1
GP		 603 printk(" irq not available\n");
604 dev->irq = 0;
605 }
606 }
607
608 DEBUG("s626_attach: -- it opts %d,%d -- \n",
609 it->options[0], it->options[1]);
610
611 s = dev->subdevices + 0;
612 /* analog input subdevice */
613 dev->read_subdev = s;
614 /* we support single-ended (ground) and differential */
615 s->type = COMEDI_SUBD_AI;
616 s->subdev_flags = SDF_READABLE | SDF_DIFF | SDF_CMD_READ;
617 s->n_chan = thisboard->ai_chans;
618 s->maxdata = (0xffff >> 2);
619 s->range_table = &s626_range_table;
620 s->len_chanlist = thisboard->ai_chans; /* This is the maximum chanlist
621 length that the board can
622 handle */
623 s->insn_config = s626_ai_insn_config;
624 s->insn_read = s626_ai_insn_read;
625 s->do_cmd = s626_ai_cmd;
626 s->do_cmdtest = s626_ai_cmdtest;
627 s->cancel = s626_ai_cancel;
628
629 s = dev->subdevices + 1;
630 /* analog output subdevice */
631 s->type = COMEDI_SUBD_AO;
632 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
633 s->n_chan = thisboard->ao_chans;
634 s->maxdata = (0x3fff);
635 s->range_table = &range_bipolar10;
636 s->insn_write = s626_ao_winsn;
637 s->insn_read = s626_ao_rinsn;
638
639 s = dev->subdevices + 2;
640 /* digital I/O subdevice */
641 s->type = COMEDI_SUBD_DIO;
642 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
643 s->n_chan = S626_DIO_CHANNELS;
644 s->maxdata = 1;
645 s->io_bits = 0xffff;
646 s->private = &dio_private_A;
647 s->range_table = &range_digital;
648 s->insn_config = s626_dio_insn_config;
649 s->insn_bits = s626_dio_insn_bits;
650
651 s = dev->subdevices + 3;
652 /* digital I/O subdevice */
653 s->type = COMEDI_SUBD_DIO;
654 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
655 s->n_chan = 16;
656 s->maxdata = 1;
657 s->io_bits = 0xffff;
658 s->private = &dio_private_B;
659 s->range_table = &range_digital;
660 s->insn_config = s626_dio_insn_config;
661 s->insn_bits = s626_dio_insn_bits;
662
663 s = dev->subdevices + 4;
664 /* digital I/O subdevice */
665 s->type = COMEDI_SUBD_DIO;
666 s->subdev_flags = SDF_WRITABLE | SDF_READABLE;
667 s->n_chan = 16;
668 s->maxdata = 1;
669 s->io_bits = 0xffff;
670 s->private = &dio_private_C;
671 s->range_table = &range_digital;
672 s->insn_config = s626_dio_insn_config;
673 s->insn_bits = s626_dio_insn_bits;
674
675 s = dev->subdevices + 5;
676 /* encoder (counter) subdevice */
677 s->type = COMEDI_SUBD_COUNTER;
678 s->subdev_flags = SDF_WRITABLE | SDF_READABLE | SDF_LSAMPL;
679 s->n_chan = thisboard->enc_chans;
680 s->private = enc_private_data;
681 s->insn_config = s626_enc_insn_config;
682 s->insn_read = s626_enc_insn_read;
683 s->insn_write = s626_enc_insn_write;
684 s->maxdata = 0xffffff;
685 s->range_table = &range_unknown;
686
b6c77757 687 /* stop ai_command */
11e865c1
GP		 688 devpriv->ai_cmd_running = 0;
689
690 if (devpriv->base_addr && (devpriv->allocatedBuf == 2)) {
691 dma_addr_t pPhysBuf;
692 uint16_t chan;
693
b6c77757 694 /* enab DEBI and audio pins, enable I2C interface. */
11e865c1 695 MC_ENABLE(P_MC1, MC1_DEBI | MC1_AUDIO | MC1_I2C);
b6c77757
BP		 696 /* Configure DEBI operating mode. */
697 WR7146(P_DEBICFG, DEBI_CFG_SLAVE16 /* Local bus is 16 */
698 /* bits wide. */
699 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) /* Declare DEBI */
700 /* transfer timeout */
701 /* interval. */
702 | DEBI_SWAP /* Set up byte lane */
703 /* steering. */
704 | DEBI_CFG_INTEL); /* Intel-compatible */
705 /* local bus (DEBI */
706 /* never times out). */
11e865c1
GP		 707 DEBUG("s626_attach: %d debi init -- %d\n",
708 DEBI_CFG_SLAVE16 | (DEBI_TOUT << DEBI_CFG_TOUT_BIT) |
709 DEBI_SWAP | DEBI_CFG_INTEL,
710 DEBI_CFG_INTEL | DEBI_CFG_TOQ | DEBI_CFG_INCQ |
711 DEBI_CFG_16Q);
712
b6c77757
BP		 713 /* DEBI INIT S626 WR7146( P_DEBICFG, DEBI_CFG_INTEL | DEBI_CFG_TOQ */
714 /* | DEBI_CFG_INCQ| DEBI_CFG_16Q); //end */
11e865c1 715
b6c77757
BP		 716 /* Paging is disabled. */
717 WR7146(P_DEBIPAGE, DEBI_PAGE_DISABLE); /* Disable MMU paging. */
11e865c1 718
b6c77757 719 /* Init GPIO so that ADC Start* is negated. */
11e865c1
GP		 720 WR7146(P_GPIO, GPIO_BASE | GPIO1_HI);
721
b6c77757
BP		 722 /* IsBoardRevA is a boolean that indicates whether the board is RevA.
723 *
724 * VERSION 2.01 CHANGE: REV A & B BOARDS NOW SUPPORTED BY DYNAMIC
725 * EEPROM ADDRESS SELECTION. Initialize the I2C interface, which
726 * is used to access the onboard serial EEPROM. The EEPROM's I2C
727 * DeviceAddress is hardwired to a value that is dependent on the
728 * 626 board revision. On all board revisions, the EEPROM stores
729 * TrimDAC calibration constants for analog I/O. On RevB and
730 * higher boards, the DeviceAddress is hardwired to 0 to enable
731 * the EEPROM to also store the PCI SubVendorID and SubDeviceID;
732 * this is the address at which the SAA7146 expects a
733 * configuration EEPROM to reside. On RevA boards, the EEPROM
734 * device address, which is hardwired to 4, prevents the SAA7146
735 * from retrieving PCI sub-IDs, so the SAA7146 uses its built-in
736 * default values, instead.
737 */
738
739 /* devpriv->I2Cards= IsBoardRevA ? 0xA8 : 0xA0; // Set I2C EEPROM */
740 /* DeviceType (0xA0) */
741 /* and DeviceAddress<<1. */
742
743 devpriv->I2CAdrs = 0xA0; /* I2C device address for onboard */
744 /* eeprom(revb) */
745
746 /* Issue an I2C ABORT command to halt any I2C operation in */
747 /* progress and reset BUSY flag. */
748 WR7146(P_I2CSTAT, I2C_CLKSEL | I2C_ABORT);
749 /* Write I2C control: abort any I2C activity. */
750 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
751 /* Invoke command upload */
c7427409
BP		 752 while ((RR7146(P_MC2) & MC2_UPLD_IIC) == 0)
753 ;
b6c77757
BP		 754 /* and wait for upload to complete. */
755
756 /* Per SAA7146 data sheet, write to STATUS reg twice to
757 * reset all I2C error flags. */
11e865c1 758 for (i = 0; i < 2; i++) {
b6c77757
BP		 759 WR7146(P_I2CSTAT, I2C_CLKSEL);
760 /* Write I2C control: reset error flags. */
761 MC_ENABLE(P_MC2, MC2_UPLD_IIC); /* Invoke command upload */
c7427409
BP		 762 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
763 ;
b6c77757 764 /* and wait for upload to complete. */
11e865c1
GP		 765 }
766
b6c77757
BP		 767 /* Init audio interface functional attributes: set DAC/ADC
768 * serial clock rates, invert DAC serial clock so that
769 * DAC data setup times are satisfied, enable DAC serial
770 * clock out.
771 */
772
11e865c1
GP		 773 WR7146(P_ACON2, ACON2_INIT);
774
b6c77757
BP		 775 /* Set up TSL1 slot list, which is used to control the
776 * accumulation of ADC data: RSD1 = shift data in on SD1.
777 * SIB_A1 = store data uint8_t at next available location in
778 * FB BUFFER1 register. */
779 WR7146(P_TSL1, RSD1 | SIB_A1);
780 /* Fetch ADC high data uint8_t. */
781 WR7146(P_TSL1 + 4, RSD1 | SIB_A1 | EOS);
782 /* Fetch ADC low data uint8_t; end of TSL1. */
783
784 /* enab TSL1 slot list so that it executes all the time. */
11e865c1
GP		 785 WR7146(P_ACON1, ACON1_ADCSTART);
786
b6c77757 787 /* Initialize RPS registers used for ADC. */
11e865c1 788
b6c77757 789 /* Physical start of RPS program. */
11e865c1
GP		 790 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
791
b6c77757
BP		 792 WR7146(P_RPSPAGE1, 0);
793 /* RPS program performs no explicit mem writes. */
794 WR7146(P_RPS1_TOUT, 0); /* Disable RPS timeouts. */
11e865c1 795
b6c77757
BP		 796 /* SAA7146 BUG WORKAROUND. Initialize SAA7146 ADC interface
797 * to a known state by invoking ADCs until FB BUFFER 1
798 * register shows that it is correctly receiving ADC data.
799 * This is necessary because the SAA7146 ADC interface does
800 * not start up in a defined state after a PCI reset.
801 */
11e865c1
GP		 802
803/* PollList = EOPL; // Create a simple polling */
804/* // list for analog input */
805/* // channel 0. */
806/* ResetADC( dev, &PollList ); */
807
808/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); //( &AdcData ); // */
809/* //Get initial ADC */
810/* //value. */
811
812/* StartVal = data[0]; */
813
814/* // VERSION 2.01 CHANGE: TIMEOUT ADDED TO PREVENT HANGED EXECUTION. */
815/* // Invoke ADCs until the new ADC value differs from the initial */
816/* // value or a timeout occurs. The timeout protects against the */
817/* // possibility that the driver is restarting and the ADC data is a */
818/* // fixed value resulting from the applied ADC analog input being */
819/* // unusually quiet or at the rail. */
820
821/* for ( index = 0; index < 500; index++ ) */
822/* { */
823/* s626_ai_rinsn(dev,dev->subdevices,NULL,data); */
824/* AdcData = data[0]; //ReadADC( &AdcData ); */
825/* if ( AdcData != StartVal ) */
826/* break; */
827/* } */
828
b6c77757 829 /* end initADC */
11e865c1 830
b6c77757 831 /* init the DAC interface */
11e865c1 832
b6c77757
BP		 833 /* Init Audio2's output DMAC attributes: burst length = 1
834 * DWORD, threshold = 1 DWORD.
835 */
11e865c1
GP		 836 WR7146(P_PCI_BT_A, 0);
837
b6c77757
BP		 838 /* Init Audio2's output DMA physical addresses. The protection
839 * address is set to 1 DWORD past the base address so that a
840 * single DWORD will be transferred each time a DMA transfer is
841 * enabled. */
11e865c1
GP		 842
843 pPhysBuf =
844 devpriv->ANABuf.PhysicalBase +
845 (DAC_WDMABUF_OS * sizeof(uint32_t));
846
b6c77757
BP		 847 WR7146(P_BASEA2_OUT, (uint32_t) pPhysBuf); /* Buffer base adrs. */
848 WR7146(P_PROTA2_OUT, (uint32_t) (pPhysBuf + sizeof(uint32_t))); /* Protection address. */
11e865c1 849
b6c77757
BP		 850 /* Cache Audio2's output DMA buffer logical address. This is
851 * where DAC data is buffered for A2 output DMA transfers. */
11e865c1
GP		 852 devpriv->pDacWBuf =
853 (uint32_t *) devpriv->ANABuf.LogicalBase +
854 DAC_WDMABUF_OS;
855
b6c77757
BP		 856 /* Audio2's output channels does not use paging. The protection
857 * violation handling bit is set so that the DMAC will
858 * automatically halt and its PCI address pointer will be reset
859 * when the protection address is reached. */
860
11e865c1
GP		 861 WR7146(P_PAGEA2_OUT, 8);
862
b6c77757
BP		 863 /* Initialize time slot list 2 (TSL2), which is used to control
864 * the clock generation for and serialization of data to be sent
865 * to the DAC devices. Slot 0 is a NOP that is used to trap TSL
866 * execution; this permits other slots to be safely modified
867 * without first turning off the TSL sequencer (which is
868 * apparently impossible to do). Also, SD3 (which is driven by a
869 * pull-up resistor) is shifted in and stored to the MSB of
870 * FB_BUFFER2 to be used as evidence that the slot sequence has
871 * not yet finished executing.
872 */
873
874 SETVECT(0, XSD2 | RSD3 | SIB_A2 | EOS);
875 /* Slot 0: Trap TSL execution, shift 0xFF into FB_BUFFER2. */
876
877 /* Initialize slot 1, which is constant. Slot 1 causes a
878 * DWORD to be transferred from audio channel 2's output FIFO
879 * to the FIFO's output buffer so that it can be serialized
880 * and sent to the DAC during subsequent slots. All remaining
881 * slots are dynamically populated as required by the target
882 * DAC device.
883 */
884 SETVECT(1, LF_A2);
885 /* Slot 1: Fetch DWORD from Audio2's output FIFO. */
886
887 /* Start DAC's audio interface (TSL2) running. */
11e865c1
GP		 888 WR7146(P_ACON1, ACON1_DACSTART);
889
b6c77757 890 /* end init DAC interface */
11e865c1 891
b6c77757
BP		 892 /* Init Trim DACs to calibrated values. Do it twice because the
893 * SAA7146 audio channel does not always reset properly and
894 * sometimes causes the first few TrimDAC writes to malfunction.
895 */
11e865c1
GP		 896
897 LoadTrimDACs(dev);
b6c77757 898 LoadTrimDACs(dev); /* Insurance. */
11e865c1 899
b6c77757
BP		 900 /* Manually init all gate array hardware in case this is a soft
901 * reset (we have no way of determining whether this is a warm
902 * or cold start). This is necessary because the gate array will
903 * reset only in response to a PCI hard reset; there is no soft
904 * reset function. */
11e865c1 905
b6c77757
BP		 906 /* Init all DAC outputs to 0V and init all DAC setpoint and
907 * polarity images.
908 */
11e865c1
GP		 909 for (chan = 0; chan < S626_DAC_CHANNELS; chan++)
910 SetDAC(dev, chan, 0);
911
b6c77757
BP		 912 /* Init image of WRMISC2 Battery Charger Enabled control bit.
913 * This image is used when the state of the charger control bit,
914 * which has no direct hardware readback mechanism, is queried.
915 */
11e865c1
GP		 916 devpriv->ChargeEnabled = 0;
917
b6c77757
BP		 918 /* Init image of watchdog timer interval in WRMISC2. This image
919 * maintains the value of the control bits of MISC2 are
920 * continuously reset to zero as long as the WD timer is disabled.
921 */
11e865c1
GP		 922 devpriv->WDInterval = 0;
923
b6c77757
BP		 924 /* Init Counter Interrupt enab mask for RDMISC2. This mask is
925 * applied against MISC2 when testing to determine which timer
926 * events are requesting interrupt service.
927 */
11e865c1
GP		 928 devpriv->CounterIntEnabs = 0;
929
b6c77757 930 /* Init counters. */
11e865c1
GP		 931 CountersInit(dev);
932
b6c77757
BP		 933 /* Without modifying the state of the Battery Backup enab, disable
934 * the watchdog timer, set DIO channels 0-5 to operate in the
935 * standard DIO (vs. counter overflow) mode, disable the battery
936 * charger, and reset the watchdog interval selector to zero.
937 */
11e865c1
GP		 938 WriteMISC2(dev, (uint16_t) (DEBIread(dev,
939 LP_RDMISC2) & MISC2_BATT_ENABLE));
940
b6c77757 941 /* Initialize the digital I/O subsystem. */
11e865c1
GP		 942 s626_dio_init(dev);
943
b6c77757
BP		 944 /* enable interrupt test */
945 /* writel(IRQ_GPIO3 | IRQ_RPS1,devpriv->base_addr+P_IER); */
11e865c1
GP		 946 }
947
948 DEBUG("s626_attach: comedi%d s626 attached %04x\n", dev->minor,
949 (uint32_t) devpriv->base_addr);
950
951 return 1;
952}
953
954static lsampl_t s626_ai_reg_to_uint(int data)
955{
956 lsampl_t tempdata;
957
958 tempdata = (data >> 18);
959 if (tempdata & 0x2000)
960 tempdata &= 0x1fff;
961 else
962 tempdata += (1 << 13);
963
964 return tempdata;
965}
966
967/* static lsampl_t s626_uint_to_reg(comedi_subdevice *s, int data){ */
968/* return 0; */
969/* } */
970
971static irqreturn_t s626_irq_handler(int irq, void *d PT_REGS_ARG)
972{
973 comedi_device *dev = d;
974 comedi_subdevice *s;
975 comedi_cmd *cmd;
976 enc_private *k;
977 unsigned long flags;
978 int32_t *readaddr;
979 uint32_t irqtype, irqstatus;
980 int i = 0;
981 sampl_t tempdata;
982 uint8_t group;
983 uint16_t irqbit;
984
985 DEBUG("s626_irq_handler: interrupt request recieved!!!\n");
986
987 if (dev->attached == 0)
988 return IRQ_NONE;
b6c77757 989 /* lock to avoid race with comedi_poll */
11e865c1
GP		 990 comedi_spin_lock_irqsave(&dev->spinlock, flags);
991
b6c77757 992 /* save interrupt enable register state */
11e865c1
GP		 993 irqstatus = readl(devpriv->base_addr + P_IER);
994
b6c77757 995 /* read interrupt type */
11e865c1
GP		 996 irqtype = readl(devpriv->base_addr + P_ISR);
997
b6c77757 998 /* disable master interrupt */
11e865c1
GP		 999 writel(0, devpriv->base_addr + P_IER);
1000
b6c77757 1001 /* clear interrupt */
11e865c1
GP		 1002 writel(irqtype, devpriv->base_addr + P_ISR);
1003
b6c77757 1004 /* do somethings */
11e865c1
GP		 1005 DEBUG("s626_irq_handler: interrupt type %d\n", irqtype);
1006
1007 switch (irqtype) {
b6c77757 1008 case IRQ_RPS1: /* end_of_scan occurs */
11e865c1
GP		 1009
1010 DEBUG("s626_irq_handler: RPS1 irq detected\n");
1011
b6c77757 1012 /* manage ai subdevice */
11e865c1
GP		 1013 s = dev->subdevices;
1014 cmd = &(s->async->cmd);
1015
b6c77757
BP		 1016 /* Init ptr to DMA buffer that holds new ADC data. We skip the
1017 * first uint16_t in the buffer because it contains junk data from
1018 * the final ADC of the previous poll list scan.
1019 */
11e865c1
GP		 1020 readaddr = (int32_t *) devpriv->ANABuf.LogicalBase + 1;
1021
b6c77757 1022 /* get the data and hand it over to comedi */
11e865c1 1023 for (i = 0; i < (s->async->cmd.chanlist_len); i++) {
b6c77757
BP		 1024 /* Convert ADC data to 16-bit integer values and copy to application */
1025 /* buffer. */
11e865c1
GP		 1026 tempdata = s626_ai_reg_to_uint((int)*readaddr);
1027 readaddr++;
1028
b6c77757
BP		 1029 /* put data into read buffer */
1030 /* comedi_buf_put(s->async, tempdata); */
11e865c1
GP		 1031 if (cfc_write_to_buffer(s, tempdata) == 0)
1032 printk("s626_irq_handler: cfc_write_to_buffer error!\n");
1033
1034 DEBUG("s626_irq_handler: ai channel %d acquired: %d\n",
1035 i, tempdata);
1036 }
1037
b6c77757 1038 /* end of scan occurs */
11e865c1
GP		 1039 s->async->events |= COMEDI_CB_EOS;
1040
1041 if (!(devpriv->ai_continous))
1042 devpriv->ai_sample_count--;
1043 if (devpriv->ai_sample_count <= 0) {
1044 devpriv->ai_cmd_running = 0;
1045
b6c77757 1046 /* Stop RPS program. */
11e865c1
GP		 1047 MC_DISABLE(P_MC1, MC1_ERPS1);
1048
b6c77757 1049 /* send end of acquisition */
11e865c1
GP		 1050 s->async->events |= COMEDI_CB_EOA;
1051
b6c77757 1052 /* disable master interrupt */
11e865c1
GP		 1053 irqstatus = 0;
1054 }
1055
1056 if (devpriv->ai_cmd_running && cmd->scan_begin_src == TRIG_EXT) {
1057 DEBUG("s626_irq_handler: enable interrupt on dio channel %d\n", cmd->scan_begin_arg);
1058
1059 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1060
1061 DEBUG("s626_irq_handler: External trigger is set!!!\n");
1062 }
b6c77757 1063 /* tell comedi that data is there */
11e865c1
GP		 1064 DEBUG("s626_irq_handler: events %d\n", s->async->events);
1065 comedi_event(dev, s);
1066 break;
b6c77757 1067 case IRQ_GPIO3: /* check dio and conter interrupt */
11e865c1
GP		 1068
1069 DEBUG("s626_irq_handler: GPIO3 irq detected\n");
1070
b6c77757 1071 /* manage ai subdevice */
11e865c1
GP		 1072 s = dev->subdevices;
1073 cmd = &(s->async->cmd);
1074
b6c77757 1075 /* s626_dio_clear_irq(dev); */
11e865c1
GP		 1076
1077 for (group = 0; group < S626_DIO_BANKS; group++) {
1078 irqbit = 0;
b6c77757 1079 /* read interrupt type */
11e865c1
GP		 1080 irqbit = DEBIread(dev,
1081 ((dio_private *) (dev->subdevices + 2 +
1082 group)->private)->RDCapFlg);
1083
b6c77757 1084 /* check if interrupt is generated from dio channels */
11e865c1
GP		 1085 if (irqbit) {
1086 s626_dio_reset_irq(dev, group, irqbit);
1087 DEBUG("s626_irq_handler: check interrupt on dio group %d %d\n", group, i);
1088 if (devpriv->ai_cmd_running) {
b6c77757 1089 /* check if interrupt is an ai acquisition start trigger */
11e865c1
GP		 1090 if ((irqbit >> (cmd->start_arg -
1091 (16 * group)))
1092 == 1
1093 && cmd->start_src == TRIG_EXT) {
1094 DEBUG("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", cmd->start_arg);
1095
b6c77757 1096 /* Start executing the RPS program. */
11e865c1
GP		 1097 MC_ENABLE(P_MC1, MC1_ERPS1);
1098
1099 DEBUG("s626_irq_handler: aquisition start triggered!!!\n");
1100
1101 if (cmd->scan_begin_src ==
1102 TRIG_EXT) {
1103 DEBUG("s626_ai_cmd: enable interrupt on dio channel %d\n", cmd->scan_begin_arg);
1104
1105 s626_dio_set_irq(dev,
1106 cmd->
1107 scan_begin_arg);
1108
1109 DEBUG("s626_irq_handler: External scan trigger is set!!!\n");
1110 }
1111 }
1112 if ((irqbit >> (cmd->scan_begin_arg -
1113 (16 * group)))
1114 == 1
1115 && cmd->scan_begin_src ==
1116 TRIG_EXT) {
1117 DEBUG("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", cmd->scan_begin_arg);
1118
b6c77757 1119 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1120 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1121
1122 DEBUG("s626_irq_handler: scan triggered!!! %d\n", devpriv->ai_sample_count);
1123 if (cmd->convert_src ==
1124 TRIG_EXT) {
1125
1126 DEBUG("s626_ai_cmd: enable interrupt on dio channel %d group %d\n", cmd->convert_arg - (16 * group), group);
1127
1128 devpriv->
1129 ai_convert_count
1130 =
1131 cmd->
1132 chanlist_len;
1133
1134 s626_dio_set_irq(dev,
1135 cmd->
1136 convert_arg);
1137
1138 DEBUG("s626_irq_handler: External convert trigger is set!!!\n");
1139 }
1140
1141 if (cmd->convert_src ==
1142 TRIG_TIMER) {
1143 k = &encpriv[5];
1144 devpriv->
1145 ai_convert_count
1146 =
1147 cmd->
1148 chanlist_len;
1149 k->SetEnable(dev, k,
1150 CLKENAB_ALWAYS);
1151 }
1152 }
1153 if ((irqbit >> (cmd->convert_arg -
1154 (16 * group)))
1155 == 1
1156 && cmd->convert_src ==
1157 TRIG_EXT) {
1158 DEBUG("s626_irq_handler: Edge capture interrupt recieved from channel %d\n", cmd->convert_arg);
1159
b6c77757 1160 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1161 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1162
1163 DEBUG("s626_irq_handler: adc convert triggered!!!\n");
1164
1165 devpriv->ai_convert_count--;
1166
1167 if (devpriv->ai_convert_count >
1168 0) {
1169
1170 DEBUG("s626_ai_cmd: enable interrupt on dio channel %d group %d\n", cmd->convert_arg - (16 * group), group);
1171
1172 s626_dio_set_irq(dev,
1173 cmd->
1174 convert_arg);
1175
1176 DEBUG("s626_irq_handler: External trigger is set!!!\n");
1177 }
1178 }
1179 }
1180 break;
1181 }
1182 }
1183
b6c77757 1184 /* read interrupt type */
11e865c1
GP		 1185 irqbit = DEBIread(dev, LP_RDMISC2);
1186
b6c77757 1187 /* check interrupt on counters */
11e865c1
GP		 1188 DEBUG("s626_irq_handler: check counters interrupt %d\n",
1189 irqbit);
1190
1191 if (irqbit & IRQ_COINT1A) {
1192 DEBUG("s626_irq_handler: interrupt on counter 1A overflow\n");
1193 k = &encpriv[0];
1194
b6c77757 1195 /* clear interrupt capture flag */
11e865c1
GP		 1196 k->ResetCapFlags(dev, k);
1197 }
1198 if (irqbit & IRQ_COINT2A) {
1199 DEBUG("s626_irq_handler: interrupt on counter 2A overflow\n");
1200 k = &encpriv[1];
1201
b6c77757 1202 /* clear interrupt capture flag */
11e865c1
GP		 1203 k->ResetCapFlags(dev, k);
1204 }
1205 if (irqbit & IRQ_COINT3A) {
1206 DEBUG("s626_irq_handler: interrupt on counter 3A overflow\n");
1207 k = &encpriv[2];
1208
b6c77757 1209 /* clear interrupt capture flag */
11e865c1
GP		 1210 k->ResetCapFlags(dev, k);
1211 }
1212 if (irqbit & IRQ_COINT1B) {
1213 DEBUG("s626_irq_handler: interrupt on counter 1B overflow\n");
1214 k = &encpriv[3];
1215
b6c77757 1216 /* clear interrupt capture flag */
11e865c1
GP		 1217 k->ResetCapFlags(dev, k);
1218 }
1219 if (irqbit & IRQ_COINT2B) {
1220 DEBUG("s626_irq_handler: interrupt on counter 2B overflow\n");
1221 k = &encpriv[4];
1222
b6c77757 1223 /* clear interrupt capture flag */
11e865c1
GP		 1224 k->ResetCapFlags(dev, k);
1225
1226 if (devpriv->ai_convert_count > 0) {
1227 devpriv->ai_convert_count--;
1228 if (devpriv->ai_convert_count == 0)
1229 k->SetEnable(dev, k, CLKENAB_INDEX);
1230
1231 if (cmd->convert_src == TRIG_TIMER) {
1232 DEBUG("s626_irq_handler: conver timer trigger!!! %d\n", devpriv->ai_convert_count);
1233
b6c77757 1234 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1235 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1236 }
1237 }
1238 }
1239 if (irqbit & IRQ_COINT3B) {
1240 DEBUG("s626_irq_handler: interrupt on counter 3B overflow\n");
1241 k = &encpriv[5];
1242
b6c77757 1243 /* clear interrupt capture flag */
11e865c1
GP		 1244 k->ResetCapFlags(dev, k);
1245
1246 if (cmd->scan_begin_src == TRIG_TIMER) {
1247 DEBUG("s626_irq_handler: scan timer trigger!!!\n");
1248
b6c77757 1249 /* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1250 MC_ENABLE(P_MC2, MC2_ADC_RPS);
1251 }
1252
1253 if (cmd->convert_src == TRIG_TIMER) {
1254 DEBUG("s626_irq_handler: convert timer trigger is set\n");
1255 k = &encpriv[4];
1256 devpriv->ai_convert_count = cmd->chanlist_len;
1257 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1258 }
1259 }
1260 }
1261
b6c77757 1262 /* enable interrupt */
11e865c1
GP		 1263 writel(irqstatus, devpriv->base_addr + P_IER);
1264
1265 DEBUG("s626_irq_handler: exit interrupt service routine.\n");
1266
1267 comedi_spin_unlock_irqrestore(&dev->spinlock, flags);
1268 return IRQ_HANDLED;
1269}
1270
e473e912 1271static int s626_detach(comedi_device *dev)
11e865c1
GP		 1272{
1273 if (devpriv) {
b6c77757 1274 /* stop ai_command */
11e865c1
GP		 1275 devpriv->ai_cmd_running = 0;
1276
1277 if (devpriv->base_addr) {
b6c77757
BP		 1278 /* interrupt mask */
1279 WR7146(P_IER, 0); /* Disable master interrupt. */
1280 WR7146(P_ISR, IRQ_GPIO3 | IRQ_RPS1); /* Clear board's IRQ status flag. */
11e865c1 1281
b6c77757 1282 /* Disable the watchdog timer and battery charger. */
11e865c1
GP		 1283 WriteMISC2(dev, 0);
1284
b6c77757 1285 /* Close all interfaces on 7146 device. */
11e865c1
GP		 1286 WR7146(P_MC1, MC1_SHUTDOWN);
1287 WR7146(P_ACON1, ACON1_BASE);
1288
1289 CloseDMAB(dev, &devpriv->RPSBuf, DMABUF_SIZE);
1290 CloseDMAB(dev, &devpriv->ANABuf, DMABUF_SIZE);
1291 }
1292
1293 if (dev->irq) {
1294 comedi_free_irq(dev->irq, dev);
1295 }
1296
1297 if (devpriv->base_addr) {
1298 iounmap(devpriv->base_addr);
1299 }
1300
1301 if (devpriv->pdev) {
1302 if (devpriv->got_regions) {
1303 comedi_pci_disable(devpriv->pdev);
1304 }
1305 pci_dev_put(devpriv->pdev);
1306 }
1307 }
1308
1309 DEBUG("s626_detach: S626 detached!\n");
1310
1311 return 0;
1312}
1313
1314/*
1315 * this functions build the RPS program for hardware driven acquistion
1316 */
e473e912 1317void ResetADC(comedi_device *dev, uint8_t *ppl)
11e865c1
GP		 1318{
1319 register uint32_t *pRPS;
1320 uint32_t JmpAdrs;
1321 uint16_t i;
1322 uint16_t n;
1323 uint32_t LocalPPL;
1324 comedi_cmd *cmd = &(dev->subdevices->async->cmd);
1325
b6c77757 1326 /* Stop RPS program in case it is currently running. */
11e865c1
GP		 1327 MC_DISABLE(P_MC1, MC1_ERPS1);
1328
b6c77757 1329 /* Set starting logical address to write RPS commands. */
11e865c1
GP		 1330 pRPS = (uint32_t *) devpriv->RPSBuf.LogicalBase;
1331
b6c77757 1332 /* Initialize RPS instruction pointer. */
11e865c1
GP		 1333 WR7146(P_RPSADDR1, (uint32_t) devpriv->RPSBuf.PhysicalBase);
1334
b6c77757 1335 /* Construct RPS program in RPSBuf DMA buffer */
11e865c1
GP		 1336
1337 if (cmd != NULL && cmd->scan_begin_src != TRIG_FOLLOW) {
1338 DEBUG("ResetADC: scan_begin pause inserted\n");
b6c77757 1339 /* Wait for Start trigger. */
11e865c1
GP		 1340 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1341 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1342 }
b6c77757
BP		 1343
1344 /* SAA7146 BUG WORKAROUND Do a dummy DEBI Write. This is necessary
1345 * because the first RPS DEBI Write following a non-RPS DEBI write
1346 * seems to always fail. If we don't do this dummy write, the ADC
1347 * gain might not be set to the value required for the first slot in
1348 * the poll list; the ADC gain would instead remain unchanged from
1349 * the previously programmed value.
1350 */
1351 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1352 /* Write DEBI Write command and address to shadow RAM. */
1353
11e865c1 1354 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
b6c77757
BP		 1355 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1356 /* Write DEBI immediate data to shadow RAM: */
1357
1358 *pRPS++ = GSEL_BIPOLAR5V;
1359 /* arbitrary immediate data value. */
1360
1361 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1362 /* Reset "shadow RAM uploaded" flag. */
1363 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1364 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to finish. */
1365
1366 /* Digitize all slots in the poll list. This is implemented as a
1367 * for loop to limit the slot count to 16 in case the application
1368 * forgot to set the EOPL flag in the final slot.
1369 */
11e865c1 1370 for (devpriv->AdcItems = 0; devpriv->AdcItems < 16; devpriv->AdcItems++) {
b6c77757
BP		 1371 /* Convert application's poll list item to private board class
1372 * format. Each app poll list item is an uint8_t with form
1373 * (EOPL,x,x,RANGE,CHAN<3:0>), where RANGE code indicates 0 =
1374 * +-10V, 1 = +-5V, and EOPL = End of Poll List marker.
1375 */
11e865c1
GP		 1376 LocalPPL =
1377 (*ppl << 8) | (*ppl & 0x10 ? GSEL_BIPOLAR5V :
1378 GSEL_BIPOLAR10V);
1379
b6c77757
BP		 1380 /* Switch ADC analog gain. */
1381 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2); /* Write DEBI command */
1382 /* and address to */
1383 /* shadow RAM. */
11e865c1 1384 *pRPS++ = DEBI_CMD_WRWORD | LP_GSEL;
b6c77757
BP		 1385 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2); /* Write DEBI */
1386 /* immediate data to */
1387 /* shadow RAM. */
11e865c1 1388 *pRPS++ = LocalPPL;
b6c77757
BP		 1389 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI; /* Reset "shadow RAM uploaded" */
1390 /* flag. */
1391 *pRPS++ = RPS_UPLOAD | RPS_DEBI; /* Invoke shadow RAM upload. */
1392 *pRPS++ = RPS_PAUSE | RPS_DEBI; /* Wait for shadow upload to */
1393 /* finish. */
1394
1395 /* Select ADC analog input channel. */
1396 *pRPS++ = RPS_LDREG | (P_DEBICMD >> 2);
1397 /* Write DEBI command and address to shadow RAM. */
11e865c1 1398 *pRPS++ = DEBI_CMD_WRWORD | LP_ISEL;
b6c77757
BP		 1399 *pRPS++ = RPS_LDREG | (P_DEBIAD >> 2);
1400 /* Write DEBI immediate data to shadow RAM. */
11e865c1 1401 *pRPS++ = LocalPPL;
b6c77757
BP		 1402 *pRPS++ = RPS_CLRSIGNAL | RPS_DEBI;
1403 /* Reset "shadow RAM uploaded" flag. */
1404
1405 *pRPS++ = RPS_UPLOAD | RPS_DEBI;
1406 /* Invoke shadow RAM upload. */
1407
1408 *pRPS++ = RPS_PAUSE | RPS_DEBI;
1409 /* Wait for shadow upload to finish. */
1410
1411 /* Delay at least 10 microseconds for analog input settling.
1412 * Instead of padding with NOPs, we use RPS_JUMP instructions
1413 * here; this allows us to produce a longer delay than is
1414 * possible with NOPs because each RPS_JUMP flushes the RPS'
1415 * instruction prefetch pipeline.
1416 */
11e865c1
GP		 1417 JmpAdrs =
1418 (uint32_t) devpriv->RPSBuf.PhysicalBase +
1419 (uint32_t) ((unsigned long)pRPS -
1420 (unsigned long)devpriv->RPSBuf.LogicalBase);
1421 for (i = 0; i < (10 * RPSCLK_PER_US / 2); i++) {
b6c77757
BP		 1422 JmpAdrs += 8; /* Repeat to implement time delay: */
1423 *pRPS++ = RPS_JUMP; /* Jump to next RPS instruction. */
11e865c1
GP		 1424 *pRPS++ = JmpAdrs;
1425 }
1426
1427 if (cmd != NULL && cmd->convert_src != TRIG_NOW) {
1428 DEBUG("ResetADC: convert pause inserted\n");
b6c77757 1429 /* Wait for Start trigger. */
11e865c1
GP		 1430 *pRPS++ = RPS_PAUSE | RPS_SIGADC;
1431 *pRPS++ = RPS_CLRSIGNAL | RPS_SIGADC;
1432 }
b6c77757
BP		 1433 /* Start ADC by pulsing GPIO1. */
1434 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
11e865c1
GP		 1435 *pRPS++ = GPIO_BASE | GPIO1_LO;
1436 *pRPS++ = RPS_NOP;
b6c77757
BP		 1437 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1438 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
11e865c1
GP		 1439 *pRPS++ = GPIO_BASE | GPIO1_HI;
1440
b6c77757
BP		 1441 /* Wait for ADC to complete (GPIO2 is asserted high when ADC not
1442 * busy) and for data from previous conversion to shift into FB
1443 * BUFFER 1 register.
1444 */
1445 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1446
b6c77757 1447 /* Transfer ADC data from FB BUFFER 1 register to DMA buffer. */
11e865c1
GP		 1448 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2);
1449 *pRPS++ =
1450 (uint32_t) devpriv->ANABuf.PhysicalBase +
1451 (devpriv->AdcItems << 2);
1452
b6c77757
BP		 1453 /* If this slot's EndOfPollList flag is set, all channels have */
1454 /* now been processed. */
11e865c1 1455 if (*ppl++ & EOPL) {
b6c77757
BP		 1456 devpriv->AdcItems++; /* Adjust poll list item count. */
1457 break; /* Exit poll list processing loop. */
11e865c1
GP		 1458 }
1459 }
1460 DEBUG("ResetADC: ADC items %d \n", devpriv->AdcItems);
1461
b6c77757
BP		 1462 /* VERSION 2.01 CHANGE: DELAY CHANGED FROM 250NS to 2US. Allow the
1463 * ADC to stabilize for 2 microseconds before starting the final
1464 * (dummy) conversion. This delay is necessary to allow sufficient
1465 * time between last conversion finished and the start of the dummy
1466 * conversion. Without this delay, the last conversion's data value
1467 * is sometimes set to the previous conversion's data value.
1468 */
11e865c1
GP		 1469 for (n = 0; n < (2 * RPSCLK_PER_US); n++)
1470 *pRPS++ = RPS_NOP;
1471
b6c77757
BP		 1472 /* Start a dummy conversion to cause the data from the last
1473 * conversion of interest to be shifted in.
1474 */
1475 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* Begin ADC Start pulse. */
11e865c1
GP		 1476 *pRPS++ = GPIO_BASE | GPIO1_LO;
1477 *pRPS++ = RPS_NOP;
b6c77757
BP		 1478 /* VERSION 2.03 CHANGE: STRETCH OUT ADC START PULSE. */
1479 *pRPS++ = RPS_LDREG | (P_GPIO >> 2); /* End ADC Start pulse. */
11e865c1
GP		 1480 *pRPS++ = GPIO_BASE | GPIO1_HI;
1481
b6c77757
BP		 1482 /* Wait for the data from the last conversion of interest to arrive
1483 * in FB BUFFER 1 register.
1484 */
1485 *pRPS++ = RPS_PAUSE | RPS_GPIO2; /* Wait for ADC done. */
11e865c1 1486
b6c77757
BP		 1487 /* Transfer final ADC data from FB BUFFER 1 register to DMA buffer. */
1488 *pRPS++ = RPS_STREG | (BUGFIX_STREG(P_FB_BUFFER1) >> 2); /* */
11e865c1
GP		 1489 *pRPS++ =
1490 (uint32_t) devpriv->ANABuf.PhysicalBase +
1491 (devpriv->AdcItems << 2);
1492
b6c77757
BP		 1493 /* Indicate ADC scan loop is finished. */
1494 /* *pRPS++= RPS_CLRSIGNAL | RPS_SIGADC ; // Signal ReadADC() that scan is done. */
11e865c1 1495
b6c77757 1496 /* invoke interrupt */
11e865c1
GP		 1497 if (devpriv->ai_cmd_running == 1) {
1498 DEBUG("ResetADC: insert irq in ADC RPS task\n");
1499 *pRPS++ = RPS_IRQ;
1500 }
b6c77757
BP		 1501 /* Restart RPS program at its beginning. */
1502 *pRPS++ = RPS_JUMP; /* Branch to start of RPS program. */
11e865c1
GP		 1503 *pRPS++ = (uint32_t) devpriv->RPSBuf.PhysicalBase;
1504
b6c77757 1505 /* End of RPS program build */
11e865c1
GP		 1506}
1507
1508/* TO COMPLETE, IF NECESSARY */
e473e912
BP		 1509static int s626_ai_insn_config(comedi_device *dev, comedi_subdevice *s,
1510 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 1511{
1512
1513 return -EINVAL;
1514}
1515
1516/* static int s626_ai_rinsn(comedi_device *dev,comedi_subdevice *s,comedi_insn *insn,lsampl_t *data) */
1517/* { */
1518/* register uint8_t i; */
1519/* register int32_t *readaddr; */
1520
1521/* DEBUG("as626_ai_rinsn: ai_rinsn enter \n"); */
1522
b6c77757 1523/* Trigger ADC scan loop start by setting RPS Signal 0. */
11e865c1
GP		 1524/* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
1525
b6c77757 1526/* Wait until ADC scan loop is finished (RPS Signal 0 reset). */
11e865c1
GP		 1527/* while ( MC_TEST( P_MC2, MC2_ADC_RPS ) ); */
1528
b6c77757
BP		 1529/* Init ptr to DMA buffer that holds new ADC data. We skip the
1530 * first uint16_t in the buffer because it contains junk data from
1531 * the final ADC of the previous poll list scan.
1532 */
11e865c1
GP		 1533/* readaddr = (uint32_t *)devpriv->ANABuf.LogicalBase + 1; */
1534
b6c77757 1535/* Convert ADC data to 16-bit integer values and copy to application buffer. */
11e865c1
GP		 1536/* for ( i = 0; i < devpriv->AdcItems; i++ ) { */
1537/* *data = s626_ai_reg_to_uint( *readaddr++ ); */
1538/* DEBUG("s626_ai_rinsn: data %d \n",*data); */
1539/* data++; */
1540/* } */
1541
1542/* DEBUG("s626_ai_rinsn: ai_rinsn escape \n"); */
1543/* return i; */
1544/* } */
1545
e473e912
BP		 1546static int s626_ai_insn_read(comedi_device *dev, comedi_subdevice *s,
1547 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 1548{
1549 uint16_t chan = CR_CHAN(insn->chanspec);
1550 uint16_t range = CR_RANGE(insn->chanspec);
1551 uint16_t AdcSpec = 0;
1552 uint32_t GpioImage;
1553 int n;
1554
b6c77757
BP		 1555 /* interrupt call test */
1556/* writel(IRQ_GPIO3,devpriv->base_addr+P_PSR); */
1557 /* Writing a logical 1 into any of the RPS_PSR bits causes the
1558 * corresponding interrupt to be generated if enabled
1559 */
11e865c1
GP		 1560
1561 DEBUG("s626_ai_insn_read: entering\n");
1562
b6c77757
BP		 1563 /* Convert application's ADC specification into form
1564 * appropriate for register programming.
1565 */
11e865c1
GP		 1566 if (range == 0)
1567 AdcSpec = (chan << 8) | (GSEL_BIPOLAR5V);
1568 else
1569 AdcSpec = (chan << 8) | (GSEL_BIPOLAR10V);
1570
b6c77757
BP		 1571 /* Switch ADC analog gain. */
1572 DEBIwrite(dev, LP_GSEL, AdcSpec); /* Set gain. */
11e865c1 1573
b6c77757
BP		 1574 /* Select ADC analog input channel. */
1575 DEBIwrite(dev, LP_ISEL, AdcSpec); /* Select channel. */
11e865c1
GP		 1576
1577 for (n = 0; n < insn->n; n++) {
1578
b6c77757 1579 /* Delay 10 microseconds for analog input settling. */
11e865c1
GP		 1580 comedi_udelay(10);
1581
b6c77757 1582 /* Start ADC by pulsing GPIO1 low. */
11e865c1 1583 GpioImage = RR7146(P_GPIO);
b6c77757 1584 /* Assert ADC Start command */
11e865c1 1585 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1586 /* and stretch it out. */
11e865c1
GP		 1587 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1588 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1589 /* Negate ADC Start command. */
11e865c1
GP		 1590 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1591
b6c77757
BP		 1592 /* Wait for ADC to complete (GPIO2 is asserted high when */
1593 /* ADC not busy) and for data from previous conversion to */
1594 /* shift into FB BUFFER 1 register. */
11e865c1 1595
b6c77757 1596 /* Wait for ADC done. */
c7427409
BP		 1597 while (!(RR7146(P_PSR) & PSR_GPIO2))
1598 ;
11e865c1 1599
b6c77757 1600 /* Fetch ADC data. */
11e865c1
GP		 1601 if (n != 0)
1602 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1603
b6c77757
BP		 1604 /* Allow the ADC to stabilize for 4 microseconds before
1605 * starting the next (final) conversion. This delay is
1606 * necessary to allow sufficient time between last
1607 * conversion finished and the start of the next
1608 * conversion. Without this delay, the last conversion's
1609 * data value is sometimes set to the previous
1610 * conversion's data value.
1611 */
11e865c1
GP		 1612 comedi_udelay(4);
1613 }
1614
b6c77757
BP		 1615 /* Start a dummy conversion to cause the data from the
1616 * previous conversion to be shifted in. */
11e865c1
GP		 1617 GpioImage = RR7146(P_GPIO);
1618
b6c77757 1619 /* Assert ADC Start command */
11e865c1 1620 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1621 /* and stretch it out. */
11e865c1
GP		 1622 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
1623 WR7146(P_GPIO, GpioImage & ~GPIO1_HI);
b6c77757 1624 /* Negate ADC Start command. */
11e865c1
GP		 1625 WR7146(P_GPIO, GpioImage | GPIO1_HI);
1626
b6c77757 1627 /* Wait for the data to arrive in FB BUFFER 1 register. */
11e865c1 1628
b6c77757 1629 /* Wait for ADC done. */
c7427409
BP		 1630 while (!(RR7146(P_PSR) & PSR_GPIO2))
1631 ;
11e865c1 1632
b6c77757 1633 /* Fetch ADC data from audio interface's input shift register. */
11e865c1 1634
b6c77757 1635 /* Fetch ADC data. */
11e865c1
GP		 1636 if (n != 0)
1637 data[n - 1] = s626_ai_reg_to_uint(RR7146(P_FB_BUFFER1));
1638
1639 DEBUG("s626_ai_insn_read: samples %d, data %d\n", n, data[n - 1]);
1640
1641 return n;
1642}
1643
e473e912 1644static int s626_ai_load_polllist(uint8_t *ppl, comedi_cmd *cmd)
11e865c1
GP		 1645{
1646
1647 int n;
1648
1649 for (n = 0; n < cmd->chanlist_len; n++) {
1650 if (CR_RANGE((cmd->chanlist)[n]) == 0)
1651 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_5V);
1652 else
1653 ppl[n] = (CR_CHAN((cmd->chanlist)[n])) | (RANGE_10V);
1654 }
1655 ppl[n - 1] |= EOPL;
1656
1657 return n;
1658}
1659
e473e912 1660static int s626_ai_inttrig(comedi_device *dev, comedi_subdevice *s,
11e865c1
GP		 1661 unsigned int trignum)
1662{
1663 if (trignum != 0)
1664 return -EINVAL;
1665
1666 DEBUG("s626_ai_inttrig: trigger adc start...");
1667
b6c77757 1668 /* Start executing the RPS program. */
11e865c1
GP		 1669 MC_ENABLE(P_MC1, MC1_ERPS1);
1670
1671 s->async->inttrig = NULL;
1672
1673 DEBUG(" done\n");
1674
1675 return 1;
1676}
1677
1678/* TO COMPLETE */
e473e912 1679static int s626_ai_cmd(comedi_device *dev, comedi_subdevice *s)
11e865c1
GP		 1680{
1681
1682 uint8_t ppl[16];
1683 comedi_cmd *cmd = &s->async->cmd;
1684 enc_private *k;
1685 int tick;
1686
1687 DEBUG("s626_ai_cmd: entering command function\n");
1688
1689 if (devpriv->ai_cmd_running) {
1690 printk("s626_ai_cmd: Another ai_cmd is running %d\n",
1691 dev->minor);
1692 return -EBUSY;
1693 }
b6c77757 1694 /* disable interrupt */
11e865c1
GP		 1695 writel(0, devpriv->base_addr + P_IER);
1696
b6c77757 1697 /* clear interrupt request */
11e865c1
GP		 1698 writel(IRQ_RPS1 | IRQ_GPIO3, devpriv->base_addr + P_ISR);
1699
b6c77757 1700 /* clear any pending interrupt */
11e865c1 1701 s626_dio_clear_irq(dev);
b6c77757 1702 /* s626_enc_clear_irq(dev); */
11e865c1 1703
b6c77757 1704 /* reset ai_cmd_running flag */
11e865c1
GP		 1705 devpriv->ai_cmd_running = 0;
1706
b6c77757 1707 /* test if cmd is valid */
11e865c1
GP		 1708 if (cmd == NULL) {
1709 DEBUG("s626_ai_cmd: NULL command\n");
1710 return -EINVAL;
1711 } else {
1712 DEBUG("s626_ai_cmd: command recieved!!!\n");
1713 }
1714
1715 if (dev->irq == 0) {
1716 comedi_error(dev,
1717 "s626_ai_cmd: cannot run command without an irq");
1718 return -EIO;
1719 }
1720
1721 s626_ai_load_polllist(ppl, cmd);
1722 devpriv->ai_cmd_running = 1;
1723 devpriv->ai_convert_count = 0;
1724
1725 switch (cmd->scan_begin_src) {
1726 case TRIG_FOLLOW:
1727 break;
1728 case TRIG_TIMER:
b6c77757 1729 /* set a conter to generate adc trigger at scan_begin_arg interval */
11e865c1
GP		 1730 k = &encpriv[5];
1731 tick = s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1732 cmd->flags & TRIG_ROUND_MASK);
1733
b6c77757 1734 /* load timer value and enable interrupt */
11e865c1
GP		 1735 s626_timer_load(dev, k, tick);
1736 k->SetEnable(dev, k, CLKENAB_ALWAYS);
1737
1738 DEBUG("s626_ai_cmd: scan trigger timer is set with value %d\n",
1739 tick);
1740
1741 break;
1742 case TRIG_EXT:
b6c77757 1743 /* set the digital line and interrupt for scan trigger */
11e865c1
GP		 1744 if (cmd->start_src != TRIG_EXT)
1745 s626_dio_set_irq(dev, cmd->scan_begin_arg);
1746
1747 DEBUG("s626_ai_cmd: External scan trigger is set!!!\n");
1748
1749 break;
1750 }
1751
1752 switch (cmd->convert_src) {
1753 case TRIG_NOW:
1754 break;
1755 case TRIG_TIMER:
b6c77757 1756 /* set a conter to generate adc trigger at convert_arg interval */
11e865c1
GP		 1757 k = &encpriv[4];
1758 tick = s626_ns_to_timer((int *)&cmd->convert_arg,
1759 cmd->flags & TRIG_ROUND_MASK);
1760
b6c77757 1761 /* load timer value and enable interrupt */
11e865c1
GP		 1762 s626_timer_load(dev, k, tick);
1763 k->SetEnable(dev, k, CLKENAB_INDEX);
1764
1765 DEBUG("s626_ai_cmd: convert trigger timer is set with value %d\n", tick);
1766 break;
1767 case TRIG_EXT:
b6c77757 1768 /* set the digital line and interrupt for convert trigger */
11e865c1
GP		 1769 if (cmd->scan_begin_src != TRIG_EXT
1770 && cmd->start_src == TRIG_EXT)
1771 s626_dio_set_irq(dev, cmd->convert_arg);
1772
1773 DEBUG("s626_ai_cmd: External convert trigger is set!!!\n");
1774
1775 break;
1776 }
1777
1778 switch (cmd->stop_src) {
1779 case TRIG_COUNT:
b6c77757 1780 /* data arrives as one packet */
11e865c1
GP		 1781 devpriv->ai_sample_count = cmd->stop_arg;
1782 devpriv->ai_continous = 0;
1783 break;
1784 case TRIG_NONE:
b6c77757 1785 /* continous aquisition */
11e865c1
GP		 1786 devpriv->ai_continous = 1;
1787 devpriv->ai_sample_count = 0;
1788 break;
1789 }
1790
1791 ResetADC(dev, ppl);
1792
1793 switch (cmd->start_src) {
1794 case TRIG_NOW:
b6c77757
BP		 1795 /* Trigger ADC scan loop start by setting RPS Signal 0. */
1796 /* MC_ENABLE( P_MC2, MC2_ADC_RPS ); */
11e865c1 1797
b6c77757 1798 /* Start executing the RPS program. */
11e865c1
GP		 1799 MC_ENABLE(P_MC1, MC1_ERPS1);
1800
1801 DEBUG("s626_ai_cmd: ADC triggered\n");
1802 s->async->inttrig = NULL;
1803 break;
1804 case TRIG_EXT:
b6c77757 1805 /* configure DIO channel for acquisition trigger */
11e865c1
GP		 1806 s626_dio_set_irq(dev, cmd->start_arg);
1807
1808 DEBUG("s626_ai_cmd: External start trigger is set!!!\n");
1809
1810 s->async->inttrig = NULL;
1811 break;
1812 case TRIG_INT:
1813 s->async->inttrig = s626_ai_inttrig;
1814 break;
1815 }
1816
b6c77757 1817 /* enable interrupt */
11e865c1
GP		 1818 writel(IRQ_GPIO3 | IRQ_RPS1, devpriv->base_addr + P_IER);
1819
1820 DEBUG("s626_ai_cmd: command function terminated\n");
1821
1822 return 0;
1823}
1824
e473e912
BP		 1825static int s626_ai_cmdtest(comedi_device *dev, comedi_subdevice *s,
1826 comedi_cmd *cmd)
11e865c1
GP		 1827{
1828 int err = 0;
1829 int tmp;
1830
1831 /* cmdtest tests a particular command to see if it is valid. Using
1832 * the cmdtest ioctl, a user can create a valid cmd and then have it
1833 * executes by the cmd ioctl.
1834 *
1835 * cmdtest returns 1,2,3,4 or 0, depending on which tests the
1836 * command passes. */
1837
1838 /* step 1: make sure trigger sources are trivially valid */
1839
1840 tmp = cmd->start_src;
1841 cmd->start_src &= TRIG_NOW | TRIG_INT | TRIG_EXT;
1842 if (!cmd->start_src || tmp != cmd->start_src)
1843 err++;
1844
1845 tmp = cmd->scan_begin_src;
1846 cmd->scan_begin_src &= TRIG_TIMER | TRIG_EXT | TRIG_FOLLOW;
1847 if (!cmd->scan_begin_src || tmp != cmd->scan_begin_src)
1848 err++;
1849
1850 tmp = cmd->convert_src;
1851 cmd->convert_src &= TRIG_TIMER | TRIG_EXT | TRIG_NOW;
1852 if (!cmd->convert_src || tmp != cmd->convert_src)
1853 err++;
1854
1855 tmp = cmd->scan_end_src;
1856 cmd->scan_end_src &= TRIG_COUNT;
1857 if (!cmd->scan_end_src || tmp != cmd->scan_end_src)
1858 err++;
1859
1860 tmp = cmd->stop_src;
1861 cmd->stop_src &= TRIG_COUNT | TRIG_NONE;
1862 if (!cmd->stop_src || tmp != cmd->stop_src)
1863 err++;
1864
1865 if (err)
1866 return 1;
1867
1868 /* step 2: make sure trigger sources are unique and mutually
1869 compatible */
1870
1871 /* note that mutual compatiblity is not an issue here */
1872 if (cmd->scan_begin_src != TRIG_TIMER &&
1873 cmd->scan_begin_src != TRIG_EXT
1874 && cmd->scan_begin_src != TRIG_FOLLOW)
1875 err++;
1876 if (cmd->convert_src != TRIG_TIMER &&
1877 cmd->convert_src != TRIG_EXT && cmd->convert_src != TRIG_NOW)
1878 err++;
1879 if (cmd->stop_src != TRIG_COUNT && cmd->stop_src != TRIG_NONE)
1880 err++;
1881
1882 if (err)
1883 return 2;
1884
1885 /* step 3: make sure arguments are trivially compatible */
1886
1887 if (cmd->start_src != TRIG_EXT && cmd->start_arg != 0) {
1888 cmd->start_arg = 0;
1889 err++;
1890 }
1891
1892 if (cmd->start_src == TRIG_EXT && cmd->start_arg < 0) {
1893 cmd->start_arg = 0;
1894 err++;
1895 }
1896
1897 if (cmd->start_src == TRIG_EXT && cmd->start_arg > 39) {
1898 cmd->start_arg = 39;
1899 err++;
1900 }
1901
1902 if (cmd->scan_begin_src == TRIG_EXT && cmd->scan_begin_arg < 0) {
1903 cmd->scan_begin_arg = 0;
1904 err++;
1905 }
1906
1907 if (cmd->scan_begin_src == TRIG_EXT && cmd->scan_begin_arg > 39) {
1908 cmd->scan_begin_arg = 39;
1909 err++;
1910 }
1911
1912 if (cmd->convert_src == TRIG_EXT && cmd->convert_arg < 0) {
1913 cmd->convert_arg = 0;
1914 err++;
1915 }
1916
1917 if (cmd->convert_src == TRIG_EXT && cmd->convert_arg > 39) {
1918 cmd->convert_arg = 39;
1919 err++;
1920 }
1921#define MAX_SPEED 200000 /* in nanoseconds */
1922#define MIN_SPEED 2000000000 /* in nanoseconds */
1923
1924 if (cmd->scan_begin_src == TRIG_TIMER) {
1925 if (cmd->scan_begin_arg < MAX_SPEED) {
1926 cmd->scan_begin_arg = MAX_SPEED;
1927 err++;
1928 }
1929 if (cmd->scan_begin_arg > MIN_SPEED) {
1930 cmd->scan_begin_arg = MIN_SPEED;
1931 err++;
1932 }
1933 } else {
1934 /* external trigger */
1935 /* should be level/edge, hi/lo specification here */
1936 /* should specify multiple external triggers */
1937/* if(cmd->scan_begin_arg>9){ */
1938/* cmd->scan_begin_arg=9; */
1939/* err++; */
1940/* } */
1941 }
1942 if (cmd->convert_src == TRIG_TIMER) {
1943 if (cmd->convert_arg < MAX_SPEED) {
1944 cmd->convert_arg = MAX_SPEED;
1945 err++;
1946 }
1947 if (cmd->convert_arg > MIN_SPEED) {
1948 cmd->convert_arg = MIN_SPEED;
1949 err++;
1950 }
1951 } else {
1952 /* external trigger */
1953 /* see above */
1954/* if(cmd->convert_arg>9){ */
1955/* cmd->convert_arg=9; */
1956/* err++; */
1957/* } */
1958 }
1959
1960 if (cmd->scan_end_arg != cmd->chanlist_len) {
1961 cmd->scan_end_arg = cmd->chanlist_len;
1962 err++;
1963 }
1964 if (cmd->stop_src == TRIG_COUNT) {
1965 if (cmd->stop_arg > 0x00ffffff) {
1966 cmd->stop_arg = 0x00ffffff;
1967 err++;
1968 }
1969 } else {
1970 /* TRIG_NONE */
1971 if (cmd->stop_arg != 0) {
1972 cmd->stop_arg = 0;
1973 err++;
1974 }
1975 }
1976
1977 if (err)
1978 return 3;
1979
1980 /* step 4: fix up any arguments */
1981
1982 if (cmd->scan_begin_src == TRIG_TIMER) {
1983 tmp = cmd->scan_begin_arg;
1984 s626_ns_to_timer((int *)&cmd->scan_begin_arg,
1985 cmd->flags & TRIG_ROUND_MASK);
1986 if (tmp != cmd->scan_begin_arg)
1987 err++;
1988 }
1989 if (cmd->convert_src == TRIG_TIMER) {
1990 tmp = cmd->convert_arg;
1991 s626_ns_to_timer((int *)&cmd->convert_arg,
1992 cmd->flags & TRIG_ROUND_MASK);
1993 if (tmp != cmd->convert_arg)
1994 err++;
1995 if (cmd->scan_begin_src == TRIG_TIMER &&
1996 cmd->scan_begin_arg <
1997 cmd->convert_arg * cmd->scan_end_arg) {
1998 cmd->scan_begin_arg =
1999 cmd->convert_arg * cmd->scan_end_arg;
2000 err++;
2001 }
2002 }
2003
2004 if (err)
2005 return 4;
2006
2007 return 0;
2008}
2009
e473e912 2010static int s626_ai_cancel(comedi_device *dev, comedi_subdevice *s)
11e865c1 2011{
b6c77757 2012 /* Stop RPS program in case it is currently running. */
11e865c1
GP		 2013 MC_DISABLE(P_MC1, MC1_ERPS1);
2014
b6c77757 2015 /* disable master interrupt */
11e865c1
GP		 2016 writel(0, devpriv->base_addr + P_IER);
2017
2018 devpriv->ai_cmd_running = 0;
2019
2020 return 0;
2021}
2022
2023/* This function doesn't require a particular form, this is just what
2024 * happens to be used in some of the drivers. It should convert ns
2025 * nanoseconds to a counter value suitable for programming the device.
2026 * Also, it should adjust ns so that it cooresponds to the actual time
2027 * that the device will use. */
2028static int s626_ns_to_timer(int *nanosec, int round_mode)
2029{
2030 int divider, base;
2031
b6c77757 2032 base = 500; /* 2MHz internal clock */
11e865c1
GP		 2033
2034 switch (round_mode) {
2035 case TRIG_ROUND_NEAREST:
2036 default:
2037 divider = (*nanosec + base / 2) / base;
2038 break;
2039 case TRIG_ROUND_DOWN:
2040 divider = (*nanosec) / base;
2041 break;
2042 case TRIG_ROUND_UP:
2043 divider = (*nanosec + base - 1) / base;
2044 break;
2045 }
2046
2047 *nanosec = base * divider;
2048 return divider - 1;
2049}
2050
e473e912
BP		 2051static int s626_ao_winsn(comedi_device *dev, comedi_subdevice *s,
2052 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2053{
2054
2055 int i;
2056 uint16_t chan = CR_CHAN(insn->chanspec);
2057 int16_t dacdata;
2058
2059 for (i = 0; i < insn->n; i++) {
2060 dacdata = (int16_t) data[i];
2061 devpriv->ao_readback[CR_CHAN(insn->chanspec)] = data[i];
2062 dacdata -= (0x1fff);
2063
2064 SetDAC(dev, chan, dacdata);
2065 }
2066
2067 return i;
2068}
2069
e473e912
BP		 2070static int s626_ao_rinsn(comedi_device *dev, comedi_subdevice *s,
2071 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2072{
2073 int i;
2074
2075 for (i = 0; i < insn->n; i++) {
2076 data[i] = devpriv->ao_readback[CR_CHAN(insn->chanspec)];
2077 }
2078
2079 return i;
2080}
2081
b6c77757
BP		 2082/* *************** DIGITAL I/O FUNCTIONS ***************
2083 * All DIO functions address a group of DIO channels by means of
2084 * "group" argument. group may be 0, 1 or 2, which correspond to DIO
2085 * ports A, B and C, respectively.
2086 */
11e865c1 2087
e473e912 2088static void s626_dio_init(comedi_device *dev)
11e865c1
GP		 2089{
2090 uint16_t group;
2091 comedi_subdevice *s;
2092
b6c77757 2093 /* Prepare to treat writes to WRCapSel as capture disables. */
11e865c1
GP		 2094 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2095
b6c77757 2096 /* For each group of sixteen channels ... */
11e865c1
GP		 2097 for (group = 0; group < S626_DIO_BANKS; group++) {
2098 s = dev->subdevices + 2 + group;
b6c77757
BP		 2099 DEBIwrite(dev, diopriv->WRIntSel, 0); /* Disable all interrupts. */
2100 DEBIwrite(dev, diopriv->WRCapSel, 0xFFFF); /* Disable all event */
2101 /* captures. */
2102 DEBIwrite(dev, diopriv->WREdgSel, 0); /* Init all DIOs to */
2103 /* default edge */
2104 /* polarity. */
2105 DEBIwrite(dev, diopriv->WRDOut, 0); /* Program all outputs */
2106 /* to inactive state. */
11e865c1
GP		 2107 }
2108 DEBUG("s626_dio_init: DIO initialized \n");
2109}
2110
2111/* DIO devices are slightly special. Although it is possible to
2112 * implement the insn_read/insn_write interface, it is much more
2113 * useful to applications if you implement the insn_bits interface.
2114 * This allows packed reading/writing of the DIO channels. The comedi
2115 * core can convert between insn_bits and insn_read/write */
2116
e473e912
BP		 2117static int s626_dio_insn_bits(comedi_device *dev, comedi_subdevice *s,
2118 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2119{
2120
2121 /* Length of data must be 2 (mask and new data, see below) */
2122 if (insn->n == 0) {
2123 return 0;
2124 }
2125 if (insn->n != 2) {
2126 printk("comedi%d: s626: s626_dio_insn_bits(): Invalid instruction length\n", dev->minor);
2127 return -EINVAL;
2128 }
2129
2130 /*
2131 * The insn data consists of a mask in data[0] and the new data in
2132 * data[1]. The mask defines which bits we are concerning about.
2133 * The new data must be anded with the mask. Each channel
2134 * corresponds to a bit.
2135 */
2136 if (data[0]) {
2137 /* Check if requested ports are configured for output */
2138 if ((s->io_bits & data[0]) != data[0])
2139 return -EIO;
2140
2141 s->state &= ~data[0];
2142 s->state |= data[0] & data[1];
2143
2144 /* Write out the new digital output lines */
2145
2146 DEBIwrite(dev, diopriv->WRDOut, s->state);
2147 }
2148 data[1] = DEBIread(dev, diopriv->RDDIn);
2149
2150 return 2;
2151}
2152
e473e912
BP		 2153static int s626_dio_insn_config(comedi_device *dev, comedi_subdevice *s,
2154 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2155{
2156
2157 switch (data[0]) {
2158 case INSN_CONFIG_DIO_QUERY:
2159 data[1] =
2160 (s->io_bits & (1 << CR_CHAN(insn->
2161 chanspec))) ? COMEDI_OUTPUT :
2162 COMEDI_INPUT;
2163 return insn->n;
2164 break;
2165 case COMEDI_INPUT:
2166 s->io_bits &= ~(1 << CR_CHAN(insn->chanspec));
2167 break;
2168 case COMEDI_OUTPUT:
2169 s->io_bits |= 1 << CR_CHAN(insn->chanspec);
2170 break;
2171 default:
2172 return -EINVAL;
2173 break;
2174 }
2175 DEBIwrite(dev, diopriv->WRDOut, s->io_bits);
2176
2177 return 1;
2178}
2179
e473e912 2180static int s626_dio_set_irq(comedi_device *dev, unsigned int chan)
11e865c1
GP		 2181{
2182 unsigned int group;
2183 unsigned int bitmask;
2184 unsigned int status;
2185
b6c77757 2186 /* select dio bank */
11e865c1
GP		 2187 group = chan / 16;
2188 bitmask = 1 << (chan - (16 * group));
2189 DEBUG("s626_dio_set_irq: enable interrupt on dio channel %d group %d\n",
2190 chan - (16 * group), group);
2191
b6c77757 2192 /* set channel to capture positive edge */
11e865c1
GP		 2193 status = DEBIread(dev,
2194 ((dio_private *) (dev->subdevices + 2 +
2195 group)->private)->RDEdgSel);
2196 DEBIwrite(dev,
2197 ((dio_private *) (dev->subdevices + 2 +
2198 group)->private)->WREdgSel, bitmask | status);
2199
b6c77757 2200 /* enable interrupt on selected channel */
11e865c1
GP		 2201 status = DEBIread(dev,
2202 ((dio_private *) (dev->subdevices + 2 +
2203 group)->private)->RDIntSel);
2204 DEBIwrite(dev,
2205 ((dio_private *) (dev->subdevices + 2 +
2206 group)->private)->WRIntSel, bitmask | status);
2207
b6c77757 2208 /* enable edge capture write command */
11e865c1
GP		 2209 DEBIwrite(dev, LP_MISC1, MISC1_EDCAP);
2210
b6c77757 2211 /* enable edge capture on selected channel */
11e865c1
GP		 2212 status = DEBIread(dev,
2213 ((dio_private *) (dev->subdevices + 2 +
2214 group)->private)->RDCapSel);
2215 DEBIwrite(dev,
2216 ((dio_private *) (dev->subdevices + 2 +
2217 group)->private)->WRCapSel, bitmask | status);
2218
2219 return 0;
2220}
2221
e473e912 2222static int s626_dio_reset_irq(comedi_device *dev, unsigned int group,
11e865c1
GP		 2223 unsigned int mask)
2224{
2225 DEBUG("s626_dio_reset_irq: disable interrupt on dio channel %d group %d\n", mask, group);
2226
b6c77757 2227 /* disable edge capture write command */
11e865c1
GP		 2228 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2229
b6c77757 2230 /* enable edge capture on selected channel */
11e865c1
GP		 2231 DEBIwrite(dev,
2232 ((dio_private *) (dev->subdevices + 2 +
2233 group)->private)->WRCapSel, mask);
2234
2235 return 0;
2236}
2237
e473e912 2238static int s626_dio_clear_irq(comedi_device *dev)
11e865c1
GP		 2239{
2240 unsigned int group;
2241
b6c77757 2242 /* disable edge capture write command */
11e865c1
GP		 2243 DEBIwrite(dev, LP_MISC1, MISC1_NOEDCAP);
2244
2245 for (group = 0; group < S626_DIO_BANKS; group++) {
b6c77757 2246 /* clear pending events and interrupt */
11e865c1
GP		 2247 DEBIwrite(dev,
2248 ((dio_private *) (dev->subdevices + 2 +
2249 group)->private)->WRCapSel, 0xffff);
2250 }
2251
2252 return 0;
2253}
2254
2255/* Now this function initializes the value of the counter (data[0])
2256 and set the subdevice. To complete with trigger and interrupt
2257 configuration */
e473e912
BP		 2258static int s626_enc_insn_config(comedi_device *dev, comedi_subdevice *s,
2259 comedi_insn *insn, lsampl_t *data)
11e865c1 2260{
b6c77757
BP		 2261 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2262 /* index. */
2263 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2264 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is Counter. */
2265 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2266 /* ( CNTDIR_UP << BF_CLKPOL ) | // Count direction is Down. */
2267 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
11e865c1
GP		 2268 (CLKENAB_INDEX << BF_CLKENAB);
2269 /* uint16_t DisableIntSrc=TRUE; */
b6c77757 2270 /* uint32_t Preloadvalue; //Counter initial value */
11e865c1
GP		 2271 uint16_t valueSrclatch = LATCHSRC_AB_READ;
2272 uint16_t enab = CLKENAB_ALWAYS;
2273 enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2274
2275 DEBUG("s626_enc_insn_config: encoder config\n");
2276
b6c77757 2277 /* (data==NULL) ? (Preloadvalue=0) : (Preloadvalue=data[0]); */
11e865c1
GP		 2278
2279 k->SetMode(dev, k, Setup, TRUE);
2280 Preload(dev, k, *(insn->data));
2281 k->PulseIndex(dev, k);
2282 SetLatchSource(dev, k, valueSrclatch);
2283 k->SetEnable(dev, k, (uint16_t) (enab != 0));
2284
2285 return insn->n;
2286}
2287
e473e912
BP		 2288static int s626_enc_insn_read(comedi_device *dev, comedi_subdevice *s,
2289 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2290{
2291
2292 int n;
2293 enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2294
2295 DEBUG("s626_enc_insn_read: encoder read channel %d \n",
2296 CR_CHAN(insn->chanspec));
2297
2298 for (n = 0; n < insn->n; n++)
2299 data[n] = ReadLatch(dev, k);
2300
2301 DEBUG("s626_enc_insn_read: encoder sample %d\n", data[n]);
2302
2303 return n;
2304}
2305
e473e912
BP		 2306static int s626_enc_insn_write(comedi_device *dev, comedi_subdevice *s,
2307 comedi_insn *insn, lsampl_t *data)
11e865c1
GP		 2308{
2309
2310 enc_private *k = &encpriv[CR_CHAN(insn->chanspec)];
2311
2312 DEBUG("s626_enc_insn_write: encoder write channel %d \n",
2313 CR_CHAN(insn->chanspec));
2314
b6c77757 2315 /* Set the preload register */
11e865c1
GP		 2316 Preload(dev, k, data[0]);
2317
b6c77757
BP		 2318 /* Software index pulse forces the preload register to load */
2319 /* into the counter */
11e865c1
GP		 2320 k->SetLoadTrig(dev, k, 0);
2321 k->PulseIndex(dev, k);
2322 k->SetLoadTrig(dev, k, 2);
2323
2324 DEBUG("s626_enc_insn_write: End encoder write\n");
2325
2326 return 1;
2327}
2328
e473e912 2329static void s626_timer_load(comedi_device *dev, enc_private *k, int tick)
11e865c1 2330{
b6c77757
BP		 2331 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
2332 /* index. */
2333 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
2334 (CLKSRC_TIMER << BF_CLKSRC) | /* Operating mode is Timer. */
2335 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
2336 (CNTDIR_DOWN << BF_CLKPOL) | /* Count direction is Down. */
2337 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
11e865c1
GP		 2338 (CLKENAB_INDEX << BF_CLKENAB);
2339 uint16_t valueSrclatch = LATCHSRC_A_INDXA;
b6c77757 2340 /* uint16_t enab=CLKENAB_ALWAYS; */
11e865c1
GP		 2341
2342 k->SetMode(dev, k, Setup, FALSE);
2343
b6c77757 2344 /* Set the preload register */
11e865c1
GP		 2345 Preload(dev, k, tick);
2346
b6c77757
BP		 2347 /* Software index pulse forces the preload register to load */
2348 /* into the counter */
11e865c1
GP		 2349 k->SetLoadTrig(dev, k, 0);
2350 k->PulseIndex(dev, k);
2351
b6c77757 2352 /* set reload on counter overflow */
11e865c1
GP		 2353 k->SetLoadTrig(dev, k, 1);
2354
b6c77757 2355 /* set interrupt on overflow */
11e865c1
GP		 2356 k->SetIntSrc(dev, k, INTSRC_OVER);
2357
2358 SetLatchSource(dev, k, valueSrclatch);
b6c77757 2359 /* k->SetEnable(dev,k,(uint16_t)(enab != 0)); */
11e865c1
GP		 2360}
2361
b6c77757 2362/* *********** DAC FUNCTIONS *********** */
11e865c1 2363
b6c77757 2364/* Slot 0 base settings. */
6a98d36e 2365#define VECT0 (XSD2 | RSD3 | SIB_A2)
b6c77757 2366/* Slot 0 always shifts in 0xFF and store it to FB_BUFFER2. */
11e865c1 2367
b6c77757 2368/* TrimDac LogicalChan-to-PhysicalChan mapping table. */
11e865c1
GP		 2369static uint8_t trimchan[] = { 10, 9, 8, 3, 2, 7, 6, 1, 0, 5, 4 };
2370
b6c77757 2371/* TrimDac LogicalChan-to-EepromAdrs mapping table. */
11e865c1
GP		 2372static uint8_t trimadrs[] =
2373 { 0x40, 0x41, 0x42, 0x50, 0x51, 0x52, 0x53, 0x60, 0x61, 0x62, 0x63 };
2374
e473e912 2375static void LoadTrimDACs(comedi_device *dev)
11e865c1
GP		 2376{
2377 register uint8_t i;
2378
b6c77757 2379 /* Copy TrimDac setpoint values from EEPROM to TrimDacs. */
11e865c1
GP		 2380 for (i = 0; i < (sizeof(trimchan) / sizeof(trimchan[0])); i++)
2381 WriteTrimDAC(dev, i, I2Cread(dev, trimadrs[i]));
2382}
2383
e473e912 2384static void WriteTrimDAC(comedi_device *dev, uint8_t LogicalChan,
11e865c1
GP		 2385 uint8_t DacData)
2386{
2387 uint32_t chan;
2388
b6c77757 2389 /* Save the new setpoint in case the application needs to read it back later. */
11e865c1
GP		 2390 devpriv->TrimSetpoint[LogicalChan] = (uint8_t) DacData;
2391
b6c77757 2392 /* Map logical channel number to physical channel number. */
11e865c1
GP		 2393 chan = (uint32_t) trimchan[LogicalChan];
2394
b6c77757
BP		 2395 /* Set up TSL2 records for TrimDac write operation. All slots shift
2396 * 0xFF in from pulled-up SD3 so that the end of the slot sequence
2397 * can be detected.
2398 */
2399
2400 SETVECT(2, XSD2 | XFIFO_1 | WS3);
2401 /* Slot 2: Send high uint8_t to target TrimDac. */
2402 SETVECT(3, XSD2 | XFIFO_0 | WS3);
2403 /* Slot 3: Send low uint8_t to target TrimDac. */
2404 SETVECT(4, XSD2 | XFIFO_3 | WS1);
2405 /* Slot 4: Send NOP high uint8_t to DAC0 to keep clock running. */
2406 SETVECT(5, XSD2 | XFIFO_2 | WS1 | EOS);
2407 /* Slot 5: Send NOP low uint8_t to DAC0. */
2408
2409 /* Construct and transmit target DAC's serial packet:
2410 * ( 0000 AAAA ), ( DDDD DDDD ),( 0x00 ),( 0x00 ) where A<3:0> is the
2411 * DAC channel's address, and D<7:0> is the DAC setpoint. Append a
2412 * WORD value (that writes a channel 0 NOP command to a non-existent
2413 * main DAC channel) that serves to keep the clock running after the
2414 * packet has been sent to the target DAC.
2415 */
11e865c1 2416
b6c77757
BP		 2417 /* Address the DAC channel within the trimdac device. */
2418 SendDAC(dev, ((uint32_t) chan << 8)
2419 | (uint32_t) DacData); /* Include DAC setpoint data. */
2420}
11e865c1 2421
b6c77757
BP		 2422/* ************** EEPROM ACCESS FUNCTIONS ************** */
2423/* Read uint8_t from EEPROM. */
11e865c1 2424
e473e912 2425static uint8_t I2Cread(comedi_device *dev, uint8_t addr)
11e865c1
GP		 2426{
2427 uint8_t rtnval;
2428
b6c77757
BP		 2429 /* Send EEPROM target address. */
2430 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CW)
2431 /* Byte2 = I2C command: write to I2C EEPROM device. */
2432 | I2C_B1(I2C_ATTRSTOP, addr)
2433 /* Byte1 = EEPROM internal target address. */
f10fe574 2434 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
b6c77757 2435 /* Abort function and declare error if handshake failed. */
11e865c1
GP		 2436 DEBUG("I2Cread: error handshake I2Cread a\n");
2437 return 0;
2438 }
b6c77757
BP		 2439 /* Execute EEPROM read. */
2440 if (I2Chandshake(dev, I2C_B2(I2C_ATTRSTART, I2CR) /* Byte2 = I2C */
2441 /* command: read */
2442 /* from I2C EEPROM */
2443 /* device. */
2444 | I2C_B1(I2C_ATTRSTOP, 0) /* Byte1 receives */
2445 /* uint8_t from */
2446 /* EEPROM. */
f10fe574
BP		 2447 | I2C_B0(I2C_ATTRNOP, 0))) { /* Byte0 = Not sent. */
2448
b6c77757 2449 /* Abort function and declare error if handshake failed. */
11e865c1
GP		 2450 DEBUG("I2Cread: error handshake I2Cread b\n");
2451 return 0;
2452 }
b6c77757 2453 /* Return copy of EEPROM value. */
11e865c1
GP		 2454 rtnval = (uint8_t) (RR7146(P_I2CCTRL) >> 16);
2455 return rtnval;
2456}
2457
e473e912 2458static uint32_t I2Chandshake(comedi_device *dev, uint32_t val)
11e865c1 2459{
b6c77757 2460 /* Write I2C command to I2C Transfer Control shadow register. */
11e865c1
GP		 2461 WR7146(P_I2CCTRL, val);
2462
b6c77757
BP		 2463 /* Upload I2C shadow registers into working registers and wait for */
2464 /* upload confirmation. */
11e865c1
GP		 2465
2466 MC_ENABLE(P_MC2, MC2_UPLD_IIC);
c7427409
BP		 2467 while (!MC_TEST(P_MC2, MC2_UPLD_IIC))
2468 ;
11e865c1 2469
b6c77757 2470 /* Wait until I2C bus transfer is finished or an error occurs. */
c7427409
BP		 2471 while ((RR7146(P_I2CCTRL) & (I2C_BUSY | I2C_ERR)) == I2C_BUSY)
2472 ;
11e865c1 2473
b6c77757 2474 /* Return non-zero if I2C error occured. */
11e865c1
GP		 2475 return RR7146(P_I2CCTRL) & I2C_ERR;
2476
2477}
2478
b6c77757 2479/* Private helper function: Write setpoint to an application DAC channel. */
11e865c1 2480
e473e912 2481static void SetDAC(comedi_device *dev, uint16_t chan, short dacdata)
11e865c1
GP		 2482{
2483 register uint16_t signmask;
2484 register uint32_t WSImage;
2485
b6c77757
BP		 2486 /* Adjust DAC data polarity and set up Polarity Control Register */
2487 /* image. */
11e865c1
GP		 2488 signmask = 1 << chan;
2489 if (dacdata < 0) {
2490 dacdata = -dacdata;
2491 devpriv->Dacpol |= signmask;
2492 } else
2493 devpriv->Dacpol &= ~signmask;
2494
b6c77757 2495 /* Limit DAC setpoint value to valid range. */
11e865c1
GP		 2496 if ((uint16_t) dacdata > 0x1FFF)
2497 dacdata = 0x1FFF;
2498
b6c77757
BP		 2499 /* Set up TSL2 records (aka "vectors") for DAC update. Vectors V2
2500 * and V3 transmit the setpoint to the target DAC. V4 and V5 send
2501 * data to a non-existent TrimDac channel just to keep the clock
2502 * running after sending data to the target DAC. This is necessary
2503 * to eliminate the clock glitch that would otherwise occur at the
2504 * end of the target DAC's serial data stream. When the sequence
2505 * restarts at V0 (after executing V5), the gate array automatically
2506 * disables gating for the DAC clock and all DAC chip selects.
2507 */
2508
2509 WSImage = (chan & 2) ? WS1 : WS2;
2510 /* Choose DAC chip select to be asserted. */
2511 SETVECT(2, XSD2 | XFIFO_1 | WSImage);
2512 /* Slot 2: Transmit high data byte to target DAC. */
2513 SETVECT(3, XSD2 | XFIFO_0 | WSImage);
2514 /* Slot 3: Transmit low data byte to target DAC. */
2515 SETVECT(4, XSD2 | XFIFO_3 | WS3);
2516 /* Slot 4: Transmit to non-existent TrimDac channel to keep clock */
2517 SETVECT(5, XSD2 | XFIFO_2 | WS3 | EOS);
2518 /* Slot 5: running after writing target DAC's low data byte. */
2519
2520 /* Construct and transmit target DAC's serial packet:
2521 * ( A10D DDDD ),( DDDD DDDD ),( 0x0F ),( 0x00 ) where A is chan<0>,
2522 * and D<12:0> is the DAC setpoint. Append a WORD value (that writes
2523 * to a non-existent TrimDac channel) that serves to keep the clock
2524 * running after the packet has been sent to the target DAC.
2525 */
2526 SendDAC(dev, 0x0F000000
2527 /* Continue clock after target DAC data (write to non-existent trimdac). */
2528 | 0x00004000
2529 /* Address the two main dual-DAC devices (TSL's chip select enables
2530 * target device). */
2531 | ((uint32_t) (chan & 1) << 15)
2532 /* Address the DAC channel within the device. */
2533 | (uint32_t) dacdata); /* Include DAC setpoint data. */
11e865c1
GP		 2534
2535}
2536
b6c77757
BP		 2537/* Private helper function: Transmit serial data to DAC via Audio
2538 * channel 2. Assumes: (1) TSL2 slot records initialized, and (2)
2539 * Dacpol contains valid target image.
2540 */
11e865c1 2541
e473e912 2542static void SendDAC(comedi_device *dev, uint32_t val)
11e865c1
GP		 2543{
2544
b6c77757 2545 /* START THE SERIAL CLOCK RUNNING ------------- */
11e865c1 2546
b6c77757
BP		 2547 /* Assert DAC polarity control and enable gating of DAC serial clock
2548 * and audio bit stream signals. At this point in time we must be
2549 * assured of being in time slot 0. If we are not in slot 0, the
2550 * serial clock and audio stream signals will be disabled; this is
2551 * because the following DEBIwrite statement (which enables signals
2552 * to be passed through the gate array) would execute before the
2553 * trailing edge of WS1/WS3 (which turns off the signals), thus
2554 * causing the signals to be inactive during the DAC write.
2555 */
11e865c1
GP		 2556 DEBIwrite(dev, LP_DACPOL, devpriv->Dacpol);
2557
b6c77757 2558 /* TRANSFER OUTPUT DWORD VALUE INTO A2'S OUTPUT FIFO ---------------- */
11e865c1 2559
b6c77757 2560 /* Copy DAC setpoint value to DAC's output DMA buffer. */
11e865c1 2561
b6c77757 2562 /* WR7146( (uint32_t)devpriv->pDacWBuf, val ); */
11e865c1
GP		 2563 *devpriv->pDacWBuf = val;
2564
b6c77757
BP		 2565 /* enab the output DMA transfer. This will cause the DMAC to copy
2566 * the DAC's data value to A2's output FIFO. The DMA transfer will
2567 * then immediately terminate because the protection address is
2568 * reached upon transfer of the first DWORD value.
2569 */
11e865c1
GP		 2570 MC_ENABLE(P_MC1, MC1_A2OUT);
2571
b6c77757 2572 /* While the DMA transfer is executing ... */
11e865c1 2573
b6c77757
BP		 2574 /* Reset Audio2 output FIFO's underflow flag (along with any other
2575 * FIFO underflow/overflow flags). When set, this flag will
2576 * indicate that we have emerged from slot 0.
2577 */
11e865c1
GP		 2578 WR7146(P_ISR, ISR_AFOU);
2579
b6c77757
BP		 2580 /* Wait for the DMA transfer to finish so that there will be data
2581 * available in the FIFO when time slot 1 tries to transfer a DWORD
2582 * from the FIFO to the output buffer register. We test for DMA
2583 * Done by polling the DMAC enable flag; this flag is automatically
2584 * cleared when the transfer has finished.
2585 */
c7427409
BP		 2586 while ((RR7146(P_MC1) & MC1_A2OUT) != 0)
2587 ;
11e865c1 2588
b6c77757 2589 /* START THE OUTPUT STREAM TO THE TARGET DAC -------------------- */
11e865c1 2590
b6c77757
BP		 2591 /* FIFO data is now available, so we enable execution of time slots
2592 * 1 and higher by clearing the EOS flag in slot 0. Note that SD3
2593 * will be shifted in and stored in FB_BUFFER2 for end-of-slot-list
2594 * detection.
2595 */
11e865c1
GP		 2596 SETVECT(0, XSD2 | RSD3 | SIB_A2);
2597
b6c77757
BP		 2598 /* Wait for slot 1 to execute to ensure that the Packet will be
2599 * transmitted. This is detected by polling the Audio2 output FIFO
2600 * underflow flag, which will be set when slot 1 execution has
2601 * finished transferring the DAC's data DWORD from the output FIFO
2602 * to the output buffer register.
2603 */
c7427409
BP		 2604 while ((RR7146(P_SSR) & SSR_AF2_OUT) == 0)
2605 ;
11e865c1 2606
b6c77757
BP		 2607 /* Set up to trap execution at slot 0 when the TSL sequencer cycles
2608 * back to slot 0 after executing the EOS in slot 5. Also,
2609 * simultaneously shift out and in the 0x00 that is ALWAYS the value
2610 * stored in the last byte to be shifted out of the FIFO's DWORD
2611 * buffer register.
2612 */
11e865c1
GP		 2613 SETVECT(0, XSD2 | XFIFO_2 | RSD2 | SIB_A2 | EOS);
2614
b6c77757
BP		 2615 /* WAIT FOR THE TRANSACTION TO FINISH ----------------------- */
2616
2617 /* Wait for the TSL to finish executing all time slots before
2618 * exiting this function. We must do this so that the next DAC
2619 * write doesn't start, thereby enabling clock/chip select signals:
2620 *
2621 * 1. Before the TSL sequence cycles back to slot 0, which disables
2622 * the clock/cs signal gating and traps slot // list execution.
2623 * we have not yet finished slot 5 then the clock/cs signals are
2624 * still gated and we have not finished transmitting the stream.
2625 *
2626 * 2. While slots 2-5 are executing due to a late slot 0 trap. In
2627 * this case, the slot sequence is currently repeating, but with
2628 * clock/cs signals disabled. We must wait for slot 0 to trap
2629 * execution before setting up the next DAC setpoint DMA transfer
2630 * and enabling the clock/cs signals. To detect the end of slot 5,
2631 * we test for the FB_BUFFER2 MSB contents to be equal to 0xFF. If
2632 * the TSL has not yet finished executing slot 5 ...
2633 */
11e865c1 2634 if ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0) {
b6c77757
BP		 2635 /* The trap was set on time and we are still executing somewhere
2636 * in slots 2-5, so we now wait for slot 0 to execute and trap
2637 * TSL execution. This is detected when FB_BUFFER2 MSB changes
2638 * from 0xFF to 0x00, which slot 0 causes to happen by shifting
2639 * out/in on SD2 the 0x00 that is always referenced by slot 5.
2640 */
c7427409
BP		 2641 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) != 0)
2642 ;
11e865c1 2643 }
b6c77757
BP		 2644 /* Either (1) we were too late setting the slot 0 trap; the TSL
2645 * sequencer restarted slot 0 before we could set the EOS trap flag,
2646 * or (2) we were not late and execution is now trapped at slot 0.
2647 * In either case, we must now change slot 0 so that it will store
2648 * value 0xFF (instead of 0x00) to FB_BUFFER2 next time it executes.
2649 * In order to do this, we reprogram slot 0 so that it will shift in
2650 * SD3, which is driven only by a pull-up resistor.
2651 */
11e865c1
GP		 2652 SETVECT(0, RSD3 | SIB_A2 | EOS);
2653
b6c77757
BP		 2654 /* Wait for slot 0 to execute, at which time the TSL is setup for
2655 * the next DAC write. This is detected when FB_BUFFER2 MSB changes
2656 * from 0x00 to 0xFF.
2657 */
c7427409
BP		 2658 while ((RR7146(P_FB_BUFFER2) & 0xFF000000) == 0)
2659 ;
11e865c1
GP		 2660}
2661
e473e912 2662static void WriteMISC2(comedi_device *dev, uint16_t NewImage)
11e865c1 2663{
b6c77757
BP		 2664 DEBIwrite(dev, LP_MISC1, MISC1_WENABLE); /* enab writes to */
2665 /* MISC2 register. */
2666 DEBIwrite(dev, LP_WRMISC2, NewImage); /* Write new image to MISC2. */
2667 DEBIwrite(dev, LP_MISC1, MISC1_WDISABLE); /* Disable writes to MISC2. */
11e865c1
GP		 2668}
2669
b6c77757 2670/* Initialize the DEBI interface for all transfers. */
11e865c1 2671
e473e912 2672static uint16_t DEBIread(comedi_device *dev, uint16_t addr)
11e865c1
GP		 2673{
2674 uint16_t retval;
2675
b6c77757 2676 /* Set up DEBI control register value in shadow RAM. */
11e865c1
GP		 2677 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2678
b6c77757 2679 /* Execute the DEBI transfer. */
11e865c1
GP		 2680 DEBItransfer(dev);
2681
b6c77757 2682 /* Fetch target register value. */
11e865c1
GP		 2683 retval = (uint16_t) RR7146(P_DEBIAD);
2684
b6c77757 2685 /* Return register value. */
11e865c1
GP		 2686 return retval;
2687}
2688
b6c77757
BP		 2689/* Execute a DEBI transfer. This must be called from within a */
2690/* critical section. */
e473e912 2691static void DEBItransfer(comedi_device *dev)
11e865c1 2692{
b6c77757 2693 /* Initiate upload of shadow RAM to DEBI control register. */
11e865c1
GP		 2694 MC_ENABLE(P_MC2, MC2_UPLD_DEBI);
2695
b6c77757
BP		 2696 /* Wait for completion of upload from shadow RAM to DEBI control */
2697 /* register. */
c7427409
BP		 2698 while (!MC_TEST(P_MC2, MC2_UPLD_DEBI))
2699 ;
11e865c1 2700
b6c77757 2701 /* Wait until DEBI transfer is done. */
c7427409
BP		 2702 while (RR7146(P_PSR) & PSR_DEBI_S)
2703 ;
11e865c1
GP		 2704}
2705
b6c77757 2706/* Write a value to a gate array register. */
e473e912 2707static void DEBIwrite(comedi_device *dev, uint16_t addr, uint16_t wdata)
11e865c1
GP		 2708{
2709
b6c77757 2710 /* Set up DEBI control register value in shadow RAM. */
11e865c1
GP		 2711 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2712 WR7146(P_DEBIAD, wdata);
2713
b6c77757 2714 /* Execute the DEBI transfer. */
11e865c1
GP		 2715 DEBItransfer(dev);
2716}
2717
b6c77757
BP		 2718/* Replace the specified bits in a gate array register. Imports: mask
2719 * specifies bits that are to be preserved, wdata is new value to be
2720 * or'd with the masked original.
2721 */
e473e912 2722static void DEBIreplace(comedi_device *dev, uint16_t addr, uint16_t mask,
11e865c1
GP		 2723 uint16_t wdata)
2724{
2725
b6c77757
BP		 2726 /* Copy target gate array register into P_DEBIAD register. */
2727 WR7146(P_DEBICMD, DEBI_CMD_RDWORD | addr);
2728 /* Set up DEBI control reg value in shadow RAM. */
2729 DEBItransfer(dev); /* Execute the DEBI Read transfer. */
11e865c1 2730
b6c77757
BP		 2731 /* Write back the modified image. */
2732 WR7146(P_DEBICMD, DEBI_CMD_WRWORD | addr);
2733 /* Set up DEBI control reg value in shadow RAM. */
11e865c1 2734
b6c77757
BP		 2735 WR7146(P_DEBIAD, wdata | ((uint16_t) RR7146(P_DEBIAD) & mask));
2736 /* Modify the register image. */
2737 DEBItransfer(dev); /* Execute the DEBI Write transfer. */
11e865c1
GP		 2738}
2739
e473e912 2740static void CloseDMAB(comedi_device *dev, DMABUF *pdma, size_t bsize)
11e865c1
GP		 2741{
2742 void *vbptr;
2743 dma_addr_t vpptr;
2744
2745 DEBUG("CloseDMAB: Entering S626DRV_CloseDMAB():\n");
2746 if (pdma == NULL)
2747 return;
b6c77757 2748 /* find the matching allocation from the board struct */
11e865c1
GP		 2749
2750 vbptr = pdma->LogicalBase;
2751 vpptr = pdma->PhysicalBase;
2752 if (vbptr) {
2753 pci_free_consistent(devpriv->pdev, bsize, vbptr, vpptr);
2754 pdma->LogicalBase = 0;
2755 pdma->PhysicalBase = 0;
2756
2757 DEBUG("CloseDMAB(): Logical=%p, bsize=%d, Physical=0x%x\n",
2758 vbptr, bsize, (uint32_t) vpptr);
2759 }
2760}
2761
b6c77757
BP		 2762/* ****** COUNTER FUNCTIONS ******* */
2763/* All counter functions address a specific counter by means of the
2764 * "Counter" argument, which is a logical counter number. The Counter
2765 * argument may have any of the following legal values: 0=0A, 1=1A,
2766 * 2=2A, 3=0B, 4=1B, 5=2B.
2767 */
11e865c1 2768
b6c77757 2769/* Forward declarations for functions that are common to both A and B counters: */
11e865c1 2770
b6c77757 2771/* ****** PRIVATE COUNTER FUNCTIONS ****** */
11e865c1 2772
b6c77757 2773/* Read a counter's output latch. */
11e865c1 2774
e473e912 2775static uint32_t ReadLatch(comedi_device *dev, enc_private *k)
11e865c1
GP		 2776{
2777 register uint32_t value;
b6c77757 2778 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch enter\n"); */
11e865c1 2779
b6c77757 2780 /* Latch counts and fetch LSW of latched counts value. */
11e865c1
GP		 2781 value = (uint32_t) DEBIread(dev, k->MyLatchLsw);
2782
b6c77757 2783 /* Fetch MSW of latched counts and combine with LSW. */
11e865c1
GP		 2784 value |= ((uint32_t) DEBIread(dev, k->MyLatchLsw + 2) << 16);
2785
b6c77757 2786 /* DEBUG FIXME DEBUG("ReadLatch: Read Latch exit\n"); */
11e865c1 2787
b6c77757 2788 /* Return latched counts. */
11e865c1
GP		 2789 return value;
2790}
2791
b6c77757 2792/* Reset a counter's index and overflow event capture flags. */
11e865c1 2793
e473e912 2794static void ResetCapFlags_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 2795{
2796 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
2797 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
2798}
2799
e473e912 2800static void ResetCapFlags_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 2801{
2802 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
2803 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B);
2804}
2805
b6c77757
BP		 2806/* Return counter setup in a format (COUNTER_SETUP) that is consistent */
2807/* for both A and B counters. */
11e865c1 2808
e473e912 2809static uint16_t GetMode_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 2810{
2811 register uint16_t cra;
2812 register uint16_t crb;
2813 register uint16_t setup;
2814
b6c77757 2815 /* Fetch CRA and CRB register images. */
11e865c1
GP		 2816 cra = DEBIread(dev, k->MyCRA);
2817 crb = DEBIread(dev, k->MyCRB);
2818
b6c77757
BP		 2819 /* Populate the standardized counter setup bit fields. Note: */
2820 /* IndexSrc is restricted to ENC_X or IndxPol. */
2821 setup = ((cra & STDMSK_LOADSRC) /* LoadSrc = LoadSrcA. */
2822 | ((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcA. */
2823 | ((cra << (STDBIT_INTSRC - CRABIT_INTSRC_A)) & STDMSK_INTSRC) /* IntSrc = IntSrcA. */
2824 | ((cra << (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1))) & STDMSK_INDXSRC) /* IndxSrc = IndxSrcA<1>. */
2825 | ((cra >> (CRABIT_INDXPOL_A - STDBIT_INDXPOL)) & STDMSK_INDXPOL) /* IndxPol = IndxPolA. */
2826 | ((crb >> (CRBBIT_CLKENAB_A - STDBIT_CLKENAB)) & STDMSK_CLKENAB)); /* ClkEnab = ClkEnabA. */
2827
2828 /* Adjust mode-dependent parameters. */
2829 if (cra & (2 << CRABIT_CLKSRC_A)) /* If Timer mode (ClkSrcA<1> == 1): */
2830 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2831 | ((cra << (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) & STDMSK_CLKPOL) /* Set ClkPol to indicate count direction (ClkSrcA<0>). */
2832 | (MULT_X1 << STDBIT_CLKMULT)); /* ClkMult must be 1x in Timer mode. */
2833
2834 else /* If Counter mode (ClkSrcA<1> == 0): */
2835 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Counter mode. */
2836 | ((cra >> (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) & STDMSK_CLKPOL) /* Pass through ClkPol. */
2837 | (((cra & CRAMSK_CLKMULT_A) == (MULT_X0 << CRABIT_CLKMULT_A)) ? /* Force ClkMult to 1x if not legal, else pass through. */
11e865c1
GP		 2838 (MULT_X1 << STDBIT_CLKMULT) :
2839 ((cra >> (CRABIT_CLKMULT_A -
2840 STDBIT_CLKMULT)) &
2841 STDMSK_CLKMULT)));
2842
b6c77757 2843 /* Return adjusted counter setup. */
11e865c1
GP		 2844 return setup;
2845}
2846
e473e912 2847static uint16_t GetMode_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 2848{
2849 register uint16_t cra;
2850 register uint16_t crb;
2851 register uint16_t setup;
2852
b6c77757 2853 /* Fetch CRA and CRB register images. */
11e865c1
GP		 2854 cra = DEBIread(dev, k->MyCRA);
2855 crb = DEBIread(dev, k->MyCRB);
2856
b6c77757
BP		 2857 /* Populate the standardized counter setup bit fields. Note: */
2858 /* IndexSrc is restricted to ENC_X or IndxPol. */
2859 setup = (((crb << (STDBIT_INTSRC - CRBBIT_INTSRC_B)) & STDMSK_INTSRC) /* IntSrc = IntSrcB. */
2860 | ((crb << (STDBIT_LATCHSRC - CRBBIT_LATCHSRC)) & STDMSK_LATCHSRC) /* LatchSrc = LatchSrcB. */
2861 | ((crb << (STDBIT_LOADSRC - CRBBIT_LOADSRC_B)) & STDMSK_LOADSRC) /* LoadSrc = LoadSrcB. */
2862 | ((crb << (STDBIT_INDXPOL - CRBBIT_INDXPOL_B)) & STDMSK_INDXPOL) /* IndxPol = IndxPolB. */
2863 | ((crb >> (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) & STDMSK_CLKENAB) /* ClkEnab = ClkEnabB. */
2864 | ((cra >> ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)) & STDMSK_INDXSRC)); /* IndxSrc = IndxSrcB<1>. */
2865
2866 /* Adjust mode-dependent parameters. */
2867 if ((crb & CRBMSK_CLKMULT_B) == (MULT_X0 << CRBBIT_CLKMULT_B)) /* If Extender mode (ClkMultB == MULT_X0): */
2868 setup |= ((CLKSRC_EXTENDER << STDBIT_CLKSRC) /* Indicate Extender mode. */
2869 | (MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2870 | ((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
2871
2872 else if (cra & (2 << CRABIT_CLKSRC_B)) /* If Timer mode (ClkSrcB<1> == 1): */
2873 setup |= ((CLKSRC_TIMER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2874 | (MULT_X1 << STDBIT_CLKMULT) /* Indicate multiplier is 1x. */
2875 | ((cra >> (CRABIT_CLKSRC_B - STDBIT_CLKPOL)) & STDMSK_CLKPOL)); /* Set ClkPol equal to Timer count direction (ClkSrcB<0>). */
2876
2877 else /* If Counter mode (ClkSrcB<1> == 0): */
2878 setup |= ((CLKSRC_COUNTER << STDBIT_CLKSRC) /* Indicate Timer mode. */
2879 | ((crb >> (CRBBIT_CLKMULT_B - STDBIT_CLKMULT)) & STDMSK_CLKMULT) /* Clock multiplier is passed through. */
2880 | ((crb << (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) & STDMSK_CLKPOL)); /* Clock polarity is passed through. */
2881
2882 /* Return adjusted counter setup. */
11e865c1
GP		 2883 return setup;
2884}
2885
b6c77757
BP		 2886/*
2887 * Set the operating mode for the specified counter. The setup
2888 * parameter is treated as a COUNTER_SETUP data type. The following
2889 * parameters are programmable (all other parms are ignored): ClkMult,
2890 * ClkPol, ClkEnab, IndexSrc, IndexPol, LoadSrc.
2891 */
11e865c1 2892
e473e912 2893static void SetMode_A(comedi_device *dev, enc_private *k, uint16_t Setup,
11e865c1
GP		 2894 uint16_t DisableIntSrc)
2895{
2896 register uint16_t cra;
2897 register uint16_t crb;
b6c77757 2898 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 2899
b6c77757
BP		 2900 /* Initialize CRA and CRB images. */
2901 cra = ((setup & CRAMSK_LOADSRC_A) /* Preload trigger is passed through. */
2902 | ((setup & STDMSK_INDXSRC) >> (STDBIT_INDXSRC - (CRABIT_INDXSRC_A + 1)))); /* IndexSrc is restricted to ENC_X or IndxPol. */
11e865c1 2903
b6c77757
BP		 2904 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A /* Reset any pending CounterA event captures. */
2905 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_A - STDBIT_CLKENAB))); /* Clock enable is passed through. */
11e865c1 2906
b6c77757 2907 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
11e865c1
GP		 2908 if (!DisableIntSrc)
2909 cra |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
2910 CRABIT_INTSRC_A));
2911
b6c77757 2912 /* Populate all mode-dependent attributes of CRA & CRB images. */
11e865c1 2913 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
b6c77757
BP		 2914 case CLKSRC_EXTENDER: /* Extender Mode: Force to Timer mode */
2915 /* (Extender valid only for B counters). */
2916
2917 case CLKSRC_TIMER: /* Timer Mode: */
2918 cra |= ((2 << CRABIT_CLKSRC_A) /* ClkSrcA<1> selects system clock */
2919 | ((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRABIT_CLKSRC_A)) /* with count direction (ClkSrcA<0>) obtained from ClkPol. */
2920 | (1 << CRABIT_CLKPOL_A) /* ClkPolA behaves as always-on clock enable. */
2921 | (MULT_X1 << CRABIT_CLKMULT_A)); /* ClkMult must be 1x. */
11e865c1
GP		 2922 break;
2923
b6c77757
BP		 2924 default: /* Counter Mode: */
2925 cra |= (CLKSRC_COUNTER /* Select ENC_C and ENC_D as clock/direction inputs. */
2926 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKPOL_A - STDBIT_CLKPOL)) /* Clock polarity is passed through. */
2927 | (((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force multiplier to x1 if not legal, otherwise pass through. */
11e865c1
GP		 2928 (MULT_X1 << CRABIT_CLKMULT_A) :
2929 ((setup & STDMSK_CLKMULT) << (CRABIT_CLKMULT_A -
2930 STDBIT_CLKMULT))));
2931 }
2932
b6c77757
BP		 2933 /* Force positive index polarity if IndxSrc is software-driven only, */
2934 /* otherwise pass it through. */
11e865c1
GP		 2935 if (~setup & STDMSK_INDXSRC)
2936 cra |= ((setup & STDMSK_INDXPOL) << (CRABIT_INDXPOL_A -
2937 STDBIT_INDXPOL));
2938
b6c77757
BP		 2939 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
2940 /* enable mask to indicate the counter interrupt is disabled. */
11e865c1
GP		 2941 if (DisableIntSrc)
2942 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
2943
b6c77757
BP		 2944 /* While retaining CounterB and LatchSrc configurations, program the */
2945 /* new counter operating mode. */
11e865c1
GP		 2946 DEBIreplace(dev, k->MyCRA, CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B, cra);
2947 DEBIreplace(dev, k->MyCRB,
2948 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)), crb);
2949}
2950
e473e912 2951static void SetMode_B(comedi_device *dev, enc_private *k, uint16_t Setup,
11e865c1
GP		 2952 uint16_t DisableIntSrc)
2953{
2954 register uint16_t cra;
2955 register uint16_t crb;
b6c77757 2956 register uint16_t setup = Setup; /* Cache the Standard Setup. */
11e865c1 2957
b6c77757
BP		 2958 /* Initialize CRA and CRB images. */
2959 cra = ((setup & STDMSK_INDXSRC) << ((CRABIT_INDXSRC_B + 1) - STDBIT_INDXSRC)); /* IndexSrc field is restricted to ENC_X or IndxPol. */
11e865c1 2960
b6c77757
BP		 2961 crb = (CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B /* Reset event captures and disable interrupts. */
2962 | ((setup & STDMSK_CLKENAB) << (CRBBIT_CLKENAB_B - STDBIT_CLKENAB)) /* Clock enable is passed through. */
2963 | ((setup & STDMSK_LOADSRC) >> (STDBIT_LOADSRC - CRBBIT_LOADSRC_B))); /* Preload trigger source is passed through. */
11e865c1 2964
b6c77757 2965 /* Force IntSrc to Disabled if DisableIntSrc is asserted. */
11e865c1
GP		 2966 if (!DisableIntSrc)
2967 crb |= ((setup & STDMSK_INTSRC) >> (STDBIT_INTSRC -
2968 CRBBIT_INTSRC_B));
2969
b6c77757 2970 /* Populate all mode-dependent attributes of CRA & CRB images. */
11e865c1 2971 switch ((setup & STDMSK_CLKSRC) >> STDBIT_CLKSRC) {
b6c77757
BP		 2972 case CLKSRC_TIMER: /* Timer Mode: */
2973 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB<1> selects system clock */
2974 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction (ClkSrcB<0>) obtained from ClkPol. */
2975 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB behaves as always-on clock enable. */
2976 | (MULT_X1 << CRBBIT_CLKMULT_B)); /* ClkMultB must be 1x. */
11e865c1
GP		 2977 break;
2978
b6c77757
BP		 2979 case CLKSRC_EXTENDER: /* Extender Mode: */
2980 cra |= ((2 << CRABIT_CLKSRC_B) /* ClkSrcB source is OverflowA (same as "timer") */
2981 | ((setup & STDMSK_CLKPOL) << (CRABIT_CLKSRC_B - STDBIT_CLKPOL))); /* with direction obtained from ClkPol. */
2982 crb |= ((1 << CRBBIT_CLKPOL_B) /* ClkPolB controls IndexB -- always set to active. */
2983 | (MULT_X0 << CRBBIT_CLKMULT_B)); /* ClkMultB selects OverflowA as the clock source. */
11e865c1
GP		 2984 break;
2985
b6c77757
BP		 2986 default: /* Counter Mode: */
2987 cra |= (CLKSRC_COUNTER << CRABIT_CLKSRC_B); /* Select ENC_C and ENC_D as clock/direction inputs. */
2988 crb |= (((setup & STDMSK_CLKPOL) >> (STDBIT_CLKPOL - CRBBIT_CLKPOL_B)) /* ClkPol is passed through. */
2989 | (((setup & STDMSK_CLKMULT) == (MULT_X0 << STDBIT_CLKMULT)) ? /* Force ClkMult to x1 if not legal, otherwise pass through. */
11e865c1
GP		 2990 (MULT_X1 << CRBBIT_CLKMULT_B) :
2991 ((setup & STDMSK_CLKMULT) << (CRBBIT_CLKMULT_B -
2992 STDBIT_CLKMULT))));
2993 }
2994
b6c77757
BP		 2995 /* Force positive index polarity if IndxSrc is software-driven only, */
2996 /* otherwise pass it through. */
11e865c1
GP		 2997 if (~setup & STDMSK_INDXSRC)
2998 crb |= ((setup & STDMSK_INDXPOL) >> (STDBIT_INDXPOL -
2999 CRBBIT_INDXPOL_B));
3000
b6c77757
BP		 3001 /* If IntSrc has been forced to Disabled, update the MISC2 interrupt */
3002 /* enable mask to indicate the counter interrupt is disabled. */
11e865c1
GP		 3003 if (DisableIntSrc)
3004 devpriv->CounterIntEnabs &= ~k->MyEventBits[3];
3005
b6c77757
BP		 3006 /* While retaining CounterA and LatchSrc configurations, program the */
3007 /* new counter operating mode. */
11e865c1
GP		 3008 DEBIreplace(dev, k->MyCRA,
3009 (uint16_t) (~(CRAMSK_INDXSRC_B | CRAMSK_CLKSRC_B)), cra);
3010 DEBIreplace(dev, k->MyCRB, CRBMSK_CLKENAB_A | CRBMSK_LATCHSRC, crb);
3011}
3012
b6c77757 3013/* Return/set a counter's enable. enab: 0=always enabled, 1=enabled by index. */
11e865c1 3014
e473e912 3015static void SetEnable_A(comedi_device *dev, enc_private *k, uint16_t enab)
11e865c1
GP		 3016{
3017 DEBUG("SetEnable_A: SetEnable_A enter 3541\n");
3018 DEBIreplace(dev, k->MyCRB,
3019 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_A)),
3020 (uint16_t) (enab << CRBBIT_CLKENAB_A));
3021}
3022
e473e912 3023static void SetEnable_B(comedi_device *dev, enc_private *k, uint16_t enab)
11e865c1
GP		 3024{
3025 DEBIreplace(dev, k->MyCRB,
3026 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_CLKENAB_B)),
3027 (uint16_t) (enab << CRBBIT_CLKENAB_B));
3028}
3029
e473e912 3030static uint16_t GetEnable_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 3031{
3032 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_A) & 1;
3033}
3034
e473e912 3035static uint16_t GetEnable_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 3036{
3037 return (DEBIread(dev, k->MyCRB) >> CRBBIT_CLKENAB_B) & 1;
3038}
3039
b6c77757
BP		 3040/* Return/set a counter pair's latch trigger source. 0: On read
3041 * access, 1: A index latches A, 2: B index latches B, 3: A overflow
3042 * latches B.
3043 */
11e865c1 3044
e473e912 3045static void SetLatchSource(comedi_device *dev, enc_private *k, uint16_t value)
11e865c1
GP		 3046{
3047 DEBUG("SetLatchSource: SetLatchSource enter 3550 \n");
3048 DEBIreplace(dev, k->MyCRB,
3049 (uint16_t) (~(CRBMSK_INTCTRL | CRBMSK_LATCHSRC)),
3050 (uint16_t) (value << CRBBIT_LATCHSRC));
3051
3052 DEBUG("SetLatchSource: SetLatchSource exit \n");
3053}
3054
b6c77757
BP		 3055/*
3056 * static uint16_t GetLatchSource(comedi_device *dev, enc_private *k )
3057 * {
3058 * return ( DEBIread( dev, k->MyCRB) >> CRBBIT_LATCHSRC ) & 3;
3059 * }
3060 */
11e865c1 3061
b6c77757
BP		 3062/*
3063 * Return/set the event that will trigger transfer of the preload
3064 * register into the counter. 0=ThisCntr_Index, 1=ThisCntr_Overflow,
3065 * 2=OverflowA (B counters only), 3=disabled.
3066 */
11e865c1 3067
e473e912 3068static void SetLoadTrig_A(comedi_device *dev, enc_private *k, uint16_t Trig)
11e865c1
GP		 3069{
3070 DEBIreplace(dev, k->MyCRA, (uint16_t) (~CRAMSK_LOADSRC_A),
3071 (uint16_t) (Trig << CRABIT_LOADSRC_A));
3072}
3073
e473e912 3074static void SetLoadTrig_B(comedi_device *dev, enc_private *k, uint16_t Trig)
11e865c1
GP		 3075{
3076 DEBIreplace(dev, k->MyCRB,
3077 (uint16_t) (~(CRBMSK_LOADSRC_B | CRBMSK_INTCTRL)),
3078 (uint16_t) (Trig << CRBBIT_LOADSRC_B));
3079}
3080
e473e912 3081static uint16_t GetLoadTrig_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 3082{
3083 return (DEBIread(dev, k->MyCRA) >> CRABIT_LOADSRC_A) & 3;
3084}
3085
e473e912 3086static uint16_t GetLoadTrig_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 3087{
3088 return (DEBIread(dev, k->MyCRB) >> CRBBIT_LOADSRC_B) & 3;
3089}
3090
b6c77757
BP		 3091/* Return/set counter interrupt source and clear any captured
3092 * index/overflow events. IntSource: 0=Disabled, 1=OverflowOnly,
3093 * 2=IndexOnly, 3=IndexAndOverflow.
3094 */
11e865c1 3095
e473e912 3096static void SetIntSrc_A(comedi_device *dev, enc_private *k,
11e865c1
GP		 3097 uint16_t IntSource)
3098{
b6c77757 3099 /* Reset any pending counter overflow or index captures. */
11e865c1
GP		 3100 DEBIreplace(dev, k->MyCRB, (uint16_t) (~CRBMSK_INTCTRL),
3101 CRBMSK_INTRESETCMD | CRBMSK_INTRESET_A);
3102
b6c77757 3103 /* Program counter interrupt source. */
11e865c1
GP		 3104 DEBIreplace(dev, k->MyCRA, ~CRAMSK_INTSRC_A,
3105 (uint16_t) (IntSource << CRABIT_INTSRC_A));
3106
b6c77757 3107 /* Update MISC2 interrupt enable mask. */
11e865c1
GP		 3108 devpriv->CounterIntEnabs =
3109 (devpriv->CounterIntEnabs & ~k->MyEventBits[3]) | k->
3110 MyEventBits[IntSource];
3111}
3112
e473e912 3113static void SetIntSrc_B(comedi_device *dev, enc_private *k,
11e865c1
GP		 3114 uint16_t IntSource)
3115{
3116 uint16_t crb;
3117
b6c77757 3118 /* Cache writeable CRB register image. */
11e865c1
GP		 3119 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL;
3120
b6c77757 3121 /* Reset any pending counter overflow or index captures. */
11e865c1
GP		 3122 DEBIwrite(dev, k->MyCRB,
3123 (uint16_t) (crb | CRBMSK_INTRESETCMD | CRBMSK_INTRESET_B));
3124
b6c77757 3125 /* Program counter interrupt source. */
11e865c1
GP		 3126 DEBIwrite(dev, k->MyCRB,
3127 (uint16_t) ((crb & ~CRBMSK_INTSRC_B) | (IntSource <<
3128 CRBBIT_INTSRC_B)));
3129
b6c77757 3130 /* Update MISC2 interrupt enable mask. */
11e865c1
GP		 3131 devpriv->CounterIntEnabs =
3132 (devpriv->CounterIntEnabs & ~k->MyEventBits[3]) | k->
3133 MyEventBits[IntSource];
3134}
3135
e473e912 3136static uint16_t GetIntSrc_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 3137{
3138 return (DEBIread(dev, k->MyCRA) >> CRABIT_INTSRC_A) & 3;
3139}
3140
e473e912 3141static uint16_t GetIntSrc_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 3142{
3143 return (DEBIread(dev, k->MyCRB) >> CRBBIT_INTSRC_B) & 3;
3144}
3145
b6c77757 3146/* Return/set the clock multiplier. */
11e865c1
GP		 3147
3148/* static void SetClkMult(comedi_device *dev, enc_private *k, uint16_t value ) */
3149/* { */
3150/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKMULT ) | ( value << STDBIT_CLKMULT ) ), FALSE ); */
3151/* } */
3152
3153/* static uint16_t GetClkMult(comedi_device *dev, enc_private *k ) */
3154/* { */
3155/* return ( k->GetMode(dev, k ) >> STDBIT_CLKMULT ) & 3; */
3156/* } */
3157
b6c77757 3158/* Return/set the clock polarity. */
11e865c1
GP		 3159
3160/* static void SetClkPol( comedi_device *dev,enc_private *k, uint16_t value ) */
3161/* { */
3162/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKPOL ) | ( value << STDBIT_CLKPOL ) ), FALSE ); */
3163/* } */
3164
3165/* static uint16_t GetClkPol(comedi_device *dev, enc_private *k ) */
3166/* { */
3167/* return ( k->GetMode(dev, k ) >> STDBIT_CLKPOL ) & 1; */
3168/* } */
3169
b6c77757 3170/* Return/set the clock source. */
11e865c1
GP		 3171
3172/* static void SetClkSrc( comedi_device *dev,enc_private *k, uint16_t value ) */
3173/* { */
3174/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_CLKSRC ) | ( value << STDBIT_CLKSRC ) ), FALSE ); */
3175/* } */
3176
3177/* static uint16_t GetClkSrc( comedi_device *dev,enc_private *k ) */
3178/* { */
3179/* return ( k->GetMode(dev, k ) >> STDBIT_CLKSRC ) & 3; */
3180/* } */
3181
b6c77757 3182/* Return/set the index polarity. */
11e865c1
GP		 3183
3184/* static void SetIndexPol(comedi_device *dev, enc_private *k, uint16_t value ) */
3185/* { */
3186/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXPOL ) | ( (value != 0) << STDBIT_INDXPOL ) ), FALSE ); */
3187/* } */
3188
3189/* static uint16_t GetIndexPol(comedi_device *dev, enc_private *k ) */
3190/* { */
3191/* return ( k->GetMode(dev, k ) >> STDBIT_INDXPOL ) & 1; */
3192/* } */
3193
b6c77757 3194/* Return/set the index source. */
11e865c1
GP		 3195
3196/* static void SetIndexSrc(comedi_device *dev, enc_private *k, uint16_t value ) */
3197/* { */
3198/* DEBUG("SetIndexSrc: set index src enter 3700\n"); */
3199/* k->SetMode(dev, k, (uint16_t)( ( k->GetMode(dev, k ) & ~STDMSK_INDXSRC ) | ( (value != 0) << STDBIT_INDXSRC ) ), FALSE ); */
3200/* } */
3201
3202/* static uint16_t GetIndexSrc(comedi_device *dev, enc_private *k ) */
3203/* { */
3204/* return ( k->GetMode(dev, k ) >> STDBIT_INDXSRC ) & 1; */
3205/* } */
3206
b6c77757 3207/* Generate an index pulse. */
11e865c1 3208
e473e912 3209static void PulseIndex_A(comedi_device *dev, enc_private *k)
11e865c1
GP		 3210{
3211 register uint16_t cra;
3212
3213 DEBUG("PulseIndex_A: pulse index enter\n");
3214
b6c77757 3215 cra = DEBIread(dev, k->MyCRA); /* Pulse index. */
11e865c1
GP		 3216 DEBIwrite(dev, k->MyCRA, (uint16_t) (cra ^ CRAMSK_INDXPOL_A));
3217 DEBUG("PulseIndex_A: pulse index step1\n");
3218 DEBIwrite(dev, k->MyCRA, cra);
3219}
3220
e473e912 3221static void PulseIndex_B(comedi_device *dev, enc_private *k)
11e865c1
GP		 3222{
3223 register uint16_t crb;
3224
b6c77757 3225 crb = DEBIread(dev, k->MyCRB) & ~CRBMSK_INTCTRL; /* Pulse index. */
11e865c1
GP		 3226 DEBIwrite(dev, k->MyCRB, (uint16_t) (crb ^ CRBMSK_INDXPOL_B));
3227 DEBIwrite(dev, k->MyCRB, crb);
3228}
3229
b6c77757 3230/* Write value into counter preload register. */
11e865c1 3231
e473e912 3232static void Preload(comedi_device *dev, enc_private *k, uint32_t value)
11e865c1
GP		 3233{
3234 DEBUG("Preload: preload enter\n");
b6c77757 3235 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw), (uint16_t) value); /* Write value to preload register. */
11e865c1
GP		 3236 DEBUG("Preload: preload step 1\n");
3237 DEBIwrite(dev, (uint16_t) (k->MyLatchLsw + 2),
3238 (uint16_t) (value >> 16));
3239}
3240
e473e912 3241static void CountersInit(comedi_device *dev)
11e865c1
GP		 3242{
3243 int chan;
3244 enc_private *k;
b6c77757
BP		 3245 uint16_t Setup = (LOADSRC_INDX << BF_LOADSRC) | /* Preload upon */
3246 /* index. */
3247 (INDXSRC_SOFT << BF_INDXSRC) | /* Disable hardware index. */
3248 (CLKSRC_COUNTER << BF_CLKSRC) | /* Operating mode is counter. */
3249 (CLKPOL_POS << BF_CLKPOL) | /* Active high clock. */
3250 (CNTDIR_UP << BF_CLKPOL) | /* Count direction is up. */
3251 (CLKMULT_1X << BF_CLKMULT) | /* Clock multiplier is 1x. */
3252 (CLKENAB_INDEX << BF_CLKENAB); /* Enabled by index */
3253
3254 /* Disable all counter interrupts and clear any captured counter events. */
11e865c1
GP		 3255 for (chan = 0; chan < S626_ENCODER_CHANNELS; chan++) {
3256 k = &encpriv[chan];
3257 k->SetMode(dev, k, Setup, TRUE);
3258 k->SetIntSrc(dev, k, 0);
3259 k->ResetCapFlags(dev, k);
3260 k->SetEnable(dev, k, CLKENAB_ALWAYS);
3261 }
3262 DEBUG("CountersInit: counters initialized \n");
3263
3264}
Linux kernel - Deliverables
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