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7963eb43 JW |
1 | /******************************************************************** |
2 | * Copyright(c) 2006-2009 Broadcom Corporation. | |
3 | * | |
4 | * Name: bc_dts_glob_lnx.h | |
5 | * | |
6 | * Description: Wrapper to Windows dts_glob.h for Link-Linux usage. | |
7 | * The idea is to define additional Linux related defs | |
8 | * in this file to avoid changes to existing Windows | |
9 | * glob file. | |
10 | * | |
11 | * AU | |
12 | * | |
13 | * HISTORY: | |
14 | * | |
15 | ******************************************************************** | |
16 | * This header is free software: you can redistribute it and/or modify | |
17 | * it under the terms of the GNU Lesser General Public License as published | |
18 | * by the Free Software Foundation, either version 2.1 of the License. | |
19 | * | |
20 | * This header is distributed in the hope that it will be useful, | |
21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
23 | * GNU Lesser General Public License for more details. | |
24 | * You should have received a copy of the GNU Lesser General Public License | |
25 | * along with this header. If not, see <http://www.gnu.org/licenses/>. | |
26 | *******************************************************************/ | |
27 | ||
28 | #ifndef _BC_DTS_GLOB_LNX_H_ | |
29 | #define _BC_DTS_GLOB_LNX_H_ | |
30 | ||
31 | #ifdef __LINUX_USER__ | |
32 | #include <stdio.h> | |
33 | #include <stdlib.h> | |
34 | #include <unistd.h> | |
35 | #include <fcntl.h> | |
36 | #include <ctype.h> | |
37 | #include <string.h> | |
38 | #include <errno.h> | |
39 | #include <netdb.h> | |
40 | #include <sys/time.h> | |
41 | #include <time.h> | |
42 | #include <arpa/inet.h> | |
641b63f9 | 43 | #include <linux/param.h> |
7963eb43 JW |
44 | #include <linux/ioctl.h> |
45 | #include <sys/select.h> | |
46 | ||
47 | #define DRVIFLIB_INT_API | |
48 | ||
49 | #endif | |
50 | ||
51 | #include "bc_dts_defs.h" | |
52 | #include "bcm_70012_regs.h" /* Link Register defs */ | |
53 | ||
54 | #define CRYSTALHD_API_NAME "crystalhd" | |
55 | #define CRYSTALHD_API_DEV_NAME "/dev/crystalhd" | |
56 | ||
57 | /* | |
58 | * These are SW stack tunable parameters shared | |
59 | * between the driver and the application. | |
60 | */ | |
abfc768d | 61 | enum BC_DTS_GLOBALS { |
7963eb43 JW |
62 | BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */ |
63 | PCI_CFG_SIZE = 256, /* PCI config size buffer */ | |
64 | BC_IOCTL_DATA_POOL_SIZE = 8, /* BC_IOCTL_DATA Pool size */ | |
65 | BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/ | |
66 | BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */ | |
67 | BC_TX_LIST_CNT = 2, /* Max Tx DMA Rings */ | |
68 | BC_RX_LIST_CNT = 8, /* Max Rx DMA Rings*/ | |
69 | BC_PROC_OUTPUT_TIMEOUT = 3000, /* Milliseconds */ | |
70 | BC_INFIFO_THRESHOLD = 0x10000, | |
71 | }; | |
72 | ||
abfc768d | 73 | struct BC_CMD_REG_ACC { |
7963eb43 JW |
74 | uint32_t Offset; |
75 | uint32_t Value; | |
abfc768d | 76 | }; |
7963eb43 | 77 | |
abfc768d | 78 | struct BC_CMD_DEV_MEM { |
7963eb43 JW |
79 | uint32_t StartOff; |
80 | uint32_t NumDwords; | |
81 | uint32_t Rsrd; | |
abfc768d | 82 | }; |
7963eb43 JW |
83 | |
84 | /* FW Passthrough command structure */ | |
abfc768d | 85 | enum bc_fw_cmd_flags { |
7963eb43 JW |
86 | BC_FW_CMD_FLAGS_NONE = 0, |
87 | BC_FW_CMD_PIB_QS = 0x01, | |
88 | }; | |
89 | ||
abfc768d | 90 | struct BC_FW_CMD { |
7963eb43 JW |
91 | uint32_t cmd[BC_MAX_FW_CMD_BUFF_SZ]; |
92 | uint32_t rsp[BC_MAX_FW_CMD_BUFF_SZ]; | |
93 | uint32_t flags; | |
94 | uint32_t add_data; | |
abfc768d | 95 | }; |
7963eb43 | 96 | |
abfc768d | 97 | struct BC_HW_TYPE { |
7963eb43 JW |
98 | uint16_t PciDevId; |
99 | uint16_t PciVenId; | |
100 | uint8_t HwRev; | |
101 | uint8_t Align[3]; | |
abfc768d | 102 | }; |
7963eb43 | 103 | |
abfc768d | 104 | struct BC_PCI_CFG { |
7963eb43 JW |
105 | uint32_t Size; |
106 | uint32_t Offset; | |
107 | uint8_t pci_cfg_space[PCI_CFG_SIZE]; | |
abfc768d | 108 | }; |
7963eb43 | 109 | |
abfc768d | 110 | struct BC_VERSION_INFO { |
7963eb43 JW |
111 | uint8_t DriverMajor; |
112 | uint8_t DriverMinor; | |
113 | uint16_t DriverRevision; | |
abfc768d | 114 | }; |
7963eb43 | 115 | |
abfc768d | 116 | struct BC_START_RX_CAP { |
7963eb43 JW |
117 | uint32_t Rsrd; |
118 | uint32_t StartDeliveryThsh; | |
119 | uint32_t PauseThsh; | |
120 | uint32_t ResumeThsh; | |
abfc768d | 121 | }; |
7963eb43 | 122 | |
abfc768d | 123 | struct BC_FLUSH_RX_CAP { |
7963eb43 JW |
124 | uint32_t Rsrd; |
125 | uint32_t bDiscardOnly; | |
abfc768d | 126 | }; |
7963eb43 | 127 | |
abfc768d | 128 | struct BC_DTS_STATS { |
7963eb43 JW |
129 | uint8_t drvRLL; |
130 | uint8_t drvFLL; | |
131 | uint8_t eosDetected; | |
132 | uint8_t pwr_state_change; | |
133 | ||
134 | /* Stats from App */ | |
135 | uint32_t opFrameDropped; | |
136 | uint32_t opFrameCaptured; | |
137 | uint32_t ipSampleCnt; | |
138 | uint64_t ipTotalSize; | |
139 | uint32_t reptdFrames; | |
140 | uint32_t pauseCount; | |
141 | uint32_t pibMisses; | |
142 | uint32_t discCounter; | |
143 | ||
144 | /* Stats from Driver */ | |
145 | uint32_t TxFifoBsyCnt; | |
146 | uint32_t intCount; | |
147 | uint32_t DrvIgnIntrCnt; | |
148 | uint32_t DrvTotalFrmDropped; | |
149 | uint32_t DrvTotalHWErrs; | |
150 | uint32_t DrvTotalPIBFlushCnt; | |
151 | uint32_t DrvTotalFrmCaptured; | |
152 | uint32_t DrvPIBMisses; | |
153 | uint32_t DrvPauseTime; | |
154 | uint32_t DrvRepeatedFrms; | |
155 | uint32_t res1[13]; | |
156 | ||
abfc768d | 157 | }; |
7963eb43 | 158 | |
abfc768d | 159 | struct BC_PROC_INPUT { |
7963eb43 JW |
160 | uint8_t *pDmaBuff; |
161 | uint32_t BuffSz; | |
162 | uint8_t Mapped; | |
163 | uint8_t Encrypted; | |
164 | uint8_t Rsrd[2]; | |
165 | uint32_t DramOffset; /* For debug use only */ | |
abfc768d | 166 | }; |
7963eb43 | 167 | |
abfc768d | 168 | struct BC_DEC_YUV_BUFFS { |
7963eb43 JW |
169 | uint32_t b422Mode; |
170 | uint8_t *YuvBuff; | |
171 | uint32_t YuvBuffSz; | |
172 | uint32_t UVbuffOffset; | |
173 | uint32_t YBuffDoneSz; | |
174 | uint32_t UVBuffDoneSz; | |
175 | uint32_t RefCnt; | |
abfc768d | 176 | }; |
7963eb43 | 177 | |
abfc768d | 178 | enum DECOUT_COMPLETION_FLAGS{ |
7963eb43 JW |
179 | COMP_FLAG_NO_INFO = 0x00, |
180 | COMP_FLAG_FMT_CHANGE = 0x01, | |
181 | COMP_FLAG_PIB_VALID = 0x02, | |
182 | COMP_FLAG_DATA_VALID = 0x04, | |
183 | COMP_FLAG_DATA_ENC = 0x08, | |
184 | COMP_FLAG_DATA_BOT = 0x10, | |
185 | }; | |
186 | ||
abfc768d LD |
187 | struct BC_DEC_OUT_BUFF{ |
188 | struct BC_DEC_YUV_BUFFS OutPutBuffs; | |
189 | struct BC_PIC_INFO_BLOCK PibInfo; | |
7963eb43 JW |
190 | uint32_t Flags; |
191 | uint32_t BadFrCnt; | |
abfc768d | 192 | }; |
7963eb43 | 193 | |
abfc768d | 194 | struct BC_NOTIFY_MODE { |
7963eb43 JW |
195 | uint32_t Mode; |
196 | uint32_t Rsvr[3]; | |
abfc768d | 197 | }; |
7963eb43 | 198 | |
abfc768d | 199 | struct BC_CLOCK { |
7963eb43 JW |
200 | uint32_t clk; |
201 | uint32_t Rsvr[3]; | |
abfc768d | 202 | }; |
7963eb43 | 203 | |
abfc768d LD |
204 | struct BC_IOCTL_DATA { |
205 | enum BC_STATUS RetSts; | |
7963eb43 JW |
206 | uint32_t IoctlDataSz; |
207 | uint32_t Timeout; | |
208 | union { | |
abfc768d LD |
209 | struct BC_CMD_REG_ACC regAcc; |
210 | struct BC_CMD_DEV_MEM devMem; | |
211 | struct BC_FW_CMD fwCmd; | |
212 | struct BC_HW_TYPE hwType; | |
213 | struct BC_PCI_CFG pciCfg; | |
214 | struct BC_VERSION_INFO VerInfo; | |
215 | struct BC_PROC_INPUT ProcInput; | |
216 | struct BC_DEC_YUV_BUFFS RxBuffs; | |
217 | struct BC_DEC_OUT_BUFF DecOutData; | |
218 | struct BC_START_RX_CAP RxCap; | |
219 | struct BC_FLUSH_RX_CAP FlushRxCap; | |
220 | struct BC_DTS_STATS drvStat; | |
221 | struct BC_NOTIFY_MODE NotifyMode; | |
222 | struct BC_CLOCK clockValue; | |
7963eb43 JW |
223 | } u; |
224 | struct _BC_IOCTL_DATA *next; | |
abfc768d | 225 | }; |
7963eb43 | 226 | |
abfc768d | 227 | enum BC_DRV_CMD { |
7963eb43 JW |
228 | DRV_CMD_VERSION = 0, /* Get SW version */ |
229 | DRV_CMD_GET_HWTYPE, /* Get HW version and type Dozer/Tank */ | |
230 | DRV_CMD_REG_RD, /* Read Device Register */ | |
231 | DRV_CMD_REG_WR, /* Write Device Register */ | |
232 | DRV_CMD_FPGA_RD, /* Read FPGA Register */ | |
233 | DRV_CMD_FPGA_WR, /* Wrtie FPGA Reister */ | |
234 | DRV_CMD_MEM_RD, /* Read Device Memory */ | |
235 | DRV_CMD_MEM_WR, /* Write Device Memory */ | |
236 | DRV_CMD_RD_PCI_CFG, /* Read PCI Config Space */ | |
237 | DRV_CMD_WR_PCI_CFG, /* Write the PCI Configuration Space*/ | |
238 | DRV_CMD_FW_DOWNLOAD, /* Download Firmware */ | |
239 | DRV_ISSUE_FW_CMD, /* Issue FW Cmd (pass through mode) */ | |
240 | DRV_CMD_PROC_INPUT, /* Process Input Sample */ | |
241 | DRV_CMD_ADD_RXBUFFS, /* Add Rx side buffers to driver pool */ | |
242 | DRV_CMD_FETCH_RXBUFF, /* Get Rx DMAed buffer */ | |
243 | DRV_CMD_START_RX_CAP, /* Start Rx Buffer Capture */ | |
244 | DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now...we will enhance this later*/ | |
245 | DRV_CMD_GET_DRV_STAT, /* Get Driver Internal Statistics */ | |
246 | DRV_CMD_RST_DRV_STAT, /* Reset Driver Internal Statistics */ | |
247 | DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver in which the application is Operating*/ | |
248 | DRV_CMD_CHANGE_CLOCK, /* Change the core clock to either save power or improve performance */ | |
249 | ||
250 | /* MUST be the last one.. */ | |
251 | DRV_CMD_END, /* End of the List.. */ | |
abfc768d | 252 | }; |
7963eb43 JW |
253 | |
254 | #define BC_IOC_BASE 'b' | |
255 | #define BC_IOC_VOID _IOC_NONE | |
256 | #define BC_IOC_IOWR(nr, type) _IOWR(BC_IOC_BASE, nr, type) | |
abfc768d | 257 | #define BC_IOCTL_MB struct BC_IOCTL_DATA |
7963eb43 JW |
258 | |
259 | #define BCM_IOC_GET_VERSION BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB) | |
260 | #define BCM_IOC_GET_HWTYPE BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB) | |
261 | #define BCM_IOC_REG_RD BC_IOC_IOWR(DRV_CMD_REG_RD, BC_IOCTL_MB) | |
262 | #define BCM_IOC_REG_WR BC_IOC_IOWR(DRV_CMD_REG_WR, BC_IOCTL_MB) | |
263 | #define BCM_IOC_MEM_RD BC_IOC_IOWR(DRV_CMD_MEM_RD, BC_IOCTL_MB) | |
264 | #define BCM_IOC_MEM_WR BC_IOC_IOWR(DRV_CMD_MEM_WR, BC_IOCTL_MB) | |
265 | #define BCM_IOC_FPGA_RD BC_IOC_IOWR(DRV_CMD_FPGA_RD, BC_IOCTL_MB) | |
266 | #define BCM_IOC_FPGA_WR BC_IOC_IOWR(DRV_CMD_FPGA_WR, BC_IOCTL_MB) | |
267 | #define BCM_IOC_RD_PCI_CFG BC_IOC_IOWR(DRV_CMD_RD_PCI_CFG, BC_IOCTL_MB) | |
268 | #define BCM_IOC_WR_PCI_CFG BC_IOC_IOWR(DRV_CMD_WR_PCI_CFG, BC_IOCTL_MB) | |
269 | #define BCM_IOC_PROC_INPUT BC_IOC_IOWR(DRV_CMD_PROC_INPUT, BC_IOCTL_MB) | |
270 | #define BCM_IOC_ADD_RXBUFFS BC_IOC_IOWR(DRV_CMD_ADD_RXBUFFS, BC_IOCTL_MB) | |
271 | #define BCM_IOC_FETCH_RXBUFF BC_IOC_IOWR(DRV_CMD_FETCH_RXBUFF, BC_IOCTL_MB) | |
272 | #define BCM_IOC_FW_CMD BC_IOC_IOWR(DRV_ISSUE_FW_CMD, BC_IOCTL_MB) | |
273 | #define BCM_IOC_START_RX_CAP BC_IOC_IOWR(DRV_CMD_START_RX_CAP, BC_IOCTL_MB) | |
274 | #define BCM_IOC_FLUSH_RX_CAP BC_IOC_IOWR(DRV_CMD_FLUSH_RX_CAP, BC_IOCTL_MB) | |
275 | #define BCM_IOC_GET_DRV_STAT BC_IOC_IOWR(DRV_CMD_GET_DRV_STAT, BC_IOCTL_MB) | |
276 | #define BCM_IOC_RST_DRV_STAT BC_IOC_IOWR(DRV_CMD_RST_DRV_STAT, BC_IOCTL_MB) | |
277 | #define BCM_IOC_NOTIFY_MODE BC_IOC_IOWR(DRV_CMD_NOTIFY_MODE, BC_IOCTL_MB) | |
278 | #define BCM_IOC_FW_DOWNLOAD BC_IOC_IOWR(DRV_CMD_FW_DOWNLOAD, BC_IOCTL_MB) | |
279 | #define BCM_IOC_CHG_CLK BC_IOC_IOWR(DRV_CMD_CHANGE_CLOCK, BC_IOCTL_MB) | |
280 | #define BCM_IOC_END BC_IOC_VOID | |
281 | ||
282 | /* Wrapper for main IOCTL data */ | |
abfc768d LD |
283 | struct crystalhd_ioctl_data { |
284 | struct BC_IOCTL_DATA udata; /* IOCTL from App..*/ | |
7963eb43 JW |
285 | uint32_t u_id; /* Driver specific user ID */ |
286 | uint32_t cmd; /* Cmd ID for driver's use. */ | |
287 | void *add_cdata; /* Additional command specific data..*/ | |
288 | uint32_t add_cdata_sz; /* Additional command specific data size */ | |
abfc768d LD |
289 | struct crystalhd_ioctl_data *next; /* List/Fifo management */ |
290 | }; | |
7963eb43 | 291 | |
abfc768d | 292 | enum crystalhd_kmod_ver{ |
7963eb43 JW |
293 | crystalhd_kmod_major = 0, |
294 | crystalhd_kmod_minor = 9, | |
295 | crystalhd_kmod_rev = 27, | |
296 | }; | |
297 | ||
298 | #endif |