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717f4a5f MM |
1 | /*************************************************************************** |
2 | * Copyright (C) 2006-2010 by Marin Mitov * | |
3 | * mitov@issp.bas.bg * | |
4 | * * | |
5 | * This program is free software; you can redistribute it and/or modify * | |
6 | * it under the terms of the GNU General Public License as published by * | |
7 | * the Free Software Foundation; either version 2 of the License, or * | |
8 | * (at your option) any later version. * | |
9 | * * | |
10 | * This program is distributed in the hope that it will be useful, * | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of * | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * | |
13 | * GNU General Public License for more details. * | |
14 | * * | |
15 | * You should have received a copy of the GNU General Public License * | |
16 | * along with this program; if not, write to the * | |
17 | * Free Software Foundation, Inc., * | |
18 | * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. * | |
19 | ***************************************************************************/ | |
20 | ||
99c97852 | 21 | #include <linux/module.h> |
d42bffb8 MM |
22 | #include <linux/version.h> |
23 | #include <linux/stringify.h> | |
7ec21181 | 24 | #include <linux/delay.h> |
d42bffb8 | 25 | #include <linux/kthread.h> |
dac95cb8 | 26 | #include <linux/slab.h> |
a57941c2 MM |
27 | #include <media/v4l2-dev.h> |
28 | #include <media/v4l2-ioctl.h> | |
8ded351a | 29 | #include <media/videobuf2-dma-contig.h> |
d42bffb8 MM |
30 | |
31 | #include "dt3155v4l.h" | |
d42bffb8 MM |
32 | |
33 | #define DT3155_VENDOR_ID 0x8086 | |
34 | #define DT3155_DEVICE_ID 0x1223 | |
35 | ||
a57941c2 MM |
36 | /* DT3155_CHUNK_SIZE is 4M (2^22) 8 full size buffers */ |
37 | #define DT3155_CHUNK_SIZE (1U << 22) | |
38 | ||
39 | #define DT3155_COH_FLAGS (GFP_KERNEL | GFP_DMA32 | __GFP_COLD | __GFP_NOWARN) | |
40 | ||
41 | #define DT3155_BUF_SIZE (768 * 576) | |
42 | ||
8ded351a MM |
43 | #ifdef CONFIG_DT3155_STREAMING |
44 | #define DT3155_CAPTURE_METHOD V4L2_CAP_STREAMING | |
45 | #else | |
46 | #define DT3155_CAPTURE_METHOD V4L2_CAP_READWRITE | |
47 | #endif | |
48 | ||
d42bffb8 MM |
49 | /* global initializers (for all boards) */ |
50 | #ifdef CONFIG_DT3155_CCIR | |
51 | static const u8 csr2_init = VT_50HZ; | |
52 | #define DT3155_CURRENT_NORM V4L2_STD_625_50 | |
53 | static const unsigned int img_width = 768; | |
54 | static const unsigned int img_height = 576; | |
55 | static const unsigned int frames_per_sec = 25; | |
56 | static const struct v4l2_fmtdesc frame_std[] = { | |
57 | { | |
58 | .index = 0, | |
59 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
60 | .flags = 0, | |
61 | .description = "CCIR/50Hz 8 bits gray", | |
62 | .pixelformat = V4L2_PIX_FMT_GREY, | |
63 | }, | |
64 | }; | |
65 | #else | |
66 | static const u8 csr2_init = VT_60HZ; | |
67 | #define DT3155_CURRENT_NORM V4L2_STD_525_60 | |
68 | static const unsigned int img_width = 640; | |
69 | static const unsigned int img_height = 480; | |
70 | static const unsigned int frames_per_sec = 30; | |
71 | static const struct v4l2_fmtdesc frame_std[] = { | |
72 | { | |
73 | .index = 0, | |
74 | .type = V4L2_BUF_TYPE_VIDEO_CAPTURE, | |
75 | .flags = 0, | |
76 | .description = "RS-170/60Hz 8 bits gray", | |
77 | .pixelformat = V4L2_PIX_FMT_GREY, | |
78 | }, | |
79 | }; | |
80 | #endif | |
81 | ||
82 | #define NUM_OF_FORMATS ARRAY_SIZE(frame_std) | |
83 | ||
84 | static u8 config_init = ACQ_MODE_EVEN; | |
85 | ||
86 | /** | |
87 | * read_i2c_reg - reads an internal i2c register | |
88 | * | |
89 | * @addr: dt3155 mmio base address | |
90 | * @index: index (internal address) of register to read | |
91 | * @data: pointer to byte the read data will be placed in | |
92 | * | |
93 | * returns: zero on success or error code | |
94 | * | |
95 | * This function starts reading the specified (by index) register | |
96 | * and busy waits for the process to finish. The result is placed | |
97 | * in a byte pointed by data. | |
98 | */ | |
99 | static int | |
2342df0e | 100 | read_i2c_reg(void __iomem *addr, u8 index, u8 *data) |
d42bffb8 MM |
101 | { |
102 | u32 tmp = index; | |
103 | ||
104 | iowrite32((tmp<<17) | IIC_READ, addr + IIC_CSR2); | |
105 | mmiowb(); | |
106 | udelay(45); /* wait at least 43 usec for NEW_CYCLE to clear */ | |
107 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) { | |
108 | /* error: NEW_CYCLE not cleared */ | |
109 | printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n"); | |
110 | return -EIO; | |
111 | } | |
112 | tmp = ioread32(addr + IIC_CSR1); | |
113 | if (tmp & DIRECT_ABORT) { | |
114 | /* error: DIRECT_ABORT set */ | |
115 | printk(KERN_ERR "dt3155: DIRECT_ABORT set\n"); | |
116 | /* reset DIRECT_ABORT bit */ | |
117 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
118 | return -EIO; | |
119 | } | |
120 | *data = tmp>>24; | |
121 | return 0; | |
122 | } | |
123 | ||
124 | /** | |
125 | * write_i2c_reg - writes to an internal i2c register | |
126 | * | |
127 | * @addr: dt3155 mmio base address | |
128 | * @index: index (internal address) of register to read | |
129 | * @data: data to be written | |
130 | * | |
131 | * returns: zero on success or error code | |
132 | * | |
133 | * This function starts writting the specified (by index) register | |
134 | * and busy waits for the process to finish. | |
135 | */ | |
136 | static int | |
2342df0e | 137 | write_i2c_reg(void __iomem *addr, u8 index, u8 data) |
d42bffb8 MM |
138 | { |
139 | u32 tmp = index; | |
140 | ||
141 | iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2); | |
142 | mmiowb(); | |
143 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ | |
144 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) { | |
145 | /* error: NEW_CYCLE not cleared */ | |
146 | printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n"); | |
147 | return -EIO; | |
148 | } | |
149 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { | |
150 | /* error: DIRECT_ABORT set */ | |
151 | printk(KERN_ERR "dt3155: DIRECT_ABORT set\n"); | |
152 | /* reset DIRECT_ABORT bit */ | |
153 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
154 | return -EIO; | |
155 | } | |
156 | return 0; | |
157 | } | |
158 | ||
159 | /** | |
160 | * write_i2c_reg_nowait - writes to an internal i2c register | |
161 | * | |
162 | * @addr: dt3155 mmio base address | |
163 | * @index: index (internal address) of register to read | |
164 | * @data: data to be written | |
165 | * | |
166 | * This function starts writting the specified (by index) register | |
167 | * and then returns. | |
168 | */ | |
2342df0e | 169 | static void write_i2c_reg_nowait(void __iomem *addr, u8 index, u8 data) |
d42bffb8 MM |
170 | { |
171 | u32 tmp = index; | |
172 | ||
173 | iowrite32((tmp<<17) | IIC_WRITE | data, addr + IIC_CSR2); | |
174 | mmiowb(); | |
175 | } | |
176 | ||
177 | /** | |
178 | * wait_i2c_reg - waits the read/write to finish | |
179 | * | |
180 | * @addr: dt3155 mmio base address | |
181 | * | |
182 | * returns: zero on success or error code | |
183 | * | |
184 | * This function waits reading/writting to finish. | |
185 | */ | |
2342df0e | 186 | static int wait_i2c_reg(void __iomem *addr) |
d42bffb8 MM |
187 | { |
188 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) | |
189 | udelay(65); /* wait at least 63 usec for NEW_CYCLE to clear */ | |
190 | if (ioread32(addr + IIC_CSR2) & NEW_CYCLE) { | |
191 | /* error: NEW_CYCLE not cleared */ | |
192 | printk(KERN_ERR "dt3155: NEW_CYCLE not cleared\n"); | |
193 | return -EIO; | |
194 | } | |
195 | if (ioread32(addr + IIC_CSR1) & DIRECT_ABORT) { | |
196 | /* error: DIRECT_ABORT set */ | |
197 | printk(KERN_ERR "dt3155: DIRECT_ABORT set\n"); | |
198 | /* reset DIRECT_ABORT bit */ | |
199 | iowrite32(DIRECT_ABORT, addr + IIC_CSR1); | |
200 | return -EIO; | |
201 | } | |
202 | return 0; | |
203 | } | |
204 | ||
d42bffb8 MM |
205 | static int |
206 | dt3155_start_acq(struct dt3155_priv *pd) | |
207 | { | |
8ded351a | 208 | struct vb2_buffer *vb = pd->curr_buf; |
d42bffb8 MM |
209 | dma_addr_t dma_addr; |
210 | ||
8ded351a | 211 | dma_addr = vb2_dma_contig_plane_paddr(vb, 0); |
d42bffb8 | 212 | iowrite32(dma_addr, pd->regs + EVEN_DMA_START); |
8ded351a MM |
213 | iowrite32(dma_addr + img_width, pd->regs + ODD_DMA_START); |
214 | iowrite32(img_width, pd->regs + EVEN_DMA_STRIDE); | |
215 | iowrite32(img_width, pd->regs + ODD_DMA_STRIDE); | |
d42bffb8 MM |
216 | /* enable interrupts, clear all irq flags */ |
217 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | | |
218 | FLD_END_EVEN | FLD_END_ODD, pd->regs + INT_CSR); | |
219 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | | |
220 | FLD_DN_ODD | FLD_DN_EVEN | CAP_CONT_EVEN | CAP_CONT_ODD, | |
221 | pd->regs + CSR1); | |
222 | wait_i2c_reg(pd->regs); | |
223 | write_i2c_reg(pd->regs, CONFIG, pd->config); | |
224 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); | |
225 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); | |
226 | ||
227 | /* start the board */ | |
228 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | BUSY_ODD); | |
229 | return 0; /* success */ | |
230 | } | |
231 | ||
8ded351a MM |
232 | /* |
233 | * driver-specific callbacks (vb2_ops) | |
234 | */ | |
d42bffb8 | 235 | static int |
8ded351a MM |
236 | dt3155_queue_setup(struct vb2_queue *q, unsigned int *num_buffers, |
237 | unsigned int *num_planes, unsigned long sizes[], | |
238 | void *alloc_ctxs[]) | |
239 | { | |
240 | struct dt3155_priv *pd = vb2_get_drv_priv(q); | |
241 | void *ret; | |
242 | ||
243 | if (*num_buffers == 0) | |
244 | *num_buffers = 1; | |
245 | *num_planes = 1; | |
246 | sizes[0] = img_width * img_height; | |
247 | if (pd->q->alloc_ctx[0]) | |
248 | return 0; | |
249 | ret = vb2_dma_contig_init_ctx(&pd->pdev->dev); | |
250 | if (IS_ERR(ret)) | |
251 | return PTR_ERR(ret); | |
252 | pd->q->alloc_ctx[0] = ret; | |
253 | return 0; | |
254 | } | |
255 | ||
256 | static void | |
257 | dt3155_wait_prepare(struct vb2_queue *q) | |
d42bffb8 | 258 | { |
8ded351a | 259 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
d42bffb8 | 260 | |
8ded351a MM |
261 | mutex_unlock(pd->vdev->lock); |
262 | } | |
d42bffb8 | 263 | |
8ded351a MM |
264 | static void |
265 | dt3155_wait_finish(struct vb2_queue *q) | |
266 | { | |
267 | struct dt3155_priv *pd = vb2_get_drv_priv(q); | |
268 | ||
269 | mutex_lock(pd->vdev->lock); | |
d42bffb8 MM |
270 | } |
271 | ||
d42bffb8 | 272 | static int |
8ded351a | 273 | dt3155_buf_prepare(struct vb2_buffer *vb) |
d42bffb8 | 274 | { |
8ded351a | 275 | vb2_set_plane_payload(vb, 0, img_width * img_height); |
d42bffb8 MM |
276 | return 0; |
277 | } | |
278 | ||
d42bffb8 | 279 | static int |
8ded351a | 280 | dt3155_start_streaming(struct vb2_queue *q) |
d42bffb8 | 281 | { |
8ded351a | 282 | return 0; |
d42bffb8 MM |
283 | } |
284 | ||
8ded351a MM |
285 | static int |
286 | dt3155_stop_streaming(struct vb2_queue *q) | |
d42bffb8 | 287 | { |
8ded351a MM |
288 | struct dt3155_priv *pd = vb2_get_drv_priv(q); |
289 | struct vb2_buffer *vb; | |
290 | ||
291 | spin_lock_irq(&pd->lock); | |
292 | while (!list_empty(&pd->dmaq)) { | |
293 | vb = list_first_entry(&pd->dmaq, typeof(*vb), done_entry); | |
294 | list_del(&vb->done_entry); | |
295 | vb2_buffer_done(vb, VB2_BUF_STATE_ERROR); | |
296 | } | |
297 | spin_unlock_irq(&pd->lock); | |
298 | msleep(45); /* irq hendler will stop the hardware */ | |
299 | return 0; | |
d42bffb8 MM |
300 | } |
301 | ||
d42bffb8 | 302 | static void |
8ded351a | 303 | dt3155_buf_queue(struct vb2_buffer *vb) |
d42bffb8 | 304 | { |
8ded351a MM |
305 | struct dt3155_priv *pd = vb2_get_drv_priv(vb->vb2_queue); |
306 | ||
307 | /* pd->q->streaming = 1 when dt3155_buf_queue() is invoked */ | |
308 | spin_lock_irq(&pd->lock); | |
309 | if (pd->curr_buf) | |
310 | list_add_tail(&vb->done_entry, &pd->dmaq); | |
311 | else { | |
312 | pd->curr_buf = vb; | |
313 | dt3155_start_acq(pd); | |
314 | } | |
315 | spin_unlock_irq(&pd->lock); | |
d42bffb8 | 316 | } |
8ded351a MM |
317 | /* |
318 | * end driver-specific callbacks | |
319 | */ | |
d42bffb8 | 320 | |
8ded351a MM |
321 | const struct vb2_ops q_ops = { |
322 | .queue_setup = dt3155_queue_setup, | |
323 | .wait_prepare = dt3155_wait_prepare, | |
324 | .wait_finish = dt3155_wait_finish, | |
d42bffb8 | 325 | .buf_prepare = dt3155_buf_prepare, |
8ded351a MM |
326 | .start_streaming = dt3155_start_streaming, |
327 | .stop_streaming = dt3155_stop_streaming, | |
d42bffb8 | 328 | .buf_queue = dt3155_buf_queue, |
d42bffb8 MM |
329 | }; |
330 | ||
331 | static irqreturn_t | |
332 | dt3155_irq_handler_even(int irq, void *dev_id) | |
333 | { | |
334 | struct dt3155_priv *ipd = dev_id; | |
8ded351a | 335 | struct vb2_buffer *ivb; |
d42bffb8 MM |
336 | dma_addr_t dma_addr; |
337 | u32 tmp; | |
338 | ||
339 | tmp = ioread32(ipd->regs + INT_CSR) & (FLD_START | FLD_END_ODD); | |
340 | if (!tmp) | |
341 | return IRQ_NONE; /* not our irq */ | |
342 | if ((tmp & FLD_START) && !(tmp & FLD_END_ODD)) { | |
343 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START, | |
344 | ipd->regs + INT_CSR); | |
345 | ipd->field_count++; | |
346 | return IRQ_HANDLED; /* start of field irq */ | |
347 | } | |
348 | if ((tmp & FLD_START) && (tmp & FLD_END_ODD)) { | |
349 | if (!ipd->stats.start_before_end++) | |
350 | printk(KERN_ERR "dt3155: irq: START before END\n"); | |
351 | } | |
352 | /* check for corrupted fields */ | |
353 | /* write_i2c_reg(ipd->regs, EVEN_CSR, CSR_ERROR | CSR_DONE); */ | |
354 | /* write_i2c_reg(ipd->regs, ODD_CSR, CSR_ERROR | CSR_DONE); */ | |
355 | tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); | |
356 | if (tmp) { | |
357 | if (!ipd->stats.corrupted_fields++) | |
358 | printk(KERN_ERR "dt3155: corrupted field %u\n", tmp); | |
359 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | | |
360 | FLD_DN_ODD | FLD_DN_EVEN | | |
361 | CAP_CONT_EVEN | CAP_CONT_ODD, | |
362 | ipd->regs + CSR1); | |
363 | mmiowb(); | |
364 | } | |
365 | ||
366 | spin_lock(&ipd->lock); | |
8ded351a MM |
367 | if (ipd->curr_buf) { |
368 | do_gettimeofday(&ipd->curr_buf->v4l2_buf.timestamp); | |
369 | ipd->curr_buf->v4l2_buf.sequence = (ipd->field_count) >> 1; | |
370 | vb2_buffer_done(ipd->curr_buf, VB2_BUF_STATE_DONE); | |
371 | } | |
372 | ||
373 | if (!ipd->q->streaming || list_empty(&ipd->dmaq)) | |
d42bffb8 | 374 | goto stop_dma; |
8ded351a MM |
375 | ivb = list_first_entry(&ipd->dmaq, typeof(*ivb), done_entry); |
376 | list_del(&ivb->done_entry); | |
377 | ipd->curr_buf = ivb; | |
378 | dma_addr = vb2_dma_contig_plane_paddr(ivb, 0); | |
d42bffb8 | 379 | iowrite32(dma_addr, ipd->regs + EVEN_DMA_START); |
8ded351a MM |
380 | iowrite32(dma_addr + img_width, ipd->regs + ODD_DMA_START); |
381 | iowrite32(img_width, ipd->regs + EVEN_DMA_STRIDE); | |
382 | iowrite32(img_width, ipd->regs + ODD_DMA_STRIDE); | |
d42bffb8 MM |
383 | mmiowb(); |
384 | /* enable interrupts, clear all irq flags */ | |
385 | iowrite32(FLD_START_EN | FLD_END_ODD_EN | FLD_START | | |
386 | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); | |
387 | spin_unlock(&ipd->lock); | |
388 | return IRQ_HANDLED; | |
389 | ||
390 | stop_dma: | |
391 | ipd->curr_buf = NULL; | |
392 | /* stop the board */ | |
393 | write_i2c_reg_nowait(ipd->regs, CSR2, ipd->csr2); | |
8ded351a MM |
394 | iowrite32(FIFO_EN | SRST | FLD_CRPT_ODD | FLD_CRPT_EVEN | |
395 | FLD_DN_ODD | FLD_DN_EVEN, ipd->regs + CSR1); | |
d42bffb8 MM |
396 | /* disable interrupts, clear all irq flags */ |
397 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, ipd->regs + INT_CSR); | |
398 | spin_unlock(&ipd->lock); | |
399 | return IRQ_HANDLED; | |
400 | } | |
401 | ||
d42bffb8 MM |
402 | static int |
403 | dt3155_open(struct file *filp) | |
404 | { | |
405 | int ret = 0; | |
406 | struct dt3155_priv *pd = video_drvdata(filp); | |
407 | ||
8ded351a MM |
408 | printk(KERN_INFO "dt3155: open(): minor: %i, users: %i\n", |
409 | pd->vdev->minor, pd->users); | |
d42bffb8 | 410 | |
d42bffb8 | 411 | if (!pd->users) { |
8ded351a MM |
412 | pd->q = kzalloc(sizeof(*pd->q), GFP_KERNEL); |
413 | if (!pd->q) { | |
d42bffb8 MM |
414 | printk(KERN_ERR "dt3155: error: alloc queue\n"); |
415 | ret = -ENOMEM; | |
416 | goto err_alloc_queue; | |
417 | } | |
8ded351a MM |
418 | pd->q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; |
419 | pd->q->io_modes = VB2_READ | VB2_MMAP; | |
420 | pd->q->ops = &q_ops; | |
421 | pd->q->mem_ops = &vb2_dma_contig_memops; | |
422 | pd->q->drv_priv = pd; | |
423 | pd->curr_buf = NULL; | |
424 | pd->field_count = 0; | |
425 | vb2_queue_init(pd->q); /* cannot fail */ | |
426 | INIT_LIST_HEAD(&pd->dmaq); | |
427 | spin_lock_init(&pd->lock); | |
d42bffb8 MM |
428 | /* disable all irqs, clear all irq flags */ |
429 | iowrite32(FLD_START | FLD_END_EVEN | FLD_END_ODD, | |
430 | pd->regs + INT_CSR); | |
431 | pd->irq_handler = dt3155_irq_handler_even; | |
432 | ret = request_irq(pd->pdev->irq, pd->irq_handler, | |
433 | IRQF_SHARED, DT3155_NAME, pd); | |
434 | if (ret) { | |
435 | printk(KERN_ERR "dt3155: error: request_irq\n"); | |
436 | goto err_request_irq; | |
437 | } | |
d42bffb8 MM |
438 | } |
439 | pd->users++; | |
8ded351a | 440 | return 0; /* success */ |
d42bffb8 | 441 | err_request_irq: |
8ded351a MM |
442 | kfree(pd->q); |
443 | pd->q = NULL; | |
d42bffb8 | 444 | err_alloc_queue: |
d42bffb8 MM |
445 | return ret; |
446 | } | |
447 | ||
448 | static int | |
449 | dt3155_release(struct file *filp) | |
450 | { | |
451 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 452 | |
8ded351a MM |
453 | printk(KERN_INFO "dt3155: release(): minor: %i, users: %i\n", |
454 | pd->vdev->minor, pd->users - 1); | |
d42bffb8 | 455 | |
d42bffb8 MM |
456 | pd->users--; |
457 | BUG_ON(pd->users < 0); | |
d42bffb8 | 458 | if (!pd->users) { |
8ded351a | 459 | vb2_queue_release(pd->q); |
d42bffb8 | 460 | free_irq(pd->pdev->irq, pd); |
8ded351a MM |
461 | if (pd->q->alloc_ctx[0]) |
462 | vb2_dma_contig_cleanup_ctx(pd->q->alloc_ctx[0]); | |
463 | kfree(pd->q); | |
464 | pd->q = NULL; | |
d42bffb8 | 465 | } |
8ded351a | 466 | return 0; |
d42bffb8 MM |
467 | } |
468 | ||
469 | static ssize_t | |
470 | dt3155_read(struct file *filp, char __user *user, size_t size, loff_t *loff) | |
471 | { | |
472 | struct dt3155_priv *pd = video_drvdata(filp); | |
8ded351a MM |
473 | |
474 | return vb2_read(pd->q, user, size, loff, filp->f_flags & O_NONBLOCK); | |
d42bffb8 MM |
475 | } |
476 | ||
477 | static unsigned int | |
478 | dt3155_poll(struct file *filp, struct poll_table_struct *polltbl) | |
479 | { | |
480 | struct dt3155_priv *pd = video_drvdata(filp); | |
481 | ||
8ded351a | 482 | return vb2_poll(pd->q, filp, polltbl); |
d42bffb8 MM |
483 | } |
484 | ||
485 | static int | |
486 | dt3155_mmap(struct file *filp, struct vm_area_struct *vma) | |
487 | { | |
488 | struct dt3155_priv *pd = video_drvdata(filp); | |
489 | ||
8ded351a | 490 | return vb2_mmap(pd->q, vma); |
d42bffb8 MM |
491 | } |
492 | ||
493 | static const struct v4l2_file_operations dt3155_fops = { | |
494 | .owner = THIS_MODULE, | |
495 | .open = dt3155_open, | |
496 | .release = dt3155_release, | |
497 | .read = dt3155_read, | |
498 | .poll = dt3155_poll, | |
499 | .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */ | |
500 | .mmap = dt3155_mmap, | |
501 | }; | |
502 | ||
503 | static int | |
504 | dt3155_ioc_streamon(struct file *filp, void *p, enum v4l2_buf_type type) | |
505 | { | |
506 | struct dt3155_priv *pd = video_drvdata(filp); | |
8ded351a MM |
507 | |
508 | return vb2_streamon(pd->q, type); | |
d42bffb8 MM |
509 | } |
510 | ||
511 | static int | |
512 | dt3155_ioc_streamoff(struct file *filp, void *p, enum v4l2_buf_type type) | |
513 | { | |
514 | struct dt3155_priv *pd = video_drvdata(filp); | |
8ded351a MM |
515 | |
516 | return vb2_streamoff(pd->q, type); | |
d42bffb8 MM |
517 | } |
518 | ||
519 | static int | |
520 | dt3155_ioc_querycap(struct file *filp, void *p, struct v4l2_capability *cap) | |
521 | { | |
522 | struct dt3155_priv *pd = video_drvdata(filp); | |
523 | ||
524 | strcpy(cap->driver, DT3155_NAME); | |
525 | strcpy(cap->card, DT3155_NAME " frame grabber"); | |
526 | sprintf(cap->bus_info, "PCI:%s", pci_name(pd->pdev)); | |
527 | cap->version = | |
528 | KERNEL_VERSION(DT3155_VER_MAJ, DT3155_VER_MIN, DT3155_VER_EXT); | |
529 | cap->capabilities = V4L2_CAP_VIDEO_CAPTURE | | |
8ded351a | 530 | DT3155_CAPTURE_METHOD; |
d42bffb8 MM |
531 | return 0; |
532 | } | |
533 | ||
534 | static int | |
535 | dt3155_ioc_enum_fmt_vid_cap(struct file *filp, void *p, struct v4l2_fmtdesc *f) | |
536 | { | |
537 | if (f->index >= NUM_OF_FORMATS) | |
538 | return -EINVAL; | |
539 | *f = frame_std[f->index]; | |
540 | return 0; | |
541 | } | |
542 | ||
543 | static int | |
544 | dt3155_ioc_g_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
545 | { | |
546 | if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
547 | return -EINVAL; | |
548 | f->fmt.pix.width = img_width; | |
549 | f->fmt.pix.height = img_height; | |
550 | f->fmt.pix.pixelformat = V4L2_PIX_FMT_GREY; | |
551 | f->fmt.pix.field = V4L2_FIELD_NONE; | |
552 | f->fmt.pix.bytesperline = f->fmt.pix.width; | |
553 | f->fmt.pix.sizeimage = f->fmt.pix.width * f->fmt.pix.height; | |
554 | f->fmt.pix.colorspace = 0; | |
555 | f->fmt.pix.priv = 0; | |
556 | return 0; | |
557 | } | |
558 | ||
559 | static int | |
560 | dt3155_ioc_try_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
561 | { | |
562 | if (f->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
563 | return -EINVAL; | |
564 | if (f->fmt.pix.width == img_width && | |
565 | f->fmt.pix.height == img_height && | |
566 | f->fmt.pix.pixelformat == V4L2_PIX_FMT_GREY && | |
567 | f->fmt.pix.field == V4L2_FIELD_NONE && | |
568 | f->fmt.pix.bytesperline == f->fmt.pix.width && | |
569 | f->fmt.pix.sizeimage == f->fmt.pix.width * f->fmt.pix.height) | |
570 | return 0; | |
571 | else | |
572 | return -EINVAL; | |
573 | } | |
574 | ||
575 | static int | |
576 | dt3155_ioc_s_fmt_vid_cap(struct file *filp, void *p, struct v4l2_format *f) | |
577 | { | |
8ded351a | 578 | return dt3155_ioc_g_fmt_vid_cap(filp, p, f); |
d42bffb8 MM |
579 | } |
580 | ||
581 | static int | |
582 | dt3155_ioc_reqbufs(struct file *filp, void *p, struct v4l2_requestbuffers *b) | |
583 | { | |
584 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 585 | |
8ded351a | 586 | return vb2_reqbufs(pd->q, b); |
d42bffb8 MM |
587 | } |
588 | ||
589 | static int | |
590 | dt3155_ioc_querybuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
591 | { | |
592 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 593 | |
8ded351a | 594 | return vb2_querybuf(pd->q, b); |
d42bffb8 MM |
595 | } |
596 | ||
597 | static int | |
598 | dt3155_ioc_qbuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
599 | { | |
600 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 601 | |
8ded351a | 602 | return vb2_qbuf(pd->q, b); |
d42bffb8 MM |
603 | } |
604 | ||
605 | static int | |
606 | dt3155_ioc_dqbuf(struct file *filp, void *p, struct v4l2_buffer *b) | |
607 | { | |
608 | struct dt3155_priv *pd = video_drvdata(filp); | |
d42bffb8 | 609 | |
8ded351a | 610 | return vb2_dqbuf(pd->q, b, filp->f_flags & O_NONBLOCK); |
d42bffb8 MM |
611 | } |
612 | ||
613 | static int | |
614 | dt3155_ioc_querystd(struct file *filp, void *p, v4l2_std_id *norm) | |
615 | { | |
616 | *norm = DT3155_CURRENT_NORM; | |
617 | return 0; | |
618 | } | |
619 | ||
620 | static int | |
621 | dt3155_ioc_g_std(struct file *filp, void *p, v4l2_std_id *norm) | |
622 | { | |
623 | *norm = DT3155_CURRENT_NORM; | |
624 | return 0; | |
625 | } | |
626 | ||
627 | static int | |
628 | dt3155_ioc_s_std(struct file *filp, void *p, v4l2_std_id *norm) | |
629 | { | |
630 | if (*norm & DT3155_CURRENT_NORM) | |
631 | return 0; | |
632 | return -EINVAL; | |
633 | } | |
634 | ||
635 | static int | |
636 | dt3155_ioc_enum_input(struct file *filp, void *p, struct v4l2_input *input) | |
637 | { | |
638 | if (input->index) | |
639 | return -EINVAL; | |
640 | strcpy(input->name, "Coax in"); | |
641 | input->type = V4L2_INPUT_TYPE_CAMERA; | |
fdd2d934 MM |
642 | /* |
643 | * FIXME: input->std = 0 according to v4l2 API | |
644 | * VIDIOC_G_STD, VIDIOC_S_STD, VIDIOC_QUERYSTD and VIDIOC_ENUMSTD | |
645 | * should return -EINVAL | |
646 | */ | |
647 | input->std = DT3155_CURRENT_NORM; | |
d42bffb8 MM |
648 | input->status = 0;/* FIXME: add sync detection & V4L2_IN_ST_NO_H_LOCK */ |
649 | return 0; | |
650 | } | |
651 | ||
652 | static int | |
653 | dt3155_ioc_g_input(struct file *filp, void *p, unsigned int *i) | |
654 | { | |
655 | *i = 0; | |
656 | return 0; | |
657 | } | |
658 | ||
659 | static int | |
660 | dt3155_ioc_s_input(struct file *filp, void *p, unsigned int i) | |
661 | { | |
662 | if (i) | |
663 | return -EINVAL; | |
664 | return 0; | |
665 | } | |
666 | ||
667 | static int | |
668 | dt3155_ioc_g_parm(struct file *filp, void *p, struct v4l2_streamparm *parms) | |
669 | { | |
670 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
671 | return -EINVAL; | |
672 | parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; | |
673 | parms->parm.capture.capturemode = 0; | |
674 | parms->parm.capture.timeperframe.numerator = 1001; | |
675 | parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000; | |
676 | parms->parm.capture.extendedmode = 0; | |
fdd2d934 | 677 | parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */ |
d42bffb8 MM |
678 | return 0; |
679 | } | |
680 | ||
681 | static int | |
682 | dt3155_ioc_s_parm(struct file *filp, void *p, struct v4l2_streamparm *parms) | |
683 | { | |
684 | if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) | |
685 | return -EINVAL; | |
686 | parms->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; | |
687 | parms->parm.capture.capturemode = 0; | |
688 | parms->parm.capture.timeperframe.numerator = 1001; | |
689 | parms->parm.capture.timeperframe.denominator = frames_per_sec * 1000; | |
690 | parms->parm.capture.extendedmode = 0; | |
fdd2d934 | 691 | parms->parm.capture.readbuffers = 1; /* FIXME: 2 buffers? */ |
d42bffb8 MM |
692 | return 0; |
693 | } | |
694 | ||
695 | static const struct v4l2_ioctl_ops dt3155_ioctl_ops = { | |
696 | .vidioc_streamon = dt3155_ioc_streamon, | |
697 | .vidioc_streamoff = dt3155_ioc_streamoff, | |
698 | .vidioc_querycap = dt3155_ioc_querycap, | |
699 | /* | |
700 | .vidioc_g_priority = dt3155_ioc_g_priority, | |
701 | .vidioc_s_priority = dt3155_ioc_s_priority, | |
702 | */ | |
703 | .vidioc_enum_fmt_vid_cap = dt3155_ioc_enum_fmt_vid_cap, | |
704 | .vidioc_try_fmt_vid_cap = dt3155_ioc_try_fmt_vid_cap, | |
705 | .vidioc_g_fmt_vid_cap = dt3155_ioc_g_fmt_vid_cap, | |
706 | .vidioc_s_fmt_vid_cap = dt3155_ioc_s_fmt_vid_cap, | |
707 | .vidioc_reqbufs = dt3155_ioc_reqbufs, | |
708 | .vidioc_querybuf = dt3155_ioc_querybuf, | |
709 | .vidioc_qbuf = dt3155_ioc_qbuf, | |
710 | .vidioc_dqbuf = dt3155_ioc_dqbuf, | |
711 | .vidioc_querystd = dt3155_ioc_querystd, | |
712 | .vidioc_g_std = dt3155_ioc_g_std, | |
713 | .vidioc_s_std = dt3155_ioc_s_std, | |
714 | .vidioc_enum_input = dt3155_ioc_enum_input, | |
715 | .vidioc_g_input = dt3155_ioc_g_input, | |
716 | .vidioc_s_input = dt3155_ioc_s_input, | |
717 | /* | |
718 | .vidioc_queryctrl = dt3155_ioc_queryctrl, | |
719 | .vidioc_g_ctrl = dt3155_ioc_g_ctrl, | |
720 | .vidioc_s_ctrl = dt3155_ioc_s_ctrl, | |
721 | .vidioc_querymenu = dt3155_ioc_querymenu, | |
722 | .vidioc_g_ext_ctrls = dt3155_ioc_g_ext_ctrls, | |
723 | .vidioc_s_ext_ctrls = dt3155_ioc_s_ext_ctrls, | |
724 | */ | |
725 | .vidioc_g_parm = dt3155_ioc_g_parm, | |
726 | .vidioc_s_parm = dt3155_ioc_s_parm, | |
727 | /* | |
728 | .vidioc_cropcap = dt3155_ioc_cropcap, | |
729 | .vidioc_g_crop = dt3155_ioc_g_crop, | |
730 | .vidioc_s_crop = dt3155_ioc_s_crop, | |
731 | .vidioc_enum_framesizes = dt3155_ioc_enum_framesizes, | |
732 | .vidioc_enum_frameintervals = dt3155_ioc_enum_frameintervals, | |
d42bffb8 MM |
733 | */ |
734 | }; | |
735 | ||
736 | static int __devinit | |
8ded351a | 737 | dt3155_init_board(struct pci_dev *pdev) |
d42bffb8 | 738 | { |
8ded351a | 739 | struct dt3155_priv *pd = pci_get_drvdata(pdev); |
a57941c2 MM |
740 | void *buf_cpu; |
741 | dma_addr_t buf_dma; | |
d42bffb8 MM |
742 | int i; |
743 | u8 tmp; | |
a57941c2 | 744 | |
8ded351a | 745 | pci_set_master(pdev); /* dt3155 needs it */ |
d42bffb8 MM |
746 | |
747 | /* resetting the adapter */ | |
748 | iowrite32(FLD_CRPT_ODD | FLD_CRPT_EVEN | FLD_DN_ODD | FLD_DN_EVEN, | |
749 | pd->regs + CSR1); | |
750 | mmiowb(); | |
8ded351a | 751 | msleep(20); |
d42bffb8 MM |
752 | |
753 | /* initializing adaper registers */ | |
754 | iowrite32(FIFO_EN | SRST, pd->regs + CSR1); | |
755 | mmiowb(); | |
756 | iowrite32(0xEEEEEE01, pd->regs + EVEN_PIXEL_FMT); | |
757 | iowrite32(0xEEEEEE01, pd->regs + ODD_PIXEL_FMT); | |
758 | iowrite32(0x00000020, pd->regs + FIFO_TRIGER); | |
759 | iowrite32(0x00000103, pd->regs + XFER_MODE); | |
760 | iowrite32(0, pd->regs + RETRY_WAIT_CNT); | |
761 | iowrite32(0, pd->regs + INT_CSR); | |
762 | iowrite32(1, pd->regs + EVEN_FLD_MASK); | |
763 | iowrite32(1, pd->regs + ODD_FLD_MASK); | |
764 | iowrite32(0, pd->regs + MASK_LENGTH); | |
765 | iowrite32(0x0005007C, pd->regs + FIFO_FLAG_CNT); | |
766 | iowrite32(0x01010101, pd->regs + IIC_CLK_DUR); | |
767 | mmiowb(); | |
768 | ||
769 | /* verifying that we have a DT3155 board (not just a SAA7116 chip) */ | |
770 | read_i2c_reg(pd->regs, DT_ID, &tmp); | |
771 | if (tmp != DT3155_ID) | |
772 | return -ENODEV; | |
773 | ||
774 | /* initialize AD LUT */ | |
775 | write_i2c_reg(pd->regs, AD_ADDR, 0); | |
776 | for (i = 0; i < 256; i++) | |
777 | write_i2c_reg(pd->regs, AD_LUT, i); | |
778 | ||
779 | /* initialize ADC references */ | |
780 | /* FIXME: pos_ref & neg_ref depend on VT_50HZ */ | |
781 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); | |
782 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); | |
783 | write_i2c_reg(pd->regs, AD_ADDR, AD_POS_REF); | |
784 | write_i2c_reg(pd->regs, AD_CMD, 34); | |
785 | write_i2c_reg(pd->regs, AD_ADDR, AD_NEG_REF); | |
786 | write_i2c_reg(pd->regs, AD_CMD, 0); | |
787 | ||
788 | /* initialize PM LUT */ | |
789 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM); | |
790 | for (i = 0; i < 256; i++) { | |
791 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); | |
792 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); | |
793 | } | |
794 | write_i2c_reg(pd->regs, CONFIG, pd->config | PM_LUT_PGM | PM_LUT_SEL); | |
795 | for (i = 0; i < 256; i++) { | |
796 | write_i2c_reg(pd->regs, PM_LUT_ADDR, i); | |
797 | write_i2c_reg(pd->regs, PM_LUT_DATA, i); | |
798 | } | |
799 | write_i2c_reg(pd->regs, CONFIG, pd->config); /* ACQ_MODE_EVEN */ | |
800 | ||
801 | /* select chanel 1 for input and set sync level */ | |
802 | write_i2c_reg(pd->regs, AD_ADDR, AD_CMD_REG); | |
803 | write_i2c_reg(pd->regs, AD_CMD, VIDEO_CNL_1 | SYNC_CNL_1 | SYNC_LVL_3); | |
804 | ||
a57941c2 | 805 | /* allocate memory, and initialize the DMA machine */ |
8ded351a | 806 | buf_cpu = dma_alloc_coherent(&pdev->dev, DT3155_BUF_SIZE, &buf_dma, |
a57941c2 MM |
807 | GFP_KERNEL); |
808 | if (!buf_cpu) { | |
809 | printk(KERN_ERR "dt3155: dma_alloc_coherent " | |
d42bffb8 MM |
810 | "(in dt3155_init_board) failed\n"); |
811 | return -ENOMEM; | |
812 | } | |
a57941c2 MM |
813 | iowrite32(buf_dma, pd->regs + EVEN_DMA_START); |
814 | iowrite32(buf_dma, pd->regs + ODD_DMA_START); | |
d42bffb8 MM |
815 | iowrite32(0, pd->regs + EVEN_DMA_STRIDE); |
816 | iowrite32(0, pd->regs + ODD_DMA_STRIDE); | |
817 | ||
818 | /* Perform a pseudo even field acquire */ | |
819 | iowrite32(FIFO_EN | SRST | CAP_CONT_ODD, pd->regs + CSR1); | |
820 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | SYNC_SNTL); | |
821 | write_i2c_reg(pd->regs, CONFIG, pd->config); | |
822 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_SNGL); | |
823 | write_i2c_reg(pd->regs, CSR2, pd->csr2 | BUSY_EVEN | SYNC_SNTL); | |
824 | msleep(100); | |
825 | read_i2c_reg(pd->regs, CSR2, &tmp); | |
826 | write_i2c_reg(pd->regs, EVEN_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE); | |
827 | write_i2c_reg(pd->regs, ODD_CSR, CSR_ERROR | CSR_SNGL | CSR_DONE); | |
828 | write_i2c_reg(pd->regs, CSR2, pd->csr2); | |
829 | iowrite32(FIFO_EN | SRST | FLD_DN_EVEN | FLD_DN_ODD, pd->regs + CSR1); | |
830 | ||
a57941c2 | 831 | /* deallocate memory */ |
8ded351a | 832 | dma_free_coherent(&pdev->dev, DT3155_BUF_SIZE, buf_cpu, buf_dma); |
d42bffb8 MM |
833 | if (tmp & BUSY_EVEN) { |
834 | printk(KERN_ERR "dt3155: BUSY_EVEN not cleared\n"); | |
835 | return -EIO; | |
836 | } | |
837 | return 0; | |
838 | } | |
839 | ||
840 | static struct video_device dt3155_vdev = { | |
841 | .name = DT3155_NAME, | |
842 | .fops = &dt3155_fops, | |
843 | .ioctl_ops = &dt3155_ioctl_ops, | |
844 | .minor = -1, | |
845 | .release = video_device_release, | |
fdd2d934 | 846 | .tvnorms = DT3155_CURRENT_NORM, |
d42bffb8 MM |
847 | .current_norm = DT3155_CURRENT_NORM, |
848 | }; | |
849 | ||
a57941c2 MM |
850 | /* same as in drivers/base/dma-coherent.c */ |
851 | struct dma_coherent_mem { | |
852 | void *virt_base; | |
8ded351a | 853 | dma_addr_t device_base; |
a57941c2 MM |
854 | int size; |
855 | int flags; | |
856 | unsigned long *bitmap; | |
857 | }; | |
858 | ||
859 | static int __devinit | |
860 | dt3155_alloc_coherent(struct device *dev, size_t size, int flags) | |
861 | { | |
f932e3a3 MM |
862 | struct dma_coherent_mem *mem; |
863 | dma_addr_t dev_base; | |
a57941c2 MM |
864 | int pages = size >> PAGE_SHIFT; |
865 | int bitmap_size = BITS_TO_LONGS(pages) * sizeof(long); | |
866 | ||
867 | if ((flags & DMA_MEMORY_MAP) == 0) | |
868 | goto out; | |
869 | if (!size) | |
870 | goto out; | |
871 | if (dev->dma_mem) | |
872 | goto out; | |
873 | ||
f932e3a3 MM |
874 | mem = kzalloc(sizeof(*mem), GFP_KERNEL); |
875 | if (!mem) | |
a57941c2 | 876 | goto out; |
f932e3a3 MM |
877 | mem->virt_base = dma_alloc_coherent(dev, size, &dev_base, |
878 | DT3155_COH_FLAGS); | |
879 | if (!mem->virt_base) | |
880 | goto err_alloc_coherent; | |
881 | mem->bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
882 | if (!mem->bitmap) | |
a57941c2 MM |
883 | goto err_bitmap; |
884 | ||
f932e3a3 MM |
885 | /* coherent_dma_mask is already set to 32 bits */ |
886 | mem->device_base = dev_base; | |
887 | mem->size = pages; | |
888 | mem->flags = flags; | |
889 | dev->dma_mem = mem; | |
a57941c2 MM |
890 | return DMA_MEMORY_MAP; |
891 | ||
a57941c2 | 892 | err_bitmap: |
f932e3a3 MM |
893 | dma_free_coherent(dev, size, mem->virt_base, dev_base); |
894 | err_alloc_coherent: | |
895 | kfree(mem); | |
a57941c2 MM |
896 | out: |
897 | return 0; | |
898 | } | |
899 | ||
900 | static void __devexit | |
901 | dt3155_free_coherent(struct device *dev) | |
902 | { | |
903 | struct dma_coherent_mem *mem = dev->dma_mem; | |
904 | ||
905 | if (!mem) | |
906 | return; | |
907 | dev->dma_mem = NULL; | |
908 | dma_free_coherent(dev, mem->size << PAGE_SHIFT, | |
909 | mem->virt_base, mem->device_base); | |
910 | kfree(mem->bitmap); | |
911 | kfree(mem); | |
912 | } | |
913 | ||
d42bffb8 | 914 | static int __devinit |
8ded351a | 915 | dt3155_probe(struct pci_dev *pdev, const struct pci_device_id *id) |
d42bffb8 | 916 | { |
a57941c2 | 917 | int err; |
d42bffb8 MM |
918 | struct dt3155_priv *pd; |
919 | ||
920 | printk(KERN_INFO "dt3155: probe()\n"); | |
8ded351a | 921 | err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)); |
a57941c2 | 922 | if (err) { |
d42bffb8 MM |
923 | printk(KERN_ERR "dt3155: cannot set dma_mask\n"); |
924 | return -ENODEV; | |
925 | } | |
8ded351a | 926 | err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
a57941c2 MM |
927 | if (err) { |
928 | printk(KERN_ERR "dt3155: cannot set dma_coherent_mask\n"); | |
929 | return -ENODEV; | |
930 | } | |
d42bffb8 MM |
931 | pd = kzalloc(sizeof(*pd), GFP_KERNEL); |
932 | if (!pd) { | |
933 | printk(KERN_ERR "dt3155: cannot allocate dt3155_priv\n"); | |
934 | return -ENOMEM; | |
935 | } | |
936 | pd->vdev = video_device_alloc(); | |
937 | if (!pd->vdev) { | |
a57941c2 | 938 | printk(KERN_ERR "dt3155: cannot allocate vdev structure\n"); |
d42bffb8 MM |
939 | goto err_video_device_alloc; |
940 | } | |
941 | *pd->vdev = dt3155_vdev; | |
8ded351a | 942 | pci_set_drvdata(pdev, pd); /* for use in dt3155_remove() */ |
a57941c2 | 943 | video_set_drvdata(pd->vdev, pd); /* for use in video_fops */ |
d42bffb8 | 944 | pd->users = 0; |
8ded351a | 945 | pd->pdev = pdev; |
d42bffb8 | 946 | INIT_LIST_HEAD(&pd->dmaq); |
d42bffb8 | 947 | mutex_init(&pd->mux); |
8ded351a MM |
948 | pd->vdev->lock = &pd->mux; /* for locking v4l2_file_operations */ |
949 | spin_lock_init(&pd->lock); | |
d42bffb8 MM |
950 | pd->csr2 = csr2_init; |
951 | pd->config = config_init; | |
8ded351a | 952 | err = pci_enable_device(pdev); |
d42bffb8 MM |
953 | if (err) { |
954 | printk(KERN_ERR "dt3155: pci_dev not enabled\n"); | |
955 | goto err_enable_dev; | |
956 | } | |
8ded351a | 957 | err = pci_request_region(pdev, 0, pci_name(pdev)); |
d42bffb8 MM |
958 | if (err) |
959 | goto err_req_region; | |
8ded351a | 960 | pd->regs = pci_iomap(pdev, 0, pci_resource_len(pd->pdev, 0)); |
d42bffb8 MM |
961 | if (!pd->regs) { |
962 | err = -ENOMEM; | |
963 | printk(KERN_ERR "dt3155: pci_iomap failed\n"); | |
964 | goto err_pci_iomap; | |
965 | } | |
8ded351a | 966 | err = dt3155_init_board(pdev); |
d42bffb8 MM |
967 | if (err) { |
968 | printk(KERN_ERR "dt3155: dt3155_init_board failed\n"); | |
969 | goto err_init_board; | |
970 | } | |
971 | err = video_register_device(pd->vdev, VFL_TYPE_GRABBER, -1); | |
972 | if (err) { | |
973 | printk(KERN_ERR "dt3155: Cannot register video device\n"); | |
974 | goto err_init_board; | |
975 | } | |
8ded351a | 976 | err = dt3155_alloc_coherent(&pdev->dev, DT3155_CHUNK_SIZE, |
a57941c2 MM |
977 | DMA_MEMORY_MAP); |
978 | if (err) | |
979 | printk(KERN_INFO "dt3155: preallocated 8 buffers\n"); | |
d42bffb8 MM |
980 | printk(KERN_INFO "dt3155: /dev/video%i is ready\n", pd->vdev->minor); |
981 | return 0; /* success */ | |
982 | ||
983 | err_init_board: | |
8ded351a | 984 | pci_iounmap(pdev, pd->regs); |
d42bffb8 | 985 | err_pci_iomap: |
8ded351a | 986 | pci_release_region(pdev, 0); |
d42bffb8 | 987 | err_req_region: |
8ded351a | 988 | pci_disable_device(pdev); |
d42bffb8 MM |
989 | err_enable_dev: |
990 | video_device_release(pd->vdev); | |
991 | err_video_device_alloc: | |
992 | kfree(pd); | |
993 | return err; | |
994 | } | |
995 | ||
996 | static void __devexit | |
8ded351a | 997 | dt3155_remove(struct pci_dev *pdev) |
d42bffb8 | 998 | { |
8ded351a | 999 | struct dt3155_priv *pd = pci_get_drvdata(pdev); |
d42bffb8 MM |
1000 | |
1001 | printk(KERN_INFO "dt3155: remove()\n"); | |
8ded351a | 1002 | dt3155_free_coherent(&pdev->dev); |
d42bffb8 | 1003 | video_unregister_device(pd->vdev); |
8ded351a MM |
1004 | pci_iounmap(pdev, pd->regs); |
1005 | pci_release_region(pdev, 0); | |
1006 | pci_disable_device(pdev); | |
d42bffb8 MM |
1007 | /* |
1008 | * video_device_release() is invoked automatically | |
1009 | * see: struct video_device dt3155_vdev | |
1010 | */ | |
1011 | kfree(pd); | |
1012 | } | |
1013 | ||
1014 | static DEFINE_PCI_DEVICE_TABLE(pci_ids) = { | |
1015 | { PCI_DEVICE(DT3155_VENDOR_ID, DT3155_DEVICE_ID) }, | |
1016 | { 0, /* zero marks the end */ }, | |
1017 | }; | |
1018 | MODULE_DEVICE_TABLE(pci, pci_ids); | |
1019 | ||
1020 | static struct pci_driver pci_driver = { | |
1021 | .name = DT3155_NAME, | |
1022 | .id_table = pci_ids, | |
1023 | .probe = dt3155_probe, | |
1024 | .remove = __devexit_p(dt3155_remove), | |
1025 | }; | |
1026 | ||
1027 | static int __init | |
1028 | dt3155_init_module(void) | |
1029 | { | |
1030 | int err; | |
1031 | ||
1032 | printk(KERN_INFO "dt3155: ==================\n"); | |
1033 | printk(KERN_INFO "dt3155: init()\n"); | |
d42bffb8 MM |
1034 | err = pci_register_driver(&pci_driver); |
1035 | if (err) { | |
1036 | printk(KERN_ERR "dt3155: cannot register pci_driver\n"); | |
a57941c2 | 1037 | return err; |
d42bffb8 MM |
1038 | } |
1039 | return 0; /* succes */ | |
d42bffb8 MM |
1040 | } |
1041 | ||
1042 | static void __exit | |
1043 | dt3155_exit_module(void) | |
1044 | { | |
1045 | pci_unregister_driver(&pci_driver); | |
d42bffb8 MM |
1046 | printk(KERN_INFO "dt3155: exit()\n"); |
1047 | printk(KERN_INFO "dt3155: ==================\n"); | |
1048 | } | |
1049 | ||
1050 | module_init(dt3155_init_module); | |
1051 | module_exit(dt3155_exit_module); | |
1052 | ||
1053 | MODULE_DESCRIPTION("video4linux pci-driver for dt3155 frame grabber"); | |
1054 | MODULE_AUTHOR("Marin Mitov <mitov@issp.bas.bg>"); | |
1055 | MODULE_VERSION(DT3155_VERSION); | |
1056 | MODULE_LICENSE("GPL"); |