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33aa8d45 MD |
1 | /* |
2 | * drivers/usb/gadget/emxx_udc.c | |
3 | * EMXX FCD (Function Controller Driver) for USB. | |
4 | * | |
5 | * Copyright (C) 2010 Renesas Electronics Corporation | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 | |
9 | * as published by the Free Software Foundation. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software Foundation, | |
18 | * Inc., 51 Franklin Street, Suite 500, Boston, MA 02110-1335, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/module.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/ioport.h> | |
26 | #include <linux/slab.h> | |
27 | #include <linux/errno.h> | |
28 | #include <linux/init.h> | |
29 | #include <linux/list.h> | |
30 | #include <linux/interrupt.h> | |
31 | #include <linux/proc_fs.h> | |
32 | #include <linux/clk.h> | |
33 | #include <linux/ctype.h> | |
34 | #include <linux/string.h> | |
35 | #include <linux/dma-mapping.h> | |
36 | #include <linux/workqueue.h> | |
a790ebc1 | 37 | #include <linux/device.h> |
33aa8d45 MD |
38 | |
39 | #include <linux/usb/ch9.h> | |
40 | #include <linux/usb/gadget.h> | |
41 | ||
42 | #include <linux/irq.h> | |
43 | #include <linux/gpio.h> | |
44 | ||
45 | #include "emxx_udc.h" | |
46 | ||
47 | #define DRIVER_DESC "EMXX UDC driver" | |
48 | #define DMA_ADDR_INVALID (~(dma_addr_t)0) | |
49 | ||
50 | static const char driver_name[] = "emxx_udc"; | |
51 | static const char driver_desc[] = DRIVER_DESC; | |
52 | ||
53 | /*===========================================================================*/ | |
54 | /* Prototype */ | |
55 | static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *, struct nbu2ss_ep *); | |
56 | static void _nbu2ss_ep0_enable(struct nbu2ss_udc *); | |
57 | /*static void _nbu2ss_ep0_disable(struct nbu2ss_udc *);*/ | |
58 | static void _nbu2ss_ep_done(struct nbu2ss_ep *, struct nbu2ss_req *, int); | |
59 | static void _nbu2ss_set_test_mode(struct nbu2ss_udc *, u32 mode); | |
60 | static void _nbu2ss_endpoint_toggle_reset(struct nbu2ss_udc *udc, u8 ep_adrs); | |
61 | ||
62 | static int _nbu2ss_pullup(struct nbu2ss_udc *, int); | |
63 | static void _nbu2ss_fifo_flush(struct nbu2ss_udc *, struct nbu2ss_ep *); | |
64 | ||
65 | /*===========================================================================*/ | |
66 | /* Macro */ | |
67 | #define _nbu2ss_zero_len_pkt(udc, epnum) \ | |
68 | _nbu2ss_ep_in_end(udc, epnum, 0, 0) | |
69 | ||
70 | ||
71 | /*===========================================================================*/ | |
72 | /* Global */ | |
73 | struct nbu2ss_udc udc_controller; | |
74 | ||
75 | ||
76 | /*-------------------------------------------------------------------------*/ | |
77 | /* Read */ | |
78 | static inline u32 _nbu2ss_readl(void *address) | |
79 | { | |
ce1e3eb7 | 80 | return __raw_readl(address); |
33aa8d45 MD |
81 | } |
82 | ||
83 | /*-------------------------------------------------------------------------*/ | |
84 | /* Write */ | |
85 | static inline void _nbu2ss_writel(void *address, u32 udata) | |
86 | { | |
ce1e3eb7 | 87 | __raw_writel(udata, address); |
33aa8d45 MD |
88 | } |
89 | ||
90 | /*-------------------------------------------------------------------------*/ | |
91 | /* Set Bit */ | |
92 | static inline void _nbu2ss_bitset(void *address, u32 udata) | |
93 | { | |
94 | u32 reg_dt = __raw_readl(address) | (udata); | |
7f39ae05 | 95 | |
ce1e3eb7 | 96 | __raw_writel(reg_dt, address); |
33aa8d45 MD |
97 | } |
98 | ||
99 | /*-------------------------------------------------------------------------*/ | |
100 | /* Clear Bit */ | |
101 | static inline void _nbu2ss_bitclr(void *address, u32 udata) | |
102 | { | |
103 | u32 reg_dt = __raw_readl(address) & ~(udata); | |
7f39ae05 | 104 | |
ce1e3eb7 | 105 | __raw_writel(reg_dt, address); |
33aa8d45 MD |
106 | } |
107 | ||
108 | #ifdef UDC_DEBUG_DUMP | |
109 | /*-------------------------------------------------------------------------*/ | |
110 | static void _nbu2ss_dump_register(struct nbu2ss_udc *udc) | |
111 | { | |
112 | int i; | |
113 | u32 reg_data; | |
114 | ||
115 | pr_info("=== %s()\n", __func__); | |
116 | ||
117 | if (udc == NULL) { | |
118 | ERR("%s udc == NULL\n", __func__); | |
119 | return; | |
120 | } | |
121 | ||
122 | spin_unlock(&udc->lock); | |
123 | ||
124 | printk(KERN_DEBUG "\n-USB REG-\n"); | |
125 | for (i = 0x0 ; i < USB_BASE_SIZE ; i += 16) { | |
126 | reg_data = _nbu2ss_readl( | |
127 | (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i)); | |
128 | printk(KERN_DEBUG "USB%04x =%08x", i, (int)reg_data); | |
129 | ||
130 | reg_data = _nbu2ss_readl( | |
131 | (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 4)); | |
132 | printk(KERN_DEBUG " %08x", (int)reg_data); | |
133 | ||
134 | reg_data = _nbu2ss_readl( | |
135 | (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 8)); | |
136 | printk(KERN_DEBUG " %08x", (int)reg_data); | |
137 | ||
138 | reg_data = _nbu2ss_readl( | |
139 | (u32 *)IO_ADDRESS(USB_BASE_ADDRESS + i + 12)); | |
140 | printk(KERN_DEBUG " %08x\n", (int)reg_data); | |
141 | ||
142 | } | |
143 | ||
144 | spin_lock(&udc->lock); | |
145 | } | |
146 | #endif /* UDC_DEBUG_DUMP */ | |
147 | ||
148 | /*-------------------------------------------------------------------------*/ | |
149 | /* Endpoint 0 Callback (Complete) */ | |
150 | static void _nbu2ss_ep0_complete(struct usb_ep *_ep, struct usb_request *_req) | |
151 | { | |
152 | u8 recipient; | |
153 | u16 selector; | |
154 | u32 test_mode; | |
155 | struct usb_ctrlrequest *p_ctrl; | |
156 | struct nbu2ss_udc *udc; | |
157 | ||
158 | if ((_ep == NULL) || (_req == NULL)) | |
159 | return; | |
160 | ||
161 | udc = (struct nbu2ss_udc *)_req->context; | |
162 | p_ctrl = &udc->ctrl; | |
163 | if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
164 | ||
165 | if (p_ctrl->bRequest == USB_REQ_SET_FEATURE) { | |
166 | /*-------------------------------------------------*/ | |
167 | /* SET_FEATURE */ | |
168 | recipient = (u8)(p_ctrl->bRequestType & USB_RECIP_MASK); | |
169 | selector = p_ctrl->wValue; | |
170 | if ((recipient == USB_RECIP_DEVICE) && | |
171 | (selector == USB_DEVICE_TEST_MODE)) { | |
172 | test_mode = (u32)(p_ctrl->wIndex >> 8); | |
173 | _nbu2ss_set_test_mode(udc, test_mode); | |
174 | } | |
175 | } | |
176 | } | |
177 | } | |
178 | ||
179 | /*-------------------------------------------------------------------------*/ | |
180 | /* Initialization usb_request */ | |
181 | static void _nbu2ss_create_ep0_packet( | |
182 | struct nbu2ss_udc *udc, | |
183 | void *p_buf, | |
184 | unsigned length | |
185 | ) | |
186 | { | |
187 | udc->ep0_req.req.buf = p_buf; | |
188 | udc->ep0_req.req.length = length; | |
189 | udc->ep0_req.req.dma = 0; | |
190 | udc->ep0_req.req.zero = TRUE; | |
191 | udc->ep0_req.req.complete = _nbu2ss_ep0_complete; | |
192 | udc->ep0_req.req.status = -EINPROGRESS; | |
193 | udc->ep0_req.req.context = udc; | |
194 | udc->ep0_req.req.actual = 0; | |
195 | } | |
196 | ||
197 | /*-------------------------------------------------------------------------*/ | |
198 | /* Acquisition of the first address of RAM(FIFO) */ | |
199 | static u32 _nbu2ss_get_begin_ram_address(struct nbu2ss_udc *udc) | |
200 | { | |
201 | u32 num, buf_type; | |
202 | u32 data, last_ram_adr, use_ram_size; | |
203 | ||
204 | PT_EP_REGS p_ep_regs; | |
205 | ||
206 | last_ram_adr = (D_RAM_SIZE_CTRL / sizeof(u32)) * 2; | |
207 | use_ram_size = 0; | |
208 | ||
209 | for (num = 0; num < NUM_ENDPOINTS - 1; num++) { | |
210 | p_ep_regs = &udc->p_regs->EP_REGS[num]; | |
211 | data = _nbu2ss_readl(&p_ep_regs->EP_PCKT_ADRS); | |
212 | buf_type = _nbu2ss_readl(&p_ep_regs->EP_CONTROL) & EPn_BUF_TYPE; | |
213 | if (buf_type == 0) { | |
214 | /* Single Buffer */ | |
215 | use_ram_size += (data & EPn_MPKT) / sizeof(u32); | |
216 | } else { | |
217 | /* Double Buffer */ | |
218 | use_ram_size += ((data & EPn_MPKT) / sizeof(u32)) * 2; | |
219 | } | |
220 | ||
221 | if ((data >> 16) > last_ram_adr) | |
222 | last_ram_adr = data>>16; | |
223 | } | |
224 | ||
225 | return last_ram_adr + use_ram_size; | |
226 | } | |
227 | ||
228 | /*-------------------------------------------------------------------------*/ | |
229 | /* Construction of Endpoint */ | |
230 | static int _nbu2ss_ep_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) | |
231 | { | |
232 | u32 num; | |
233 | u32 data; | |
234 | u32 begin_adrs; | |
235 | ||
236 | if (ep->epnum == 0) | |
237 | return -EINVAL; | |
238 | ||
239 | num = ep->epnum - 1; | |
240 | ||
241 | /*-------------------------------------------------------------*/ | |
242 | /* RAM Transfer Address */ | |
243 | begin_adrs = _nbu2ss_get_begin_ram_address(udc); | |
244 | data = (begin_adrs << 16) | ep->ep.maxpacket; | |
245 | _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, data); | |
246 | ||
247 | /*-------------------------------------------------------------*/ | |
248 | /* Interrupt Enable */ | |
249 | data = 1 << (ep->epnum + 8); | |
250 | _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, data); | |
251 | ||
252 | /*-------------------------------------------------------------*/ | |
253 | /* Endpoint Type(Mode) */ | |
254 | /* Bulk, Interrupt, ISO */ | |
255 | switch (ep->ep_type) { | |
256 | case USB_ENDPOINT_XFER_BULK: | |
257 | data = EPn_BULK; | |
258 | break; | |
259 | ||
260 | case USB_ENDPOINT_XFER_INT: | |
261 | data = EPn_BUF_SINGLE | EPn_INTERRUPT; | |
262 | break; | |
263 | ||
264 | case USB_ENDPOINT_XFER_ISOC: | |
265 | data = EPn_ISO; | |
266 | break; | |
267 | ||
268 | default: | |
269 | data = 0; | |
270 | break; | |
271 | } | |
272 | ||
273 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
274 | _nbu2ss_endpoint_toggle_reset(udc, (ep->epnum|ep->direct)); | |
275 | ||
276 | if (ep->direct == USB_DIR_OUT) { | |
277 | /*---------------------------------------------------------*/ | |
278 | /* OUT */ | |
279 | data = EPn_EN | EPn_BCLR | EPn_DIR0; | |
280 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
281 | ||
282 | data = (EPn_ONAK | EPn_OSTL_EN | EPn_OSTL); | |
283 | _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
284 | ||
285 | data = (EPn_OUT_EN | EPn_OUT_END_EN); | |
286 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); | |
287 | } else { | |
288 | /*---------------------------------------------------------*/ | |
289 | /* IN */ | |
290 | data = (EPn_EN | EPn_BCLR | EPn_AUTO); | |
291 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
292 | ||
293 | data = (EPn_ISTL); | |
294 | _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
295 | ||
296 | data = (EPn_IN_EN | EPn_IN_END_EN); | |
297 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); | |
298 | } | |
299 | ||
300 | return 0; | |
301 | } | |
302 | ||
303 | /*-------------------------------------------------------------------------*/ | |
304 | /* Release of Endpoint */ | |
305 | static int _nbu2ss_epn_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) | |
306 | { | |
307 | u32 num; | |
308 | u32 data; | |
309 | ||
310 | if ((ep->epnum == 0) || (udc->vbus_active == 0)) | |
311 | return -EINVAL; | |
312 | ||
313 | num = ep->epnum - 1; | |
314 | ||
315 | /*-------------------------------------------------------------*/ | |
316 | /* RAM Transfer Address */ | |
317 | _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_PCKT_ADRS, 0); | |
318 | ||
319 | /*-------------------------------------------------------------*/ | |
320 | /* Interrupt Disable */ | |
321 | data = 1 << (ep->epnum + 8); | |
322 | _nbu2ss_bitclr(&udc->p_regs->USB_INT_ENA, data); | |
323 | ||
324 | if (ep->direct == USB_DIR_OUT) { | |
325 | /*---------------------------------------------------------*/ | |
326 | /* OUT */ | |
327 | data = EPn_ONAK | EPn_BCLR; | |
328 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
329 | ||
330 | data = EPn_EN | EPn_DIR0; | |
331 | _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
332 | ||
333 | data = EPn_OUT_EN | EPn_OUT_END_EN; | |
334 | _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); | |
335 | } else { | |
336 | /*---------------------------------------------------------*/ | |
337 | /* IN */ | |
338 | data = EPn_BCLR; | |
339 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
340 | ||
341 | data = EPn_EN | EPn_AUTO; | |
342 | _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
343 | ||
344 | data = EPn_IN_EN | EPn_IN_END_EN; | |
345 | _nbu2ss_bitclr(&udc->p_regs->EP_REGS[num].EP_INT_ENA, data); | |
346 | } | |
347 | ||
348 | return 0; | |
349 | } | |
350 | ||
351 | /*-------------------------------------------------------------------------*/ | |
352 | /* DMA setting (without Endpoint 0) */ | |
353 | static void _nbu2ss_ep_dma_init(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) | |
354 | { | |
355 | u32 num; | |
356 | u32 data; | |
357 | ||
358 | data = _nbu2ss_readl(&udc->p_regs->USBSSCONF); | |
359 | if (((ep->epnum == 0) || (data & (1 << ep->epnum)) == 0)) | |
360 | return; /* Not Support DMA */ | |
361 | ||
362 | num = ep->epnum - 1; | |
363 | ||
364 | if (ep->direct == USB_DIR_OUT) { | |
365 | /*---------------------------------------------------------*/ | |
366 | /* OUT */ | |
367 | data = ep->ep.maxpacket; | |
368 | _nbu2ss_writel(&udc->p_regs->EP_DCR[num].EP_DCR2, data); | |
369 | ||
370 | /*---------------------------------------------------------*/ | |
371 | /* Transfer Direct */ | |
372 | data = DCR1_EPn_DIR0; | |
373 | _nbu2ss_bitset(&udc->p_regs->EP_DCR[num].EP_DCR1, data); | |
374 | ||
375 | /*---------------------------------------------------------*/ | |
376 | /* DMA Mode etc. */ | |
377 | data = EPn_STOP_MODE | EPn_STOP_SET | EPn_DMAMODE0; | |
378 | _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); | |
379 | } else { | |
380 | /*---------------------------------------------------------*/ | |
381 | /* IN */ | |
382 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, EPn_AUTO); | |
383 | ||
384 | /*---------------------------------------------------------*/ | |
385 | /* DMA Mode etc. */ | |
386 | data = EPn_BURST_SET | EPn_DMAMODE0; | |
387 | _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_DMA_CTRL, data); | |
388 | } | |
389 | } | |
390 | ||
391 | /*-------------------------------------------------------------------------*/ | |
392 | /* DMA setting release */ | |
393 | static void _nbu2ss_ep_dma_exit(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) | |
394 | { | |
395 | u32 num; | |
396 | u32 data; | |
397 | PT_FC_REGS preg = udc->p_regs; | |
398 | ||
399 | if (udc->vbus_active == 0) | |
400 | return; /* VBUS OFF */ | |
401 | ||
402 | data = _nbu2ss_readl(&preg->USBSSCONF); | |
403 | if ((ep->epnum == 0) || ((data & (1 << ep->epnum)) == 0)) | |
404 | return; /* Not Support DMA */ | |
405 | ||
406 | num = ep->epnum - 1; | |
407 | ||
408 | _nbu2ss_ep_dma_abort(udc, ep); | |
409 | ||
410 | if (ep->direct == USB_DIR_OUT) { | |
411 | /*---------------------------------------------------------*/ | |
412 | /* OUT */ | |
413 | _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, 0); | |
414 | _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_DIR0); | |
415 | _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); | |
416 | } else { | |
417 | /*---------------------------------------------------------*/ | |
418 | /* IN */ | |
419 | _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO); | |
420 | _nbu2ss_writel(&preg->EP_REGS[num].EP_DMA_CTRL, 0); | |
421 | } | |
422 | } | |
423 | ||
424 | /*-------------------------------------------------------------------------*/ | |
425 | /* Abort DMA */ | |
426 | static void _nbu2ss_ep_dma_abort(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) | |
427 | { | |
428 | PT_FC_REGS preg = udc->p_regs; | |
429 | ||
430 | _nbu2ss_bitclr(&preg->EP_DCR[ep->epnum-1].EP_DCR1, DCR1_EPn_REQEN); | |
431 | mdelay(DMA_DISABLE_TIME); /* DCR1_EPn_REQEN Clear */ | |
432 | _nbu2ss_bitclr(&preg->EP_REGS[ep->epnum-1].EP_DMA_CTRL, EPn_DMA_EN); | |
433 | } | |
434 | ||
435 | /*-------------------------------------------------------------------------*/ | |
436 | /* Start IN Transfer */ | |
437 | static void _nbu2ss_ep_in_end( | |
438 | struct nbu2ss_udc *udc, | |
439 | u32 epnum, | |
440 | u32 data32, | |
441 | u32 length | |
442 | ) | |
443 | { | |
444 | u32 data; | |
445 | u32 num; | |
446 | PT_FC_REGS preg = udc->p_regs; | |
447 | ||
448 | if (length >= sizeof(u32)) | |
449 | return; | |
450 | ||
451 | if (epnum == 0) { | |
452 | _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_AUTO); | |
453 | ||
454 | /* Writing of 1-4 bytes */ | |
455 | if (length) | |
456 | _nbu2ss_writel(&preg->EP0_WRITE, data32); | |
457 | ||
458 | data = ((length << 5) & EP0_DW) | EP0_DEND; | |
459 | _nbu2ss_writel(&preg->EP0_CONTROL, data); | |
460 | ||
461 | _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_AUTO); | |
462 | } else { | |
463 | num = epnum - 1; | |
464 | ||
465 | _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO); | |
466 | ||
467 | /* Writing of 1-4 bytes */ | |
468 | if (length) | |
469 | _nbu2ss_writel(&preg->EP_REGS[num].EP_WRITE, data32); | |
470 | ||
471 | data = (((((u32)length) << 5) & EPn_DW) | EPn_DEND); | |
472 | _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); | |
473 | ||
474 | _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, EPn_AUTO); | |
475 | } | |
33aa8d45 MD |
476 | } |
477 | ||
478 | #ifdef USE_DMA | |
479 | /*-------------------------------------------------------------------------*/ | |
480 | static void _nbu2ss_dma_map_single( | |
481 | struct nbu2ss_udc *udc, | |
482 | struct nbu2ss_ep *ep, | |
483 | struct nbu2ss_req *req, | |
484 | u8 direct | |
485 | ) | |
486 | { | |
487 | if (req->req.dma == DMA_ADDR_INVALID) { | |
488 | if (req->unaligned) | |
489 | req->req.dma = ep->phys_buf; | |
490 | else { | |
491 | req->req.dma = dma_map_single( | |
492 | udc->gadget.dev.parent, | |
493 | req->req.buf, | |
494 | req->req.length, | |
495 | (direct == USB_DIR_IN) | |
496 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
497 | } | |
498 | req->mapped = 1; | |
499 | } else { | |
500 | if (!req->unaligned) | |
501 | dma_sync_single_for_device( | |
502 | udc->gadget.dev.parent, | |
503 | req->req.dma, | |
504 | req->req.length, | |
505 | (direct == USB_DIR_IN) | |
506 | ? DMA_TO_DEVICE : DMA_FROM_DEVICE); | |
507 | ||
508 | req->mapped = 0; | |
509 | } | |
510 | } | |
511 | ||
512 | /*-------------------------------------------------------------------------*/ | |
513 | static void _nbu2ss_dma_unmap_single( | |
514 | struct nbu2ss_udc *udc, | |
515 | struct nbu2ss_ep *ep, | |
516 | struct nbu2ss_req *req, | |
517 | u8 direct | |
518 | ) | |
519 | { | |
520 | u8 data[4]; | |
521 | u8 *p; | |
522 | u32 count = 0; | |
523 | ||
524 | if (direct == USB_DIR_OUT) { | |
525 | count = req->req.actual % 4; | |
526 | if (count) { | |
527 | p = req->req.buf; | |
528 | p += (req->req.actual - count); | |
529 | memcpy(data, p, count); | |
530 | } | |
531 | } | |
532 | ||
533 | if (req->mapped) { | |
534 | if (req->unaligned) { | |
535 | if (direct == USB_DIR_OUT) | |
536 | memcpy(req->req.buf, ep->virt_buf, | |
537 | req->req.actual & 0xfffffffc); | |
538 | } else | |
539 | dma_unmap_single(udc->gadget.dev.parent, | |
540 | req->req.dma, req->req.length, | |
541 | (direct == USB_DIR_IN) | |
542 | ? DMA_TO_DEVICE | |
543 | : DMA_FROM_DEVICE); | |
544 | req->req.dma = DMA_ADDR_INVALID; | |
545 | req->mapped = 0; | |
546 | } else { | |
547 | if (!req->unaligned) | |
548 | dma_sync_single_for_cpu(udc->gadget.dev.parent, | |
549 | req->req.dma, req->req.length, | |
550 | (direct == USB_DIR_IN) | |
551 | ? DMA_TO_DEVICE | |
552 | : DMA_FROM_DEVICE); | |
553 | } | |
554 | ||
555 | if (count) { | |
556 | p = req->req.buf; | |
557 | p += (req->req.actual - count); | |
558 | memcpy(p, data, count); | |
559 | } | |
560 | } | |
561 | #endif | |
562 | ||
563 | /*-------------------------------------------------------------------------*/ | |
564 | /* Endpoint 0 OUT Transfer (PIO) */ | |
a2c14e97 | 565 | static int EP0_out_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length) |
33aa8d45 MD |
566 | { |
567 | u32 i; | |
568 | int nret = 0; | |
569 | u32 iWordLength = 0; | |
a2c14e97 | 570 | USB_REG_ACCESS *pBuf32 = (USB_REG_ACCESS *)pBuf; |
33aa8d45 MD |
571 | |
572 | /*------------------------------------------------------------*/ | |
573 | /* Read Length */ | |
574 | iWordLength = length / sizeof(u32); | |
575 | ||
576 | /*------------------------------------------------------------*/ | |
577 | /* PIO Read */ | |
578 | if (iWordLength) { | |
579 | for (i = 0; i < iWordLength; i++) { | |
580 | pBuf32->dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); | |
581 | pBuf32++; | |
582 | } | |
583 | nret = iWordLength * sizeof(u32); | |
584 | } | |
585 | ||
586 | return nret; | |
587 | } | |
588 | ||
589 | /*-------------------------------------------------------------------------*/ | |
590 | /* Endpoint 0 OUT Transfer (PIO, OverBytes) */ | |
a2c14e97 | 591 | static int EP0_out_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 length) |
33aa8d45 MD |
592 | { |
593 | u32 i; | |
594 | u32 iReadSize = 0; | |
595 | USB_REG_ACCESS Temp32; | |
a2c14e97 | 596 | USB_REG_ACCESS *pBuf32 = (USB_REG_ACCESS *)pBuf; |
33aa8d45 MD |
597 | |
598 | if ((0 < length) && (length < sizeof(u32))) { | |
599 | Temp32.dw = _nbu2ss_readl(&udc->p_regs->EP0_READ); | |
600 | for (i = 0 ; i < length ; i++) | |
601 | pBuf32->byte.DATA[i] = Temp32.byte.DATA[i]; | |
602 | iReadSize += length; | |
603 | } | |
604 | ||
605 | return iReadSize; | |
606 | } | |
607 | ||
608 | /*-------------------------------------------------------------------------*/ | |
609 | /* Endpoint 0 IN Transfer (PIO) */ | |
610 | static int EP0_in_PIO(struct nbu2ss_udc *udc, u8 *pBuf, u32 length) | |
611 | { | |
612 | u32 i; | |
613 | u32 iMaxLength = EP0_PACKETSIZE; | |
614 | u32 iWordLength = 0; | |
615 | u32 iWriteLength = 0; | |
a2c14e97 | 616 | USB_REG_ACCESS *pBuf32 = (USB_REG_ACCESS *)pBuf; |
33aa8d45 MD |
617 | |
618 | /*------------------------------------------------------------*/ | |
619 | /* Transfer Length */ | |
620 | if (iMaxLength < length) | |
621 | iWordLength = iMaxLength / sizeof(u32); | |
622 | else | |
623 | iWordLength = length / sizeof(u32); | |
624 | ||
625 | /*------------------------------------------------------------*/ | |
626 | /* PIO */ | |
627 | for (i = 0; i < iWordLength; i++) { | |
628 | _nbu2ss_writel(&udc->p_regs->EP0_WRITE, pBuf32->dw); | |
629 | pBuf32++; | |
630 | iWriteLength += sizeof(u32); | |
631 | } | |
632 | ||
633 | return iWriteLength; | |
634 | } | |
635 | ||
636 | /*-------------------------------------------------------------------------*/ | |
637 | /* Endpoint 0 IN Transfer (PIO, OverBytes) */ | |
638 | static int EP0_in_OverBytes(struct nbu2ss_udc *udc, u8 *pBuf, u32 iRemainSize) | |
639 | { | |
640 | u32 i; | |
641 | USB_REG_ACCESS Temp32; | |
a2c14e97 | 642 | USB_REG_ACCESS *pBuf32 = (USB_REG_ACCESS *)pBuf; |
33aa8d45 MD |
643 | |
644 | if ((0 < iRemainSize) && (iRemainSize < sizeof(u32))) { | |
645 | for (i = 0 ; i < iRemainSize ; i++) | |
646 | Temp32.byte.DATA[i] = pBuf32->byte.DATA[i]; | |
647 | _nbu2ss_ep_in_end(udc, 0, Temp32.dw, iRemainSize); | |
648 | ||
649 | return iRemainSize; | |
650 | } | |
651 | ||
652 | return 0; | |
653 | } | |
654 | ||
655 | /*-------------------------------------------------------------------------*/ | |
656 | /* Transfer NULL Packet (Epndoint 0) */ | |
657 | static int EP0_send_NULL(struct nbu2ss_udc *udc, bool pid_flag) | |
658 | { | |
659 | u32 data; | |
660 | ||
661 | data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); | |
662 | data &= ~(u32)EP0_INAK; | |
663 | ||
664 | if (pid_flag) | |
665 | data |= (EP0_INAK_EN | EP0_PIDCLR | EP0_DEND); | |
666 | else | |
667 | data |= (EP0_INAK_EN | EP0_DEND); | |
668 | ||
669 | _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); | |
670 | ||
671 | return 0; | |
672 | } | |
673 | ||
674 | /*-------------------------------------------------------------------------*/ | |
675 | /* Receive NULL Packet (Endpoint 0) */ | |
676 | static int EP0_receive_NULL(struct nbu2ss_udc *udc, bool pid_flag) | |
677 | { | |
678 | u32 data; | |
679 | ||
680 | data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); | |
681 | data &= ~(u32)EP0_ONAK; | |
682 | ||
683 | if (pid_flag) | |
684 | data |= EP0_PIDCLR; | |
685 | ||
686 | _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); | |
687 | ||
688 | return 0; | |
689 | } | |
690 | ||
691 | /*-------------------------------------------------------------------------*/ | |
692 | static int _nbu2ss_ep0_in_transfer( | |
693 | struct nbu2ss_udc *udc, | |
694 | struct nbu2ss_ep *ep, | |
695 | struct nbu2ss_req *req | |
696 | ) | |
697 | { | |
698 | u8 *pBuffer; /* IN Data Buffer */ | |
699 | u32 data; | |
700 | u32 iRemainSize = 0; | |
701 | int result = 0; | |
702 | ||
703 | /*-------------------------------------------------------------*/ | |
704 | /* End confirmation */ | |
705 | if (req->req.actual == req->req.length) { | |
706 | if ((req->req.actual % EP0_PACKETSIZE) == 0) { | |
707 | if (req->zero) { | |
708 | req->zero = 0; | |
709 | EP0_send_NULL(udc, FALSE); | |
710 | return 1; | |
711 | } | |
712 | } | |
713 | ||
714 | return 0; /* Transfer End */ | |
715 | } | |
716 | ||
717 | /*-------------------------------------------------------------*/ | |
718 | /* NAK release */ | |
719 | data = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); | |
720 | data |= EP0_INAK_EN; | |
721 | data &= ~(u32)EP0_INAK; | |
722 | _nbu2ss_writel(&udc->p_regs->EP0_CONTROL, data); | |
723 | ||
724 | iRemainSize = req->req.length - req->req.actual; | |
725 | pBuffer = (u8 *)req->req.buf; | |
726 | pBuffer += req->req.actual; | |
727 | ||
728 | /*-------------------------------------------------------------*/ | |
729 | /* Data transfer */ | |
730 | result = EP0_in_PIO(udc, pBuffer, iRemainSize); | |
731 | ||
732 | req->div_len = result; | |
733 | iRemainSize -= result; | |
734 | ||
735 | if (iRemainSize == 0) { | |
736 | EP0_send_NULL(udc, FALSE); | |
737 | return result; | |
738 | } | |
739 | ||
740 | if ((iRemainSize < sizeof(u32)) && (result != EP0_PACKETSIZE)) { | |
741 | pBuffer += result; | |
742 | result += EP0_in_OverBytes(udc, pBuffer, iRemainSize); | |
743 | req->div_len = result; | |
744 | } | |
745 | ||
746 | return result; | |
747 | } | |
748 | ||
749 | /*-------------------------------------------------------------------------*/ | |
750 | static int _nbu2ss_ep0_out_transfer( | |
751 | struct nbu2ss_udc *udc, | |
752 | struct nbu2ss_ep *ep, | |
753 | struct nbu2ss_req *req | |
754 | ) | |
755 | { | |
756 | u8 *pBuffer; | |
757 | u32 iRemainSize; | |
758 | u32 iRecvLength; | |
759 | int result = 0; | |
760 | int fRcvZero; | |
761 | ||
762 | /*-------------------------------------------------------------*/ | |
763 | /* Receive data confirmation */ | |
764 | iRecvLength = _nbu2ss_readl(&udc->p_regs->EP0_LENGTH) & EP0_LDATA; | |
765 | if (iRecvLength != 0) { | |
766 | ||
767 | fRcvZero = 0; | |
768 | ||
769 | iRemainSize = req->req.length - req->req.actual; | |
770 | pBuffer = (u8 *)req->req.buf; | |
771 | pBuffer += req->req.actual; | |
772 | ||
773 | result = EP0_out_PIO(udc, pBuffer | |
774 | , min(iRemainSize, iRecvLength)); | |
775 | if (result < 0) | |
776 | return result; | |
777 | ||
778 | req->req.actual += result; | |
779 | iRecvLength -= result; | |
780 | ||
781 | if ((0 < iRecvLength) && (iRecvLength < sizeof(u32))) { | |
782 | pBuffer += result; | |
783 | iRemainSize -= result; | |
784 | ||
785 | result = EP0_out_OverBytes(udc, pBuffer | |
786 | , min(iRemainSize, iRecvLength)); | |
787 | req->req.actual += result; | |
788 | } | |
789 | } else { | |
790 | fRcvZero = 1; | |
791 | } | |
792 | ||
793 | /*-------------------------------------------------------------*/ | |
794 | /* End confirmation */ | |
795 | if (req->req.actual == req->req.length) { | |
796 | if ((req->req.actual % EP0_PACKETSIZE) == 0) { | |
797 | if (req->zero) { | |
798 | req->zero = 0; | |
799 | EP0_receive_NULL(udc, FALSE); | |
800 | return 1; | |
801 | } | |
802 | } | |
803 | ||
804 | return 0; /* Transfer End */ | |
805 | } | |
806 | ||
807 | if ((req->req.actual % EP0_PACKETSIZE) != 0) | |
808 | return 0; /* Short Packet Transfer End */ | |
809 | ||
810 | if (req->req.actual > req->req.length) { | |
811 | ERR(" *** Overrun Error\n"); | |
812 | return -EOVERFLOW; | |
813 | } | |
814 | ||
815 | if (fRcvZero != 0) { | |
816 | iRemainSize = _nbu2ss_readl(&udc->p_regs->EP0_CONTROL); | |
817 | if (iRemainSize & EP0_ONAK) { | |
818 | /*---------------------------------------------------*/ | |
819 | /* NACK release */ | |
820 | _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_ONAK); | |
821 | } | |
822 | result = 1; | |
823 | } | |
824 | ||
825 | return result; | |
826 | } | |
827 | ||
828 | /*-------------------------------------------------------------------------*/ | |
829 | static int _nbu2ss_out_dma( | |
830 | struct nbu2ss_udc *udc, | |
831 | struct nbu2ss_req *req, | |
832 | u32 num, | |
833 | u32 length | |
834 | ) | |
835 | { | |
836 | u8 *pBuffer; | |
837 | u32 mpkt; | |
838 | u32 lmpkt; | |
839 | u32 dmacnt; | |
840 | u32 burst = 1; | |
841 | u32 data; | |
842 | int result = -EINVAL; | |
843 | PT_FC_REGS preg = udc->p_regs; | |
844 | ||
845 | if (req->dma_flag) | |
846 | return 1; /* DMA is forwarded */ | |
847 | ||
848 | req->dma_flag = TRUE; | |
849 | pBuffer = (u8 *)req->req.dma; | |
850 | pBuffer += req->req.actual; | |
851 | ||
852 | /* DMA Address */ | |
853 | _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer); | |
854 | ||
855 | /* Number of transfer packets */ | |
856 | mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT; | |
857 | dmacnt = (length / mpkt); | |
858 | lmpkt = (length % mpkt) & ~(u32)0x03; | |
859 | ||
860 | if (DMA_MAX_COUNT < dmacnt) { | |
861 | dmacnt = DMA_MAX_COUNT; | |
862 | lmpkt = 0; | |
863 | } else if (0 != lmpkt) { | |
864 | if (0 == dmacnt) | |
865 | burst = 0; /* Burst OFF */ | |
866 | dmacnt++; | |
867 | } | |
868 | ||
869 | data = mpkt | (lmpkt << 16); | |
870 | _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); | |
871 | ||
872 | data = ((dmacnt & 0xff) << 16) | DCR1_EPn_DIR0 | DCR1_EPn_REQEN; | |
873 | _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); | |
874 | ||
875 | if (0 == burst) { | |
876 | _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, 0); | |
877 | _nbu2ss_bitclr(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET); | |
878 | } else { | |
879 | _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT | |
880 | , (dmacnt << 16)); | |
881 | _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_BURST_SET); | |
882 | } | |
883 | _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN); | |
884 | ||
885 | result = length & ~(u32)0x03; | |
886 | req->div_len = result; | |
887 | ||
888 | return result; | |
889 | } | |
890 | ||
891 | /*-------------------------------------------------------------------------*/ | |
892 | static int _nbu2ss_epn_out_pio( | |
893 | struct nbu2ss_udc *udc, | |
894 | struct nbu2ss_ep *ep, | |
895 | struct nbu2ss_req *req, | |
896 | u32 length | |
897 | ) | |
898 | { | |
899 | u8 *pBuffer; | |
900 | u32 i; | |
901 | u32 data; | |
902 | u32 iWordLength; | |
903 | USB_REG_ACCESS Temp32; | |
904 | USB_REG_ACCESS *pBuf32; | |
905 | int result = 0; | |
906 | PT_FC_REGS preg = udc->p_regs; | |
907 | ||
908 | if (req->dma_flag) | |
909 | return 1; /* DMA is forwarded */ | |
910 | ||
911 | if (length == 0) | |
912 | return 0; | |
913 | ||
914 | pBuffer = (u8 *)req->req.buf; | |
915 | pBuf32 = (USB_REG_ACCESS *)(pBuffer + req->req.actual); | |
916 | ||
917 | iWordLength = length / sizeof(u32); | |
918 | if (iWordLength > 0) { | |
919 | /*---------------------------------------------------------*/ | |
920 | /* Copy of every four bytes */ | |
921 | for (i = 0; i < iWordLength; i++) { | |
922 | pBuf32->dw = | |
923 | _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_READ); | |
924 | pBuf32++; | |
925 | } | |
926 | result = iWordLength * sizeof(u32); | |
927 | } | |
928 | ||
929 | data = length - result; | |
930 | if (data > 0) { | |
931 | /*---------------------------------------------------------*/ | |
932 | /* Copy of fraction byte */ | |
933 | Temp32.dw = _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_READ); | |
934 | for (i = 0 ; i < data ; i++) | |
935 | pBuf32->byte.DATA[i] = Temp32.byte.DATA[i]; | |
936 | result += data; | |
937 | } | |
938 | ||
939 | req->req.actual += result; | |
940 | ||
941 | if ((req->req.actual == req->req.length) | |
942 | || ((req->req.actual % ep->ep.maxpacket) != 0)) { | |
943 | ||
944 | result = 0; | |
945 | } | |
946 | ||
947 | return result; | |
948 | } | |
949 | ||
950 | /*-------------------------------------------------------------------------*/ | |
951 | static int _nbu2ss_epn_out_data( | |
952 | struct nbu2ss_udc *udc, | |
953 | struct nbu2ss_ep *ep, | |
954 | struct nbu2ss_req *req, | |
955 | u32 data_size | |
956 | ) | |
957 | { | |
958 | u32 num; | |
959 | u32 iBufSize; | |
960 | int nret = 1; | |
961 | ||
962 | if (ep->epnum == 0) | |
963 | return -EINVAL; | |
964 | ||
965 | num = ep->epnum - 1; | |
966 | ||
967 | iBufSize = min((req->req.length - req->req.actual), data_size); | |
968 | ||
969 | if ((ep->ep_type != USB_ENDPOINT_XFER_INT) | |
970 | && (req->req.dma != 0) | |
971 | && (iBufSize >= sizeof(u32))) { | |
972 | nret = _nbu2ss_out_dma(udc, req, num, iBufSize); | |
973 | } else { | |
974 | iBufSize = min(iBufSize, (u32)ep->ep.maxpacket); | |
975 | nret = _nbu2ss_epn_out_pio(udc, ep, req, iBufSize); | |
976 | } | |
977 | ||
978 | return nret; | |
979 | } | |
980 | ||
981 | /*-------------------------------------------------------------------------*/ | |
982 | static int _nbu2ss_epn_out_transfer( | |
983 | struct nbu2ss_udc *udc, | |
984 | struct nbu2ss_ep *ep, | |
985 | struct nbu2ss_req *req | |
986 | ) | |
987 | { | |
988 | u32 num; | |
989 | u32 iRecvLength; | |
990 | int result = 1; | |
991 | PT_FC_REGS preg = udc->p_regs; | |
992 | ||
993 | if (ep->epnum == 0) | |
994 | return -EINVAL; | |
995 | ||
996 | num = ep->epnum - 1; | |
997 | ||
998 | /*-------------------------------------------------------------*/ | |
999 | /* Receive Length */ | |
1000 | iRecvLength | |
1001 | = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) & EPn_LDATA; | |
1002 | ||
1003 | if (iRecvLength != 0) { | |
1004 | result = _nbu2ss_epn_out_data(udc, ep, req, iRecvLength); | |
1005 | if (iRecvLength < ep->ep.maxpacket) { | |
1006 | if (iRecvLength == result) { | |
1007 | req->req.actual += result; | |
1008 | result = 0; | |
1009 | } | |
1010 | } | |
1011 | } else { | |
1012 | if ((req->req.actual == req->req.length) | |
1013 | || ((req->req.actual % ep->ep.maxpacket) != 0)) { | |
1014 | ||
1015 | result = 0; | |
1016 | } | |
1017 | } | |
1018 | ||
1019 | if (result == 0) { | |
1020 | if ((req->req.actual % ep->ep.maxpacket) == 0) { | |
1021 | if (req->zero) { | |
1022 | req->zero = 0; | |
1023 | return 1; | |
1024 | } | |
1025 | } | |
1026 | } | |
1027 | ||
1028 | if (req->req.actual > req->req.length) { | |
1029 | ERR(" *** Overrun Error\n"); | |
1030 | ERR(" *** actual = %d, length = %d\n", | |
1031 | req->req.actual, req->req.length); | |
1032 | result = -EOVERFLOW; | |
1033 | } | |
1034 | ||
1035 | return result; | |
1036 | } | |
1037 | ||
1038 | /*-------------------------------------------------------------------------*/ | |
1039 | static int _nbu2ss_in_dma( | |
1040 | struct nbu2ss_udc *udc, | |
1041 | struct nbu2ss_ep *ep, | |
1042 | struct nbu2ss_req *req, | |
1043 | u32 num, | |
1044 | u32 length | |
1045 | ) | |
1046 | { | |
1047 | u8 *pBuffer; | |
1048 | u32 mpkt; /* MaxPacketSize */ | |
1049 | u32 lmpkt; /* Last Packet Data Size */ | |
1050 | u32 dmacnt; /* IN Data Size */ | |
1051 | u32 iWriteLength; | |
1052 | u32 data; | |
1053 | int result = -EINVAL; | |
1054 | PT_FC_REGS preg = udc->p_regs; | |
1055 | ||
1056 | if (req->dma_flag) | |
1057 | return 1; /* DMA is forwarded */ | |
1058 | ||
1059 | #ifdef USE_DMA | |
1060 | if (req->req.actual == 0) | |
1061 | _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_IN); | |
1062 | #endif | |
1063 | req->dma_flag = TRUE; | |
1064 | ||
1065 | /* MAX Packet Size */ | |
1066 | mpkt = _nbu2ss_readl(&preg->EP_REGS[num].EP_PCKT_ADRS) & EPn_MPKT; | |
1067 | ||
1068 | if ((DMA_MAX_COUNT * mpkt) < length) | |
1069 | iWriteLength = DMA_MAX_COUNT * mpkt; | |
1070 | else | |
1071 | iWriteLength = length; | |
1072 | ||
1073 | /*------------------------------------------------------------*/ | |
1074 | /* Number of transmission packets */ | |
1075 | if (mpkt < iWriteLength) { | |
1076 | dmacnt = iWriteLength / mpkt; | |
1077 | lmpkt = (iWriteLength % mpkt) & ~(u32)0x3; | |
1078 | if (lmpkt != 0) | |
1079 | dmacnt++; | |
1080 | else | |
1081 | lmpkt = mpkt & ~(u32)0x3; | |
1082 | ||
1083 | } else { | |
1084 | dmacnt = 1; | |
1085 | lmpkt = iWriteLength & ~(u32)0x3; | |
1086 | } | |
1087 | ||
1088 | /* Packet setting */ | |
1089 | data = mpkt | (lmpkt << 16); | |
1090 | _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR2, data); | |
1091 | ||
1092 | /* Address setting */ | |
1093 | pBuffer = (u8 *)req->req.dma; | |
1094 | pBuffer += req->req.actual; | |
1095 | _nbu2ss_writel(&preg->EP_DCR[num].EP_TADR, (u32)pBuffer); | |
1096 | ||
1097 | /* Packet and DMA setting */ | |
1098 | data = ((dmacnt & 0xff) << 16) | DCR1_EPn_REQEN; | |
1099 | _nbu2ss_writel(&preg->EP_DCR[num].EP_DCR1, data); | |
1100 | ||
1101 | /* Packet setting of EPC */ | |
1102 | data = dmacnt << 16; | |
1103 | _nbu2ss_writel(&preg->EP_REGS[num].EP_LEN_DCNT, data); | |
1104 | ||
1105 | /*DMA setting of EPC */ | |
1106 | _nbu2ss_bitset(&preg->EP_REGS[num].EP_DMA_CTRL, EPn_DMA_EN); | |
1107 | ||
1108 | result = iWriteLength & ~(u32)0x3; | |
1109 | req->div_len = result; | |
1110 | ||
1111 | return result; | |
1112 | } | |
1113 | ||
1114 | /*-------------------------------------------------------------------------*/ | |
1115 | static int _nbu2ss_epn_in_pio( | |
1116 | struct nbu2ss_udc *udc, | |
1117 | struct nbu2ss_ep *ep, | |
1118 | struct nbu2ss_req *req, | |
1119 | u32 length | |
1120 | ) | |
1121 | { | |
1122 | u8 *pBuffer; | |
1123 | u32 i; | |
1124 | u32 data; | |
1125 | u32 iWordLength; | |
1126 | USB_REG_ACCESS Temp32; | |
1127 | USB_REG_ACCESS *pBuf32 = NULL; | |
1128 | int result = 0; | |
1129 | PT_FC_REGS preg = udc->p_regs; | |
1130 | ||
1131 | if (req->dma_flag) | |
1132 | return 1; /* DMA is forwarded */ | |
1133 | ||
1134 | if (length > 0) { | |
1135 | pBuffer = (u8 *)req->req.buf; | |
1136 | pBuf32 = (USB_REG_ACCESS *)(pBuffer + req->req.actual); | |
1137 | ||
1138 | iWordLength = length / sizeof(u32); | |
1139 | if (iWordLength > 0) { | |
1140 | for (i = 0; i < iWordLength; i++) { | |
1141 | _nbu2ss_writel( | |
1142 | &preg->EP_REGS[ep->epnum-1].EP_WRITE | |
1143 | , pBuf32->dw | |
1144 | ); | |
1145 | ||
1146 | pBuf32++; | |
1147 | } | |
1148 | result = iWordLength * sizeof(u32); | |
1149 | } | |
1150 | } | |
1151 | ||
1152 | if (result != ep->ep.maxpacket) { | |
1153 | data = length - result; | |
1154 | Temp32.dw = 0; | |
1155 | for (i = 0 ; i < data ; i++) | |
1156 | Temp32.byte.DATA[i] = pBuf32->byte.DATA[i]; | |
1157 | ||
1158 | _nbu2ss_ep_in_end(udc, ep->epnum, Temp32.dw, data); | |
1159 | result += data; | |
1160 | } | |
1161 | ||
1162 | req->div_len = result; | |
1163 | ||
1164 | return result; | |
1165 | } | |
1166 | ||
1167 | /*-------------------------------------------------------------------------*/ | |
1168 | static int _nbu2ss_epn_in_data( | |
1169 | struct nbu2ss_udc *udc, | |
1170 | struct nbu2ss_ep *ep, | |
1171 | struct nbu2ss_req *req, | |
1172 | u32 data_size | |
1173 | ) | |
1174 | { | |
1175 | u32 num; | |
1176 | int nret = 1; | |
1177 | ||
1178 | if (ep->epnum == 0) | |
1179 | return -EINVAL; | |
1180 | ||
1181 | num = ep->epnum - 1; | |
1182 | ||
1183 | if ((ep->ep_type != USB_ENDPOINT_XFER_INT) | |
1184 | && (req->req.dma != 0) | |
1185 | && (data_size >= sizeof(u32))) { | |
1186 | nret = _nbu2ss_in_dma(udc, ep, req, num, data_size); | |
1187 | } else { | |
1188 | data_size = min(data_size, (u32)ep->ep.maxpacket); | |
1189 | nret = _nbu2ss_epn_in_pio(udc, ep, req, data_size); | |
1190 | } | |
1191 | ||
1192 | return nret; | |
1193 | } | |
1194 | ||
1195 | /*-------------------------------------------------------------------------*/ | |
1196 | static int _nbu2ss_epn_in_transfer( | |
1197 | struct nbu2ss_udc *udc, | |
1198 | struct nbu2ss_ep *ep, | |
1199 | struct nbu2ss_req *req | |
1200 | ) | |
1201 | { | |
1202 | u32 num; | |
1203 | u32 iBufSize; | |
1204 | int result = 0; | |
1205 | u32 status; | |
1206 | ||
1207 | if (ep->epnum == 0) | |
1208 | return -EINVAL; | |
1209 | ||
1210 | num = ep->epnum - 1; | |
1211 | ||
1212 | status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS); | |
1213 | ||
1214 | /*-------------------------------------------------------------*/ | |
1215 | /* State confirmation of FIFO */ | |
1216 | if (req->req.actual == 0) { | |
1217 | if ((status & EPn_IN_EMPTY) == 0) | |
1218 | return 1; /* Not Empty */ | |
1219 | ||
1220 | } else { | |
1221 | if ((status & EPn_IN_FULL) != 0) | |
1222 | return 1; /* Not Empty */ | |
1223 | } | |
1224 | ||
1225 | /*-------------------------------------------------------------*/ | |
1226 | /* Start tranfer */ | |
1227 | iBufSize = req->req.length - req->req.actual; | |
1228 | if (iBufSize > 0) | |
1229 | result = _nbu2ss_epn_in_data(udc, ep, req, iBufSize); | |
1230 | else if (req->req.length == 0) | |
1231 | _nbu2ss_zero_len_pkt(udc, ep->epnum); | |
1232 | ||
1233 | return result; | |
1234 | } | |
1235 | ||
1236 | /*-------------------------------------------------------------------------*/ | |
1237 | static int _nbu2ss_start_transfer( | |
1238 | struct nbu2ss_udc *udc, | |
1239 | struct nbu2ss_ep *ep, | |
1240 | struct nbu2ss_req *req, | |
1241 | bool bflag) | |
1242 | { | |
1243 | int nret = -EINVAL; | |
1244 | ||
1245 | req->dma_flag = FALSE; | |
1246 | req->div_len = 0; | |
1247 | ||
1248 | if (req->req.length == 0) | |
1249 | req->zero = 0; | |
1250 | else { | |
1251 | if ((req->req.length % ep->ep.maxpacket) == 0) | |
1252 | req->zero = req->req.zero; | |
1253 | else | |
1254 | req->zero = 0; | |
1255 | } | |
1256 | ||
1257 | if (ep->epnum == 0) { | |
1258 | /* EP0 */ | |
1259 | switch (udc->ep0state) { | |
1260 | case EP0_IN_DATA_PHASE: | |
1261 | nret = _nbu2ss_ep0_in_transfer(udc, ep, req); | |
1262 | break; | |
1263 | ||
1264 | case EP0_OUT_DATA_PHASE: | |
1265 | nret = _nbu2ss_ep0_out_transfer(udc, ep, req); | |
1266 | break; | |
1267 | ||
1268 | case EP0_IN_STATUS_PHASE: | |
1269 | nret = EP0_send_NULL(udc, TRUE); | |
1270 | break; | |
1271 | ||
1272 | default: | |
1273 | break; | |
1274 | } | |
1275 | ||
1276 | } else { | |
1277 | /* EPn */ | |
1278 | if (ep->direct == USB_DIR_OUT) { | |
1279 | /* OUT */ | |
1280 | if (bflag == FALSE) | |
1281 | nret = _nbu2ss_epn_out_transfer(udc, ep, req); | |
1282 | } else { | |
1283 | /* IN */ | |
1284 | nret = _nbu2ss_epn_in_transfer(udc, ep, req); | |
1285 | } | |
1286 | } | |
1287 | ||
1288 | return nret; | |
1289 | } | |
1290 | ||
1291 | /*-------------------------------------------------------------------------*/ | |
1292 | static void _nbu2ss_restert_transfer(struct nbu2ss_ep *ep) | |
1293 | { | |
1294 | u32 length; | |
1295 | bool bflag = FALSE; | |
1296 | struct nbu2ss_req *req; | |
1297 | ||
1298 | if (list_empty(&ep->queue)) | |
1299 | req = NULL; | |
1300 | else | |
1301 | req = list_entry(ep->queue.next, struct nbu2ss_req, queue); | |
1302 | ||
1303 | if (req == NULL) | |
1304 | return; | |
1305 | ||
1306 | if (ep->epnum > 0) { | |
1307 | length = _nbu2ss_readl( | |
1308 | &ep->udc->p_regs->EP_REGS[ep->epnum-1].EP_LEN_DCNT); | |
1309 | ||
1310 | length &= EPn_LDATA; | |
1311 | if (length < ep->ep.maxpacket) | |
1312 | bflag = TRUE; | |
1313 | } | |
1314 | ||
1315 | _nbu2ss_start_transfer(ep->udc, ep, req, bflag); | |
1316 | } | |
1317 | ||
1318 | /*-------------------------------------------------------------------------*/ | |
1319 | /* Endpoint Toggle Reset */ | |
1320 | static void _nbu2ss_endpoint_toggle_reset( | |
1321 | struct nbu2ss_udc *udc, | |
1322 | u8 ep_adrs) | |
1323 | { | |
1324 | u8 num; | |
1325 | u32 data; | |
1326 | ||
1327 | if ((ep_adrs == 0) || (ep_adrs == 0x80)) | |
1328 | return; | |
1329 | ||
1330 | num = (ep_adrs & 0x7F) - 1; | |
1331 | ||
1332 | if (ep_adrs & USB_DIR_IN) | |
1333 | data = EPn_IPIDCLR; | |
1334 | else | |
1335 | data = EPn_BCLR | EPn_OPIDCLR; | |
1336 | ||
1337 | _nbu2ss_bitset(&udc->p_regs->EP_REGS[num].EP_CONTROL, data); | |
1338 | } | |
1339 | ||
1340 | /*-------------------------------------------------------------------------*/ | |
1341 | /* Endpoint STALL set */ | |
1342 | static void _nbu2ss_set_endpoint_stall( | |
1343 | struct nbu2ss_udc *udc, | |
1344 | u8 ep_adrs, | |
1345 | bool bstall) | |
1346 | { | |
1347 | u8 num, epnum; | |
1348 | u32 data; | |
1349 | struct nbu2ss_ep *ep; | |
1350 | PT_FC_REGS preg = udc->p_regs; | |
1351 | ||
1352 | if ((ep_adrs == 0) || (ep_adrs == 0x80)) { | |
1353 | if (bstall) { | |
1354 | /* Set STALL */ | |
1355 | _nbu2ss_bitset(&preg->EP0_CONTROL, EP0_STL); | |
1356 | } else { | |
1357 | /* Clear STALL */ | |
1358 | _nbu2ss_bitclr(&preg->EP0_CONTROL, EP0_STL); | |
1359 | } | |
1360 | } else { | |
1361 | epnum = ep_adrs & USB_ENDPOINT_NUMBER_MASK; | |
1362 | num = epnum - 1; | |
1363 | ep = &udc->ep[epnum]; | |
1364 | ||
1365 | if (bstall) { | |
1366 | /* Set STALL */ | |
1367 | ep->halted = TRUE; | |
1368 | ||
1369 | if (ep_adrs & USB_DIR_IN) | |
1370 | data = EPn_BCLR | EPn_ISTL; | |
1371 | else | |
1372 | data = EPn_OSTL_EN | EPn_OSTL; | |
1373 | ||
1374 | _nbu2ss_bitset(&preg->EP_REGS[num].EP_CONTROL, data); | |
1375 | } else { | |
1376 | /* Clear STALL */ | |
1377 | ep->stalled = FALSE; | |
1378 | if (ep_adrs & USB_DIR_IN) { | |
1379 | _nbu2ss_bitclr(&preg->EP_REGS[num].EP_CONTROL | |
1380 | , EPn_ISTL); | |
1381 | } else { | |
1382 | data = | |
1383 | _nbu2ss_readl(&preg->EP_REGS[num].EP_CONTROL); | |
1384 | ||
1385 | data &= ~EPn_OSTL; | |
1386 | data |= EPn_OSTL_EN; | |
1387 | ||
1388 | _nbu2ss_writel(&preg->EP_REGS[num].EP_CONTROL | |
1389 | , data); | |
1390 | } | |
1391 | ||
1392 | ep->stalled = FALSE; | |
1393 | if (ep->halted) { | |
1394 | ep->halted = FALSE; | |
1395 | _nbu2ss_restert_transfer(ep); | |
1396 | } | |
1397 | } | |
1398 | } | |
33aa8d45 MD |
1399 | } |
1400 | ||
1401 | ||
1402 | /*-------------------------------------------------------------------------*/ | |
1403 | /* Device Descriptor */ | |
1404 | static struct usb_device_descriptor device_desc = { | |
1405 | .bLength = sizeof(device_desc), | |
1406 | .bDescriptorType = USB_DT_DEVICE, | |
1407 | .bcdUSB = __constant_cpu_to_le16(0x0200), | |
1408 | .bDeviceClass = USB_CLASS_VENDOR_SPEC, | |
1409 | .bDeviceSubClass = 0x00, | |
1410 | .bDeviceProtocol = 0x00, | |
1411 | .bMaxPacketSize0 = 64, | |
1412 | .idVendor = __constant_cpu_to_le16 (0x0409), | |
1413 | .idProduct = __constant_cpu_to_le16 (0xfff0), | |
1414 | .bcdDevice = 0xffff, | |
1415 | .iManufacturer = 0x00, | |
1416 | .iProduct = 0x00, | |
1417 | .iSerialNumber = 0x00, | |
1418 | .bNumConfigurations = 0x01, | |
1419 | }; | |
1420 | ||
1421 | /*-------------------------------------------------------------------------*/ | |
1422 | static void _nbu2ss_set_test_mode(struct nbu2ss_udc *udc, u32 mode) | |
1423 | { | |
1424 | u32 data; | |
1425 | ||
1426 | if (mode > MAX_TEST_MODE_NUM) | |
1427 | return; | |
1428 | ||
1429 | pr_info("SET FEATURE : test mode = %d\n", mode); | |
1430 | ||
1431 | data = _nbu2ss_readl(&udc->p_regs->USB_CONTROL); | |
1432 | data &= ~TEST_FORCE_ENABLE; | |
1433 | data |= mode << TEST_MODE_SHIFT; | |
1434 | ||
1435 | _nbu2ss_writel(&udc->p_regs->USB_CONTROL, data); | |
1436 | _nbu2ss_bitset(&udc->p_regs->TEST_CONTROL, CS_TESTMODEEN); | |
1437 | } | |
1438 | ||
1439 | /*-------------------------------------------------------------------------*/ | |
1440 | static int _nbu2ss_set_feature_device( | |
1441 | struct nbu2ss_udc *udc, | |
1442 | u16 selector, | |
1443 | u16 wIndex | |
1444 | ) | |
1445 | { | |
1446 | int result = -EOPNOTSUPP; | |
1447 | ||
1448 | switch (selector) { | |
1449 | case USB_DEVICE_REMOTE_WAKEUP: | |
1450 | if (0x0000 == wIndex) { | |
1451 | udc->remote_wakeup = U2F_ENABLE; | |
1452 | result = 0; | |
1453 | } | |
1454 | break; | |
1455 | ||
1456 | case USB_DEVICE_TEST_MODE: | |
1457 | wIndex = wIndex >> 8; | |
1458 | if (wIndex <= MAX_TEST_MODE_NUM) | |
1459 | result = 0; | |
1460 | break; | |
1461 | ||
1462 | default: | |
1463 | break; | |
1464 | } | |
1465 | ||
1466 | return result; | |
1467 | } | |
1468 | ||
1469 | /*-------------------------------------------------------------------------*/ | |
1470 | static int _nbu2ss_get_ep_stall(struct nbu2ss_udc *udc, u8 ep_adrs) | |
1471 | { | |
1472 | u8 epnum; | |
1473 | u32 data = 0, bit_data; | |
1474 | PT_FC_REGS preg = udc->p_regs; | |
1475 | ||
1476 | epnum = ep_adrs & ~USB_ENDPOINT_DIR_MASK; | |
1477 | if (epnum == 0) { | |
1478 | data = _nbu2ss_readl(&preg->EP0_CONTROL); | |
1479 | bit_data = EP0_STL; | |
1480 | ||
1481 | } else { | |
1482 | data = _nbu2ss_readl(&preg->EP_REGS[epnum-1].EP_CONTROL); | |
1483 | if ((data & EPn_EN) == 0) | |
1484 | return -1; | |
1485 | ||
1486 | if (ep_adrs & USB_ENDPOINT_DIR_MASK) | |
1487 | bit_data = EPn_ISTL; | |
1488 | else | |
1489 | bit_data = EPn_OSTL; | |
1490 | } | |
1491 | ||
1492 | if ((data & bit_data) == 0) | |
1493 | return 0; | |
1494 | else | |
1495 | return 1; | |
1496 | } | |
1497 | ||
1498 | /*-------------------------------------------------------------------------*/ | |
1499 | static inline int _nbu2ss_req_feature(struct nbu2ss_udc *udc, bool bset) | |
1500 | { | |
1501 | u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK); | |
1502 | u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN); | |
1503 | u16 selector = udc->ctrl.wValue; | |
1504 | u16 wIndex = udc->ctrl.wIndex; | |
1505 | u8 ep_adrs; | |
1506 | int result = -EOPNOTSUPP; | |
1507 | ||
1508 | if ((0x0000 != udc->ctrl.wLength) || | |
1509 | (USB_DIR_OUT != direction)) { | |
1510 | return -EINVAL; | |
1511 | } | |
1512 | ||
1513 | switch (recipient) { | |
1514 | case USB_RECIP_DEVICE: | |
1515 | if (bset) | |
1516 | result = | |
1517 | _nbu2ss_set_feature_device(udc, selector, wIndex); | |
1518 | break; | |
1519 | ||
1520 | case USB_RECIP_ENDPOINT: | |
1521 | if (0x0000 == (wIndex & 0xFF70)) { | |
1522 | if (USB_ENDPOINT_HALT == selector) { | |
1523 | ep_adrs = wIndex & 0xFF; | |
1524 | if (bset == FALSE) { | |
1525 | _nbu2ss_endpoint_toggle_reset( | |
1526 | udc, ep_adrs); | |
1527 | } | |
1528 | ||
1529 | _nbu2ss_set_endpoint_stall( | |
1530 | udc, ep_adrs, bset); | |
1531 | ||
1532 | result = 0; | |
1533 | } | |
1534 | } | |
1535 | break; | |
1536 | ||
1537 | default: | |
1538 | break; | |
1539 | } | |
1540 | ||
1541 | if (result >= 0) | |
1542 | _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0); | |
1543 | ||
1544 | return result; | |
1545 | } | |
1546 | ||
1547 | /*-------------------------------------------------------------------------*/ | |
1548 | static inline enum usb_device_speed _nbu2ss_get_speed(struct nbu2ss_udc *udc) | |
1549 | { | |
1550 | u32 data; | |
1551 | enum usb_device_speed speed = USB_SPEED_FULL; | |
1552 | ||
1553 | data = _nbu2ss_readl(&udc->p_regs->USB_STATUS); | |
1554 | if (data & HIGH_SPEED) | |
1555 | speed = USB_SPEED_HIGH; | |
1556 | ||
1557 | return speed; | |
1558 | } | |
1559 | ||
1560 | /*-------------------------------------------------------------------------*/ | |
1561 | static void _nbu2ss_epn_set_stall( | |
1562 | struct nbu2ss_udc *udc, | |
1563 | struct nbu2ss_ep *ep | |
1564 | ) | |
1565 | { | |
1566 | u8 ep_adrs; | |
1567 | u32 regdata; | |
1568 | int limit_cnt = 0; | |
1569 | ||
1570 | PT_FC_REGS preg = udc->p_regs; | |
1571 | ||
1572 | if (ep->direct == USB_DIR_IN) { | |
1573 | for (limit_cnt = 0 | |
1574 | ; limit_cnt < IN_DATA_EMPTY_COUNT | |
1575 | ; limit_cnt++) { | |
1576 | ||
1577 | regdata = _nbu2ss_readl( | |
1578 | &preg->EP_REGS[ep->epnum-1].EP_STATUS); | |
1579 | ||
1580 | if ((regdata & EPn_IN_DATA) == 0) | |
1581 | break; | |
1582 | ||
1583 | mdelay(1); | |
1584 | } | |
1585 | } | |
1586 | ||
1587 | ep_adrs = ep->epnum | ep->direct; | |
1588 | _nbu2ss_set_endpoint_stall(udc, ep_adrs, 1); | |
1589 | } | |
1590 | ||
1591 | /*-------------------------------------------------------------------------*/ | |
1592 | static int std_req_get_status(struct nbu2ss_udc *udc) | |
1593 | { | |
1594 | u32 length; | |
1595 | u16 status_data = 0; | |
1596 | u8 recipient = (u8)(udc->ctrl.bRequestType & USB_RECIP_MASK); | |
1597 | u8 direction = (u8)(udc->ctrl.bRequestType & USB_DIR_IN); | |
1598 | u8 ep_adrs; | |
1599 | int result = -EINVAL; | |
1600 | ||
1601 | if ((0x0000 != udc->ctrl.wValue) | |
1602 | || (USB_DIR_IN != direction)) { | |
1603 | ||
1604 | return result; | |
1605 | } | |
1606 | ||
1607 | length = min(udc->ctrl.wLength, (u16)sizeof(status_data)); | |
1608 | ||
1609 | switch (recipient) { | |
1610 | case USB_RECIP_DEVICE: | |
1611 | if (udc->ctrl.wIndex == 0x0000) { | |
1612 | if (udc->self_powered) | |
1613 | status_data |= (1 << USB_DEVICE_SELF_POWERED); | |
1614 | ||
1615 | if (udc->remote_wakeup) | |
1616 | status_data |= (1 << USB_DEVICE_REMOTE_WAKEUP); | |
1617 | ||
1618 | result = 0; | |
1619 | } | |
1620 | break; | |
1621 | ||
1622 | case USB_RECIP_ENDPOINT: | |
1623 | if (0x0000 == (udc->ctrl.wIndex & 0xFF70)) { | |
1624 | ep_adrs = (u8)(udc->ctrl.wIndex & 0xFF); | |
1625 | result = _nbu2ss_get_ep_stall(udc, ep_adrs); | |
1626 | ||
1627 | if (result > 0) | |
1628 | status_data |= (1 << USB_ENDPOINT_HALT); | |
1629 | } | |
1630 | break; | |
1631 | ||
1632 | default: | |
1633 | break; | |
1634 | } | |
1635 | ||
1636 | if (result >= 0) { | |
1637 | memcpy(udc->ep0_buf, &status_data, length); | |
1638 | _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, length); | |
1639 | _nbu2ss_ep0_in_transfer(udc, &udc->ep[0], &udc->ep0_req); | |
1640 | ||
1641 | } else { | |
1642 | ERR("*** Error GET_STATUS\n"); | |
1643 | } | |
1644 | ||
1645 | return result; | |
1646 | } | |
1647 | ||
1648 | /*-------------------------------------------------------------------------*/ | |
1649 | static int std_req_clear_feature(struct nbu2ss_udc *udc) | |
1650 | { | |
1651 | return _nbu2ss_req_feature(udc, FALSE); | |
1652 | } | |
1653 | ||
1654 | /*-------------------------------------------------------------------------*/ | |
1655 | static int std_req_set_feature(struct nbu2ss_udc *udc) | |
1656 | { | |
1657 | return _nbu2ss_req_feature(udc, TRUE); | |
1658 | } | |
1659 | ||
1660 | /*-------------------------------------------------------------------------*/ | |
1661 | static int std_req_set_address(struct nbu2ss_udc *udc) | |
1662 | { | |
1663 | int result = 0; | |
1664 | u32 wValue = udc->ctrl.wValue; | |
1665 | ||
1666 | if ((0x00 != udc->ctrl.bRequestType) || | |
1667 | (0x0000 != udc->ctrl.wIndex) || | |
1668 | (0x0000 != udc->ctrl.wLength)) { | |
1669 | return -EINVAL; | |
1670 | } | |
1671 | ||
1672 | if (wValue != (wValue & 0x007F)) | |
1673 | return -EINVAL; | |
1674 | ||
1675 | wValue = wValue << USB_ADRS_SHIFT; | |
1676 | ||
1677 | _nbu2ss_writel(&udc->p_regs->USB_ADDRESS, wValue); | |
1678 | _nbu2ss_create_ep0_packet(udc, udc->ep0_buf, 0); | |
1679 | ||
1680 | return result; | |
1681 | } | |
1682 | ||
1683 | /*-------------------------------------------------------------------------*/ | |
1684 | static int std_req_set_configuration(struct nbu2ss_udc *udc) | |
1685 | { | |
1686 | u32 ConfigValue = (u32)(udc->ctrl.wValue & 0x00ff); | |
1687 | ||
1688 | if ((0x0000 != udc->ctrl.wIndex) || | |
1689 | (0x0000 != udc->ctrl.wLength) || | |
1690 | (0x00 != udc->ctrl.bRequestType)) { | |
1691 | return -EINVAL; | |
1692 | } | |
1693 | ||
1694 | udc->curr_config = ConfigValue; | |
1695 | ||
1696 | if (ConfigValue > 0) { | |
1697 | _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, CONF); | |
1698 | udc->devstate = USB_STATE_CONFIGURED; | |
1699 | ||
1700 | } else { | |
1701 | _nbu2ss_bitclr(&udc->p_regs->USB_CONTROL, CONF); | |
1702 | udc->devstate = USB_STATE_ADDRESS; | |
1703 | } | |
1704 | ||
1705 | return 0; | |
1706 | } | |
1707 | ||
1708 | /*-------------------------------------------------------------------------*/ | |
1709 | static inline void _nbu2ss_read_request_data(struct nbu2ss_udc *udc, u32 *pdata) | |
1710 | { | |
1711 | if ((udc == NULL) && (pdata == NULL)) | |
1712 | return; | |
1713 | ||
1714 | *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA0); | |
1715 | pdata++; | |
1716 | *pdata = _nbu2ss_readl(&udc->p_regs->SETUP_DATA1); | |
1717 | } | |
1718 | ||
1719 | /*-------------------------------------------------------------------------*/ | |
1720 | static inline int _nbu2ss_decode_request(struct nbu2ss_udc *udc) | |
1721 | { | |
1722 | bool bcall_back = TRUE; | |
1723 | int nret = -EINVAL; | |
1724 | struct usb_ctrlrequest *p_ctrl; | |
1725 | ||
1726 | p_ctrl = &udc->ctrl; | |
1727 | _nbu2ss_read_request_data(udc, (u32 *)p_ctrl); | |
1728 | ||
1729 | /* ep0 state control */ | |
1730 | if (p_ctrl->wLength == 0) { | |
1731 | udc->ep0state = EP0_IN_STATUS_PHASE; | |
1732 | ||
1733 | } else { | |
1734 | if (p_ctrl->bRequestType & USB_DIR_IN) | |
1735 | udc->ep0state = EP0_IN_DATA_PHASE; | |
1736 | else | |
1737 | udc->ep0state = EP0_OUT_DATA_PHASE; | |
1738 | } | |
1739 | ||
1740 | if ((p_ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) { | |
1741 | switch (p_ctrl->bRequest) { | |
1742 | case USB_REQ_GET_STATUS: | |
1743 | nret = std_req_get_status(udc); | |
1744 | bcall_back = FALSE; | |
1745 | break; | |
1746 | ||
1747 | case USB_REQ_CLEAR_FEATURE: | |
1748 | nret = std_req_clear_feature(udc); | |
1749 | bcall_back = FALSE; | |
1750 | break; | |
1751 | ||
1752 | case USB_REQ_SET_FEATURE: | |
1753 | nret = std_req_set_feature(udc); | |
1754 | bcall_back = FALSE; | |
1755 | break; | |
1756 | ||
1757 | case USB_REQ_SET_ADDRESS: | |
1758 | nret = std_req_set_address(udc); | |
1759 | bcall_back = FALSE; | |
1760 | break; | |
1761 | ||
1762 | case USB_REQ_SET_CONFIGURATION: | |
1763 | nret = std_req_set_configuration(udc); | |
1764 | break; | |
1765 | ||
1766 | default: | |
1767 | break; | |
1768 | } | |
1769 | } | |
1770 | ||
1771 | if (bcall_back == FALSE) { | |
1772 | if (udc->ep0state == EP0_IN_STATUS_PHASE) { | |
1773 | if (nret >= 0) { | |
1774 | /*--------------------------------------*/ | |
1775 | /* Status Stage */ | |
1776 | nret = EP0_send_NULL(udc, TRUE); | |
1777 | } | |
1778 | } | |
1779 | ||
1780 | } else { | |
1781 | spin_unlock(&udc->lock); | |
1782 | nret = udc->driver->setup(&udc->gadget, &udc->ctrl); | |
1783 | spin_lock(&udc->lock); | |
1784 | } | |
1785 | ||
1786 | if (nret < 0) | |
1787 | udc->ep0state = EP0_IDLE; | |
1788 | ||
1789 | return nret; | |
1790 | } | |
1791 | ||
1792 | /*-------------------------------------------------------------------------*/ | |
1793 | static inline int _nbu2ss_ep0_in_data_stage(struct nbu2ss_udc *udc) | |
1794 | { | |
1795 | int nret; | |
1796 | struct nbu2ss_req *req; | |
1797 | struct nbu2ss_ep *ep = &udc->ep[0]; | |
1798 | ||
1799 | if (list_empty(&ep->queue)) | |
1800 | req = NULL; | |
1801 | else | |
1802 | req = list_entry(ep->queue.next, struct nbu2ss_req, queue); | |
1803 | ||
1804 | if (req == NULL) | |
1805 | req = &udc->ep0_req; | |
1806 | ||
1807 | req->req.actual += req->div_len; | |
1808 | req->div_len = 0; | |
1809 | ||
1810 | nret = _nbu2ss_ep0_in_transfer(udc, ep, req); | |
1811 | if (nret == 0) { | |
1812 | udc->ep0state = EP0_OUT_STATUS_PAHSE; | |
1813 | EP0_receive_NULL(udc, TRUE); | |
1814 | } | |
1815 | ||
1816 | return 0; | |
1817 | } | |
1818 | ||
1819 | /*-------------------------------------------------------------------------*/ | |
1820 | static inline int _nbu2ss_ep0_out_data_stage(struct nbu2ss_udc *udc) | |
1821 | { | |
1822 | int nret; | |
1823 | struct nbu2ss_req *req; | |
1824 | struct nbu2ss_ep *ep = &udc->ep[0]; | |
1825 | ||
1826 | if (list_empty(&ep->queue)) | |
1827 | req = NULL; | |
1828 | else | |
1829 | req = list_entry(ep->queue.next, struct nbu2ss_req, queue); | |
1830 | ||
1831 | if (req == NULL) | |
1832 | req = &udc->ep0_req; | |
1833 | ||
1834 | nret = _nbu2ss_ep0_out_transfer(udc, ep, req); | |
1835 | if (nret == 0) { | |
1836 | udc->ep0state = EP0_IN_STATUS_PHASE; | |
1837 | EP0_send_NULL(udc, TRUE); | |
1838 | ||
1839 | } else if (nret < 0) { | |
1840 | _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, EP0_BCLR); | |
1841 | req->req.status = nret; | |
1842 | } | |
1843 | ||
1844 | return 0; | |
1845 | } | |
1846 | ||
1847 | /*-------------------------------------------------------------------------*/ | |
1848 | static inline int _nbu2ss_ep0_status_stage(struct nbu2ss_udc *udc) | |
1849 | { | |
1850 | struct nbu2ss_req *req; | |
1851 | struct nbu2ss_ep *ep = &udc->ep[0]; | |
1852 | ||
1853 | if (list_empty(&ep->queue)) | |
1854 | req = NULL; | |
1855 | else | |
1856 | req = list_entry(ep->queue.next, struct nbu2ss_req, queue); | |
1857 | ||
1858 | if (req == NULL) { | |
1859 | req = &udc->ep0_req; | |
1860 | if (req->req.complete) | |
1861 | req->req.complete(&ep->ep, &req->req); | |
1862 | ||
1863 | } else { | |
1864 | if (req->req.complete) | |
1865 | _nbu2ss_ep_done(ep, req, 0); | |
1866 | } | |
1867 | ||
1868 | udc->ep0state = EP0_IDLE; | |
1869 | ||
1870 | return 0; | |
1871 | } | |
1872 | ||
1873 | /*-------------------------------------------------------------------------*/ | |
1874 | static inline void _nbu2ss_ep0_int(struct nbu2ss_udc *udc) | |
1875 | { | |
1876 | int i; | |
1877 | u32 status; | |
1878 | u32 intr; | |
1879 | int nret = -1; | |
1880 | ||
1881 | status = _nbu2ss_readl(&udc->p_regs->EP0_STATUS); | |
1882 | intr = status & EP0_STATUS_RW_BIT; | |
1883 | _nbu2ss_writel(&udc->p_regs->EP0_STATUS, ~(u32)intr); | |
1884 | ||
1885 | status &= (SETUP_INT | EP0_IN_INT | EP0_OUT_INT | |
1886 | | STG_END_INT | EP0_OUT_NULL_INT); | |
1887 | ||
1888 | if (status == 0) { | |
1889 | pr_info("--- %s Not Decode Interrupt\n", __func__); | |
1890 | pr_info("--- EP0_STATUS = 0x%08x\n", intr); | |
1891 | return; | |
1892 | } | |
1893 | ||
1894 | if (udc->gadget.speed == USB_SPEED_UNKNOWN) | |
1895 | udc->gadget.speed = _nbu2ss_get_speed(udc); | |
1896 | ||
1897 | for (i = 0; i < EP0_END_XFER; i++) { | |
1898 | switch (udc->ep0state) { | |
1899 | case EP0_IDLE: | |
1900 | if (status & SETUP_INT) { | |
1901 | status = 0; | |
1902 | nret = _nbu2ss_decode_request(udc); | |
1903 | } | |
1904 | break; | |
1905 | ||
1906 | case EP0_IN_DATA_PHASE: | |
1907 | if (status & EP0_IN_INT) { | |
1908 | status &= ~EP0_IN_INT; | |
1909 | nret = _nbu2ss_ep0_in_data_stage(udc); | |
1910 | } | |
1911 | break; | |
1912 | ||
1913 | case EP0_OUT_DATA_PHASE: | |
1914 | if (status & EP0_OUT_INT) { | |
1915 | status &= ~EP0_OUT_INT; | |
1916 | nret = _nbu2ss_ep0_out_data_stage(udc); | |
1917 | } | |
1918 | break; | |
1919 | ||
1920 | case EP0_IN_STATUS_PHASE: | |
1921 | if ((status & STG_END_INT) || (status & SETUP_INT)) { | |
1922 | status &= ~(STG_END_INT | EP0_IN_INT); | |
1923 | nret = _nbu2ss_ep0_status_stage(udc); | |
1924 | } | |
1925 | break; | |
1926 | ||
1927 | case EP0_OUT_STATUS_PAHSE: | |
1928 | if ((status & STG_END_INT) | |
1929 | || (status & SETUP_INT) | |
1930 | || (status & EP0_OUT_NULL_INT)) { | |
1931 | status &= ~(STG_END_INT | |
1932 | | EP0_OUT_INT | |
1933 | | EP0_OUT_NULL_INT); | |
1934 | ||
1935 | nret = _nbu2ss_ep0_status_stage(udc); | |
1936 | } | |
1937 | ||
1938 | break; | |
1939 | ||
1940 | default: | |
1941 | status = 0; | |
1942 | break; | |
1943 | } | |
1944 | ||
1945 | if (status == 0) | |
1946 | break; | |
1947 | } | |
1948 | ||
1949 | if (nret < 0) { | |
1950 | /* Send Stall */ | |
1951 | _nbu2ss_set_endpoint_stall(udc, 0, TRUE); | |
1952 | } | |
1953 | } | |
1954 | ||
1955 | /*-------------------------------------------------------------------------*/ | |
1956 | static void _nbu2ss_ep_done( | |
1957 | struct nbu2ss_ep *ep, | |
1958 | struct nbu2ss_req *req, | |
1959 | int status) | |
1960 | { | |
1961 | struct nbu2ss_udc *udc = ep->udc; | |
1962 | ||
1963 | list_del_init(&req->queue); | |
1964 | ||
1965 | if (status == -ECONNRESET) | |
1966 | _nbu2ss_fifo_flush(udc, ep); | |
1967 | ||
1968 | if (likely(req->req.status == -EINPROGRESS)) | |
1969 | req->req.status = status; | |
1970 | ||
1971 | if (ep->stalled) | |
1972 | _nbu2ss_epn_set_stall(udc, ep); | |
1973 | else { | |
1974 | if (!list_empty(&ep->queue)) | |
1975 | _nbu2ss_restert_transfer(ep); | |
1976 | } | |
1977 | ||
1978 | #ifdef USE_DMA | |
1979 | if ((ep->direct == USB_DIR_OUT) && (ep->epnum > 0) && | |
1980 | (req->req.dma != 0)) | |
1981 | _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_OUT); | |
1982 | #endif | |
1983 | ||
1984 | spin_unlock(&udc->lock); | |
1985 | req->req.complete(&ep->ep, &req->req); | |
1986 | spin_lock(&udc->lock); | |
1987 | } | |
1988 | ||
1989 | /*-------------------------------------------------------------------------*/ | |
1990 | static inline void _nbu2ss_epn_in_int( | |
1991 | struct nbu2ss_udc *udc, | |
1992 | struct nbu2ss_ep *ep, | |
1993 | struct nbu2ss_req *req) | |
1994 | { | |
1995 | int result = 0; | |
1996 | u32 status; | |
1997 | ||
1998 | PT_FC_REGS preg = udc->p_regs; | |
1999 | ||
2000 | if (req->dma_flag) | |
2001 | return; /* DMA is forwarded */ | |
2002 | ||
2003 | req->req.actual += req->div_len; | |
2004 | req->div_len = 0; | |
2005 | ||
2006 | if (req->req.actual != req->req.length) { | |
2007 | /*---------------------------------------------------------*/ | |
2008 | /* remainder of data */ | |
2009 | result = _nbu2ss_epn_in_transfer(udc, ep, req); | |
2010 | ||
2011 | } else { | |
2012 | if ((req->zero != 0) | |
2013 | && ((req->req.actual % ep->ep.maxpacket) == 0)) { | |
2014 | ||
2015 | status = | |
2016 | _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_STATUS); | |
2017 | ||
2018 | if ((status & EPn_IN_FULL) == 0) { | |
2019 | /*-----------------------------------------*/ | |
2020 | /* 0 Length Packet */ | |
2021 | req->zero = 0; | |
2022 | _nbu2ss_zero_len_pkt(udc, ep->epnum); | |
2023 | } | |
2024 | return; | |
2025 | } | |
2026 | } | |
2027 | ||
2028 | if (result <= 0) { | |
2029 | /*---------------------------------------------------------*/ | |
2030 | /* Complete */ | |
2031 | _nbu2ss_ep_done(ep, req, result); | |
2032 | } | |
2033 | } | |
2034 | ||
2035 | /*-------------------------------------------------------------------------*/ | |
2036 | static inline void _nbu2ss_epn_out_int( | |
2037 | struct nbu2ss_udc *udc, | |
2038 | struct nbu2ss_ep *ep, | |
2039 | struct nbu2ss_req *req) | |
2040 | { | |
2041 | int result; | |
2042 | ||
2043 | result = _nbu2ss_epn_out_transfer(udc, ep, req); | |
2044 | if (result <= 0) | |
2045 | _nbu2ss_ep_done(ep, req, result); | |
33aa8d45 MD |
2046 | } |
2047 | ||
2048 | /*-------------------------------------------------------------------------*/ | |
2049 | static inline void _nbu2ss_epn_in_dma_int( | |
2050 | struct nbu2ss_udc *udc, | |
2051 | struct nbu2ss_ep *ep, | |
2052 | struct nbu2ss_req *req) | |
2053 | { | |
2054 | u32 mpkt; | |
2055 | u32 size; | |
2056 | struct usb_request *preq; | |
2057 | ||
2058 | preq = &req->req; | |
2059 | ||
2060 | if (req->dma_flag == FALSE) | |
2061 | return; | |
2062 | ||
2063 | preq->actual += req->div_len; | |
2064 | req->div_len = 0; | |
2065 | req->dma_flag = FALSE; | |
2066 | ||
2067 | #ifdef USE_DMA | |
2068 | _nbu2ss_dma_unmap_single(udc, ep, req, USB_DIR_IN); | |
2069 | #endif | |
2070 | ||
2071 | if (preq->actual != preq->length) { | |
2072 | _nbu2ss_epn_in_transfer(udc, ep, req); | |
2073 | } else { | |
2074 | mpkt = ep->ep.maxpacket; | |
2075 | size = preq->actual % mpkt; | |
2076 | if (size > 0) { | |
2077 | if (((preq->actual & 0x03) == 0) && (size < mpkt)) | |
2078 | _nbu2ss_ep_in_end(udc, ep->epnum, 0, 0); | |
2079 | } else { | |
2080 | _nbu2ss_epn_in_int(udc, ep, req); | |
2081 | } | |
2082 | } | |
33aa8d45 MD |
2083 | } |
2084 | ||
2085 | /*-------------------------------------------------------------------------*/ | |
2086 | static inline void _nbu2ss_epn_out_dma_int( | |
2087 | struct nbu2ss_udc *udc, | |
2088 | struct nbu2ss_ep *ep, | |
2089 | struct nbu2ss_req *req) | |
2090 | { | |
2091 | int i; | |
2092 | u32 num; | |
2093 | u32 dmacnt, ep_dmacnt; | |
2094 | u32 mpkt; | |
2095 | PT_FC_REGS preg = udc->p_regs; | |
2096 | ||
2097 | num = ep->epnum - 1; | |
2098 | ||
2099 | if (req->req.actual == req->req.length) { | |
2100 | if ((req->req.length % ep->ep.maxpacket) | |
2101 | && (req->zero == 0)) { | |
2102 | req->div_len = 0; | |
2103 | req->dma_flag = FALSE; | |
2104 | _nbu2ss_ep_done(ep, req, 0); | |
2105 | return; | |
2106 | } | |
2107 | } | |
2108 | ||
2109 | ep_dmacnt = _nbu2ss_readl(&preg->EP_REGS[num].EP_LEN_DCNT) | |
2110 | & EPn_DMACNT; | |
2111 | ep_dmacnt >>= 16; | |
2112 | ||
2113 | for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { | |
2114 | dmacnt = _nbu2ss_readl(&preg->EP_DCR[num].EP_DCR1) | |
2115 | & DCR1_EPn_DMACNT; | |
2116 | dmacnt >>= 16; | |
2117 | if (ep_dmacnt == dmacnt) | |
2118 | break; | |
2119 | } | |
2120 | ||
2121 | _nbu2ss_bitclr(&preg->EP_DCR[num].EP_DCR1, DCR1_EPn_REQEN); | |
2122 | ||
2123 | if (dmacnt != 0) { | |
2124 | mpkt = ep->ep.maxpacket; | |
2125 | if ((req->div_len % mpkt) == 0) | |
2126 | req->div_len -= mpkt * dmacnt; | |
2127 | } | |
2128 | ||
2129 | if ((req->req.actual % ep->ep.maxpacket) > 0) { | |
2130 | if (req->req.actual == req->div_len) { | |
2131 | req->div_len = 0; | |
2132 | req->dma_flag = FALSE; | |
2133 | _nbu2ss_ep_done(ep, req, 0); | |
2134 | return; | |
2135 | } | |
2136 | } | |
2137 | ||
2138 | req->req.actual += req->div_len; | |
2139 | req->div_len = 0; | |
2140 | req->dma_flag = FALSE; | |
2141 | ||
2142 | _nbu2ss_epn_out_int(udc, ep, req); | |
2143 | } | |
2144 | ||
2145 | /*-------------------------------------------------------------------------*/ | |
2146 | static inline void _nbu2ss_epn_int(struct nbu2ss_udc *udc, u32 epnum) | |
2147 | { | |
2148 | u32 num; | |
2149 | u32 status; | |
2150 | ||
2151 | struct nbu2ss_req *req; | |
2152 | struct nbu2ss_ep *ep = &udc->ep[epnum]; | |
2153 | ||
2154 | num = epnum - 1; | |
2155 | ||
2156 | /* Interrupt Status */ | |
2157 | status = _nbu2ss_readl(&udc->p_regs->EP_REGS[num].EP_STATUS); | |
2158 | ||
2159 | /* Interrupt Clear */ | |
2160 | _nbu2ss_writel(&udc->p_regs->EP_REGS[num].EP_STATUS, ~(u32)status); | |
2161 | ||
2162 | if (list_empty(&ep->queue)) | |
2163 | req = NULL; | |
2164 | else | |
2165 | req = list_entry(ep->queue.next, struct nbu2ss_req, queue); | |
2166 | ||
2167 | if (req == NULL) { | |
2168 | /* pr_warning("=== %s(%d) req == NULL\n", __func__, epnum); */ | |
2169 | return; | |
2170 | } | |
2171 | ||
2172 | if (status & EPn_OUT_END_INT) { | |
2173 | status &= ~EPn_OUT_INT; | |
2174 | _nbu2ss_epn_out_dma_int(udc, ep, req); | |
2175 | } | |
2176 | ||
2177 | if (status & EPn_OUT_INT) | |
2178 | _nbu2ss_epn_out_int(udc, ep, req); | |
2179 | ||
2180 | if (status & EPn_IN_END_INT) { | |
2181 | status &= ~EPn_IN_INT; | |
2182 | _nbu2ss_epn_in_dma_int(udc, ep, req); | |
2183 | } | |
2184 | ||
2185 | if (status & EPn_IN_INT) | |
2186 | _nbu2ss_epn_in_int(udc, ep, req); | |
2187 | } | |
2188 | ||
2189 | /*-------------------------------------------------------------------------*/ | |
2190 | static inline void _nbu2ss_ep_int(struct nbu2ss_udc *udc, u32 epnum) | |
2191 | { | |
2192 | if (epnum == 0) | |
2193 | _nbu2ss_ep0_int(udc); | |
2194 | else | |
2195 | _nbu2ss_epn_int(udc, epnum); | |
2196 | } | |
2197 | ||
2198 | /*-------------------------------------------------------------------------*/ | |
2199 | static void _nbu2ss_ep0_enable(struct nbu2ss_udc *udc) | |
2200 | { | |
2201 | _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL, (EP0_AUTO | EP0_BCLR)); | |
2202 | _nbu2ss_writel(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT); | |
33aa8d45 MD |
2203 | } |
2204 | ||
2205 | #if 0 | |
2206 | /*-------------------------------------------------------------------------*/ | |
2207 | static void _nbu2ss_ep0_disable(struct nbu2ss_udc *udc) | |
2208 | { | |
2209 | _nbu2ss_bitclr(&udc->p_regs->EP0_INT_ENA, EP0_INT_EN_BIT); | |
2210 | ||
2211 | _nbu2ss_bitset(&udc->p_regs->EP0_CONTROL | |
2212 | , (EP0_BCLR | EP0_INAK | EP0_ONAK | EP0_BCLR)); | |
2213 | ||
2214 | _nbu2ss_bitclr(&udc->p_regs->EP0_CONTROL, EP0_AUTO); | |
33aa8d45 MD |
2215 | } |
2216 | #endif | |
2217 | ||
2218 | /*-------------------------------------------------------------------------*/ | |
2219 | static int _nbu2ss_nuke(struct nbu2ss_udc *udc, | |
2220 | struct nbu2ss_ep *ep, | |
2221 | int status) | |
2222 | { | |
2223 | struct nbu2ss_req *req; | |
2224 | ||
2225 | /* Endpoint Disable */ | |
2226 | _nbu2ss_epn_exit(udc, ep); | |
2227 | ||
2228 | /* DMA Disable */ | |
2229 | _nbu2ss_ep_dma_exit(udc, ep); | |
2230 | ||
2231 | if (list_empty(&ep->queue)) | |
2232 | return 0; | |
2233 | ||
2234 | /* called with irqs blocked */ | |
2235 | while (!list_empty(&ep->queue)) { | |
2236 | req = list_entry(ep->queue.next, struct nbu2ss_req, queue); | |
2237 | _nbu2ss_ep_done(ep, req, status); | |
2238 | } | |
2239 | ||
2240 | return 0; | |
2241 | } | |
2242 | ||
2243 | /*-------------------------------------------------------------------------*/ | |
2244 | static void _nbu2ss_quiesce(struct nbu2ss_udc *udc) | |
2245 | { | |
2246 | struct nbu2ss_ep *ep; | |
2247 | ||
2248 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
2249 | ||
2250 | _nbu2ss_nuke(udc, &udc->ep[0], -ESHUTDOWN); | |
2251 | ||
2252 | /* Endpoint n */ | |
2253 | list_for_each_entry(ep, &udc->gadget.ep_list, ep.ep_list) { | |
2254 | _nbu2ss_nuke(udc, ep, -ESHUTDOWN); | |
2255 | } | |
2256 | } | |
2257 | ||
2258 | /*-------------------------------------------------------------------------*/ | |
2259 | static int _nbu2ss_pullup(struct nbu2ss_udc *udc, int is_on) | |
2260 | { | |
2261 | u32 reg_dt; | |
2262 | ||
2263 | if (!udc) { | |
2264 | ERR("%s, bad param\n", __func__); | |
2265 | return -EINVAL; | |
2266 | } | |
2267 | ||
2268 | if (udc->vbus_active == 0) | |
2269 | return -ESHUTDOWN; | |
2270 | ||
2271 | if (is_on) { | |
2272 | /* D+ Pullup */ | |
2273 | /* INFO(" --- D+ Pullup\n"); */ | |
2274 | ||
2275 | if (udc->driver) { | |
2276 | reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | |
2277 | | PUE2) & ~(u32)CONNECTB; | |
2278 | ||
2279 | _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt); | |
2280 | } | |
2281 | ||
2282 | } else { | |
2283 | /* D+ Pulldown */ | |
2284 | /* INFO(" --- D+ Pulldown\n"); */ | |
2285 | ||
2286 | reg_dt = (_nbu2ss_readl(&udc->p_regs->USB_CONTROL) | CONNECTB) | |
2287 | & ~(u32)PUE2; | |
2288 | ||
2289 | _nbu2ss_writel(&udc->p_regs->USB_CONTROL, reg_dt); | |
2290 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
2291 | } | |
2292 | ||
2293 | return 0; | |
2294 | } | |
2295 | ||
2296 | /*-------------------------------------------------------------------------*/ | |
2297 | static void _nbu2ss_fifo_flush(struct nbu2ss_udc *udc, struct nbu2ss_ep *ep) | |
2298 | { | |
2299 | PT_FC_REGS p = udc->p_regs; | |
2300 | ||
2301 | if (udc->vbus_active == 0) | |
2302 | return; | |
2303 | ||
2304 | if (ep->epnum == 0) { | |
2305 | /* EP0 */ | |
2306 | _nbu2ss_bitset(&p->EP0_CONTROL, EP0_BCLR); | |
2307 | ||
2308 | } else { | |
2309 | /* EPn */ | |
2310 | _nbu2ss_ep_dma_abort(udc, ep); | |
2311 | _nbu2ss_bitset(&p->EP_REGS[ep->epnum - 1].EP_CONTROL, EPn_BCLR); | |
2312 | } | |
2313 | } | |
2314 | ||
2315 | /*-------------------------------------------------------------------------*/ | |
2316 | static int _nbu2ss_enable_controller(struct nbu2ss_udc *udc) | |
2317 | { | |
2318 | int waitcnt = 0; | |
2319 | ||
2320 | if (udc->udc_enabled) | |
2321 | return 0; | |
2322 | ||
2323 | #if 0 | |
2324 | emxx_open_clockgate(EMXX_CLK_USB1); | |
2325 | /* emxx_clkctrl_off(EMXX_CLKCTRL_USB1); */ | |
2326 | /* emxx_clkctrl_on(EMXX_CLKCTRL_USB1); */ | |
2327 | emxx_unreset_device(EMXX_RST_USB1); | |
2328 | #endif | |
2329 | /* | |
2330 | Reset | |
2331 | */ | |
2332 | _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST)); | |
2333 | udelay(EPC_RST_DISABLE_TIME); /* 1us wait */ | |
2334 | ||
2335 | _nbu2ss_bitclr(&udc->p_regs->EPCTR, DIRPD); | |
2336 | mdelay(EPC_DIRPD_DISABLE_TIME); /* 1ms wait */ | |
2337 | ||
2338 | _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST); | |
2339 | ||
2340 | _nbu2ss_writel(&udc->p_regs->AHBSCTR, WAIT_MODE); | |
2341 | ||
2342 | #if 0 | |
2343 | /* DMA Mode Setting */ | |
2344 | if ((system_rev & EMXX_REV_MASK) == EMXX_REV_ES1) { | |
2345 | _nbu2ss_bitset(&udc->p_regs->AHBMCTR, BURST_TYPE); | |
2346 | _nbu2ss_bitclr(&udc->p_regs->AHBMCTR, HTRANS_MODE); | |
2347 | } else | |
2348 | #endif | |
2349 | _nbu2ss_writel(&udc->p_regs->AHBMCTR, | |
2350 | HBUSREQ_MODE | HTRANS_MODE | WBURST_TYPE); | |
2351 | ||
2352 | while (!(_nbu2ss_readl(&udc->p_regs->EPCTR) & PLL_LOCK)) { | |
2353 | waitcnt++; | |
2354 | udelay(1); /* 1us wait */ | |
2355 | if (waitcnt == EPC_PLL_LOCK_COUNT) { | |
2356 | ERR("*** Reset Cancel failed\n"); | |
2357 | return -EINVAL; | |
2358 | } | |
2359 | }; | |
2360 | ||
2361 | #if 0 | |
2362 | if ((system_rev & EMXX_REV_MASK) < EMXX_REV_ES3) | |
2363 | #endif | |
2364 | _nbu2ss_bitset(&udc->p_regs->UTMI_CHARACTER_1, USB_SQUSET); | |
2365 | ||
2366 | _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, (INT_SEL | SOF_RCV)); | |
2367 | ||
2368 | /* EP0 */ | |
2369 | _nbu2ss_ep0_enable(udc); | |
2370 | ||
2371 | /* USB Interrupt Enable */ | |
2372 | _nbu2ss_bitset(&udc->p_regs->USB_INT_ENA, USB_INT_EN_BIT); | |
2373 | ||
2374 | udc->udc_enabled = TRUE; | |
2375 | ||
2376 | return 0; | |
2377 | } | |
2378 | ||
2379 | ||
2380 | /*-------------------------------------------------------------------------*/ | |
2381 | static void _nbu2ss_reset_controller(struct nbu2ss_udc *udc) | |
2382 | { | |
2383 | _nbu2ss_bitset(&udc->p_regs->EPCTR, EPC_RST); | |
2384 | _nbu2ss_bitclr(&udc->p_regs->EPCTR, EPC_RST); | |
2385 | } | |
2386 | ||
2387 | /*-------------------------------------------------------------------------*/ | |
2388 | static void _nbu2ss_disable_controller(struct nbu2ss_udc *udc) | |
2389 | { | |
2390 | if (udc->udc_enabled) { | |
2391 | udc->udc_enabled = FALSE; | |
2392 | _nbu2ss_reset_controller(udc); | |
2393 | _nbu2ss_bitset(&udc->p_regs->EPCTR, (DIRPD | EPC_RST)); | |
2394 | } | |
2395 | #if 0 | |
2396 | emxx_reset_device(EMXX_RST_USB1); | |
2397 | /* emxx_clkctrl_on(EMXX_CLKCTRL_USB1); */ | |
2398 | emxx_close_clockgate(EMXX_CLK_USB1); | |
2399 | #endif | |
2400 | } | |
2401 | ||
2402 | /*-------------------------------------------------------------------------*/ | |
2403 | static inline void _nbu2ss_check_vbus(struct nbu2ss_udc *udc) | |
2404 | { | |
2405 | int nret; | |
2406 | u32 reg_dt; | |
2407 | ||
2408 | /* chattering */ | |
2409 | mdelay(VBUS_CHATTERING_MDELAY); /* wait (ms) */ | |
2410 | ||
2411 | /* VBUS ON Check*/ | |
2412 | reg_dt = gpio_get_value(VBUS_VALUE); | |
2413 | if (reg_dt == 0) { | |
2414 | ||
2415 | udc->linux_suspended = 0; | |
2416 | ||
2417 | _nbu2ss_reset_controller(udc); | |
2418 | pr_info(" ----- VBUS OFF\n"); | |
2419 | ||
2420 | if (udc->vbus_active == 1) { | |
2421 | /* VBUS OFF */ | |
2422 | udc->vbus_active = 0; | |
2423 | if (udc->usb_suspended) { | |
2424 | udc->usb_suspended = 0; | |
2425 | /* _nbu2ss_reset_controller(udc); */ | |
2426 | } | |
2427 | udc->devstate = USB_STATE_NOTATTACHED; | |
2428 | ||
2429 | _nbu2ss_quiesce(udc); | |
2430 | if (udc->driver) { | |
2431 | spin_unlock(&udc->lock); | |
2432 | udc->driver->disconnect(&udc->gadget); | |
2433 | spin_lock(&udc->lock); | |
2434 | } | |
2435 | ||
2436 | _nbu2ss_disable_controller(udc); | |
2437 | } | |
2438 | } else { | |
2439 | mdelay(5); /* wait (5ms) */ | |
2440 | reg_dt = gpio_get_value(VBUS_VALUE); | |
2441 | if (reg_dt == 0) | |
2442 | return; | |
2443 | ||
2444 | pr_info(" ----- VBUS ON\n"); | |
2445 | ||
2446 | if (udc->linux_suspended) | |
2447 | return; | |
2448 | ||
2449 | if (udc->vbus_active == 0) { | |
2450 | /* VBUS ON */ | |
2451 | udc->vbus_active = 1; | |
2452 | udc->devstate = USB_STATE_POWERED; | |
2453 | ||
2454 | nret = _nbu2ss_enable_controller(udc); | |
2455 | if (nret < 0) { | |
2456 | _nbu2ss_disable_controller(udc); | |
2457 | udc->vbus_active = 0; | |
2458 | return; | |
2459 | } | |
2460 | ||
2461 | _nbu2ss_pullup(udc, 1); | |
2462 | ||
2463 | #ifdef UDC_DEBUG_DUMP | |
2464 | _nbu2ss_dump_register(udc); | |
2465 | #endif /* UDC_DEBUG_DUMP */ | |
2466 | ||
2467 | } else { | |
2468 | if (udc->devstate == USB_STATE_POWERED) | |
2469 | _nbu2ss_pullup(udc, 1); | |
2470 | } | |
2471 | } | |
33aa8d45 MD |
2472 | } |
2473 | ||
2474 | /*-------------------------------------------------------------------------*/ | |
2475 | static inline void _nbu2ss_int_bus_reset(struct nbu2ss_udc *udc) | |
2476 | { | |
2477 | udc->devstate = USB_STATE_DEFAULT; | |
2478 | udc->remote_wakeup = 0; | |
2479 | ||
2480 | _nbu2ss_quiesce(udc); | |
2481 | ||
2482 | udc->ep0state = EP0_IDLE; | |
2483 | } | |
2484 | ||
2485 | /*-------------------------------------------------------------------------*/ | |
2486 | static inline void _nbu2ss_int_usb_resume(struct nbu2ss_udc *udc) | |
2487 | { | |
2488 | if (udc->usb_suspended == 1) { | |
2489 | udc->usb_suspended = 0; | |
2490 | if (udc->driver && udc->driver->resume) { | |
2491 | spin_unlock(&udc->lock); | |
2492 | udc->driver->resume(&udc->gadget); | |
2493 | spin_lock(&udc->lock); | |
2494 | } | |
2495 | } | |
2496 | } | |
2497 | ||
2498 | /*-------------------------------------------------------------------------*/ | |
2499 | static inline void _nbu2ss_int_usb_suspend(struct nbu2ss_udc *udc) | |
2500 | { | |
2501 | u32 reg_dt; | |
2502 | ||
2503 | if (udc->usb_suspended == 0) { | |
2504 | reg_dt = gpio_get_value(VBUS_VALUE); | |
2505 | ||
2506 | if (reg_dt == 0) | |
2507 | return; | |
2508 | ||
2509 | udc->usb_suspended = 1; | |
2510 | if (udc->driver && udc->driver->suspend) { | |
2511 | spin_unlock(&udc->lock); | |
2512 | udc->driver->suspend(&udc->gadget); | |
2513 | spin_lock(&udc->lock); | |
2514 | } | |
2515 | ||
2516 | _nbu2ss_bitset(&udc->p_regs->USB_CONTROL, SUSPEND); | |
2517 | } | |
2518 | } | |
2519 | ||
2520 | /*-------------------------------------------------------------------------*/ | |
2521 | /* VBUS (GPIO153) Interrupt */ | |
2522 | static irqreturn_t _nbu2ss_vbus_irq(int irq, void *_udc) | |
2523 | { | |
2524 | struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc; | |
2525 | ||
2526 | spin_lock(&udc->lock); | |
2527 | _nbu2ss_check_vbus(udc); | |
2528 | spin_unlock(&udc->lock); | |
2529 | ||
2530 | return IRQ_HANDLED; | |
2531 | } | |
2532 | ||
2533 | /*-------------------------------------------------------------------------*/ | |
2534 | /* Interrupt (udc) */ | |
2535 | static irqreturn_t _nbu2ss_udc_irq(int irq, void *_udc) | |
2536 | { | |
2537 | u8 suspend_flag = 0; | |
2538 | u32 status; | |
2539 | u32 epnum, int_bit; | |
2540 | ||
2541 | struct nbu2ss_udc *udc = (struct nbu2ss_udc *)_udc; | |
2542 | PT_FC_REGS preg = udc->p_regs; | |
2543 | ||
2544 | if (gpio_get_value(VBUS_VALUE) == 0) { | |
2545 | _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW); | |
2546 | _nbu2ss_writel(&preg->USB_INT_ENA, 0); | |
2547 | return IRQ_HANDLED; | |
2548 | } | |
2549 | ||
2550 | spin_lock(&udc->lock); | |
2551 | ||
2552 | for (;;) { | |
2553 | if (gpio_get_value(VBUS_VALUE) == 0) { | |
2554 | _nbu2ss_writel(&preg->USB_INT_STA, ~USB_INT_STA_RW); | |
2555 | _nbu2ss_writel(&preg->USB_INT_ENA, 0); | |
2556 | status = 0; | |
2557 | } else | |
2558 | status = _nbu2ss_readl(&preg->USB_INT_STA); | |
2559 | ||
2560 | if (status == 0) | |
2561 | break; | |
2562 | ||
2563 | _nbu2ss_writel(&preg->USB_INT_STA, ~(status & USB_INT_STA_RW)); | |
2564 | ||
2565 | if (status & USB_RST_INT) { | |
2566 | /* USB Reset */ | |
2567 | _nbu2ss_int_bus_reset(udc); | |
2568 | } | |
2569 | ||
2570 | if (status & RSUM_INT) { | |
2571 | /* Resume */ | |
2572 | _nbu2ss_int_usb_resume(udc); | |
2573 | } | |
2574 | ||
2575 | if (status & SPND_INT) { | |
2576 | /* Suspend */ | |
2577 | suspend_flag = 1; | |
2578 | } | |
2579 | ||
2580 | if (status & EPn_INT) { | |
2581 | /* EP INT */ | |
2582 | int_bit = status >> 8; | |
2583 | ||
2584 | for (epnum = 0; epnum < NUM_ENDPOINTS; epnum++) { | |
2585 | ||
2586 | if (0x01 & int_bit) | |
2587 | _nbu2ss_ep_int(udc, epnum); | |
2588 | ||
2589 | int_bit >>= 1; | |
2590 | ||
2591 | if (int_bit == 0) | |
2592 | break; | |
2593 | } | |
2594 | } | |
2595 | } | |
2596 | ||
2597 | if (suspend_flag) | |
2598 | _nbu2ss_int_usb_suspend(udc); | |
2599 | ||
2600 | spin_unlock(&udc->lock); | |
2601 | ||
2602 | return IRQ_HANDLED; | |
2603 | } | |
2604 | ||
2605 | /*-------------------------------------------------------------------------*/ | |
2606 | /* usb_ep_ops */ | |
2607 | static int nbu2ss_ep_enable( | |
2608 | struct usb_ep *_ep, | |
2609 | const struct usb_endpoint_descriptor *desc) | |
2610 | { | |
2611 | u8 ep_type; | |
2612 | unsigned long flags; | |
2613 | ||
2614 | struct nbu2ss_ep *ep; | |
2615 | struct nbu2ss_udc *udc; | |
2616 | ||
2617 | if ((_ep == NULL) || (desc == NULL)) { | |
2618 | ERR(" *** %s, bad param\n", __func__); | |
2619 | return -EINVAL; | |
2620 | } | |
2621 | ||
2622 | ep = container_of(_ep, struct nbu2ss_ep, ep); | |
2623 | if ((ep == NULL) || (ep->udc == NULL)) { | |
2624 | ERR(" *** %s, ep == NULL !!\n", __func__); | |
2625 | return -EINVAL; | |
2626 | } | |
2627 | ||
2628 | ep_type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; | |
2629 | if ((ep_type == USB_ENDPOINT_XFER_CONTROL) | |
2630 | || (ep_type == USB_ENDPOINT_XFER_ISOC)) { | |
2631 | ||
2632 | ERR(" *** %s, bat bmAttributes\n", __func__); | |
2633 | return -EINVAL; | |
2634 | } | |
2635 | ||
2636 | udc = ep->udc; | |
2637 | if (udc->vbus_active == 0) | |
2638 | return -ESHUTDOWN; | |
2639 | ||
2640 | if ((udc->driver == NULL) | |
2641 | || (udc->gadget.speed == USB_SPEED_UNKNOWN)) { | |
2642 | ||
2643 | ERR(" *** %s, udc !!\n", __func__); | |
2644 | return -ESHUTDOWN; | |
2645 | } | |
2646 | ||
2647 | spin_lock_irqsave(&udc->lock, flags); | |
2648 | ||
2649 | ep->desc = desc; | |
2650 | ep->epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK; | |
2651 | ep->direct = desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK; | |
2652 | ep->ep_type = ep_type; | |
2653 | ep->wedged = 0; | |
2654 | ep->halted = FALSE; | |
2655 | ep->stalled = FALSE; | |
2656 | ||
2657 | ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize); | |
2658 | ||
2659 | /* DMA setting */ | |
2660 | _nbu2ss_ep_dma_init(udc, ep); | |
2661 | ||
2662 | /* Endpoint setting */ | |
2663 | _nbu2ss_ep_init(udc, ep); | |
2664 | ||
2665 | spin_unlock_irqrestore(&udc->lock, flags); | |
2666 | ||
2667 | return 0; | |
2668 | } | |
2669 | ||
2670 | /*-------------------------------------------------------------------------*/ | |
2671 | static int nbu2ss_ep_disable(struct usb_ep *_ep) | |
2672 | { | |
2673 | struct nbu2ss_ep *ep; | |
2674 | struct nbu2ss_udc *udc; | |
2675 | unsigned long flags; | |
2676 | ||
2677 | if (_ep == NULL) { | |
2678 | ERR(" *** %s, bad param\n", __func__); | |
2679 | return -EINVAL; | |
2680 | } | |
2681 | ||
2682 | ep = container_of(_ep, struct nbu2ss_ep, ep); | |
2683 | if ((ep == NULL) || (ep->udc == NULL)) { | |
2684 | ERR(" *** %s, ep == NULL !!\n", __func__); | |
2685 | return -EINVAL; | |
2686 | } | |
2687 | ||
2688 | udc = ep->udc; | |
2689 | if (udc->vbus_active == 0) | |
2690 | return -ESHUTDOWN; | |
2691 | ||
2692 | spin_lock_irqsave(&udc->lock, flags); | |
2693 | _nbu2ss_nuke(udc, ep, -EINPROGRESS); /* dequeue request */ | |
2694 | spin_unlock_irqrestore(&udc->lock, flags); | |
2695 | ||
2696 | return 0; | |
2697 | } | |
2698 | ||
2699 | /*-------------------------------------------------------------------------*/ | |
2700 | static struct usb_request *nbu2ss_ep_alloc_request( | |
2701 | struct usb_ep *ep, | |
2702 | gfp_t gfp_flags) | |
2703 | { | |
2704 | struct nbu2ss_req *req; | |
2705 | ||
2706 | req = kzalloc(sizeof(*req), gfp_flags); | |
2707 | if (!req) | |
2708 | return 0; | |
2709 | ||
2710 | #ifdef USE_DMA | |
2711 | req->req.dma = DMA_ADDR_INVALID; | |
2712 | #endif | |
2713 | INIT_LIST_HEAD(&req->queue); | |
2714 | ||
2715 | return &req->req; | |
2716 | } | |
2717 | ||
2718 | /*-------------------------------------------------------------------------*/ | |
2719 | static void nbu2ss_ep_free_request( | |
2720 | struct usb_ep *_ep, | |
2721 | struct usb_request *_req) | |
2722 | { | |
2723 | struct nbu2ss_req *req; | |
2724 | ||
2725 | if (_req != NULL) { | |
2726 | req = container_of(_req, struct nbu2ss_req, req); | |
2727 | ||
2728 | if (req != NULL) | |
2729 | kfree(req); | |
2730 | } | |
2731 | } | |
2732 | ||
2733 | /*-------------------------------------------------------------------------*/ | |
2734 | static int nbu2ss_ep_queue( | |
2735 | struct usb_ep *_ep, | |
2736 | struct usb_request *_req, | |
2737 | gfp_t gfp_flags) | |
2738 | { | |
2739 | struct nbu2ss_req *req; | |
2740 | struct nbu2ss_ep *ep; | |
2741 | struct nbu2ss_udc *udc; | |
2742 | unsigned long flags; | |
2743 | bool bflag; | |
2744 | int result = -EINVAL; | |
2745 | ||
2746 | /* catch various bogus parameters */ | |
2747 | if ((_ep == NULL) || (_req == NULL)) { | |
2748 | if (_ep == NULL) | |
2749 | ERR("*** %s --- _ep == NULL\n", __func__); | |
2750 | ||
2751 | if (_req == NULL) | |
2752 | ERR("*** %s --- _req == NULL\n", __func__); | |
2753 | ||
2754 | return -EINVAL; | |
2755 | } | |
2756 | ||
2757 | req = container_of(_req, struct nbu2ss_req, req); | |
2758 | if (unlikely | |
2759 | (!_req->complete || !_req->buf | |
2760 | || !list_empty(&req->queue))) { | |
2761 | ||
2762 | if (!_req->complete) | |
2763 | ERR("*** %s --- !_req->complete\n", __func__); | |
2764 | ||
2765 | if (!_req->buf) | |
2766 | ERR("*** %s --- !_req->buf\n", __func__); | |
2767 | ||
2768 | if (!list_empty(&req->queue)) | |
2769 | ERR("*** %s --- !list_empty(&req->queue)\n", __func__); | |
2770 | ||
2771 | return -EINVAL; | |
2772 | } | |
2773 | ||
2774 | ep = container_of(_ep, struct nbu2ss_ep, ep); | |
2775 | udc = ep->udc; | |
2776 | ||
2777 | /* INFO("=== %s(ep%d), zero=%d\n", __func__, ep->epnum, _req->zero); */ | |
2778 | ||
2779 | if (udc->vbus_active == 0) { | |
2780 | pr_info("Can't ep_queue (VBUS OFF)\n"); | |
2781 | return -ESHUTDOWN; | |
2782 | } | |
2783 | ||
2784 | if (unlikely(!udc->driver)) { | |
2785 | ERR("%s, bogus device state %p\n", __func__, udc->driver); | |
2786 | return -ESHUTDOWN; | |
2787 | } | |
2788 | ||
2789 | spin_lock_irqsave(&udc->lock, flags); | |
2790 | ||
2791 | #ifdef USE_DMA | |
2792 | if ((u32)req->req.buf & 0x3) | |
2793 | req->unaligned = TRUE; | |
2794 | else | |
2795 | req->unaligned = FALSE; | |
2796 | ||
2797 | if (req->unaligned) { | |
2798 | if (ep->virt_buf == NULL) | |
2799 | ep->virt_buf = (u8 *)dma_alloc_coherent( | |
2800 | NULL, PAGE_SIZE, | |
2801 | &ep->phys_buf, GFP_KERNEL | GFP_DMA); | |
2802 | if (ep->epnum > 0) { | |
2803 | if (ep->direct == USB_DIR_IN) | |
2804 | memcpy(ep->virt_buf, req->req.buf, | |
2805 | req->req.length); | |
2806 | } | |
2807 | } | |
2808 | ||
2809 | if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT) && | |
2810 | (req->req.dma != 0)) | |
2811 | _nbu2ss_dma_map_single(udc, ep, req, USB_DIR_OUT); | |
2812 | #endif | |
2813 | ||
2814 | _req->status = -EINPROGRESS; | |
2815 | _req->actual = 0; | |
2816 | ||
2817 | bflag = list_empty(&ep->queue); | |
2818 | list_add_tail(&req->queue, &ep->queue); | |
2819 | ||
2820 | if ((bflag != FALSE) && (ep->stalled == FALSE)) { | |
2821 | ||
2822 | result = _nbu2ss_start_transfer(udc, ep, req, FALSE); | |
2823 | if (result < 0) { | |
2824 | ERR(" *** %s, result = %d\n", __func__, result); | |
2825 | list_del(&req->queue); | |
2826 | } else if ((ep->epnum > 0) && (ep->direct == USB_DIR_OUT)) { | |
2827 | #ifdef USE_DMA | |
2828 | if (req->req.length < 4 && | |
2829 | req->req.length == req->req.actual) | |
2830 | #else | |
2831 | if (req->req.length == req->req.actual) | |
2832 | #endif | |
2833 | _nbu2ss_ep_done(ep, req, result); | |
2834 | } | |
2835 | } | |
2836 | ||
2837 | spin_unlock_irqrestore(&udc->lock, flags); | |
2838 | ||
2839 | return 0; | |
2840 | } | |
2841 | ||
2842 | /*-------------------------------------------------------------------------*/ | |
2843 | static int nbu2ss_ep_dequeue( | |
2844 | struct usb_ep *_ep, | |
2845 | struct usb_request *_req) | |
2846 | { | |
2847 | struct nbu2ss_req *req; | |
2848 | struct nbu2ss_ep *ep; | |
2849 | struct nbu2ss_udc *udc; | |
2850 | unsigned long flags; | |
2851 | ||
2852 | /*INFO("=== %s()\n", __func__);*/ | |
2853 | ||
2854 | /* catch various bogus parameters */ | |
2855 | if ((_ep == NULL) || (_req == NULL)) { | |
2856 | /* ERR("%s, bad param(1)\n", __func__); */ | |
2857 | return -EINVAL; | |
2858 | } | |
2859 | ||
2860 | ep = container_of(_ep, struct nbu2ss_ep, ep); | |
2861 | if (!ep) { | |
2862 | ERR("%s, ep == NULL !!\n", __func__); | |
2863 | return -EINVAL; | |
2864 | } | |
2865 | ||
2866 | udc = ep->udc; | |
2867 | if (udc == NULL) | |
2868 | return -EINVAL; | |
2869 | ||
2870 | spin_lock_irqsave(&udc->lock, flags); | |
2871 | ||
2872 | /* make sure it's actually queued on this endpoint */ | |
2873 | list_for_each_entry(req, &ep->queue, queue) { | |
2874 | if (&req->req == _req) | |
2875 | break; | |
2876 | } | |
2877 | if (&req->req != _req) { | |
2878 | spin_unlock_irqrestore(&udc->lock, flags); | |
2879 | pr_debug("%s no queue(EINVAL)\n", __func__); | |
2880 | return -EINVAL; | |
2881 | } | |
2882 | ||
2883 | _nbu2ss_ep_done(ep, req, -ECONNRESET); | |
2884 | ||
2885 | spin_unlock_irqrestore(&udc->lock, flags); | |
2886 | ||
2887 | return 0; | |
2888 | } | |
2889 | ||
2890 | /*-------------------------------------------------------------------------*/ | |
2891 | static int nbu2ss_ep_set_halt(struct usb_ep *_ep, int value) | |
2892 | { | |
2893 | u8 ep_adrs; | |
2894 | unsigned long flags; | |
2895 | ||
2896 | struct nbu2ss_ep *ep; | |
2897 | struct nbu2ss_udc *udc; | |
2898 | ||
2899 | /* INFO("=== %s()\n", __func__); */ | |
2900 | ||
2901 | if (!_ep) { | |
2902 | ERR("%s, bad param\n", __func__); | |
2903 | return -EINVAL; | |
2904 | } | |
2905 | ||
2906 | ep = container_of(_ep, struct nbu2ss_ep, ep); | |
2907 | if (!ep) { | |
2908 | ERR("%s, bad ep\n", __func__); | |
2909 | return -EINVAL; | |
2910 | } | |
2911 | ||
2912 | udc = ep->udc; | |
2913 | if (!udc) { | |
2914 | ERR(" *** %s, bad udc\n", __func__); | |
2915 | return -EINVAL; | |
2916 | } | |
2917 | ||
2918 | spin_lock_irqsave(&udc->lock, flags); | |
2919 | ||
2920 | ep_adrs = ep->epnum | ep->direct; | |
2921 | if (value == 0) { | |
2922 | _nbu2ss_set_endpoint_stall(udc, ep_adrs, value); | |
2923 | ep->stalled = FALSE; | |
2924 | } else { | |
2925 | if (list_empty(&ep->queue)) | |
2926 | _nbu2ss_epn_set_stall(udc, ep); | |
2927 | else | |
2928 | ep->stalled = TRUE; | |
2929 | } | |
2930 | ||
2931 | if (value == 0) | |
2932 | ep->wedged = 0; | |
2933 | ||
2934 | spin_unlock_irqrestore(&udc->lock, flags); | |
2935 | ||
2936 | return 0; | |
2937 | } | |
2938 | ||
2939 | static int nbu2ss_ep_set_wedge(struct usb_ep *_ep) | |
2940 | { | |
2941 | return nbu2ss_ep_set_halt(_ep, 1); | |
2942 | } | |
2943 | ||
2944 | /*-------------------------------------------------------------------------*/ | |
2945 | static int nbu2ss_ep_fifo_status(struct usb_ep *_ep) | |
2946 | { | |
2947 | u32 data; | |
2948 | struct nbu2ss_ep *ep; | |
2949 | struct nbu2ss_udc *udc; | |
2950 | unsigned long flags; | |
2951 | PT_FC_REGS preg; | |
2952 | ||
2953 | /* INFO("=== %s()\n", __func__); */ | |
2954 | ||
2955 | if (!_ep) { | |
2956 | ERR("%s, bad param\n", __func__); | |
2957 | return -EINVAL; | |
2958 | } | |
2959 | ||
2960 | ep = container_of(_ep, struct nbu2ss_ep, ep); | |
2961 | if (!ep) { | |
2962 | ERR("%s, bad ep\n", __func__); | |
2963 | return -EINVAL; | |
2964 | } | |
2965 | ||
2966 | udc = ep->udc; | |
2967 | if (!udc) { | |
2968 | ERR("%s, bad udc\n", __func__); | |
2969 | return -EINVAL; | |
2970 | } | |
2971 | ||
2972 | preg = udc->p_regs; | |
2973 | ||
2974 | data = gpio_get_value(VBUS_VALUE); | |
2975 | if (data == 0) | |
2976 | return -EINVAL; | |
2977 | ||
2978 | spin_lock_irqsave(&udc->lock, flags); | |
2979 | ||
2980 | if (ep->epnum == 0) { | |
2981 | data = _nbu2ss_readl(&preg->EP0_LENGTH) & EP0_LDATA; | |
2982 | ||
2983 | } else { | |
2984 | data = _nbu2ss_readl(&preg->EP_REGS[ep->epnum-1].EP_LEN_DCNT) | |
2985 | & EPn_LDATA; | |
2986 | } | |
2987 | ||
2988 | spin_unlock_irqrestore(&udc->lock, flags); | |
2989 | ||
2990 | return 0; | |
2991 | } | |
2992 | ||
2993 | /*-------------------------------------------------------------------------*/ | |
2994 | static void nbu2ss_ep_fifo_flush(struct usb_ep *_ep) | |
2995 | { | |
2996 | u32 data; | |
2997 | struct nbu2ss_ep *ep; | |
2998 | struct nbu2ss_udc *udc; | |
2999 | unsigned long flags; | |
3000 | ||
3001 | /* INFO("=== %s()\n", __func__); */ | |
3002 | ||
3003 | if (!_ep) { | |
3004 | ERR("%s, bad param\n", __func__); | |
3005 | return; | |
3006 | } | |
3007 | ||
3008 | ep = container_of(_ep, struct nbu2ss_ep, ep); | |
3009 | if (!_ep) { | |
3010 | ERR("%s, bad ep\n", __func__); | |
3011 | return; | |
3012 | } | |
3013 | ||
3014 | udc = ep->udc; | |
3015 | if (!udc) { | |
3016 | ERR("%s, bad udc\n", __func__); | |
3017 | return; | |
3018 | } | |
3019 | ||
3020 | data = gpio_get_value(VBUS_VALUE); | |
3021 | if (data == 0) | |
3022 | return; | |
3023 | ||
3024 | spin_lock_irqsave(&udc->lock, flags); | |
3025 | _nbu2ss_fifo_flush(udc, ep); | |
3026 | spin_unlock_irqrestore(&udc->lock, flags); | |
3027 | } | |
3028 | ||
3029 | /*-------------------------------------------------------------------------*/ | |
3030 | static struct usb_ep_ops nbu2ss_ep_ops = { | |
3031 | .enable = nbu2ss_ep_enable, | |
3032 | .disable = nbu2ss_ep_disable, | |
3033 | ||
3034 | .alloc_request = nbu2ss_ep_alloc_request, | |
3035 | .free_request = nbu2ss_ep_free_request, | |
3036 | ||
3037 | .queue = nbu2ss_ep_queue, | |
3038 | .dequeue = nbu2ss_ep_dequeue, | |
3039 | ||
3040 | .set_halt = nbu2ss_ep_set_halt, | |
3041 | .set_wedge = nbu2ss_ep_set_wedge, | |
3042 | ||
3043 | .fifo_status = nbu2ss_ep_fifo_status, | |
3044 | .fifo_flush = nbu2ss_ep_fifo_flush, | |
3045 | }; | |
3046 | ||
3047 | ||
3048 | /*-------------------------------------------------------------------------*/ | |
3049 | /* usb_gadget_ops */ | |
3050 | ||
3051 | /*-------------------------------------------------------------------------*/ | |
3052 | static int nbu2ss_gad_get_frame(struct usb_gadget *pgadget) | |
3053 | { | |
3054 | u32 data; | |
3055 | struct nbu2ss_udc *udc; | |
3056 | ||
3057 | /* INFO("=== %s()\n", __func__); */ | |
3058 | ||
3059 | if (pgadget == NULL) { | |
3060 | ERR("%s, bad param\n", __func__); | |
3061 | return -EINVAL; | |
3062 | } | |
3063 | ||
3064 | udc = container_of(pgadget, struct nbu2ss_udc, gadget); | |
3065 | if (udc == NULL) { | |
3066 | ERR("%s, udc == NULL\n", __func__); | |
3067 | return -EINVAL; | |
3068 | } | |
3069 | ||
3070 | data = gpio_get_value(VBUS_VALUE); | |
3071 | if (data == 0) | |
3072 | return -EINVAL; | |
3073 | ||
3074 | data = _nbu2ss_readl(&udc->p_regs->USB_ADDRESS) & FRAME; | |
3075 | ||
3076 | return data; | |
3077 | } | |
3078 | ||
3079 | /*-------------------------------------------------------------------------*/ | |
3080 | static int nbu2ss_gad_wakeup(struct usb_gadget *pgadget) | |
3081 | { | |
3082 | int i; | |
3083 | u32 data; | |
3084 | ||
3085 | struct nbu2ss_udc *udc; | |
3086 | ||
3087 | /* INFO("=== %s()\n", __func__); */ | |
3088 | ||
3089 | if (pgadget == NULL) { | |
3090 | ERR("%s, bad param\n", __func__); | |
3091 | return -EINVAL; | |
3092 | } | |
3093 | ||
3094 | udc = container_of(pgadget, struct nbu2ss_udc, gadget); | |
3095 | if (udc == NULL) { | |
3096 | ERR("%s, udc == NULL\n", __func__); | |
3097 | return -EINVAL; | |
3098 | } | |
3099 | ||
3100 | data = gpio_get_value(VBUS_VALUE); | |
3101 | if (data == 0) { | |
3102 | pr_warning("VBUS LEVEL = %d\n", data); | |
3103 | return -EINVAL; | |
3104 | } | |
3105 | ||
3106 | _nbu2ss_bitset(&udc->p_regs->EPCTR, PLL_RESUME); | |
3107 | ||
3108 | for (i = 0; i < EPC_PLL_LOCK_COUNT; i++) { | |
3109 | data = _nbu2ss_readl(&udc->p_regs->EPCTR); | |
3110 | ||
3111 | if (data & PLL_LOCK) | |
3112 | break; | |
3113 | } | |
3114 | ||
3115 | _nbu2ss_bitclr(&udc->p_regs->EPCTR, PLL_RESUME); | |
3116 | ||
3117 | return 0; | |
3118 | } | |
3119 | ||
3120 | /*-------------------------------------------------------------------------*/ | |
3121 | static int nbu2ss_gad_set_selfpowered(struct usb_gadget *pgadget, | |
3122 | int is_selfpowered) | |
3123 | { | |
3124 | struct nbu2ss_udc *udc; | |
3125 | unsigned long flags; | |
3126 | ||
3127 | /* INFO("=== %s()\n", __func__); */ | |
3128 | ||
3129 | if (pgadget == NULL) { | |
3130 | ERR("%s, bad param\n", __func__); | |
3131 | return -EINVAL; | |
3132 | } | |
3133 | ||
3134 | udc = container_of(pgadget, struct nbu2ss_udc, gadget); | |
3135 | ||
3136 | spin_lock_irqsave(&udc->lock, flags); | |
3137 | udc->self_powered = (is_selfpowered != 0); | |
3138 | spin_unlock_irqrestore(&udc->lock, flags); | |
3139 | ||
3140 | return 0; | |
3141 | } | |
3142 | ||
3143 | /*-------------------------------------------------------------------------*/ | |
3144 | static int nbu2ss_gad_vbus_session(struct usb_gadget *pgadget, int is_active) | |
3145 | { | |
3146 | /* INFO("=== %s()\n", __func__); */ | |
3147 | return 0; | |
3148 | } | |
3149 | ||
3150 | /*-------------------------------------------------------------------------*/ | |
3151 | static int nbu2ss_gad_vbus_draw(struct usb_gadget *pgadget, unsigned mA) | |
3152 | { | |
3153 | struct nbu2ss_udc *udc; | |
3154 | unsigned long flags; | |
3155 | ||
3156 | /* INFO("=== %s()\n", __func__); */ | |
3157 | ||
3158 | if (pgadget == NULL) { | |
3159 | ERR("%s, bad param\n", __func__); | |
3160 | return -EINVAL; | |
3161 | } | |
3162 | ||
3163 | udc = container_of(pgadget, struct nbu2ss_udc, gadget); | |
3164 | ||
3165 | spin_lock_irqsave(&udc->lock, flags); | |
3166 | udc->mA = mA; | |
3167 | spin_unlock_irqrestore(&udc->lock, flags); | |
3168 | ||
3169 | return 0; | |
3170 | } | |
3171 | ||
3172 | /*-------------------------------------------------------------------------*/ | |
3173 | static int nbu2ss_gad_pullup(struct usb_gadget *pgadget, int is_on) | |
3174 | { | |
3175 | struct nbu2ss_udc *udc; | |
3176 | unsigned long flags; | |
3177 | ||
3178 | /* INFO("=== %s()\n", __func__); */ | |
3179 | ||
3180 | if (pgadget == NULL) { | |
3181 | ERR("%s, bad param\n", __func__); | |
3182 | return -EINVAL; | |
3183 | } | |
3184 | ||
3185 | udc = container_of(pgadget, struct nbu2ss_udc, gadget); | |
3186 | ||
3187 | if (udc->driver == NULL) { | |
3188 | pr_warning("%s, Not Regist Driver\n", __func__); | |
3189 | return -EINVAL; | |
3190 | } | |
3191 | ||
3192 | if (udc->vbus_active == 0) | |
3193 | return -ESHUTDOWN; | |
3194 | ||
3195 | spin_lock_irqsave(&udc->lock, flags); | |
3196 | _nbu2ss_pullup(udc, is_on); | |
3197 | spin_unlock_irqrestore(&udc->lock, flags); | |
3198 | ||
3199 | return 0; | |
3200 | } | |
3201 | ||
3202 | /*-------------------------------------------------------------------------*/ | |
3203 | static int nbu2ss_gad_ioctl( | |
3204 | struct usb_gadget *pgadget, | |
3205 | unsigned code, | |
3206 | unsigned long param) | |
3207 | { | |
3208 | /* INFO("=== %s()\n", __func__); */ | |
3209 | return 0; | |
3210 | } | |
3211 | ||
3212 | ||
3213 | static const struct usb_gadget_ops nbu2ss_gadget_ops = { | |
3214 | .get_frame = nbu2ss_gad_get_frame, | |
3215 | .wakeup = nbu2ss_gad_wakeup, | |
3216 | .set_selfpowered = nbu2ss_gad_set_selfpowered, | |
3217 | .vbus_session = nbu2ss_gad_vbus_session, | |
3218 | .vbus_draw = nbu2ss_gad_vbus_draw, | |
3219 | .pullup = nbu2ss_gad_pullup, | |
3220 | .ioctl = nbu2ss_gad_ioctl, | |
3221 | }; | |
3222 | ||
3223 | static char g_ep0_name[] = "ep0"; | |
3224 | static char g_ep1_name[] = "ep1-bulk"; | |
3225 | static char g_ep2_name[] = "ep2-bulk"; | |
3226 | static char g_ep3_name[] = "ep3in-int"; | |
3227 | static char g_ep4_name[] = "ep4-iso"; | |
3228 | static char g_ep5_name[] = "ep5-iso"; | |
3229 | static char g_ep6_name[] = "ep6-bulk"; | |
3230 | static char g_ep7_name[] = "ep7-bulk"; | |
3231 | static char g_ep8_name[] = "ep8in-int"; | |
3232 | static char g_ep9_name[] = "ep9-iso"; | |
3233 | static char g_epa_name[] = "epa-iso"; | |
3234 | static char g_epb_name[] = "epb-bulk"; | |
3235 | static char g_epc_name[] = "epc-nulk"; | |
3236 | static char g_epd_name[] = "epdin-int"; | |
3237 | ||
3238 | static char *gp_ep_name[NUM_ENDPOINTS] = { | |
3239 | g_ep0_name, | |
3240 | g_ep1_name, | |
3241 | g_ep2_name, | |
3242 | g_ep3_name, | |
3243 | g_ep4_name, | |
3244 | g_ep5_name, | |
3245 | g_ep6_name, | |
3246 | g_ep7_name, | |
3247 | g_ep8_name, | |
3248 | g_ep9_name, | |
3249 | g_epa_name, | |
3250 | g_epb_name, | |
3251 | g_epc_name, | |
3252 | g_epd_name, | |
3253 | }; | |
3254 | ||
3255 | /*-------------------------------------------------------------------------*/ | |
3256 | static void __init nbu2ss_drv_set_ep_info( | |
3257 | struct nbu2ss_udc *udc, | |
3258 | struct nbu2ss_ep *ep, | |
3259 | u8 *name) | |
3260 | { | |
3261 | ep->udc = udc; | |
3262 | ep->desc = NULL; | |
3263 | ||
3264 | ep->ep.driver_data = NULL; | |
3265 | ep->ep.name = name; | |
3266 | ep->ep.ops = &nbu2ss_ep_ops; | |
3267 | ||
3268 | if (isdigit(name[2])) { | |
3269 | ||
3270 | long num; | |
3271 | int res; | |
3272 | char tempbuf[2]; | |
3273 | ||
3274 | tempbuf[0] = name[2]; | |
3275 | tempbuf[1] = '\0'; | |
6de2a1a7 | 3276 | res = kstrtol(tempbuf, 16, &num); |
33aa8d45 MD |
3277 | |
3278 | if (num == 0) | |
3279 | ep->ep.maxpacket = EP0_PACKETSIZE; | |
3280 | else | |
3281 | ep->ep.maxpacket = EP_PACKETSIZE; | |
3282 | ||
3283 | } else { | |
3284 | ep->ep.maxpacket = EP_PACKETSIZE; | |
3285 | } | |
3286 | ||
3287 | list_add_tail(&ep->ep.ep_list, &udc->gadget.ep_list); | |
3288 | INIT_LIST_HEAD(&ep->queue); | |
3289 | } | |
3290 | ||
3291 | /*-------------------------------------------------------------------------*/ | |
3292 | static void __init nbu2ss_drv_ep_init(struct nbu2ss_udc *udc) | |
3293 | { | |
3294 | int i; | |
3295 | ||
3296 | INIT_LIST_HEAD(&udc->gadget.ep_list); | |
3297 | udc->gadget.ep0 = &udc->ep[0].ep; | |
3298 | ||
3299 | ||
3300 | for (i = 0; i < NUM_ENDPOINTS; i++) | |
3301 | nbu2ss_drv_set_ep_info(udc, &udc->ep[i], gp_ep_name[i]); | |
3302 | ||
3303 | list_del_init(&udc->ep[0].ep.ep_list); | |
3304 | } | |
3305 | ||
3306 | /*-------------------------------------------------------------------------*/ | |
3307 | /* platform_driver */ | |
3308 | static int __init nbu2ss_drv_contest_init( | |
3309 | struct platform_device *pdev, | |
3310 | struct nbu2ss_udc *udc) | |
3311 | { | |
3312 | spin_lock_init(&udc->lock); | |
3313 | udc->dev = &pdev->dev; | |
3314 | ||
3315 | udc->self_powered = 1; | |
3316 | udc->devstate = USB_STATE_NOTATTACHED; | |
3317 | udc->pdev = pdev; | |
3318 | udc->mA = 0; | |
3319 | ||
3320 | udc->pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32); | |
3321 | ||
3322 | /* init Endpoint */ | |
3323 | nbu2ss_drv_ep_init(udc); | |
3324 | ||
3325 | /* init Gadget */ | |
3326 | udc->gadget.ops = &nbu2ss_gadget_ops; | |
3327 | udc->gadget.ep0 = &udc->ep[0].ep; | |
3328 | udc->gadget.speed = USB_SPEED_UNKNOWN; | |
3329 | udc->gadget.name = driver_name; | |
a2c14e97 | 3330 | /* udc->gadget.is_dualspeed = 1; */ |
33aa8d45 MD |
3331 | |
3332 | device_initialize(&udc->gadget.dev); | |
3333 | ||
3334 | dev_set_name(&udc->gadget.dev, "gadget"); | |
3335 | udc->gadget.dev.parent = &pdev->dev; | |
3336 | udc->gadget.dev.dma_mask = pdev->dev.dma_mask; | |
3337 | ||
3338 | return 0; | |
3339 | } | |
3340 | ||
3341 | /* | |
3342 | * probe - binds to the platform device | |
3343 | */ | |
3344 | static int nbu2ss_drv_probe(struct platform_device *pdev) | |
3345 | { | |
3346 | int status = -ENODEV; | |
3347 | struct nbu2ss_udc *udc; | |
96b29cac MD |
3348 | struct resource *r; |
3349 | int irq; | |
3350 | void __iomem *mmio_base; | |
33aa8d45 MD |
3351 | |
3352 | udc = &udc_controller; | |
3353 | memset(udc, 0, sizeof(struct nbu2ss_udc)); | |
3354 | ||
3355 | platform_set_drvdata(pdev, udc); | |
3356 | ||
96b29cac MD |
3357 | /* require I/O memory and IRQ to be provided as resources */ |
3358 | r = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
a790ebc1 SK |
3359 | mmio_base = devm_ioremap_resource(&pdev->dev, r); |
3360 | if (IS_ERR(mmio_base)) | |
96b29cac | 3361 | return PTR_ERR(mmio_base); |
33aa8d45 | 3362 | |
96b29cac MD |
3363 | irq = platform_get_irq(pdev, 0); |
3364 | if (irq < 0) { | |
3365 | dev_err(&pdev->dev, "failed to get IRQ\n"); | |
3366 | return irq; | |
33aa8d45 | 3367 | } |
96b29cac MD |
3368 | status = devm_request_irq(&pdev->dev, irq, _nbu2ss_udc_irq, |
3369 | 0, driver_name, udc); | |
33aa8d45 MD |
3370 | |
3371 | /* IO Memory */ | |
96b29cac | 3372 | udc->p_regs = (PT_FC_REGS)mmio_base; |
33aa8d45 MD |
3373 | |
3374 | /* USB Function Controller Interrupt */ | |
33aa8d45 MD |
3375 | if (status != 0) { |
3376 | ERR("request_irq(USB_UDC_IRQ_1) failed\n"); | |
96b29cac | 3377 | goto cleanup1; |
33aa8d45 MD |
3378 | } |
3379 | ||
3380 | /* Driver Initialization */ | |
3381 | status = nbu2ss_drv_contest_init(pdev, udc); | |
3382 | if (status < 0) { | |
3383 | /* Error */ | |
3384 | goto cleanup1; | |
3385 | } | |
3386 | ||
3387 | /* VBUS Interrupt */ | |
3388 | irq_set_irq_type(INT_VBUS, IRQ_TYPE_EDGE_BOTH); | |
3389 | status = request_irq(INT_VBUS, | |
3390 | _nbu2ss_vbus_irq, | |
3391 | IRQF_SHARED, | |
3392 | driver_name, | |
3393 | udc); | |
3394 | ||
3395 | if (status != 0) { | |
3396 | ERR("request_irq(INT_VBUS) failed\n"); | |
3397 | goto cleanup1; | |
3398 | } | |
3399 | ||
3400 | return status; | |
3401 | ||
3402 | cleanup1: | |
33aa8d45 MD |
3403 | return status; |
3404 | } | |
3405 | ||
3406 | /*-------------------------------------------------------------------------*/ | |
3407 | static void nbu2ss_drv_shutdown(struct platform_device *pdev) | |
3408 | { | |
3409 | struct nbu2ss_udc *udc; | |
3410 | ||
3411 | udc = platform_get_drvdata(pdev); | |
3412 | if (udc == NULL) | |
3413 | return; | |
3414 | ||
3415 | _nbu2ss_disable_controller(udc); | |
3416 | } | |
3417 | ||
3418 | /*-------------------------------------------------------------------------*/ | |
3419 | static int __exit nbu2ss_drv_remove(struct platform_device *pdev) | |
3420 | { | |
3421 | struct nbu2ss_udc *udc; | |
3422 | struct nbu2ss_ep *ep; | |
3423 | int i; | |
3424 | ||
3425 | udc = &udc_controller; | |
3426 | ||
3427 | for (i = 0; i < NUM_ENDPOINTS; i++) { | |
3428 | ep = &udc->ep[i]; | |
3429 | if (ep->virt_buf) | |
3430 | dma_free_coherent(NULL, PAGE_SIZE, | |
3431 | (void *)ep->virt_buf, ep->phys_buf); | |
3432 | } | |
3433 | ||
33aa8d45 MD |
3434 | /* Interrupt Handler - Release */ |
3435 | free_irq(INT_VBUS, udc); | |
3436 | ||
33aa8d45 MD |
3437 | return 0; |
3438 | } | |
3439 | ||
3440 | /*-------------------------------------------------------------------------*/ | |
3441 | static int nbu2ss_drv_suspend(struct platform_device *pdev, pm_message_t state) | |
3442 | { | |
3443 | struct nbu2ss_udc *udc; | |
3444 | ||
3445 | udc = platform_get_drvdata(pdev); | |
3446 | if (udc == NULL) | |
3447 | return 0; | |
3448 | ||
3449 | if (udc->vbus_active) { | |
3450 | udc->vbus_active = 0; | |
3451 | udc->devstate = USB_STATE_NOTATTACHED; | |
3452 | udc->linux_suspended = 1; | |
3453 | ||
3454 | if (udc->usb_suspended) { | |
3455 | udc->usb_suspended = 0; | |
3456 | _nbu2ss_reset_controller(udc); | |
3457 | } | |
3458 | ||
3459 | _nbu2ss_quiesce(udc); | |
3460 | } | |
3461 | _nbu2ss_disable_controller(udc); | |
3462 | ||
3463 | return 0; | |
3464 | } | |
3465 | ||
3466 | /*-------------------------------------------------------------------------*/ | |
3467 | static int nbu2ss_drv_resume(struct platform_device *pdev) | |
3468 | { | |
3469 | u32 data; | |
3470 | struct nbu2ss_udc *udc; | |
3471 | ||
3472 | udc = platform_get_drvdata(pdev); | |
3473 | if (udc == NULL) | |
3474 | return 0; | |
3475 | ||
3476 | data = gpio_get_value(VBUS_VALUE); | |
3477 | if (data) { | |
3478 | udc->vbus_active = 1; | |
3479 | udc->devstate = USB_STATE_POWERED; | |
3480 | _nbu2ss_enable_controller(udc); | |
3481 | _nbu2ss_pullup(udc, 1); | |
3482 | } | |
3483 | ||
3484 | udc->linux_suspended = 0; | |
3485 | ||
3486 | return 0; | |
3487 | } | |
3488 | ||
3489 | ||
3490 | static struct platform_driver udc_driver = { | |
3491 | .probe = nbu2ss_drv_probe, | |
3492 | .shutdown = nbu2ss_drv_shutdown, | |
3493 | .remove = __exit_p(nbu2ss_drv_remove), | |
3494 | .suspend = nbu2ss_drv_suspend, | |
3495 | .resume = nbu2ss_drv_resume, | |
3496 | .driver = { | |
3497 | .owner = THIS_MODULE, | |
3498 | .name = driver_name, | |
3499 | }, | |
3500 | }; | |
3501 | ||
464cad2c | 3502 | module_platform_driver(udc_driver); |
33aa8d45 MD |
3503 | |
3504 | MODULE_DESCRIPTION(DRIVER_DESC); | |
3505 | MODULE_AUTHOR("Renesas Electronics Corporation"); | |
3506 | MODULE_LICENSE("GPL"); | |
3507 | ||
3508 |