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33aa8d45 MD |
1 | /* |
2 | * EMXX FCD (Function Controller Driver) for USB. | |
3 | * | |
4 | * Copyright (C) 2010 Renesas Electronics Corporation | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 | |
8 | * as published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
33aa8d45 MD |
14 | */ |
15 | ||
33aa8d45 MD |
16 | #ifndef _LINUX_EMXX_H |
17 | #define _LINUX_EMXX_H | |
18 | ||
33aa8d45 MD |
19 | /*---------------------------------------------------------------------------*/ |
20 | /*----------------- Default undef */ | |
21 | #if 0 | |
22 | #define DEBUG | |
23 | #define UDC_DEBUG_DUMP | |
24 | #endif | |
25 | ||
33aa8d45 MD |
26 | /*----------------- Default define */ |
27 | #define USE_DMA 1 | |
28 | #define USE_SUSPEND_WAIT 1 | |
29 | ||
33aa8d45 MD |
30 | #ifndef TRUE |
31 | #define TRUE 1 | |
32 | #define FALSE 0 | |
33 | #endif | |
34 | ||
33aa8d45 | 35 | /*------------ Board dependence(Resource) */ |
33aa8d45 MD |
36 | #define VBUS_VALUE GPIO_VBUS |
37 | ||
38 | /* below hacked up for staging integration */ | |
39 | #define GPIO_VBUS 0 /* GPIO_P153 on KZM9D */ | |
40 | #define INT_VBUS 0 /* IRQ for GPIO_P153 */ | |
33aa8d45 MD |
41 | |
42 | /*------------ Board dependence(Wait) */ | |
43 | ||
44 | /* CHATTERING wait time ms */ | |
45 | #define VBUS_CHATTERING_MDELAY 1 | |
46 | /* DMA Abort wait time ms */ | |
47 | #define DMA_DISABLE_TIME 10 | |
48 | ||
33aa8d45 MD |
49 | /*------------ Controller dependence */ |
50 | #define NUM_ENDPOINTS 14 /* Endpoint */ | |
51 | #define REG_EP_NUM 15 /* Endpoint Register */ | |
52 | #define DMA_MAX_COUNT 256 /* DMA Block */ | |
53 | ||
33aa8d45 MD |
54 | #define EPC_RST_DISABLE_TIME 1 /* 1 usec */ |
55 | #define EPC_DIRPD_DISABLE_TIME 1 /* 1 msec */ | |
56 | #define EPC_PLL_LOCK_COUNT 1000 /* 1000 */ | |
57 | #define IN_DATA_EMPTY_COUNT 1000 /* 1000 */ | |
58 | ||
59 | #define CHATGER_TIME 700 /* 700msec */ | |
60 | #define USB_SUSPEND_TIME 2000 /* 2 sec */ | |
61 | ||
33aa8d45 MD |
62 | /* U2F FLAG */ |
63 | #define U2F_ENABLE 1 | |
64 | #define U2F_DISABLE 0 | |
65 | ||
33aa8d45 MD |
66 | /*------- BIT */ |
67 | #define BIT00 0x00000001 | |
68 | #define BIT01 0x00000002 | |
69 | #define BIT02 0x00000004 | |
70 | #define BIT03 0x00000008 | |
71 | #define BIT04 0x00000010 | |
72 | #define BIT05 0x00000020 | |
73 | #define BIT06 0x00000040 | |
74 | #define BIT07 0x00000080 | |
75 | #define BIT08 0x00000100 | |
76 | #define BIT09 0x00000200 | |
77 | #define BIT10 0x00000400 | |
78 | #define BIT11 0x00000800 | |
79 | #define BIT12 0x00001000 | |
80 | #define BIT13 0x00002000 | |
81 | #define BIT14 0x00004000 | |
82 | #define BIT15 0x00008000 | |
83 | #define BIT16 0x00010000 | |
84 | #define BIT17 0x00020000 | |
85 | #define BIT18 0x00040000 | |
86 | #define BIT19 0x00080000 | |
87 | #define BIT20 0x00100000 | |
88 | #define BIT21 0x00200000 | |
89 | #define BIT22 0x00400000 | |
90 | #define BIT23 0x00800000 | |
91 | #define BIT24 0x01000000 | |
92 | #define BIT25 0x02000000 | |
93 | #define BIT26 0x04000000 | |
94 | #define BIT27 0x08000000 | |
95 | #define BIT28 0x10000000 | |
96 | #define BIT29 0x20000000 | |
97 | #define BIT30 0x40000000 | |
98 | #define BIT31 0x80000000 | |
99 | ||
33aa8d45 MD |
100 | #define TEST_FORCE_ENABLE (BIT18+BIT16) |
101 | ||
102 | #define INT_SEL BIT10 | |
103 | #define CONSTFS BIT09 | |
104 | #define SOF_RCV BIT08 | |
105 | #define RSUM_IN BIT07 | |
106 | #define SUSPEND BIT06 | |
107 | #define CONF BIT05 | |
108 | #define DEFAULT BIT04 | |
109 | #define CONNECTB BIT03 | |
110 | #define PUE2 BIT02 | |
111 | ||
112 | #define MAX_TEST_MODE_NUM 0x05 | |
113 | #define TEST_MODE_SHIFT 16 | |
114 | ||
115 | /*------- (0x0004) USB Status Register */ | |
116 | #define SPEED_MODE BIT06 | |
117 | #define HIGH_SPEED BIT06 | |
118 | ||
119 | #define CONF BIT05 | |
120 | #define DEFAULT BIT04 | |
121 | #define USB_RST BIT03 | |
122 | #define SPND_OUT BIT02 | |
123 | #define RSUM_OUT BIT01 | |
124 | ||
125 | /*------- (0x0008) USB Address Register */ | |
126 | #define USB_ADDR 0x007F0000 | |
127 | #define SOF_STATUS BIT15 | |
128 | #define UFRAME (BIT14+BIT13+BIT12) | |
129 | #define FRAME 0x000007FF | |
130 | ||
131 | #define USB_ADRS_SHIFT 16 | |
132 | ||
133 | /*------- (0x000C) UTMI Characteristic 1 Register */ | |
134 | #define SQUSET (BIT07+BIT06+BIT05+BIT04) | |
135 | ||
136 | #define USB_SQUSET (BIT06+BIT05+BIT04) | |
137 | ||
138 | /*------- (0x0010) TEST Control Register */ | |
139 | #define FORCEHS BIT02 | |
140 | #define CS_TESTMODEEN BIT01 | |
141 | #define LOOPBACK BIT00 | |
142 | ||
143 | /*------- (0x0018) Setup Data 0 Register */ | |
144 | /*------- (0x001C) Setup Data 1 Register */ | |
145 | ||
146 | /*------- (0x0020) USB Interrupt Status Register */ | |
147 | #define EPn_INT 0x00FFFF00 | |
148 | #define EP15_INT BIT23 | |
149 | #define EP14_INT BIT22 | |
150 | #define EP13_INT BIT21 | |
151 | #define EP12_INT BIT20 | |
152 | #define EP11_INT BIT19 | |
153 | #define EP10_INT BIT18 | |
154 | #define EP9_INT BIT17 | |
155 | #define EP8_INT BIT16 | |
156 | #define EP7_INT BIT15 | |
157 | #define EP6_INT BIT14 | |
158 | #define EP5_INT BIT13 | |
159 | #define EP4_INT BIT12 | |
160 | #define EP3_INT BIT11 | |
161 | #define EP2_INT BIT10 | |
162 | #define EP1_INT BIT09 | |
163 | #define EP0_INT BIT08 | |
164 | #define SPEED_MODE_INT BIT06 | |
165 | #define SOF_ERROR_INT BIT05 | |
166 | #define SOF_INT BIT04 | |
167 | #define USB_RST_INT BIT03 | |
168 | #define SPND_INT BIT02 | |
169 | #define RSUM_INT BIT01 | |
170 | ||
171 | #define USB_INT_STA_RW 0x7E | |
172 | ||
173 | /*------- (0x0024) USB Interrupt Enable Register */ | |
174 | #define EP15_0_EN 0x00FFFF00 | |
175 | #define EP15_EN BIT23 | |
176 | #define EP14_EN BIT22 | |
177 | #define EP13_EN BIT21 | |
178 | #define EP12_EN BIT20 | |
179 | #define EP11_EN BIT19 | |
180 | #define EP10_EN BIT18 | |
181 | #define EP9_EN BIT17 | |
182 | #define EP8_EN BIT16 | |
183 | #define EP7_EN BIT15 | |
184 | #define EP6_EN BIT14 | |
185 | #define EP5_EN BIT13 | |
186 | #define EP4_EN BIT12 | |
187 | #define EP3_EN BIT11 | |
188 | #define EP2_EN BIT10 | |
189 | #define EP1_EN BIT09 | |
190 | #define EP0_EN BIT08 | |
191 | #define SPEED_MODE_EN BIT06 | |
192 | #define SOF_ERROR_EN BIT05 | |
193 | #define SOF_EN BIT04 | |
194 | #define USB_RST_EN BIT03 | |
195 | #define SPND_EN BIT02 | |
196 | #define RSUM_EN BIT01 | |
197 | ||
198 | #define USB_INT_EN_BIT \ | |
199 | (EP0_EN|SPEED_MODE_EN|USB_RST_EN|SPND_EN|RSUM_EN) | |
200 | ||
201 | /*------- (0x0028) EP0 Control Register */ | |
202 | #define EP0_STGSEL BIT18 | |
203 | #define EP0_OVERSEL BIT17 | |
204 | #define EP0_AUTO BIT16 | |
205 | #define EP0_PIDCLR BIT09 | |
206 | #define EP0_BCLR BIT08 | |
207 | #define EP0_DEND BIT07 | |
208 | #define EP0_DW (BIT06+BIT05) | |
209 | #define EP0_DW4 0 | |
210 | #define EP0_DW3 (BIT06+BIT05) | |
211 | #define EP0_DW2 BIT06 | |
212 | #define EP0_DW1 BIT05 | |
213 | ||
214 | #define EP0_INAK_EN BIT04 | |
215 | #define EP0_PERR_NAK_CLR BIT03 | |
216 | #define EP0_STL BIT02 | |
217 | #define EP0_INAK BIT01 | |
218 | #define EP0_ONAK BIT00 | |
219 | ||
220 | /*------- (0x002C) EP0 Status Register */ | |
221 | #define EP0_PID BIT18 | |
222 | #define EP0_PERR_NAK BIT17 | |
223 | #define EP0_PERR_NAK_INT BIT16 | |
224 | #define EP0_OUT_NAK_INT BIT15 | |
225 | #define EP0_OUT_NULL BIT14 | |
226 | #define EP0_OUT_FULL BIT13 | |
227 | #define EP0_OUT_EMPTY BIT12 | |
228 | #define EP0_IN_NAK_INT BIT11 | |
229 | #define EP0_IN_DATA BIT10 | |
230 | #define EP0_IN_FULL BIT09 | |
231 | #define EP0_IN_EMPTY BIT08 | |
232 | #define EP0_OUT_NULL_INT BIT07 | |
233 | #define EP0_OUT_OR_INT BIT06 | |
234 | #define EP0_OUT_INT BIT05 | |
235 | #define EP0_IN_INT BIT04 | |
236 | #define EP0_STALL_INT BIT03 | |
237 | #define STG_END_INT BIT02 | |
238 | #define STG_START_INT BIT01 | |
239 | #define SETUP_INT BIT00 | |
240 | ||
241 | #define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF) | |
242 | ||
243 | /*------- (0x0030) EP0 Interrupt Enable Register */ | |
244 | #define EP0_PERR_NAK_EN BIT16 | |
245 | #define EP0_OUT_NAK_EN BIT15 | |
246 | ||
247 | #define EP0_IN_NAK_EN BIT11 | |
248 | ||
249 | #define EP0_OUT_NULL_EN BIT07 | |
250 | #define EP0_OUT_OR_EN BIT06 | |
251 | #define EP0_OUT_EN BIT05 | |
252 | #define EP0_IN_EN BIT04 | |
253 | #define EP0_STALL_EN BIT03 | |
254 | #define STG_END_EN BIT02 | |
255 | #define STG_START_EN BIT01 | |
256 | #define SETUP_EN BIT00 | |
257 | ||
258 | #define EP0_INT_EN_BIT \ | |
259 | (EP0_OUT_OR_EN|EP0_OUT_EN|EP0_IN_EN|STG_END_EN|SETUP_EN) | |
260 | ||
261 | /*------- (0x0034) EP0 Length Register */ | |
262 | #define EP0_LDATA 0x0000007F | |
263 | ||
264 | /*------- (0x0038) EP0 Read Register */ | |
265 | /*------- (0x003C) EP0 Write Register */ | |
266 | ||
267 | /*------- (0x0040:) EPn Control Register */ | |
268 | #define EPn_EN BIT31 | |
269 | #define EPn_BUF_TYPE BIT30 | |
270 | #define EPn_BUF_SINGLE BIT30 | |
271 | ||
272 | #define EPn_DIR0 BIT26 | |
273 | #define EPn_MODE (BIT25+BIT24) | |
274 | #define EPn_BULK 0 | |
275 | #define EPn_INTERRUPT BIT24 | |
276 | #define EPn_ISO BIT25 | |
277 | ||
278 | #define EPn_OVERSEL BIT17 | |
279 | #define EPn_AUTO BIT16 | |
280 | ||
281 | #define EPn_IPIDCLR BIT11 | |
282 | #define EPn_OPIDCLR BIT10 | |
283 | #define EPn_BCLR BIT09 | |
284 | #define EPn_CBCLR BIT08 | |
285 | #define EPn_DEND BIT07 | |
286 | #define EPn_DW (BIT06+BIT05) | |
287 | #define EPn_DW4 0 | |
288 | #define EPn_DW3 (BIT06+BIT05) | |
289 | #define EPn_DW2 BIT06 | |
290 | #define EPn_DW1 BIT05 | |
291 | ||
292 | #define EPn_OSTL_EN BIT04 | |
293 | #define EPn_ISTL BIT03 | |
294 | #define EPn_OSTL BIT02 | |
295 | ||
296 | #define EPn_ONAK BIT00 | |
297 | ||
298 | /*------- (0x0044:) EPn Status Register */ | |
299 | #define EPn_ISO_PIDERR BIT29 /* R */ | |
300 | #define EPn_OPID BIT28 /* R */ | |
301 | #define EPn_OUT_NOTKN BIT27 /* R */ | |
302 | #define EPn_ISO_OR BIT26 /* R */ | |
303 | ||
304 | #define EPn_ISO_CRC BIT24 /* R */ | |
305 | #define EPn_OUT_END_INT BIT23 /* RW */ | |
306 | #define EPn_OUT_OR_INT BIT22 /* RW */ | |
307 | #define EPn_OUT_NAK_ERR_INT BIT21 /* RW */ | |
308 | #define EPn_OUT_STALL_INT BIT20 /* RW */ | |
309 | #define EPn_OUT_INT BIT19 /* RW */ | |
310 | #define EPn_OUT_NULL_INT BIT18 /* RW */ | |
311 | #define EPn_OUT_FULL BIT17 /* R */ | |
312 | #define EPn_OUT_EMPTY BIT16 /* R */ | |
313 | ||
314 | #define EPn_IPID BIT10 /* R */ | |
315 | #define EPn_IN_NOTKN BIT09 /* R */ | |
316 | #define EPn_ISO_UR BIT08 /* R */ | |
317 | #define EPn_IN_END_INT BIT07 /* RW */ | |
318 | ||
319 | #define EPn_IN_NAK_ERR_INT BIT05 /* RW */ | |
320 | #define EPn_IN_STALL_INT BIT04 /* RW */ | |
321 | #define EPn_IN_INT BIT03 /* RW */ | |
322 | #define EPn_IN_DATA BIT02 /* R */ | |
323 | #define EPn_IN_FULL BIT01 /* R */ | |
324 | #define EPn_IN_EMPTY BIT00 /* R */ | |
325 | ||
326 | #define EPn_INT_EN \ | |
327 | (EPn_OUT_END_INT|EPn_OUT_INT|EPn_IN_END_INT|EPn_IN_INT) | |
328 | ||
329 | /*------- (0x0048:) EPn Interrupt Enable Register */ | |
330 | #define EPn_OUT_END_EN BIT23 /* RW */ | |
331 | #define EPn_OUT_OR_EN BIT22 /* RW */ | |
332 | #define EPn_OUT_NAK_ERR_EN BIT21 /* RW */ | |
333 | #define EPn_OUT_STALL_EN BIT20 /* RW */ | |
334 | #define EPn_OUT_EN BIT19 /* RW */ | |
335 | #define EPn_OUT_NULL_EN BIT18 /* RW */ | |
336 | ||
337 | #define EPn_IN_END_EN BIT07 /* RW */ | |
338 | ||
339 | #define EPn_IN_NAK_ERR_EN BIT05 /* RW */ | |
340 | #define EPn_IN_STALL_EN BIT04 /* RW */ | |
341 | #define EPn_IN_EN BIT03 /* RW */ | |
342 | ||
343 | /*------- (0x004C:) EPn Interrupt Enable Register */ | |
344 | #define EPn_STOP_MODE BIT11 | |
345 | #define EPn_DEND_SET BIT10 | |
346 | #define EPn_BURST_SET BIT09 | |
347 | #define EPn_STOP_SET BIT08 | |
348 | ||
349 | #define EPn_DMA_EN BIT04 | |
350 | ||
351 | #define EPn_DMAMODE0 BIT00 | |
352 | ||
353 | /*------- (0x0050:) EPn MaxPacket & BaseAddress Register */ | |
354 | #define EPn_BASEAD 0x1FFF0000 | |
355 | #define EPn_MPKT 0x000007FF | |
356 | ||
357 | /*------- (0x0054:) EPn Length & DMA Count Register */ | |
358 | #define EPn_DMACNT 0x01FF0000 | |
359 | #define EPn_LDATA 0x000007FF | |
360 | ||
361 | /*------- (0x0058:) EPn Read Register */ | |
362 | /*------- (0x005C:) EPn Write Register */ | |
363 | ||
364 | /*------- (0x1000) AHBSCTR Register */ | |
365 | #define WAIT_MODE BIT00 | |
366 | ||
367 | /*------- (0x1004) AHBMCTR Register */ | |
368 | #define ARBITER_CTR BIT31 /* RW */ | |
369 | #define MCYCLE_RST BIT12 /* RW */ | |
370 | ||
371 | #define ENDIAN_CTR (BIT09+BIT08) /* RW */ | |
372 | #define ENDIAN_BYTE_SWAP BIT09 | |
373 | #define ENDIAN_HALF_WORD_SWAP ENDIAN_CTR | |
374 | ||
375 | #define HBUSREQ_MODE BIT05 /* RW */ | |
376 | #define HTRANS_MODE BIT04 /* RW */ | |
377 | ||
378 | #define WBURST_TYPE BIT02 /* RW */ | |
379 | #define BURST_TYPE (BIT01+BIT00) /* RW */ | |
380 | #define BURST_MAX_16 0 | |
381 | #define BURST_MAX_8 BIT00 | |
382 | #define BURST_MAX_4 BIT01 | |
383 | #define BURST_SINGLE BURST_TYPE | |
384 | ||
385 | /*------- (0x1008) AHBBINT Register */ | |
386 | #define DMA_ENDINT 0xFFFE0000 /* RW */ | |
387 | ||
388 | #define AHB_VBUS_INT BIT13 /* RW */ | |
389 | ||
390 | #define MBUS_ERRINT BIT06 /* RW */ | |
391 | ||
392 | #define SBUS_ERRINT0 BIT04 /* RW */ | |
393 | #define ERR_MASTER 0x0000000F /* R */ | |
394 | ||
395 | /*------- (0x100C) AHBBINTEN Register */ | |
396 | #define DMA_ENDINTEN 0xFFFE0000 /* RW */ | |
397 | ||
398 | #define VBUS_INTEN BIT13 /* RW */ | |
399 | ||
400 | #define MBUS_ERRINTEN BIT06 /* RW */ | |
401 | ||
402 | #define SBUS_ERRINT0EN BIT04 /* RW */ | |
403 | ||
404 | /*------- (0x1010) EPCTR Register */ | |
405 | #define DIRPD BIT12 /* RW */ | |
406 | ||
407 | #define VBUS_LEVEL BIT08 /* R */ | |
408 | ||
409 | #define PLL_RESUME BIT05 /* RW */ | |
410 | #define PLL_LOCK BIT04 /* R */ | |
411 | ||
33aa8d45 MD |
412 | #define EPC_RST BIT00 /* RW */ |
413 | ||
414 | /*------- (0x1014) USBF_EPTEST Register */ | |
415 | #define LINESTATE (BIT09+BIT08) /* R */ | |
416 | #define DM_LEVEL BIT09 /* R */ | |
417 | #define DP_LEVEL BIT08 /* R */ | |
418 | ||
419 | #define PHY_TST BIT01 /* RW */ | |
420 | #define PHY_TSTCLK BIT00 /* RW */ | |
421 | ||
422 | /*------- (0x1020) USBSSVER Register */ | |
423 | #define AHBB_VER 0x00FF0000 /* R */ | |
424 | #define EPC_VER 0x0000FF00 /* R */ | |
425 | #define SS_VER 0x000000FF /* R */ | |
426 | ||
427 | /*------- (0x1024) USBSSCONF Register */ | |
428 | #define EP_AVAILABLE 0xFFFF0000 /* R */ | |
429 | #define DMA_AVAILABLE 0x0000FFFF /* R */ | |
430 | ||
431 | /*------- (0x1110:) EPnDCR1 Register */ | |
432 | #define DCR1_EPn_DMACNT 0x00FF0000 /* RW */ | |
433 | ||
434 | #define DCR1_EPn_DIR0 BIT01 /* RW */ | |
435 | #define DCR1_EPn_REQEN BIT00 /* RW */ | |
436 | ||
437 | /*------- (0x1114:) EPnDCR2 Register */ | |
438 | #define DCR2_EPn_LMPKT 0x07FF0000 /* RW */ | |
439 | ||
440 | #define DCR2_EPn_MPKT 0x000007FF /* RW */ | |
441 | ||
442 | /*------- (0x1118:) EPnTADR Register */ | |
443 | #define EPn_TADR 0xFFFFFFFF /* RW */ | |
444 | ||
33aa8d45 MD |
445 | /*===========================================================================*/ |
446 | /* Struct */ | |
f6ef6c09 HM |
447 | /*------- ep_regs */ |
448 | struct ep_regs { | |
33aa8d45 MD |
449 | u32 EP_CONTROL; /* EP Control */ |
450 | u32 EP_STATUS; /* EP Status */ | |
451 | u32 EP_INT_ENA; /* EP Interrupt Enable */ | |
452 | u32 EP_DMA_CTRL; /* EP DMA Control */ | |
453 | u32 EP_PCKT_ADRS; /* EP Maxpacket & BaseAddress */ | |
454 | u32 EP_LEN_DCNT; /* EP Length & DMA count */ | |
455 | u32 EP_READ; /* EP Read */ | |
456 | u32 EP_WRITE; /* EP Write */ | |
f6ef6c09 | 457 | }; |
33aa8d45 | 458 | |
f6ef6c09 HM |
459 | /*------- ep_dcr */ |
460 | struct ep_dcr { | |
33aa8d45 MD |
461 | u32 EP_DCR1; /* EP_DCR1 */ |
462 | u32 EP_DCR2; /* EP_DCR2 */ | |
463 | u32 EP_TADR; /* EP_TADR */ | |
464 | u32 Reserved; /* Reserved */ | |
f6ef6c09 | 465 | }; |
33aa8d45 MD |
466 | |
467 | /*------- Function Registers */ | |
f6ef6c09 | 468 | struct fc_regs { |
33aa8d45 MD |
469 | u32 USB_CONTROL; /* (0x0000) USB Control */ |
470 | u32 USB_STATUS; /* (0x0004) USB Status */ | |
471 | u32 USB_ADDRESS; /* (0x0008) USB Address */ | |
472 | u32 UTMI_CHARACTER_1; /* (0x000C) UTMI Setting */ | |
473 | u32 TEST_CONTROL; /* (0x0010) TEST Control */ | |
474 | u32 Reserved_14; /* (0x0014) Reserved */ | |
475 | u32 SETUP_DATA0; /* (0x0018) Setup Data0 */ | |
476 | u32 SETUP_DATA1; /* (0x001C) Setup Data1 */ | |
477 | u32 USB_INT_STA; /* (0x0020) USB Interrupt Status */ | |
478 | u32 USB_INT_ENA; /* (0x0024) USB Interrupt Enable */ | |
479 | u32 EP0_CONTROL; /* (0x0028) EP0 Control */ | |
480 | u32 EP0_STATUS; /* (0x002C) EP0 Status */ | |
481 | u32 EP0_INT_ENA; /* (0x0030) EP0 Interrupt Enable */ | |
482 | u32 EP0_LENGTH; /* (0x0034) EP0 Length */ | |
483 | u32 EP0_READ; /* (0x0038) EP0 Read */ | |
484 | u32 EP0_WRITE; /* (0x003C) EP0 Write */ | |
485 | ||
f6ef6c09 | 486 | struct ep_regs EP_REGS[REG_EP_NUM]; /* Endpoint Register */ |
33aa8d45 MD |
487 | |
488 | u8 Reserved220[0x1000-0x220]; /* (0x0220:0x0FFF) Reserved */ | |
489 | ||
490 | u32 AHBSCTR; /* (0x1000) AHBSCTR */ | |
491 | u32 AHBMCTR; /* (0x1004) AHBMCTR */ | |
492 | u32 AHBBINT; /* (0x1008) AHBBINT */ | |
493 | u32 AHBBINTEN; /* (0x100C) AHBBINTEN */ | |
494 | u32 EPCTR; /* (0x1010) EPCTR */ | |
495 | u32 USBF_EPTEST; /* (0x1014) USBF_EPTEST */ | |
496 | ||
497 | u8 Reserved1018[0x20-0x18]; /* (0x1018:0x101F) Reserved */ | |
498 | ||
499 | u32 USBSSVER; /* (0x1020) USBSSVER */ | |
500 | u32 USBSSCONF; /* (0x1024) USBSSCONF */ | |
501 | ||
502 | u8 Reserved1028[0x110-0x28]; /* (0x1028:0x110F) Reserved */ | |
503 | ||
f6ef6c09 | 504 | struct ep_dcr EP_DCR[REG_EP_NUM]; /* */ |
33aa8d45 MD |
505 | |
506 | u8 Reserved1200[0x1000-0x200]; /* Reserved */ | |
f6ef6c09 | 507 | } __aligned(32); |
33aa8d45 | 508 | |
33aa8d45 MD |
509 | #define EP0_PACKETSIZE 64 |
510 | #define EP_PACKETSIZE 1024 | |
511 | ||
512 | /* EPn RAM SIZE */ | |
513 | #define D_RAM_SIZE_CTRL 64 | |
514 | ||
515 | /* EPn Bulk Endpoint Max Packet Size */ | |
516 | #define D_FS_RAM_SIZE_BULK 64 | |
517 | #define D_HS_RAM_SIZE_BULK 512 | |
518 | ||
33aa8d45 MD |
519 | struct nbu2ss_udc; |
520 | ||
33aa8d45 MD |
521 | enum ep0_state { |
522 | EP0_IDLE, | |
523 | EP0_IN_DATA_PHASE, | |
524 | EP0_OUT_DATA_PHASE, | |
525 | EP0_IN_STATUS_PHASE, | |
526 | EP0_OUT_STATUS_PAHSE, | |
527 | EP0_END_XFER, | |
528 | EP0_SUSPEND, | |
529 | EP0_STALL, | |
530 | }; | |
531 | ||
532 | struct nbu2ss_req { | |
533 | struct usb_request req; | |
534 | struct list_head queue; | |
535 | ||
536 | u32 div_len; | |
537 | bool dma_flag; | |
538 | bool zero; | |
539 | ||
540 | bool unaligned; | |
541 | ||
542 | unsigned mapped:1; | |
543 | }; | |
544 | ||
545 | struct nbu2ss_ep { | |
546 | struct usb_ep ep; | |
547 | struct list_head queue; | |
548 | ||
549 | struct nbu2ss_udc *udc; | |
550 | ||
551 | const struct usb_endpoint_descriptor *desc; | |
552 | ||
553 | u8 epnum; | |
554 | u8 direct; | |
555 | u8 ep_type; | |
556 | ||
557 | unsigned wedged:1; | |
558 | unsigned halted:1; | |
559 | unsigned stalled:1; | |
560 | ||
561 | u8 *virt_buf; | |
562 | dma_addr_t phys_buf; | |
563 | }; | |
564 | ||
33aa8d45 MD |
565 | struct nbu2ss_udc { |
566 | struct usb_gadget gadget; | |
567 | struct usb_gadget_driver *driver; | |
568 | struct platform_device *pdev; | |
569 | struct device *dev; | |
570 | spinlock_t lock; | |
571 | struct completion *pdone; | |
572 | ||
573 | enum ep0_state ep0state; | |
574 | enum usb_device_state devstate; | |
575 | struct usb_ctrlrequest ctrl; | |
576 | struct nbu2ss_req ep0_req; | |
577 | u8 ep0_buf[EP0_PACKETSIZE]; | |
578 | ||
579 | struct nbu2ss_ep ep[NUM_ENDPOINTS]; | |
580 | ||
581 | unsigned softconnect:1; | |
582 | unsigned vbus_active:1; | |
583 | unsigned linux_suspended:1; | |
584 | unsigned linux_resume:1; | |
585 | unsigned usb_suspended:1; | |
33aa8d45 MD |
586 | unsigned remote_wakeup:1; |
587 | unsigned udc_enabled:1; | |
588 | ||
589 | unsigned mA; | |
590 | ||
591 | u32 curr_config; /* Current Configuration Number */ | |
592 | ||
f6ef6c09 | 593 | struct fc_regs *p_regs; |
33aa8d45 MD |
594 | }; |
595 | ||
596 | /* USB register access structure */ | |
f6ef6c09 | 597 | union usb_reg_access { |
33aa8d45 MD |
598 | struct { |
599 | unsigned char DATA[4]; | |
600 | } byte; | |
601 | unsigned int dw; | |
f6ef6c09 | 602 | }; |
33aa8d45 MD |
603 | |
604 | /*-------------------------------------------------------------------------*/ | |
33aa8d45 MD |
605 | |
606 | #endif /* _LINUX_EMXX_H */ |