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d2796743 ME |
1 | /* |
2 | * Agere Systems Inc. | |
3 | * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs | |
4 | * | |
5 | * Copyright © 2005 Agere Systems Inc. | |
6 | * All rights reserved. | |
7 | * http://www.agere.com | |
8 | * | |
9 | * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com> | |
10 | * | |
11 | *------------------------------------------------------------------------------ | |
12 | * | |
13 | * SOFTWARE LICENSE | |
14 | * | |
15 | * This software is provided subject to the following terms and conditions, | |
16 | * which you should read carefully before using the software. Using this | |
17 | * software indicates your acceptance of these terms and conditions. If you do | |
18 | * not agree with these terms and conditions, do not use the software. | |
19 | * | |
20 | * Copyright © 2005 Agere Systems Inc. | |
21 | * All rights reserved. | |
22 | * | |
23 | * Redistribution and use in source or binary forms, with or without | |
24 | * modifications, are permitted provided that the following conditions are met: | |
25 | * | |
26 | * . Redistributions of source code must retain the above copyright notice, this | |
27 | * list of conditions and the following Disclaimer as comments in the code as | |
28 | * well as in the documentation and/or other materials provided with the | |
29 | * distribution. | |
30 | * | |
31 | * . Redistributions in binary form must reproduce the above copyright notice, | |
32 | * this list of conditions and the following Disclaimer in the documentation | |
33 | * and/or other materials provided with the distribution. | |
34 | * | |
35 | * . Neither the name of Agere Systems Inc. nor the names of the contributors | |
36 | * may be used to endorse or promote products derived from this software | |
37 | * without specific prior written permission. | |
38 | * | |
39 | * Disclaimer | |
40 | * | |
41 | * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, | |
42 | * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF | |
43 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY | |
44 | * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN | |
45 | * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY | |
46 | * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES | |
47 | * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; | |
48 | * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND | |
49 | * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT | |
50 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT | |
51 | * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH | |
52 | * DAMAGE. | |
53 | * | |
54 | */ | |
55 | ||
e58b89da TY |
56 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
57 | ||
d2796743 ME |
58 | #include <linux/pci.h> |
59 | #include <linux/init.h> | |
60 | #include <linux/module.h> | |
61 | #include <linux/types.h> | |
62 | #include <linux/kernel.h> | |
63 | ||
64 | #include <linux/sched.h> | |
65 | #include <linux/ptrace.h> | |
66 | #include <linux/slab.h> | |
67 | #include <linux/ctype.h> | |
68 | #include <linux/string.h> | |
69 | #include <linux/timer.h> | |
70 | #include <linux/interrupt.h> | |
71 | #include <linux/in.h> | |
72 | #include <linux/delay.h> | |
73 | #include <linux/bitops.h> | |
74 | #include <linux/io.h> | |
d2796743 ME |
75 | |
76 | #include <linux/netdevice.h> | |
77 | #include <linux/etherdevice.h> | |
78 | #include <linux/skbuff.h> | |
79 | #include <linux/if_arp.h> | |
80 | #include <linux/ioport.h> | |
81 | #include <linux/crc32.h> | |
82 | #include <linux/random.h> | |
83 | #include <linux/phy.h> | |
84 | ||
d2796743 ME |
85 | #include "et131x.h" |
86 | ||
87 | MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>"); | |
88 | MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>"); | |
89 | MODULE_LICENSE("Dual BSD/GPL"); | |
397d3e60 | 90 | MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems"); |
d2796743 | 91 | |
bd156af6 ME |
92 | /* EEPROM defines */ |
93 | #define MAX_NUM_REGISTER_POLLS 1000 | |
94 | #define MAX_NUM_WRITE_RETRIES 2 | |
95 | ||
96 | /* MAC defines */ | |
97 | #define COUNTER_WRAP_16_BIT 0x10000 | |
98 | #define COUNTER_WRAP_12_BIT 0x1000 | |
99 | ||
100 | /* PCI defines */ | |
101 | #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */ | |
102 | #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */ | |
103 | ||
104 | /* ISR defines */ | |
105 | /* | |
106 | * For interrupts, normal running is: | |
107 | * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt, | |
108 | * watchdog_interrupt & txdma_xfer_done | |
109 | * | |
110 | * In both cases, when flow control is enabled for either Tx or bi-direction, | |
111 | * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the | |
112 | * buffer rings are running low. | |
113 | */ | |
114 | #define INT_MASK_DISABLE 0xffffffff | |
115 | ||
116 | /* NOTE: Masking out MAC_STAT Interrupt for now... | |
117 | * #define INT_MASK_ENABLE 0xfff6bf17 | |
118 | * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7 | |
119 | */ | |
120 | #define INT_MASK_ENABLE 0xfffebf17 | |
121 | #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7 | |
122 | ||
1c1c1b5f ME |
123 | /* General defines */ |
124 | /* Packet and header sizes */ | |
125 | #define NIC_MIN_PACKET_SIZE 60 | |
126 | ||
127 | /* Multicast list size */ | |
128 | #define NIC_MAX_MCAST_LIST 128 | |
129 | ||
130 | /* Supported Filters */ | |
131 | #define ET131X_PACKET_TYPE_DIRECTED 0x0001 | |
132 | #define ET131X_PACKET_TYPE_MULTICAST 0x0002 | |
133 | #define ET131X_PACKET_TYPE_BROADCAST 0x0004 | |
134 | #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008 | |
135 | #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010 | |
136 | ||
137 | /* Tx Timeout */ | |
138 | #define ET131X_TX_TIMEOUT (1 * HZ) | |
139 | #define NIC_SEND_HANG_THRESHOLD 0 | |
140 | ||
141 | /* MP_TCB flags */ | |
142 | #define fMP_DEST_MULTI 0x00000001 | |
143 | #define fMP_DEST_BROAD 0x00000002 | |
144 | ||
145 | /* MP_ADAPTER flags */ | |
1c1c1b5f | 146 | #define fMP_ADAPTER_INTERRUPT_IN_USE 0x00000008 |
1c1c1b5f ME |
147 | |
148 | /* MP_SHARED flags */ | |
1c1c1b5f ME |
149 | #define fMP_ADAPTER_LOWER_POWER 0x00200000 |
150 | ||
151 | #define fMP_ADAPTER_NON_RECOVER_ERROR 0x00800000 | |
1c1c1b5f | 152 | #define fMP_ADAPTER_HARDWARE_ERROR 0x04000000 |
1c1c1b5f ME |
153 | |
154 | #define fMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000 | |
1c1c1b5f ME |
155 | |
156 | /* Some offsets in PCI config space that are actually used. */ | |
1c1c1b5f ME |
157 | #define ET1310_PCI_MAC_ADDRESS 0xA4 |
158 | #define ET1310_PCI_EEPROM_STATUS 0xB2 | |
159 | #define ET1310_PCI_ACK_NACK 0xC0 | |
160 | #define ET1310_PCI_REPLAY 0xC2 | |
161 | #define ET1310_PCI_L0L1LATENCY 0xCF | |
162 | ||
26d19bf6 | 163 | /* PCI Product IDs */ |
1c1c1b5f ME |
164 | #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */ |
165 | #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */ | |
166 | ||
167 | /* Define order of magnitude converter */ | |
168 | #define NANO_IN_A_MICRO 1000 | |
169 | ||
170 | #define PARM_RX_NUM_BUFS_DEF 4 | |
171 | #define PARM_RX_TIME_INT_DEF 10 | |
172 | #define PARM_RX_MEM_END_DEF 0x2bc | |
173 | #define PARM_TX_TIME_INT_DEF 40 | |
174 | #define PARM_TX_NUM_BUFS_DEF 4 | |
175 | #define PARM_DMA_CACHE_DEF 0 | |
176 | ||
562550b0 | 177 | /* RX defines */ |
788ca84a ME |
178 | #define FBR_CHUNKS 32 |
179 | #define MAX_DESC_PER_RING_RX 1024 | |
562550b0 ME |
180 | |
181 | /* number of RFDs - default and min */ | |
562550b0 | 182 | #define RFD_LOW_WATER_MARK 40 |
562550b0 | 183 | #define NIC_DEFAULT_NUM_RFD 1024 |
6abafc16 | 184 | #define NUM_FBRS 2 |
562550b0 ME |
185 | |
186 | #define NUM_PACKETS_HANDLED 256 | |
187 | ||
562550b0 ME |
188 | #define ALCATEL_MULTICAST_PKT 0x01000000 |
189 | #define ALCATEL_BROADCAST_PKT 0x02000000 | |
190 | ||
191 | /* typedefs for Free Buffer Descriptors */ | |
192 | struct fbr_desc { | |
193 | u32 addr_lo; | |
194 | u32 addr_hi; | |
195 | u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */ | |
196 | }; | |
197 | ||
198 | /* Packet Status Ring Descriptors | |
199 | * | |
200 | * Word 0: | |
201 | * | |
202 | * top 16 bits are from the Alcatel Status Word as enumerated in | |
203 | * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2) | |
204 | * | |
205 | * 0: hp hash pass | |
206 | * 1: ipa IP checksum assist | |
207 | * 2: ipp IP checksum pass | |
208 | * 3: tcpa TCP checksum assist | |
209 | * 4: tcpp TCP checksum pass | |
210 | * 5: wol WOL Event | |
211 | * 6: rxmac_error RXMAC Error Indicator | |
212 | * 7: drop Drop packet | |
213 | * 8: ft Frame Truncated | |
214 | * 9: jp Jumbo Packet | |
215 | * 10: vp VLAN Packet | |
216 | * 11-15: unused | |
217 | * 16: asw_prev_pkt_dropped e.g. IFG too small on previous | |
218 | * 17: asw_RX_DV_event short receive event detected | |
219 | * 18: asw_false_carrier_event bad carrier since last good packet | |
220 | * 19: asw_code_err one or more nibbles signalled as errors | |
221 | * 20: asw_CRC_err CRC error | |
222 | * 21: asw_len_chk_err frame length field incorrect | |
223 | * 22: asw_too_long frame length > 1518 bytes | |
224 | * 23: asw_OK valid CRC + no code error | |
225 | * 24: asw_multicast has a multicast address | |
226 | * 25: asw_broadcast has a broadcast address | |
227 | * 26: asw_dribble_nibble spurious bits after EOP | |
228 | * 27: asw_control_frame is a control frame | |
229 | * 28: asw_pause_frame is a pause frame | |
230 | * 29: asw_unsupported_op unsupported OP code | |
231 | * 30: asw_VLAN_tag VLAN tag detected | |
232 | * 31: asw_long_evt Rx long event | |
233 | * | |
234 | * Word 1: | |
235 | * 0-15: length length in bytes | |
236 | * 16-25: bi Buffer Index | |
237 | * 26-27: ri Ring Index | |
238 | * 28-31: reserved | |
239 | */ | |
240 | ||
241 | struct pkt_stat_desc { | |
242 | u32 word0; | |
243 | u32 word1; | |
244 | }; | |
245 | ||
246 | /* Typedefs for the RX DMA status word */ | |
247 | ||
248 | /* | |
249 | * rx status word 0 holds part of the status bits of the Rx DMA engine | |
250 | * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word | |
251 | * which contains the Free Buffer ring 0 and 1 available offset. | |
252 | * | |
253 | * bit 0-9 FBR1 offset | |
254 | * bit 10 Wrap flag for FBR1 | |
255 | * bit 16-25 FBR0 offset | |
256 | * bit 26 Wrap flag for FBR0 | |
257 | */ | |
258 | ||
259 | /* | |
260 | * RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine | |
261 | * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word | |
262 | * which contains the Packet Status Ring available offset. | |
263 | * | |
264 | * bit 0-15 reserved | |
265 | * bit 16-27 PSRoffset | |
266 | * bit 28 PSRwrap | |
267 | * bit 29-31 unused | |
268 | */ | |
269 | ||
270 | /* | |
271 | * struct rx_status_block is a structure representing the status of the Rx | |
272 | * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020 | |
273 | */ | |
274 | struct rx_status_block { | |
275 | u32 word0; | |
276 | u32 word1; | |
277 | }; | |
278 | ||
279 | /* | |
6abafc16 ME |
280 | * Structure for look-up table holding free buffer ring pointers, addresses |
281 | * and state. | |
562550b0 ME |
282 | */ |
283 | struct fbr_lookup { | |
6abafc16 | 284 | void *virt[MAX_DESC_PER_RING_RX]; |
6abafc16 ME |
285 | u32 bus_high[MAX_DESC_PER_RING_RX]; |
286 | u32 bus_low[MAX_DESC_PER_RING_RX]; | |
287 | void *ring_virtaddr; | |
288 | dma_addr_t ring_physaddr; | |
289 | void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; | |
290 | dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS]; | |
6abafc16 ME |
291 | u32 local_full; |
292 | u32 num_entries; | |
983e4b35 | 293 | dma_addr_t buffsize; |
562550b0 ME |
294 | }; |
295 | ||
296 | /* | |
297 | * struct rx_ring is the sructure representing the adaptor's local | |
298 | * reference(s) to the rings | |
299 | */ | |
300 | struct rx_ring { | |
6abafc16 | 301 | struct fbr_lookup *fbr[NUM_FBRS]; |
562550b0 ME |
302 | void *ps_ring_virtaddr; |
303 | dma_addr_t ps_ring_physaddr; | |
304 | u32 local_psr_full; | |
305 | u32 psr_num_entries; | |
306 | ||
307 | struct rx_status_block *rx_status_block; | |
308 | dma_addr_t rx_status_bus; | |
309 | ||
562550b0 ME |
310 | /* RECV */ |
311 | struct list_head recv_list; | |
312 | u32 num_ready_recv; | |
313 | ||
314 | u32 num_rfd; | |
315 | ||
316 | bool unfinished_receives; | |
562550b0 ME |
317 | }; |
318 | ||
17ec9ff3 ME |
319 | /* TX defines */ |
320 | /* | |
321 | * word 2 of the control bits in the Tx Descriptor ring for the ET-1310 | |
322 | * | |
323 | * 0-15: length of packet | |
324 | * 16-27: VLAN tag | |
325 | * 28: VLAN CFI | |
326 | * 29-31: VLAN priority | |
327 | * | |
328 | * word 3 of the control bits in the Tx Descriptor ring for the ET-1310 | |
329 | * | |
330 | * 0: last packet in the sequence | |
331 | * 1: first packet in the sequence | |
332 | * 2: interrupt the processor when this pkt sent | |
333 | * 3: Control word - no packet data | |
334 | * 4: Issue half-duplex backpressure : XON/XOFF | |
335 | * 5: send pause frame | |
336 | * 6: Tx frame has error | |
337 | * 7: append CRC | |
338 | * 8: MAC override | |
339 | * 9: pad packet | |
340 | * 10: Packet is a Huge packet | |
341 | * 11: append VLAN tag | |
342 | * 12: IP checksum assist | |
343 | * 13: TCP checksum assist | |
344 | * 14: UDP checksum assist | |
345 | */ | |
346 | ||
a129be84 ME |
347 | #define TXDESC_FLAG_LASTPKT 0x0001 |
348 | #define TXDESC_FLAG_FIRSTPKT 0x0002 | |
349 | #define TXDESC_FLAG_INTPROC 0x0004 | |
350 | ||
17ec9ff3 ME |
351 | /* struct tx_desc represents each descriptor on the ring */ |
352 | struct tx_desc { | |
353 | u32 addr_hi; | |
354 | u32 addr_lo; | |
355 | u32 len_vlan; /* control words how to xmit the */ | |
356 | u32 flags; /* data (detailed above) */ | |
357 | }; | |
358 | ||
359 | /* | |
360 | * The status of the Tx DMA engine it sits in free memory, and is pointed to | |
361 | * by 0x101c / 0x1020. This is a DMA10 type | |
362 | */ | |
363 | ||
364 | /* TCB (Transmit Control Block: Host Side) */ | |
365 | struct tcb { | |
366 | struct tcb *next; /* Next entry in ring */ | |
367 | u32 flags; /* Our flags for the packet */ | |
368 | u32 count; /* Used to spot stuck/lost packets */ | |
369 | u32 stale; /* Used to spot stuck/lost packets */ | |
370 | struct sk_buff *skb; /* Network skb we are tied to */ | |
371 | u32 index; /* Ring indexes */ | |
372 | u32 index_start; | |
373 | }; | |
374 | ||
375 | /* Structure representing our local reference(s) to the ring */ | |
376 | struct tx_ring { | |
377 | /* TCB (Transmit Control Block) memory and lists */ | |
378 | struct tcb *tcb_ring; | |
379 | ||
380 | /* List of TCBs that are ready to be used */ | |
381 | struct tcb *tcb_qhead; | |
382 | struct tcb *tcb_qtail; | |
383 | ||
384 | /* list of TCBs that are currently being sent. NOTE that access to all | |
385 | * three of these (including used) are controlled via the | |
386 | * TCBSendQLock. This lock should be secured prior to incementing / | |
387 | * decrementing used, or any queue manipulation on send_head / | |
388 | * tail | |
389 | */ | |
390 | struct tcb *send_head; | |
391 | struct tcb *send_tail; | |
392 | int used; | |
393 | ||
394 | /* The actual descriptor ring */ | |
395 | struct tx_desc *tx_desc_ring; | |
396 | dma_addr_t tx_desc_ring_pa; | |
397 | ||
398 | /* send_idx indicates where we last wrote to in the descriptor ring. */ | |
399 | u32 send_idx; | |
400 | ||
401 | /* The location of the write-back status block */ | |
402 | u32 *tx_status; | |
403 | dma_addr_t tx_status_pa; | |
404 | ||
405 | /* Packets since the last IRQ: used for interrupt coalescing */ | |
406 | int since_irq; | |
407 | }; | |
408 | ||
fd0651a6 ME |
409 | /* |
410 | * Do not change these values: if changed, then change also in respective | |
411 | * TXdma and Rxdma engines | |
412 | */ | |
413 | #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */ | |
414 | #define NUM_TCB 64 | |
415 | ||
416 | /* | |
417 | * These values are all superseded by registry entries to facilitate tuning. | |
418 | * Once the desired performance has been achieved, the optimal registry values | |
419 | * should be re-populated to these #defines: | |
420 | */ | |
fd0651a6 ME |
421 | #define TX_ERROR_PERIOD 1000 |
422 | ||
423 | #define LO_MARK_PERCENT_FOR_PSR 15 | |
424 | #define LO_MARK_PERCENT_FOR_RX 15 | |
425 | ||
426 | /* RFD (Receive Frame Descriptor) */ | |
427 | struct rfd { | |
428 | struct list_head list_node; | |
429 | struct sk_buff *skb; | |
430 | u32 len; /* total size of receive frame */ | |
431 | u16 bufferindex; | |
432 | u8 ringindex; | |
433 | }; | |
434 | ||
435 | /* Flow Control */ | |
436 | #define FLOW_BOTH 0 | |
437 | #define FLOW_TXONLY 1 | |
438 | #define FLOW_RXONLY 2 | |
439 | #define FLOW_NONE 3 | |
440 | ||
441 | /* Struct to define some device statistics */ | |
442 | struct ce_stats { | |
443 | /* MIB II variables | |
444 | * | |
445 | * NOTE: atomic_t types are only guaranteed to store 24-bits; if we | |
446 | * MUST have 32, then we'll need another way to perform atomic | |
447 | * operations | |
448 | */ | |
449 | u32 unicast_pkts_rcvd; | |
450 | atomic_t unicast_pkts_xmtd; | |
451 | u32 multicast_pkts_rcvd; | |
452 | atomic_t multicast_pkts_xmtd; | |
453 | u32 broadcast_pkts_rcvd; | |
454 | atomic_t broadcast_pkts_xmtd; | |
455 | u32 rcvd_pkts_dropped; | |
456 | ||
457 | /* Tx Statistics. */ | |
458 | u32 tx_underflows; | |
459 | ||
460 | u32 tx_collisions; | |
461 | u32 tx_excessive_collisions; | |
462 | u32 tx_first_collisions; | |
463 | u32 tx_late_collisions; | |
464 | u32 tx_max_pkt_errs; | |
465 | u32 tx_deferred; | |
466 | ||
467 | /* Rx Statistics. */ | |
468 | u32 rx_overflows; | |
469 | ||
470 | u32 rx_length_errs; | |
471 | u32 rx_align_errs; | |
472 | u32 rx_crc_errs; | |
473 | u32 rx_code_violations; | |
474 | u32 rx_other_errs; | |
475 | ||
476 | u32 synchronous_iterations; | |
477 | u32 interrupt_status; | |
478 | }; | |
479 | ||
480 | /* The private adapter structure */ | |
481 | struct et131x_adapter { | |
482 | struct net_device *netdev; | |
483 | struct pci_dev *pdev; | |
484 | struct mii_bus *mii_bus; | |
485 | struct phy_device *phydev; | |
486 | struct work_struct task; | |
487 | ||
488 | /* Flags that indicate current state of the adapter */ | |
489 | u32 flags; | |
490 | ||
491 | /* local link state, to determine if a state change has occurred */ | |
492 | int link; | |
493 | ||
494 | /* Configuration */ | |
495 | u8 rom_addr[ETH_ALEN]; | |
496 | u8 addr[ETH_ALEN]; | |
497 | bool has_eeprom; | |
498 | u8 eeprom_data[2]; | |
499 | ||
500 | /* Spinlocks */ | |
501 | spinlock_t lock; | |
502 | ||
503 | spinlock_t tcb_send_qlock; | |
504 | spinlock_t tcb_ready_qlock; | |
505 | spinlock_t send_hw_lock; | |
506 | ||
507 | spinlock_t rcv_lock; | |
508 | spinlock_t rcv_pend_lock; | |
509 | spinlock_t fbr_lock; | |
510 | ||
511 | spinlock_t phy_lock; | |
512 | ||
513 | /* Packet Filter and look ahead size */ | |
514 | u32 packet_filter; | |
515 | ||
516 | /* multicast list */ | |
517 | u32 multicast_addr_count; | |
518 | u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN]; | |
519 | ||
520 | /* Pointer to the device's PCI register space */ | |
521 | struct address_map __iomem *regs; | |
522 | ||
523 | /* Registry parameters */ | |
524 | u8 wanted_flow; /* Flow we want for 802.3x flow control */ | |
525 | u32 registry_jumbo_packet; /* Max supported ethernet packet size */ | |
526 | ||
527 | /* Derived from the registry: */ | |
528 | u8 flowcontrol; /* flow control validated by the far-end */ | |
529 | ||
530 | /* Minimize init-time */ | |
531 | struct timer_list error_timer; | |
532 | ||
533 | /* variable putting the phy into coma mode when boot up with no cable | |
534 | * plugged in after 5 seconds | |
535 | */ | |
536 | u8 boot_coma; | |
537 | ||
538 | /* Next two used to save power information at power down. This | |
539 | * information will be used during power up to set up parts of Power | |
540 | * Management in JAGCore | |
541 | */ | |
542 | u16 pdown_speed; | |
543 | u8 pdown_duplex; | |
544 | ||
545 | /* Tx Memory Variables */ | |
546 | struct tx_ring tx_ring; | |
547 | ||
548 | /* Rx Memory Variables */ | |
549 | struct rx_ring rx_ring; | |
550 | ||
551 | /* Stats */ | |
552 | struct ce_stats stats; | |
553 | ||
554 | struct net_device_stats net_stats; | |
555 | }; | |
556 | ||
d2796743 ME |
557 | static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status) |
558 | { | |
559 | u32 reg; | |
560 | int i; | |
561 | ||
562 | /* | |
563 | * 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and | |
564 | * bits 7,1:0 both equal to 1, at least once after reset. | |
565 | * Subsequent operations need only to check that bits 1:0 are equal | |
566 | * to 1 prior to starting a single byte read/write | |
567 | */ | |
568 | ||
569 | for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) { | |
570 | /* Read registers grouped in DWORD1 */ | |
571 | if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®)) | |
572 | return -EIO; | |
573 | ||
574 | /* I2C idle and Phy Queue Avail both true */ | |
575 | if ((reg & 0x3000) == 0x3000) { | |
576 | if (status) | |
577 | *status = reg; | |
578 | return reg & 0xFF; | |
579 | } | |
580 | } | |
581 | return -ETIMEDOUT; | |
582 | } | |
583 | ||
d2796743 ME |
584 | /** |
585 | * eeprom_write - Write a byte to the ET1310's EEPROM | |
586 | * @adapter: pointer to our private adapter structure | |
587 | * @addr: the address to write | |
588 | * @data: the value to write | |
589 | * | |
590 | * Returns 1 for a successful write. | |
591 | */ | |
592 | static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data) | |
593 | { | |
594 | struct pci_dev *pdev = adapter->pdev; | |
595 | int index = 0; | |
596 | int retries; | |
597 | int err = 0; | |
598 | int i2c_wack = 0; | |
599 | int writeok = 0; | |
600 | u32 status; | |
601 | u32 val = 0; | |
602 | ||
603 | /* | |
604 | * For an EEPROM, an I2C single byte write is defined as a START | |
605 | * condition followed by the device address, EEPROM address, one byte | |
606 | * of data and a STOP condition. The STOP condition will trigger the | |
607 | * EEPROM's internally timed write cycle to the nonvolatile memory. | |
608 | * All inputs are disabled during this write cycle and the EEPROM will | |
609 | * not respond to any access until the internal write is complete. | |
610 | */ | |
611 | ||
612 | err = eeprom_wait_ready(pdev, NULL); | |
613 | if (err) | |
614 | return err; | |
615 | ||
616 | /* | |
617 | * 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0, | |
618 | * and bits 1:0 both =0. Bit 5 should be set according to the | |
619 | * type of EEPROM being accessed (1=two byte addressing, 0=one | |
620 | * byte addressing). | |
621 | */ | |
622 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, | |
623 | LBCIF_CONTROL_LBCIF_ENABLE | LBCIF_CONTROL_I2C_WRITE)) | |
624 | return -EIO; | |
625 | ||
626 | i2c_wack = 1; | |
627 | ||
628 | /* Prepare EEPROM address for Step 3 */ | |
629 | ||
630 | for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) { | |
631 | /* Write the address to the LBCIF Address Register */ | |
632 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr)) | |
633 | break; | |
634 | /* | |
635 | * Write the data to the LBCIF Data Register (the I2C write | |
636 | * will begin). | |
637 | */ | |
638 | if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data)) | |
639 | break; | |
640 | /* | |
641 | * Monitor bit 1:0 of the LBCIF Status Register. When bits | |
642 | * 1:0 are both equal to 1, the I2C write has completed and the | |
643 | * internal write cycle of the EEPROM is about to start. | |
644 | * (bits 1:0 = 01 is a legal state while waiting from both | |
645 | * equal to 1, but bits 1:0 = 10 is invalid and implies that | |
646 | * something is broken). | |
647 | */ | |
648 | err = eeprom_wait_ready(pdev, &status); | |
649 | if (err < 0) | |
650 | return 0; | |
651 | ||
652 | /* | |
653 | * Check bit 3 of the LBCIF Status Register. If equal to 1, | |
654 | * an error has occurred.Don't break here if we are revision | |
655 | * 1, this is so we do a blind write for load bug. | |
656 | */ | |
657 | if ((status & LBCIF_STATUS_GENERAL_ERROR) | |
658 | && adapter->pdev->revision == 0) | |
659 | break; | |
660 | ||
661 | /* | |
662 | * Check bit 2 of the LBCIF Status Register. If equal to 1 an | |
663 | * ACK error has occurred on the address phase of the write. | |
664 | * This could be due to an actual hardware failure or the | |
665 | * EEPROM may still be in its internal write cycle from a | |
666 | * previous write. This write operation was ignored and must be | |
667 | *repeated later. | |
668 | */ | |
669 | if (status & LBCIF_STATUS_ACK_ERROR) { | |
670 | /* | |
671 | * This could be due to an actual hardware failure | |
672 | * or the EEPROM may still be in its internal write | |
673 | * cycle from a previous write. This write operation | |
674 | * was ignored and must be repeated later. | |
675 | */ | |
676 | udelay(10); | |
677 | continue; | |
678 | } | |
679 | ||
680 | writeok = 1; | |
681 | break; | |
682 | } | |
683 | ||
684 | /* | |
685 | * Set bit 6 of the LBCIF Control Register = 0. | |
686 | */ | |
687 | udelay(10); | |
688 | ||
689 | while (i2c_wack) { | |
690 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, | |
691 | LBCIF_CONTROL_LBCIF_ENABLE)) | |
692 | writeok = 0; | |
693 | ||
694 | /* Do read until internal ACK_ERROR goes away meaning write | |
695 | * completed | |
696 | */ | |
697 | do { | |
698 | pci_write_config_dword(pdev, | |
699 | LBCIF_ADDRESS_REGISTER, | |
700 | addr); | |
701 | do { | |
702 | pci_read_config_dword(pdev, | |
703 | LBCIF_DATA_REGISTER, &val); | |
704 | } while ((val & 0x00010000) == 0); | |
705 | } while (val & 0x00040000); | |
706 | ||
707 | if ((val & 0xFF00) != 0xC000 || index == 10000) | |
708 | break; | |
709 | index++; | |
710 | } | |
711 | return writeok ? 0 : -EIO; | |
712 | } | |
713 | ||
714 | /** | |
715 | * eeprom_read - Read a byte from the ET1310's EEPROM | |
716 | * @adapter: pointer to our private adapter structure | |
717 | * @addr: the address from which to read | |
718 | * @pdata: a pointer to a byte in which to store the value of the read | |
719 | * @eeprom_id: the ID of the EEPROM | |
720 | * @addrmode: how the EEPROM is to be accessed | |
721 | * | |
722 | * Returns 1 for a successful read | |
723 | */ | |
724 | static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata) | |
725 | { | |
726 | struct pci_dev *pdev = adapter->pdev; | |
727 | int err; | |
728 | u32 status; | |
729 | ||
730 | /* | |
731 | * A single byte read is similar to the single byte write, with the | |
732 | * exception of the data flow: | |
733 | */ | |
734 | ||
735 | err = eeprom_wait_ready(pdev, NULL); | |
736 | if (err) | |
737 | return err; | |
738 | /* | |
739 | * Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0, | |
740 | * and bits 1:0 both =0. Bit 5 should be set according to the type | |
741 | * of EEPROM being accessed (1=two byte addressing, 0=one byte | |
742 | * addressing). | |
743 | */ | |
744 | if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER, | |
745 | LBCIF_CONTROL_LBCIF_ENABLE)) | |
746 | return -EIO; | |
747 | /* | |
748 | * Write the address to the LBCIF Address Register (I2C read will | |
749 | * begin). | |
750 | */ | |
751 | if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr)) | |
752 | return -EIO; | |
753 | /* | |
754 | * Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read | |
755 | * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure | |
756 | * has occurred). | |
757 | */ | |
758 | err = eeprom_wait_ready(pdev, &status); | |
759 | if (err < 0) | |
760 | return err; | |
761 | /* | |
762 | * Regardless of error status, read data byte from LBCIF Data | |
763 | * Register. | |
764 | */ | |
765 | *pdata = err; | |
766 | /* | |
767 | * Check bit 2 of the LBCIF Status Register. If = 1, | |
768 | * then an error has occurred. | |
769 | */ | |
770 | return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0; | |
771 | } | |
772 | ||
eb7a6ca6 | 773 | static int et131x_init_eeprom(struct et131x_adapter *adapter) |
d2796743 ME |
774 | { |
775 | struct pci_dev *pdev = adapter->pdev; | |
776 | u8 eestatus; | |
777 | ||
778 | /* We first need to check the EEPROM Status code located at offset | |
779 | * 0xB2 of config space | |
780 | */ | |
a129be84 | 781 | pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus); |
d2796743 ME |
782 | |
783 | /* THIS IS A WORKAROUND: | |
784 | * I need to call this function twice to get my card in a | |
785 | * LG M1 Express Dual running. I tried also a msleep before this | |
a129be84 | 786 | * function, because I thought there could be some time conditions |
d2796743 ME |
787 | * but it didn't work. Call the whole function twice also work. |
788 | */ | |
789 | if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) { | |
790 | dev_err(&pdev->dev, | |
791 | "Could not read PCI config space for EEPROM Status\n"); | |
792 | return -EIO; | |
793 | } | |
794 | ||
795 | /* Determine if the error(s) we care about are present. If they are | |
796 | * present we need to fail. | |
797 | */ | |
798 | if (eestatus & 0x4C) { | |
799 | int write_failed = 0; | |
800 | if (pdev->revision == 0x01) { | |
801 | int i; | |
802 | static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF }; | |
803 | ||
804 | /* Re-write the first 4 bytes if we have an eeprom | |
805 | * present and the revision id is 1, this fixes the | |
806 | * corruption seen with 1310 B Silicon | |
807 | */ | |
808 | for (i = 0; i < 3; i++) | |
809 | if (eeprom_write(adapter, i, eedata[i]) < 0) | |
810 | write_failed = 1; | |
811 | } | |
812 | if (pdev->revision != 0x01 || write_failed) { | |
813 | dev_err(&pdev->dev, | |
814 | "Fatal EEPROM Status Error - 0x%04x\n", eestatus); | |
815 | ||
816 | /* This error could mean that there was an error | |
817 | * reading the eeprom or that the eeprom doesn't exist. | |
818 | * We will treat each case the same and not try to | |
819 | * gather additional information that normally would | |
820 | * come from the eeprom, like MAC Address | |
821 | */ | |
822 | adapter->has_eeprom = 0; | |
823 | return -EIO; | |
824 | } | |
825 | } | |
826 | adapter->has_eeprom = 1; | |
827 | ||
828 | /* Read the EEPROM for information regarding LED behavior. Refer to | |
829 | * ET1310_phy.c, et131x_xcvr_init(), for its use. | |
830 | */ | |
831 | eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]); | |
832 | eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]); | |
833 | ||
834 | if (adapter->eeprom_data[0] != 0xcd) | |
835 | /* Disable all optional features */ | |
836 | adapter->eeprom_data[1] = 0x00; | |
837 | ||
838 | return 0; | |
839 | } | |
840 | ||
8310c602 ME |
841 | /** |
842 | * et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310. | |
843 | * @adapter: pointer to our adapter structure | |
844 | */ | |
eb7a6ca6 | 845 | static void et131x_rx_dma_enable(struct et131x_adapter *adapter) |
8310c602 ME |
846 | { |
847 | /* Setup the receive dma configuration register for normal operation */ | |
3040d056 | 848 | u32 csr = ET_RXDMA_CSR_FBR1_ENABLE; |
8310c602 | 849 | |
f0ada678 | 850 | if (adapter->rx_ring.fbr[1]->buffsize == 4096) |
3040d056 | 851 | csr |= ET_RXDMA_CSR_FBR1_SIZE_LO; |
f0ada678 | 852 | else if (adapter->rx_ring.fbr[1]->buffsize == 8192) |
3040d056 | 853 | csr |= ET_RXDMA_CSR_FBR1_SIZE_HI; |
f0ada678 | 854 | else if (adapter->rx_ring.fbr[1]->buffsize == 16384) |
3040d056 | 855 | csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI; |
b5254867 | 856 | |
3040d056 | 857 | csr |= ET_RXDMA_CSR_FBR0_ENABLE; |
f0ada678 | 858 | if (adapter->rx_ring.fbr[0]->buffsize == 256) |
3040d056 | 859 | csr |= ET_RXDMA_CSR_FBR0_SIZE_LO; |
f0ada678 | 860 | else if (adapter->rx_ring.fbr[0]->buffsize == 512) |
3040d056 | 861 | csr |= ET_RXDMA_CSR_FBR0_SIZE_HI; |
f0ada678 | 862 | else if (adapter->rx_ring.fbr[0]->buffsize == 1024) |
3040d056 | 863 | csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI; |
8310c602 ME |
864 | writel(csr, &adapter->regs->rxdma.csr); |
865 | ||
866 | csr = readl(&adapter->regs->rxdma.csr); | |
3040d056 | 867 | if (csr & ET_RXDMA_CSR_HALT_STATUS) { |
8310c602 ME |
868 | udelay(5); |
869 | csr = readl(&adapter->regs->rxdma.csr); | |
3040d056 | 870 | if (csr & ET_RXDMA_CSR_HALT_STATUS) { |
8310c602 ME |
871 | dev_err(&adapter->pdev->dev, |
872 | "RX Dma failed to exit halt state. CSR 0x%08x\n", | |
873 | csr); | |
874 | } | |
875 | } | |
876 | } | |
877 | ||
878 | /** | |
879 | * et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310 | |
880 | * @adapter: pointer to our adapter structure | |
881 | */ | |
eb7a6ca6 | 882 | static void et131x_rx_dma_disable(struct et131x_adapter *adapter) |
8310c602 ME |
883 | { |
884 | u32 csr; | |
885 | /* Setup the receive dma configuration register */ | |
3040d056 ME |
886 | writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE, |
887 | &adapter->regs->rxdma.csr); | |
8310c602 | 888 | csr = readl(&adapter->regs->rxdma.csr); |
3040d056 | 889 | if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) { |
8310c602 ME |
890 | udelay(5); |
891 | csr = readl(&adapter->regs->rxdma.csr); | |
3040d056 | 892 | if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) |
8310c602 | 893 | dev_err(&adapter->pdev->dev, |
3040d056 ME |
894 | "RX Dma failed to enter halt state. CSR 0x%08x\n", |
895 | csr); | |
8310c602 ME |
896 | } |
897 | } | |
898 | ||
899 | /** | |
900 | * et131x_tx_dma_enable - re-start of Tx_DMA on the ET1310. | |
901 | * @adapter: pointer to our adapter structure | |
902 | * | |
903 | * Mainly used after a return to the D0 (full-power) state from a lower state. | |
904 | */ | |
eb7a6ca6 | 905 | static void et131x_tx_dma_enable(struct et131x_adapter *adapter) |
8310c602 ME |
906 | { |
907 | /* Setup the transmit dma configuration register for normal | |
908 | * operation | |
909 | */ | |
910 | writel(ET_TXDMA_SNGL_EPKT|(PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT), | |
911 | &adapter->regs->txdma.csr); | |
912 | } | |
913 | ||
914 | static inline void add_10bit(u32 *v, int n) | |
915 | { | |
916 | *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP); | |
917 | } | |
918 | ||
919 | static inline void add_12bit(u32 *v, int n) | |
920 | { | |
921 | *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP); | |
922 | } | |
923 | ||
d2796743 ME |
924 | /** |
925 | * et1310_config_mac_regs1 - Initialize the first part of MAC regs | |
926 | * @adapter: pointer to our adapter structure | |
927 | */ | |
eb7a6ca6 | 928 | static void et1310_config_mac_regs1(struct et131x_adapter *adapter) |
d2796743 ME |
929 | { |
930 | struct mac_regs __iomem *macregs = &adapter->regs->mac; | |
931 | u32 station1; | |
932 | u32 station2; | |
933 | u32 ipg; | |
934 | ||
935 | /* First we need to reset everything. Write to MAC configuration | |
936 | * register 1 to perform reset. | |
937 | */ | |
a129be84 ME |
938 | writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET | |
939 | ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC | | |
940 | ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC, | |
941 | ¯egs->cfg1); | |
d2796743 ME |
942 | |
943 | /* Next lets configure the MAC Inter-packet gap register */ | |
944 | ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */ | |
945 | ipg |= 0x50 << 8; /* ifg enforce 0x50 */ | |
946 | writel(ipg, ¯egs->ipg); | |
947 | ||
948 | /* Next lets configure the MAC Half Duplex register */ | |
949 | /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */ | |
950 | writel(0x00A1F037, ¯egs->hfdp); | |
951 | ||
952 | /* Next lets configure the MAC Interface Control register */ | |
953 | writel(0, ¯egs->if_ctrl); | |
954 | ||
955 | /* Let's move on to setting up the mii management configuration */ | |
a129be84 | 956 | writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg); |
d2796743 ME |
957 | |
958 | /* Next lets configure the MAC Station Address register. These | |
959 | * values are read from the EEPROM during initialization and stored | |
960 | * in the adapter structure. We write what is stored in the adapter | |
961 | * structure to the MAC Station Address registers high and low. This | |
962 | * station address is used for generating and checking pause control | |
963 | * packets. | |
964 | */ | |
965 | station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) | | |
966 | (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT); | |
967 | station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) | | |
968 | (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) | | |
969 | (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) | | |
970 | adapter->addr[2]; | |
971 | writel(station1, ¯egs->station_addr_1); | |
972 | writel(station2, ¯egs->station_addr_2); | |
973 | ||
ac399bc0 | 974 | /* Max ethernet packet in bytes that will be passed by the mac without |
d2796743 ME |
975 | * being truncated. Allow the MAC to pass 4 more than our max packet |
976 | * size. This is 4 for the Ethernet CRC. | |
977 | * | |
978 | * Packets larger than (registry_jumbo_packet) that do not contain a | |
979 | * VLAN ID will be dropped by the Rx function. | |
980 | */ | |
981 | writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len); | |
982 | ||
983 | /* clear out MAC config reset */ | |
984 | writel(0, ¯egs->cfg1); | |
985 | } | |
986 | ||
987 | /** | |
988 | * et1310_config_mac_regs2 - Initialize the second part of MAC regs | |
989 | * @adapter: pointer to our adapter structure | |
990 | */ | |
eb7a6ca6 | 991 | static void et1310_config_mac_regs2(struct et131x_adapter *adapter) |
d2796743 ME |
992 | { |
993 | int32_t delay = 0; | |
994 | struct mac_regs __iomem *mac = &adapter->regs->mac; | |
995 | struct phy_device *phydev = adapter->phydev; | |
996 | u32 cfg1; | |
997 | u32 cfg2; | |
998 | u32 ifctrl; | |
999 | u32 ctl; | |
1000 | ||
1001 | ctl = readl(&adapter->regs->txmac.ctl); | |
1002 | cfg1 = readl(&mac->cfg1); | |
1003 | cfg2 = readl(&mac->cfg2); | |
1004 | ifctrl = readl(&mac->if_ctrl); | |
1005 | ||
1006 | /* Set up the if mode bits */ | |
a129be84 | 1007 | cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK; |
d2796743 | 1008 | if (phydev && phydev->speed == SPEED_1000) { |
a129be84 | 1009 | cfg2 |= ET_MAC_CFG2_IFMODE_1000; |
d2796743 | 1010 | /* Phy mode bit */ |
a129be84 | 1011 | ifctrl &= ~ET_MAC_IFCTRL_PHYMODE; |
d2796743 | 1012 | } else { |
a129be84 ME |
1013 | cfg2 |= ET_MAC_CFG2_IFMODE_100; |
1014 | ifctrl |= ET_MAC_IFCTRL_PHYMODE; | |
d2796743 ME |
1015 | } |
1016 | ||
1017 | /* We need to enable Rx/Tx */ | |
a129be84 ME |
1018 | cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE | |
1019 | ET_MAC_CFG1_TX_FLOW; | |
d2796743 | 1020 | /* Initialize loop back to off */ |
a129be84 | 1021 | cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW); |
d2796743 ME |
1022 | if (adapter->flowcontrol == FLOW_RXONLY || |
1023 | adapter->flowcontrol == FLOW_BOTH) | |
a129be84 | 1024 | cfg1 |= ET_MAC_CFG1_RX_FLOW; |
d2796743 ME |
1025 | writel(cfg1, &mac->cfg1); |
1026 | ||
1027 | /* Now we need to initialize the MAC Configuration 2 register */ | |
1028 | /* preamble 7, check length, huge frame off, pad crc, crc enable | |
1029 | full duplex off */ | |
a129be84 ME |
1030 | cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT; |
1031 | cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK; | |
1032 | cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC; | |
1033 | cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE; | |
1034 | cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME; | |
1035 | cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX; | |
d2796743 ME |
1036 | |
1037 | /* Turn on duplex if needed */ | |
1038 | if (phydev && phydev->duplex == DUPLEX_FULL) | |
a129be84 | 1039 | cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX; |
d2796743 | 1040 | |
a129be84 | 1041 | ifctrl &= ~ET_MAC_IFCTRL_GHDMODE; |
d2796743 | 1042 | if (phydev && phydev->duplex == DUPLEX_HALF) |
a129be84 | 1043 | ifctrl |= ET_MAC_IFCTRL_GHDMODE; |
d2796743 ME |
1044 | |
1045 | writel(ifctrl, &mac->if_ctrl); | |
1046 | writel(cfg2, &mac->cfg2); | |
1047 | ||
1048 | do { | |
1049 | udelay(10); | |
1050 | delay++; | |
1051 | cfg1 = readl(&mac->cfg1); | |
a129be84 | 1052 | } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100); |
d2796743 ME |
1053 | |
1054 | if (delay == 100) { | |
1055 | dev_warn(&adapter->pdev->dev, | |
1056 | "Syncd bits did not respond correctly cfg1 word 0x%08x\n", | |
1057 | cfg1); | |
1058 | } | |
1059 | ||
1060 | /* Enable txmac */ | |
a129be84 | 1061 | ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE; |
d2796743 ME |
1062 | writel(ctl, &adapter->regs->txmac.ctl); |
1063 | ||
1064 | /* Ready to start the RXDMA/TXDMA engine */ | |
1065 | if (adapter->flags & fMP_ADAPTER_LOWER_POWER) { | |
1066 | et131x_rx_dma_enable(adapter); | |
1067 | et131x_tx_dma_enable(adapter); | |
1068 | } | |
1069 | } | |
1070 | ||
2288760e ME |
1071 | /** |
1072 | * et1310_in_phy_coma - check if the device is in phy coma | |
1073 | * @adapter: pointer to our adapter structure | |
1074 | * | |
1075 | * Returns 0 if the device is not in phy coma, 1 if it is in phy coma | |
1076 | */ | |
eb7a6ca6 | 1077 | static int et1310_in_phy_coma(struct et131x_adapter *adapter) |
2288760e ME |
1078 | { |
1079 | u32 pmcsr; | |
1080 | ||
1081 | pmcsr = readl(&adapter->regs->global.pm_csr); | |
1082 | ||
1083 | return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0; | |
1084 | } | |
1085 | ||
eb7a6ca6 | 1086 | static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter) |
a4d444bd ME |
1087 | { |
1088 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; | |
834d0ee3 FR |
1089 | u32 hash1 = 0; |
1090 | u32 hash2 = 0; | |
1091 | u32 hash3 = 0; | |
1092 | u32 hash4 = 0; | |
a4d444bd ME |
1093 | u32 pm_csr; |
1094 | ||
1095 | /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision | |
1096 | * the multi-cast LIST. If it is NOT specified, (and "ALL" is not | |
1097 | * specified) then we should pass NO multi-cast addresses to the | |
1098 | * driver. | |
1099 | */ | |
1100 | if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) { | |
834d0ee3 FR |
1101 | int i; |
1102 | ||
a4d444bd | 1103 | /* Loop through our multicast array and set up the device */ |
834d0ee3 FR |
1104 | for (i = 0; i < adapter->multicast_addr_count; i++) { |
1105 | u32 result; | |
1106 | ||
1107 | result = ether_crc(6, adapter->multicast_list[i]); | |
a4d444bd ME |
1108 | |
1109 | result = (result & 0x3F800000) >> 23; | |
1110 | ||
1111 | if (result < 32) { | |
1112 | hash1 |= (1 << result); | |
1113 | } else if ((31 < result) && (result < 64)) { | |
1114 | result -= 32; | |
1115 | hash2 |= (1 << result); | |
1116 | } else if ((63 < result) && (result < 96)) { | |
1117 | result -= 64; | |
1118 | hash3 |= (1 << result); | |
1119 | } else { | |
1120 | result -= 96; | |
1121 | hash4 |= (1 << result); | |
1122 | } | |
1123 | } | |
1124 | } | |
1125 | ||
1126 | /* Write out the new hash to the device */ | |
1127 | pm_csr = readl(&adapter->regs->global.pm_csr); | |
1128 | if (!et1310_in_phy_coma(adapter)) { | |
1129 | writel(hash1, &rxmac->multi_hash1); | |
1130 | writel(hash2, &rxmac->multi_hash2); | |
1131 | writel(hash3, &rxmac->multi_hash3); | |
1132 | writel(hash4, &rxmac->multi_hash4); | |
1133 | } | |
1134 | } | |
1135 | ||
eb7a6ca6 | 1136 | static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter) |
a4d444bd ME |
1137 | { |
1138 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; | |
1139 | u32 uni_pf1; | |
1140 | u32 uni_pf2; | |
1141 | u32 uni_pf3; | |
1142 | u32 pm_csr; | |
1143 | ||
1144 | /* Set up unicast packet filter reg 3 to be the first two octets of | |
1145 | * the MAC address for both address | |
1146 | * | |
1147 | * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the | |
1148 | * MAC address for second address | |
1149 | * | |
1150 | * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the | |
1151 | * MAC address for first address | |
1152 | */ | |
a129be84 ME |
1153 | uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) | |
1154 | (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) | | |
1155 | (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) | | |
a4d444bd ME |
1156 | adapter->addr[1]; |
1157 | ||
a129be84 ME |
1158 | uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) | |
1159 | (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) | | |
1160 | (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) | | |
a4d444bd ME |
1161 | adapter->addr[5]; |
1162 | ||
a129be84 ME |
1163 | uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) | |
1164 | (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) | | |
1165 | (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) | | |
a4d444bd ME |
1166 | adapter->addr[5]; |
1167 | ||
1168 | pm_csr = readl(&adapter->regs->global.pm_csr); | |
1169 | if (!et1310_in_phy_coma(adapter)) { | |
1170 | writel(uni_pf1, &rxmac->uni_pf_addr1); | |
1171 | writel(uni_pf2, &rxmac->uni_pf_addr2); | |
1172 | writel(uni_pf3, &rxmac->uni_pf_addr3); | |
1173 | } | |
1174 | } | |
1175 | ||
eb7a6ca6 | 1176 | static void et1310_config_rxmac_regs(struct et131x_adapter *adapter) |
d2796743 ME |
1177 | { |
1178 | struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac; | |
1179 | struct phy_device *phydev = adapter->phydev; | |
1180 | u32 sa_lo; | |
1181 | u32 sa_hi = 0; | |
1182 | u32 pf_ctrl = 0; | |
1183 | ||
1184 | /* Disable the MAC while it is being configured (also disable WOL) */ | |
1185 | writel(0x8, &rxmac->ctrl); | |
1186 | ||
1187 | /* Initialize WOL to disabled. */ | |
1188 | writel(0, &rxmac->crc0); | |
1189 | writel(0, &rxmac->crc12); | |
1190 | writel(0, &rxmac->crc34); | |
1191 | ||
1192 | /* We need to set the WOL mask0 - mask4 next. We initialize it to | |
1193 | * its default Values of 0x00000000 because there are not WOL masks | |
1194 | * as of this time. | |
1195 | */ | |
1196 | writel(0, &rxmac->mask0_word0); | |
1197 | writel(0, &rxmac->mask0_word1); | |
1198 | writel(0, &rxmac->mask0_word2); | |
1199 | writel(0, &rxmac->mask0_word3); | |
1200 | ||
1201 | writel(0, &rxmac->mask1_word0); | |
1202 | writel(0, &rxmac->mask1_word1); | |
1203 | writel(0, &rxmac->mask1_word2); | |
1204 | writel(0, &rxmac->mask1_word3); | |
1205 | ||
1206 | writel(0, &rxmac->mask2_word0); | |
1207 | writel(0, &rxmac->mask2_word1); | |
1208 | writel(0, &rxmac->mask2_word2); | |
1209 | writel(0, &rxmac->mask2_word3); | |
1210 | ||
1211 | writel(0, &rxmac->mask3_word0); | |
1212 | writel(0, &rxmac->mask3_word1); | |
1213 | writel(0, &rxmac->mask3_word2); | |
1214 | writel(0, &rxmac->mask3_word3); | |
1215 | ||
1216 | writel(0, &rxmac->mask4_word0); | |
1217 | writel(0, &rxmac->mask4_word1); | |
1218 | writel(0, &rxmac->mask4_word2); | |
1219 | writel(0, &rxmac->mask4_word3); | |
1220 | ||
1221 | /* Lets setup the WOL Source Address */ | |
a129be84 ME |
1222 | sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) | |
1223 | (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) | | |
1224 | (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) | | |
d2796743 ME |
1225 | adapter->addr[5]; |
1226 | writel(sa_lo, &rxmac->sa_lo); | |
1227 | ||
a129be84 | 1228 | sa_hi = (u32) (adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) | |
d2796743 ME |
1229 | adapter->addr[1]; |
1230 | writel(sa_hi, &rxmac->sa_hi); | |
1231 | ||
1232 | /* Disable all Packet Filtering */ | |
1233 | writel(0, &rxmac->pf_ctrl); | |
1234 | ||
1235 | /* Let's initialize the Unicast Packet filtering address */ | |
1236 | if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) { | |
1237 | et1310_setup_device_for_unicast(adapter); | |
a129be84 | 1238 | pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE; |
d2796743 ME |
1239 | } else { |
1240 | writel(0, &rxmac->uni_pf_addr1); | |
1241 | writel(0, &rxmac->uni_pf_addr2); | |
1242 | writel(0, &rxmac->uni_pf_addr3); | |
1243 | } | |
1244 | ||
1245 | /* Let's initialize the Multicast hash */ | |
1246 | if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) { | |
a129be84 | 1247 | pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE; |
d2796743 ME |
1248 | et1310_setup_device_for_multicast(adapter); |
1249 | } | |
1250 | ||
1251 | /* Runt packet filtering. Didn't work in version A silicon. */ | |
a129be84 ME |
1252 | pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT; |
1253 | pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE; | |
d2796743 ME |
1254 | |
1255 | if (adapter->registry_jumbo_packet > 8192) | |
1256 | /* In order to transmit jumbo packets greater than 8k, the | |
1257 | * FIFO between RxMAC and RxDMA needs to be reduced in size | |
1258 | * to (16k - Jumbo packet size). In order to implement this, | |
1259 | * we must use "cut through" mode in the RxMAC, which chops | |
1260 | * packets down into segments which are (max_size * 16). In | |
1261 | * this case we selected 256 bytes, since this is the size of | |
1262 | * the PCI-Express TLP's that the 1310 uses. | |
1263 | * | |
1264 | * seg_en on, fc_en off, size 0x10 | |
1265 | */ | |
1266 | writel(0x41, &rxmac->mcif_ctrl_max_seg); | |
1267 | else | |
1268 | writel(0, &rxmac->mcif_ctrl_max_seg); | |
1269 | ||
1270 | /* Initialize the MCIF water marks */ | |
1271 | writel(0, &rxmac->mcif_water_mark); | |
1272 | ||
1273 | /* Initialize the MIF control */ | |
1274 | writel(0, &rxmac->mif_ctrl); | |
1275 | ||
1276 | /* Initialize the Space Available Register */ | |
1277 | writel(0, &rxmac->space_avail); | |
1278 | ||
1279 | /* Initialize the the mif_ctrl register | |
1280 | * bit 3: Receive code error. One or more nibbles were signaled as | |
1281 | * errors during the reception of the packet. Clear this | |
1282 | * bit in Gigabit, set it in 100Mbit. This was derived | |
1283 | * experimentally at UNH. | |
1284 | * bit 4: Receive CRC error. The packet's CRC did not match the | |
1285 | * internally generated CRC. | |
1286 | * bit 5: Receive length check error. Indicates that frame length | |
1287 | * field value in the packet does not match the actual data | |
1288 | * byte length and is not a type field. | |
1289 | * bit 16: Receive frame truncated. | |
1290 | * bit 17: Drop packet enable | |
1291 | */ | |
1292 | if (phydev && phydev->speed == SPEED_100) | |
1293 | writel(0x30038, &rxmac->mif_ctrl); | |
1294 | else | |
1295 | writel(0x30030, &rxmac->mif_ctrl); | |
1296 | ||
1297 | /* Finally we initialize RxMac to be enabled & WOL disabled. Packet | |
1298 | * filter is always enabled since it is where the runt packets are | |
1299 | * supposed to be dropped. For version A silicon, runt packet | |
1300 | * dropping doesn't work, so it is disabled in the pf_ctrl register, | |
1301 | * but we still leave the packet filter on. | |
1302 | */ | |
1303 | writel(pf_ctrl, &rxmac->pf_ctrl); | |
a129be84 | 1304 | writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl); |
d2796743 ME |
1305 | } |
1306 | ||
eb7a6ca6 | 1307 | static void et1310_config_txmac_regs(struct et131x_adapter *adapter) |
d2796743 ME |
1308 | { |
1309 | struct txmac_regs __iomem *txmac = &adapter->regs->txmac; | |
1310 | ||
1311 | /* We need to update the Control Frame Parameters | |
1312 | * cfpt - control frame pause timer set to 64 (0x40) | |
1313 | * cfep - control frame extended pause timer set to 0x0 | |
1314 | */ | |
1315 | if (adapter->flowcontrol == FLOW_NONE) | |
1316 | writel(0, &txmac->cf_param); | |
1317 | else | |
1318 | writel(0x40, &txmac->cf_param); | |
1319 | } | |
1320 | ||
eb7a6ca6 | 1321 | static void et1310_config_macstat_regs(struct et131x_adapter *adapter) |
d2796743 ME |
1322 | { |
1323 | struct macstat_regs __iomem *macstat = | |
1324 | &adapter->regs->macstat; | |
1325 | ||
1326 | /* Next we need to initialize all the macstat registers to zero on | |
1327 | * the device. | |
1328 | */ | |
1329 | writel(0, &macstat->txrx_0_64_byte_frames); | |
1330 | writel(0, &macstat->txrx_65_127_byte_frames); | |
1331 | writel(0, &macstat->txrx_128_255_byte_frames); | |
1332 | writel(0, &macstat->txrx_256_511_byte_frames); | |
1333 | writel(0, &macstat->txrx_512_1023_byte_frames); | |
1334 | writel(0, &macstat->txrx_1024_1518_byte_frames); | |
1335 | writel(0, &macstat->txrx_1519_1522_gvln_frames); | |
1336 | ||
1337 | writel(0, &macstat->rx_bytes); | |
1338 | writel(0, &macstat->rx_packets); | |
1339 | writel(0, &macstat->rx_fcs_errs); | |
1340 | writel(0, &macstat->rx_multicast_packets); | |
1341 | writel(0, &macstat->rx_broadcast_packets); | |
1342 | writel(0, &macstat->rx_control_frames); | |
1343 | writel(0, &macstat->rx_pause_frames); | |
1344 | writel(0, &macstat->rx_unknown_opcodes); | |
1345 | writel(0, &macstat->rx_align_errs); | |
1346 | writel(0, &macstat->rx_frame_len_errs); | |
1347 | writel(0, &macstat->rx_code_errs); | |
1348 | writel(0, &macstat->rx_carrier_sense_errs); | |
1349 | writel(0, &macstat->rx_undersize_packets); | |
1350 | writel(0, &macstat->rx_oversize_packets); | |
1351 | writel(0, &macstat->rx_fragment_packets); | |
1352 | writel(0, &macstat->rx_jabbers); | |
1353 | writel(0, &macstat->rx_drops); | |
1354 | ||
1355 | writel(0, &macstat->tx_bytes); | |
1356 | writel(0, &macstat->tx_packets); | |
1357 | writel(0, &macstat->tx_multicast_packets); | |
1358 | writel(0, &macstat->tx_broadcast_packets); | |
1359 | writel(0, &macstat->tx_pause_frames); | |
1360 | writel(0, &macstat->tx_deferred); | |
1361 | writel(0, &macstat->tx_excessive_deferred); | |
1362 | writel(0, &macstat->tx_single_collisions); | |
1363 | writel(0, &macstat->tx_multiple_collisions); | |
1364 | writel(0, &macstat->tx_late_collisions); | |
1365 | writel(0, &macstat->tx_excessive_collisions); | |
1366 | writel(0, &macstat->tx_total_collisions); | |
1367 | writel(0, &macstat->tx_pause_honored_frames); | |
1368 | writel(0, &macstat->tx_drops); | |
1369 | writel(0, &macstat->tx_jabbers); | |
1370 | writel(0, &macstat->tx_fcs_errs); | |
1371 | writel(0, &macstat->tx_control_frames); | |
1372 | writel(0, &macstat->tx_oversize_frames); | |
1373 | writel(0, &macstat->tx_undersize_frames); | |
1374 | writel(0, &macstat->tx_fragments); | |
1375 | writel(0, &macstat->carry_reg1); | |
1376 | writel(0, &macstat->carry_reg2); | |
1377 | ||
1378 | /* Unmask any counters that we want to track the overflow of. | |
1379 | * Initially this will be all counters. It may become clear later | |
1380 | * that we do not need to track all counters. | |
1381 | */ | |
1382 | writel(0xFFFFBE32, &macstat->carry_reg1_mask); | |
1383 | writel(0xFFFE7E8B, &macstat->carry_reg2_mask); | |
1384 | } | |
1385 | ||
2288760e ME |
1386 | /** |
1387 | * et131x_phy_mii_read - Read from the PHY through the MII Interface on the MAC | |
1388 | * @adapter: pointer to our private adapter structure | |
1389 | * @addr: the address of the transceiver | |
1390 | * @reg: the register to read | |
1391 | * @value: pointer to a 16-bit value in which the value will be stored | |
1392 | * | |
1393 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
1394 | */ | |
eb7a6ca6 | 1395 | static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr, |
2288760e ME |
1396 | u8 reg, u16 *value) |
1397 | { | |
1398 | struct mac_regs __iomem *mac = &adapter->regs->mac; | |
1399 | int status = 0; | |
1400 | u32 delay = 0; | |
1401 | u32 mii_addr; | |
1402 | u32 mii_cmd; | |
1403 | u32 mii_indicator; | |
1404 | ||
1405 | /* Save a local copy of the registers we are dealing with so we can | |
1406 | * set them back | |
1407 | */ | |
1408 | mii_addr = readl(&mac->mii_mgmt_addr); | |
1409 | mii_cmd = readl(&mac->mii_mgmt_cmd); | |
1410 | ||
1411 | /* Stop the current operation */ | |
1412 | writel(0, &mac->mii_mgmt_cmd); | |
1413 | ||
1414 | /* Set up the register we need to read from on the correct PHY */ | |
a129be84 | 1415 | writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr); |
2288760e ME |
1416 | |
1417 | writel(0x1, &mac->mii_mgmt_cmd); | |
1418 | ||
1419 | do { | |
1420 | udelay(50); | |
1421 | delay++; | |
1422 | mii_indicator = readl(&mac->mii_mgmt_indicator); | |
a129be84 | 1423 | } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50); |
2288760e ME |
1424 | |
1425 | /* If we hit the max delay, we could not read the register */ | |
1426 | if (delay == 50) { | |
1427 | dev_warn(&adapter->pdev->dev, | |
1428 | "reg 0x%08x could not be read\n", reg); | |
1429 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", | |
1430 | mii_indicator); | |
1431 | ||
1432 | status = -EIO; | |
1433 | } | |
1434 | ||
1435 | /* If we hit here we were able to read the register and we need to | |
1436 | * return the value to the caller */ | |
a129be84 | 1437 | *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK; |
2288760e ME |
1438 | |
1439 | /* Stop the read operation */ | |
1440 | writel(0, &mac->mii_mgmt_cmd); | |
1441 | ||
1442 | /* set the registers we touched back to the state at which we entered | |
1443 | * this function | |
1444 | */ | |
1445 | writel(mii_addr, &mac->mii_mgmt_addr); | |
1446 | writel(mii_cmd, &mac->mii_mgmt_cmd); | |
1447 | ||
1448 | return status; | |
1449 | } | |
1450 | ||
eb7a6ca6 | 1451 | static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value) |
2288760e ME |
1452 | { |
1453 | struct phy_device *phydev = adapter->phydev; | |
1454 | ||
1455 | if (!phydev) | |
1456 | return -EIO; | |
1457 | ||
1458 | return et131x_phy_mii_read(adapter, phydev->addr, reg, value); | |
1459 | } | |
1460 | ||
1461 | /** | |
1462 | * et131x_mii_write - Write to a PHY register through the MII interface of the MAC | |
1463 | * @adapter: pointer to our private adapter structure | |
1464 | * @reg: the register to read | |
1465 | * @value: 16-bit value to write | |
1466 | * | |
1467 | * FIXME: one caller in netdev still | |
1468 | * | |
1469 | * Return 0 on success, errno on failure (as defined in errno.h) | |
1470 | */ | |
eb7a6ca6 | 1471 | static int et131x_mii_write(struct et131x_adapter *adapter, u8 reg, u16 value) |
2288760e ME |
1472 | { |
1473 | struct mac_regs __iomem *mac = &adapter->regs->mac; | |
1474 | struct phy_device *phydev = adapter->phydev; | |
1475 | int status = 0; | |
1476 | u8 addr; | |
1477 | u32 delay = 0; | |
1478 | u32 mii_addr; | |
1479 | u32 mii_cmd; | |
1480 | u32 mii_indicator; | |
1481 | ||
1482 | if (!phydev) | |
1483 | return -EIO; | |
1484 | ||
1485 | addr = phydev->addr; | |
1486 | ||
1487 | /* Save a local copy of the registers we are dealing with so we can | |
1488 | * set them back | |
1489 | */ | |
1490 | mii_addr = readl(&mac->mii_mgmt_addr); | |
1491 | mii_cmd = readl(&mac->mii_mgmt_cmd); | |
1492 | ||
1493 | /* Stop the current operation */ | |
1494 | writel(0, &mac->mii_mgmt_cmd); | |
1495 | ||
1496 | /* Set up the register we need to write to on the correct PHY */ | |
a129be84 | 1497 | writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr); |
2288760e ME |
1498 | |
1499 | /* Add the value to write to the registers to the mac */ | |
1500 | writel(value, &mac->mii_mgmt_ctrl); | |
1501 | ||
1502 | do { | |
1503 | udelay(50); | |
1504 | delay++; | |
1505 | mii_indicator = readl(&mac->mii_mgmt_indicator); | |
a129be84 | 1506 | } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100); |
2288760e ME |
1507 | |
1508 | /* If we hit the max delay, we could not write the register */ | |
1509 | if (delay == 100) { | |
1510 | u16 tmp; | |
1511 | ||
1512 | dev_warn(&adapter->pdev->dev, | |
1513 | "reg 0x%08x could not be written", reg); | |
1514 | dev_warn(&adapter->pdev->dev, "status is 0x%08x\n", | |
1515 | mii_indicator); | |
1516 | dev_warn(&adapter->pdev->dev, "command is 0x%08x\n", | |
1517 | readl(&mac->mii_mgmt_cmd)); | |
1518 | ||
1519 | et131x_mii_read(adapter, reg, &tmp); | |
1520 | ||
1521 | status = -EIO; | |
1522 | } | |
1523 | /* Stop the write operation */ | |
1524 | writel(0, &mac->mii_mgmt_cmd); | |
1525 | ||
1526 | /* | |
1527 | * set the registers we touched back to the state at which we entered | |
1528 | * this function | |
1529 | */ | |
1530 | writel(mii_addr, &mac->mii_mgmt_addr); | |
1531 | writel(mii_cmd, &mac->mii_mgmt_cmd); | |
1532 | ||
1533 | return status; | |
1534 | } | |
1535 | ||
1536 | /* Still used from _mac for BIT_READ */ | |
eb7a6ca6 FR |
1537 | static void et1310_phy_access_mii_bit(struct et131x_adapter *adapter, |
1538 | u16 action, u16 regnum, u16 bitnum, | |
1539 | u8 *value) | |
2288760e ME |
1540 | { |
1541 | u16 reg; | |
a129be84 | 1542 | u16 mask = 1 << bitnum; |
2288760e ME |
1543 | |
1544 | /* Read the requested register */ | |
1545 | et131x_mii_read(adapter, regnum, ®); | |
1546 | ||
1547 | switch (action) { | |
1548 | case TRUEPHY_BIT_READ: | |
1549 | *value = (reg & mask) >> bitnum; | |
1550 | break; | |
1551 | ||
1552 | case TRUEPHY_BIT_SET: | |
1553 | et131x_mii_write(adapter, regnum, reg | mask); | |
1554 | break; | |
1555 | ||
1556 | case TRUEPHY_BIT_CLEAR: | |
1557 | et131x_mii_write(adapter, regnum, reg & ~mask); | |
1558 | break; | |
1559 | ||
1560 | default: | |
1561 | break; | |
1562 | } | |
1563 | } | |
1564 | ||
eb7a6ca6 | 1565 | static void et1310_config_flow_control(struct et131x_adapter *adapter) |
d2796743 ME |
1566 | { |
1567 | struct phy_device *phydev = adapter->phydev; | |
1568 | ||
1569 | if (phydev->duplex == DUPLEX_HALF) { | |
1570 | adapter->flowcontrol = FLOW_NONE; | |
1571 | } else { | |
1572 | char remote_pause, remote_async_pause; | |
1573 | ||
1574 | et1310_phy_access_mii_bit(adapter, | |
1575 | TRUEPHY_BIT_READ, 5, 10, &remote_pause); | |
1576 | et1310_phy_access_mii_bit(adapter, | |
1577 | TRUEPHY_BIT_READ, 5, 11, | |
1578 | &remote_async_pause); | |
1579 | ||
1580 | if ((remote_pause == TRUEPHY_BIT_SET) && | |
1581 | (remote_async_pause == TRUEPHY_BIT_SET)) { | |
1582 | adapter->flowcontrol = adapter->wanted_flow; | |
1583 | } else if ((remote_pause == TRUEPHY_BIT_SET) && | |
1584 | (remote_async_pause == TRUEPHY_BIT_CLEAR)) { | |
1585 | if (adapter->wanted_flow == FLOW_BOTH) | |
1586 | adapter->flowcontrol = FLOW_BOTH; | |
1587 | else | |
1588 | adapter->flowcontrol = FLOW_NONE; | |
1589 | } else if ((remote_pause == TRUEPHY_BIT_CLEAR) && | |
1590 | (remote_async_pause == TRUEPHY_BIT_CLEAR)) { | |
1591 | adapter->flowcontrol = FLOW_NONE; | |
1592 | } else {/* if (remote_pause == TRUEPHY_CLEAR_BIT && | |
1593 | remote_async_pause == TRUEPHY_SET_BIT) */ | |
1594 | if (adapter->wanted_flow == FLOW_BOTH) | |
1595 | adapter->flowcontrol = FLOW_RXONLY; | |
1596 | else | |
1597 | adapter->flowcontrol = FLOW_NONE; | |
1598 | } | |
1599 | } | |
1600 | } | |
1601 | ||
1602 | /** | |
1603 | * et1310_update_macstat_host_counters - Update the local copy of the statistics | |
1604 | * @adapter: pointer to the adapter structure | |
1605 | */ | |
eb7a6ca6 | 1606 | static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter) |
d2796743 ME |
1607 | { |
1608 | struct ce_stats *stats = &adapter->stats; | |
1609 | struct macstat_regs __iomem *macstat = | |
1610 | &adapter->regs->macstat; | |
1611 | ||
1612 | stats->tx_collisions += readl(&macstat->tx_total_collisions); | |
1613 | stats->tx_first_collisions += readl(&macstat->tx_single_collisions); | |
1614 | stats->tx_deferred += readl(&macstat->tx_deferred); | |
1615 | stats->tx_excessive_collisions += | |
1616 | readl(&macstat->tx_multiple_collisions); | |
1617 | stats->tx_late_collisions += readl(&macstat->tx_late_collisions); | |
1618 | stats->tx_underflows += readl(&macstat->tx_undersize_frames); | |
1619 | stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames); | |
1620 | ||
1621 | stats->rx_align_errs += readl(&macstat->rx_align_errs); | |
1622 | stats->rx_crc_errs += readl(&macstat->rx_code_errs); | |
1623 | stats->rcvd_pkts_dropped += readl(&macstat->rx_drops); | |
1624 | stats->rx_overflows += readl(&macstat->rx_oversize_packets); | |
1625 | stats->rx_code_violations += readl(&macstat->rx_fcs_errs); | |
1626 | stats->rx_length_errs += readl(&macstat->rx_frame_len_errs); | |
1627 | stats->rx_other_errs += readl(&macstat->rx_fragment_packets); | |
1628 | } | |
1629 | ||
1630 | /** | |
1631 | * et1310_handle_macstat_interrupt | |
1632 | * @adapter: pointer to the adapter structure | |
1633 | * | |
1634 | * One of the MACSTAT counters has wrapped. Update the local copy of | |
1635 | * the statistics held in the adapter structure, checking the "wrap" | |
1636 | * bit for each counter. | |
1637 | */ | |
eb7a6ca6 | 1638 | static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter) |
d2796743 ME |
1639 | { |
1640 | u32 carry_reg1; | |
1641 | u32 carry_reg2; | |
1642 | ||
1643 | /* Read the interrupt bits from the register(s). These are Clear On | |
1644 | * Write. | |
1645 | */ | |
1646 | carry_reg1 = readl(&adapter->regs->macstat.carry_reg1); | |
1647 | carry_reg2 = readl(&adapter->regs->macstat.carry_reg2); | |
1648 | ||
1649 | writel(carry_reg1, &adapter->regs->macstat.carry_reg1); | |
1650 | writel(carry_reg2, &adapter->regs->macstat.carry_reg2); | |
1651 | ||
1652 | /* We need to do update the host copy of all the MAC_STAT counters. | |
1653 | * For each counter, check it's overflow bit. If the overflow bit is | |
1654 | * set, then increment the host version of the count by one complete | |
1655 | * revolution of the counter. This routine is called when the counter | |
1656 | * block indicates that one of the counters has wrapped. | |
1657 | */ | |
1658 | if (carry_reg1 & (1 << 14)) | |
1659 | adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT; | |
1660 | if (carry_reg1 & (1 << 8)) | |
1661 | adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT; | |
1662 | if (carry_reg1 & (1 << 7)) | |
1663 | adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT; | |
1664 | if (carry_reg1 & (1 << 2)) | |
1665 | adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT; | |
1666 | if (carry_reg1 & (1 << 6)) | |
1667 | adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT; | |
1668 | if (carry_reg1 & (1 << 3)) | |
1669 | adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT; | |
1670 | if (carry_reg1 & (1 << 0)) | |
1671 | adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT; | |
1672 | if (carry_reg2 & (1 << 16)) | |
1673 | adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT; | |
1674 | if (carry_reg2 & (1 << 15)) | |
1675 | adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT; | |
1676 | if (carry_reg2 & (1 << 6)) | |
1677 | adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT; | |
1678 | if (carry_reg2 & (1 << 8)) | |
1679 | adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT; | |
1680 | if (carry_reg2 & (1 << 5)) | |
1681 | adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT; | |
1682 | if (carry_reg2 & (1 << 4)) | |
1683 | adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT; | |
1684 | if (carry_reg2 & (1 << 2)) | |
1685 | adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT; | |
1686 | } | |
1687 | ||
eb7a6ca6 | 1688 | static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg) |
d2796743 ME |
1689 | { |
1690 | struct net_device *netdev = bus->priv; | |
1691 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
1692 | u16 value; | |
1693 | int ret; | |
1694 | ||
1695 | ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value); | |
1696 | ||
1697 | if (ret < 0) | |
1698 | return ret; | |
1699 | else | |
1700 | return value; | |
1701 | } | |
1702 | ||
bf3313a1 | 1703 | static int et131x_mdio_write(struct mii_bus *bus, int phy_addr, |
1704 | int reg, u16 value) | |
d2796743 ME |
1705 | { |
1706 | struct net_device *netdev = bus->priv; | |
1707 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
1708 | ||
1709 | return et131x_mii_write(adapter, reg, value); | |
1710 | } | |
1711 | ||
eb7a6ca6 | 1712 | static int et131x_mdio_reset(struct mii_bus *bus) |
d2796743 ME |
1713 | { |
1714 | struct net_device *netdev = bus->priv; | |
1715 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
1716 | ||
1717 | et131x_mii_write(adapter, MII_BMCR, BMCR_RESET); | |
1718 | ||
1719 | return 0; | |
1720 | } | |
1721 | ||
d2796743 ME |
1722 | /** |
1723 | * et1310_phy_power_down - PHY power control | |
1724 | * @adapter: device to control | |
1725 | * @down: true for off/false for back on | |
1726 | * | |
1727 | * one hundred, ten, one thousand megs | |
1728 | * How would you like to have your LAN accessed | |
1729 | * Can't you see that this code processed | |
1730 | * Phy power, phy power.. | |
1731 | */ | |
eb7a6ca6 | 1732 | static void et1310_phy_power_down(struct et131x_adapter *adapter, bool down) |
d2796743 ME |
1733 | { |
1734 | u16 data; | |
1735 | ||
1736 | et131x_mii_read(adapter, MII_BMCR, &data); | |
1737 | data &= ~BMCR_PDOWN; | |
1738 | if (down) | |
1739 | data |= BMCR_PDOWN; | |
1740 | et131x_mii_write(adapter, MII_BMCR, data); | |
1741 | } | |
1742 | ||
d2796743 ME |
1743 | /** |
1744 | * et131x_xcvr_init - Init the phy if we are setting it into force mode | |
1745 | * @adapter: pointer to our private adapter structure | |
1746 | * | |
1747 | */ | |
eb7a6ca6 | 1748 | static void et131x_xcvr_init(struct et131x_adapter *adapter) |
d2796743 | 1749 | { |
d2796743 ME |
1750 | u16 lcr2; |
1751 | ||
d2796743 ME |
1752 | /* Set the LED behavior such that LED 1 indicates speed (off = |
1753 | * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates | |
1754 | * link and activity (on for link, blink off for activity). | |
1755 | * | |
1756 | * NOTE: Some customizations have been added here for specific | |
1757 | * vendors; The LED behavior is now determined by vendor data in the | |
1758 | * EEPROM. However, the above description is the default. | |
1759 | */ | |
1760 | if ((adapter->eeprom_data[1] & 0x4) == 0) { | |
1761 | et131x_mii_read(adapter, PHY_LED_2, &lcr2); | |
1762 | ||
b5b86a4d | 1763 | lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T); |
d2796743 ME |
1764 | lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT); |
1765 | ||
1766 | if ((adapter->eeprom_data[1] & 0x8) == 0) | |
1767 | lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT); | |
1768 | else | |
1769 | lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT); | |
1770 | ||
1771 | et131x_mii_write(adapter, PHY_LED_2, lcr2); | |
1772 | } | |
1773 | } | |
1774 | ||
36f2771a | 1775 | /** |
c35eb3ae | 1776 | * et131x_configure_global_regs - configure JAGCore global regs |
36f2771a ME |
1777 | * @adapter: pointer to our adapter structure |
1778 | * | |
1779 | * Used to configure the global registers on the JAGCore | |
1780 | */ | |
eb7a6ca6 | 1781 | static void et131x_configure_global_regs(struct et131x_adapter *adapter) |
36f2771a ME |
1782 | { |
1783 | struct global_regs __iomem *regs = &adapter->regs->global; | |
1784 | ||
1785 | writel(0, ®s->rxq_start_addr); | |
1786 | writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr); | |
1787 | ||
1788 | if (adapter->registry_jumbo_packet < 2048) { | |
1789 | /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word | |
1790 | * block of RAM that the driver can split between Tx | |
1791 | * and Rx as it desires. Our default is to split it | |
1792 | * 50/50: | |
1793 | */ | |
1794 | writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr); | |
1795 | writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr); | |
1796 | } else if (adapter->registry_jumbo_packet < 8192) { | |
1797 | /* For jumbo packets > 2k but < 8k, split 50-50. */ | |
1798 | writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr); | |
1799 | writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr); | |
1800 | } else { | |
1801 | /* 9216 is the only packet size greater than 8k that | |
1802 | * is available. The Tx buffer has to be big enough | |
1803 | * for one whole packet on the Tx side. We'll make | |
1804 | * the Tx 9408, and give the rest to Rx | |
1805 | */ | |
1806 | writel(0x01b3, ®s->rxq_end_addr); | |
1807 | writel(0x01b4, ®s->txq_start_addr); | |
1808 | } | |
1809 | ||
1810 | /* Initialize the loopback register. Disable all loopbacks. */ | |
1811 | writel(0, ®s->loopback); | |
1812 | ||
1813 | /* MSI Register */ | |
1814 | writel(0, ®s->msi_config); | |
1815 | ||
1816 | /* By default, disable the watchdog timer. It will be enabled when | |
1817 | * a packet is queued. | |
1818 | */ | |
1819 | writel(0, ®s->watchdog_timer); | |
1820 | } | |
1821 | ||
36f2771a ME |
1822 | /** |
1823 | * et131x_config_rx_dma_regs - Start of Rx_DMA init sequence | |
1824 | * @adapter: pointer to our adapter structure | |
1825 | */ | |
eb7a6ca6 | 1826 | static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter) |
36f2771a ME |
1827 | { |
1828 | struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma; | |
1829 | struct rx_ring *rx_local = &adapter->rx_ring; | |
1830 | struct fbr_desc *fbr_entry; | |
1831 | u32 entry; | |
1832 | u32 psr_num_des; | |
1833 | unsigned long flags; | |
788ca84a | 1834 | u8 id; |
36f2771a ME |
1835 | |
1836 | /* Halt RXDMA to perform the reconfigure. */ | |
1837 | et131x_rx_dma_disable(adapter); | |
1838 | ||
25e8e8ab ME |
1839 | /* Load the completion writeback physical address */ |
1840 | writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi); | |
1841 | writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo); | |
36f2771a ME |
1842 | |
1843 | memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block)); | |
1844 | ||
1845 | /* Set the address and parameters of the packet status ring into the | |
1846 | * 1310's registers | |
1847 | */ | |
25e8e8ab ME |
1848 | writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi); |
1849 | writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo); | |
36f2771a ME |
1850 | writel(rx_local->psr_num_entries - 1, &rx_dma->psr_num_des); |
1851 | writel(0, &rx_dma->psr_full_offset); | |
1852 | ||
a129be84 | 1853 | psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK; |
36f2771a ME |
1854 | writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100, |
1855 | &rx_dma->psr_min_des); | |
1856 | ||
1857 | spin_lock_irqsave(&adapter->rcv_lock, flags); | |
1858 | ||
1859 | /* These local variables track the PSR in the adapter structure */ | |
1860 | rx_local->local_psr_full = 0; | |
1861 | ||
788ca84a ME |
1862 | for (id = 0; id < NUM_FBRS; id++) { |
1863 | u32 *num_des; | |
1864 | u32 *full_offset; | |
1865 | u32 *min_des; | |
1866 | u32 *base_hi; | |
1867 | u32 *base_lo; | |
1868 | ||
1869 | if (id == 0) { | |
788ca84a ME |
1870 | num_des = &rx_dma->fbr0_num_des; |
1871 | full_offset = &rx_dma->fbr0_full_offset; | |
1872 | min_des = &rx_dma->fbr0_min_des; | |
1873 | base_hi = &rx_dma->fbr0_base_hi; | |
1874 | base_lo = &rx_dma->fbr0_base_lo; | |
f0ada678 ME |
1875 | } else { |
1876 | num_des = &rx_dma->fbr1_num_des; | |
1877 | full_offset = &rx_dma->fbr1_full_offset; | |
1878 | min_des = &rx_dma->fbr1_min_des; | |
1879 | base_hi = &rx_dma->fbr1_base_hi; | |
1880 | base_lo = &rx_dma->fbr1_base_lo; | |
788ca84a | 1881 | } |
36f2771a | 1882 | |
788ca84a | 1883 | /* Now's the best time to initialize FBR contents */ |
3781683e ME |
1884 | fbr_entry = |
1885 | (struct fbr_desc *) rx_local->fbr[id]->ring_virtaddr; | |
1886 | for (entry = 0; | |
1887 | entry < rx_local->fbr[id]->num_entries; entry++) { | |
788ca84a ME |
1888 | fbr_entry->addr_hi = rx_local->fbr[id]->bus_high[entry]; |
1889 | fbr_entry->addr_lo = rx_local->fbr[id]->bus_low[entry]; | |
1890 | fbr_entry->word2 = entry; | |
1891 | fbr_entry++; | |
1892 | } | |
36f2771a | 1893 | |
788ca84a ME |
1894 | /* Set the address and parameters of Free buffer ring 1 and 0 |
1895 | * into the 1310's registers | |
1896 | */ | |
3781683e ME |
1897 | writel(upper_32_bits(rx_local->fbr[id]->ring_physaddr), |
1898 | base_hi); | |
1899 | writel(lower_32_bits(rx_local->fbr[id]->ring_physaddr), | |
1900 | base_lo); | |
788ca84a ME |
1901 | writel(rx_local->fbr[id]->num_entries - 1, num_des); |
1902 | writel(ET_DMA10_WRAP, full_offset); | |
36f2771a | 1903 | |
788ca84a ME |
1904 | /* This variable tracks the free buffer ring 1 full position, |
1905 | * so it has to match the above. | |
1906 | */ | |
1907 | rx_local->fbr[id]->local_full = ET_DMA10_WRAP; | |
1908 | writel(((rx_local->fbr[id]->num_entries * | |
1909 | LO_MARK_PERCENT_FOR_RX) / 100) - 1, | |
1910 | min_des); | |
1911 | } | |
36f2771a ME |
1912 | |
1913 | /* Program the number of packets we will receive before generating an | |
1914 | * interrupt. | |
1915 | * For version B silicon, this value gets updated once autoneg is | |
1916 | *complete. | |
1917 | */ | |
1918 | writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done); | |
1919 | ||
1920 | /* The "time_done" is not working correctly to coalesce interrupts | |
1921 | * after a given time period, but rather is giving us an interrupt | |
1922 | * regardless of whether we have received packets. | |
1923 | * This value gets updated once autoneg is complete. | |
1924 | */ | |
1925 | writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time); | |
1926 | ||
1927 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); | |
1928 | } | |
1929 | ||
1930 | /** | |
1931 | * et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore. | |
1932 | * @adapter: pointer to our private adapter structure | |
1933 | * | |
1934 | * Configure the transmit engine with the ring buffers we have created | |
1935 | * and prepare it for use. | |
1936 | */ | |
eb7a6ca6 | 1937 | static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter) |
36f2771a ME |
1938 | { |
1939 | struct txdma_regs __iomem *txdma = &adapter->regs->txdma; | |
1940 | ||
1941 | /* Load the hardware with the start of the transmit descriptor ring. */ | |
25e8e8ab | 1942 | writel(upper_32_bits(adapter->tx_ring.tx_desc_ring_pa), |
36f2771a | 1943 | &txdma->pr_base_hi); |
25e8e8ab | 1944 | writel(lower_32_bits(adapter->tx_ring.tx_desc_ring_pa), |
36f2771a ME |
1945 | &txdma->pr_base_lo); |
1946 | ||
1947 | /* Initialise the transmit DMA engine */ | |
1948 | writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des); | |
1949 | ||
1950 | /* Load the completion writeback physical address */ | |
25e8e8ab ME |
1951 | writel(upper_32_bits(adapter->tx_ring.tx_status_pa), |
1952 | &txdma->dma_wb_base_hi); | |
1953 | writel(lower_32_bits(adapter->tx_ring.tx_status_pa), | |
1954 | &txdma->dma_wb_base_lo); | |
36f2771a ME |
1955 | |
1956 | *adapter->tx_ring.tx_status = 0; | |
1957 | ||
1958 | writel(0, &txdma->service_request); | |
1959 | adapter->tx_ring.send_idx = 0; | |
1960 | } | |
1961 | ||
1962 | /** | |
1963 | * et131x_adapter_setup - Set the adapter up as per cassini+ documentation | |
1964 | * @adapter: pointer to our private adapter structure | |
1965 | * | |
1966 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
1967 | */ | |
eb7a6ca6 | 1968 | static void et131x_adapter_setup(struct et131x_adapter *adapter) |
36f2771a ME |
1969 | { |
1970 | /* Configure the JAGCore */ | |
1971 | et131x_configure_global_regs(adapter); | |
1972 | ||
1973 | et1310_config_mac_regs1(adapter); | |
1974 | ||
1975 | /* Configure the MMC registers */ | |
1976 | /* All we need to do is initialize the Memory Control Register */ | |
1977 | writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl); | |
1978 | ||
1979 | et1310_config_rxmac_regs(adapter); | |
1980 | et1310_config_txmac_regs(adapter); | |
1981 | ||
1982 | et131x_config_rx_dma_regs(adapter); | |
1983 | et131x_config_tx_dma_regs(adapter); | |
1984 | ||
1985 | et1310_config_macstat_regs(adapter); | |
1986 | ||
1987 | et1310_phy_power_down(adapter, 0); | |
1988 | et131x_xcvr_init(adapter); | |
1989 | } | |
1990 | ||
5da2b158 ME |
1991 | /** |
1992 | * et131x_soft_reset - Issue a soft reset to the hardware, complete for ET1310 | |
1993 | * @adapter: pointer to our private adapter structure | |
1994 | */ | |
eb7a6ca6 | 1995 | static void et131x_soft_reset(struct et131x_adapter *adapter) |
5da2b158 | 1996 | { |
a129be84 | 1997 | u32 reg; |
5da2b158 | 1998 | |
a129be84 ME |
1999 | /* Disable MAC Core */ |
2000 | reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET | | |
2001 | ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC | | |
2002 | ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC; | |
2003 | writel(reg, &adapter->regs->mac.cfg1); | |
2004 | ||
2005 | reg = ET_RESET_ALL; | |
2006 | writel(reg, &adapter->regs->global.sw_reset); | |
2007 | ||
2008 | reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC | | |
2009 | ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC; | |
2010 | writel(reg, &adapter->regs->mac.cfg1); | |
2011 | writel(0, &adapter->regs->mac.cfg1); | |
5da2b158 ME |
2012 | } |
2013 | ||
a4d444bd ME |
2014 | /** |
2015 | * et131x_enable_interrupts - enable interrupt | |
2016 | * @adapter: et131x device | |
2017 | * | |
2018 | * Enable the appropriate interrupts on the ET131x according to our | |
2019 | * configuration | |
2020 | */ | |
eb7a6ca6 | 2021 | static void et131x_enable_interrupts(struct et131x_adapter *adapter) |
a4d444bd ME |
2022 | { |
2023 | u32 mask; | |
2024 | ||
2025 | /* Enable all global interrupts */ | |
2026 | if (adapter->flowcontrol == FLOW_TXONLY || | |
2027 | adapter->flowcontrol == FLOW_BOTH) | |
2028 | mask = INT_MASK_ENABLE; | |
2029 | else | |
2030 | mask = INT_MASK_ENABLE_NO_FLOW; | |
2031 | ||
2032 | writel(mask, &adapter->regs->global.int_mask); | |
2033 | } | |
2034 | ||
2035 | /** | |
2036 | * et131x_disable_interrupts - interrupt disable | |
2037 | * @adapter: et131x device | |
2038 | * | |
2039 | * Block all interrupts from the et131x device at the device itself | |
2040 | */ | |
eb7a6ca6 | 2041 | static void et131x_disable_interrupts(struct et131x_adapter *adapter) |
a4d444bd ME |
2042 | { |
2043 | /* Disable all global interrupts */ | |
2044 | writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask); | |
2045 | } | |
2046 | ||
2047 | /** | |
2048 | * et131x_tx_dma_disable - Stop of Tx_DMA on the ET1310 | |
2049 | * @adapter: pointer to our adapter structure | |
2050 | */ | |
eb7a6ca6 | 2051 | static void et131x_tx_dma_disable(struct et131x_adapter *adapter) |
a4d444bd ME |
2052 | { |
2053 | /* Setup the tramsmit dma configuration register */ | |
3040d056 | 2054 | writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT, |
a4d444bd ME |
2055 | &adapter->regs->txdma.csr); |
2056 | } | |
2057 | ||
a4d444bd ME |
2058 | /** |
2059 | * et131x_enable_txrx - Enable tx/rx queues | |
2060 | * @netdev: device to be enabled | |
2061 | */ | |
eb7a6ca6 | 2062 | static void et131x_enable_txrx(struct net_device *netdev) |
a4d444bd ME |
2063 | { |
2064 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
2065 | ||
2066 | /* Enable the Tx and Rx DMA engines (if not already enabled) */ | |
2067 | et131x_rx_dma_enable(adapter); | |
2068 | et131x_tx_dma_enable(adapter); | |
2069 | ||
2070 | /* Enable device interrupts */ | |
2071 | if (adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE) | |
2072 | et131x_enable_interrupts(adapter); | |
2073 | ||
2074 | /* We're ready to move some data, so start the queue */ | |
2075 | netif_start_queue(netdev); | |
2076 | } | |
2077 | ||
2078 | /** | |
2079 | * et131x_disable_txrx - Disable tx/rx queues | |
2080 | * @netdev: device to be disabled | |
2081 | */ | |
eb7a6ca6 | 2082 | static void et131x_disable_txrx(struct net_device *netdev) |
a4d444bd ME |
2083 | { |
2084 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
2085 | ||
2086 | /* First thing is to stop the queue */ | |
2087 | netif_stop_queue(netdev); | |
2088 | ||
2089 | /* Stop the Tx and Rx DMA engines */ | |
2090 | et131x_rx_dma_disable(adapter); | |
2091 | et131x_tx_dma_disable(adapter); | |
2092 | ||
2093 | /* Disable device interrupts */ | |
2094 | et131x_disable_interrupts(adapter); | |
2095 | } | |
2096 | ||
8310c602 ME |
2097 | /** |
2098 | * et131x_init_send - Initialize send data structures | |
2099 | * @adapter: pointer to our private adapter structure | |
2100 | */ | |
eb7a6ca6 | 2101 | static void et131x_init_send(struct et131x_adapter *adapter) |
8310c602 ME |
2102 | { |
2103 | struct tcb *tcb; | |
2104 | u32 ct; | |
2105 | struct tx_ring *tx_ring; | |
2106 | ||
2107 | /* Setup some convenience pointers */ | |
2108 | tx_ring = &adapter->tx_ring; | |
2109 | tcb = adapter->tx_ring.tcb_ring; | |
2110 | ||
2111 | tx_ring->tcb_qhead = tcb; | |
2112 | ||
2113 | memset(tcb, 0, sizeof(struct tcb) * NUM_TCB); | |
2114 | ||
2115 | /* Go through and set up each TCB */ | |
2116 | for (ct = 0; ct++ < NUM_TCB; tcb++) | |
2117 | /* Set the link pointer in HW TCB to the next TCB in the | |
2118 | * chain | |
2119 | */ | |
2120 | tcb->next = tcb + 1; | |
2121 | ||
2122 | /* Set the tail pointer */ | |
2123 | tcb--; | |
2124 | tx_ring->tcb_qtail = tcb; | |
2125 | tcb->next = NULL; | |
2126 | /* Curr send queue should now be empty */ | |
2127 | tx_ring->send_head = NULL; | |
2128 | tx_ring->send_tail = NULL; | |
2129 | } | |
2130 | ||
d2796743 ME |
2131 | /** |
2132 | * et1310_enable_phy_coma - called when network cable is unplugged | |
2133 | * @adapter: pointer to our adapter structure | |
2134 | * | |
2135 | * driver receive an phy status change interrupt while in D0 and check that | |
2136 | * phy_status is down. | |
2137 | * | |
2138 | * -- gate off JAGCore; | |
2139 | * -- set gigE PHY in Coma mode | |
2140 | * -- wake on phy_interrupt; Perform software reset JAGCore, | |
2141 | * re-initialize jagcore and gigE PHY | |
2142 | * | |
2143 | * Add D0-ASPM-PhyLinkDown Support: | |
2144 | * -- while in D0, when there is a phy_interrupt indicating phy link | |
2145 | * down status, call the MPSetPhyComa routine to enter this active | |
2146 | * state power saving mode | |
2147 | * -- while in D0-ASPM-PhyLinkDown mode, when there is a phy_interrupt | |
2148 | * indicating linkup status, call the MPDisablePhyComa routine to | |
2149 | * restore JAGCore and gigE PHY | |
2150 | */ | |
eb7a6ca6 | 2151 | static void et1310_enable_phy_coma(struct et131x_adapter *adapter) |
d2796743 ME |
2152 | { |
2153 | unsigned long flags; | |
2154 | u32 pmcsr; | |
2155 | ||
2156 | pmcsr = readl(&adapter->regs->global.pm_csr); | |
2157 | ||
2158 | /* Save the GbE PHY speed and duplex modes. Need to restore this | |
2159 | * when cable is plugged back in | |
2160 | */ | |
2161 | /* | |
2162 | * TODO - when PM is re-enabled, check if we need to | |
2163 | * perform a similar task as this - | |
2164 | * adapter->pdown_speed = adapter->ai_force_speed; | |
2165 | * adapter->pdown_duplex = adapter->ai_force_duplex; | |
2166 | */ | |
2167 | ||
2168 | /* Stop sending packets. */ | |
2169 | spin_lock_irqsave(&adapter->send_hw_lock, flags); | |
2170 | adapter->flags |= fMP_ADAPTER_LOWER_POWER; | |
2171 | spin_unlock_irqrestore(&adapter->send_hw_lock, flags); | |
2172 | ||
2173 | /* Wait for outstanding Receive packets */ | |
2174 | ||
2175 | et131x_disable_txrx(adapter->netdev); | |
2176 | ||
2177 | /* Gate off JAGCore 3 clock domains */ | |
2178 | pmcsr &= ~ET_PMCSR_INIT; | |
2179 | writel(pmcsr, &adapter->regs->global.pm_csr); | |
2180 | ||
2181 | /* Program gigE PHY in to Coma mode */ | |
2182 | pmcsr |= ET_PM_PHY_SW_COMA; | |
2183 | writel(pmcsr, &adapter->regs->global.pm_csr); | |
2184 | } | |
2185 | ||
2186 | /** | |
2187 | * et1310_disable_phy_coma - Disable the Phy Coma Mode | |
2188 | * @adapter: pointer to our adapter structure | |
2189 | */ | |
eb7a6ca6 | 2190 | static void et1310_disable_phy_coma(struct et131x_adapter *adapter) |
d2796743 ME |
2191 | { |
2192 | u32 pmcsr; | |
2193 | ||
2194 | pmcsr = readl(&adapter->regs->global.pm_csr); | |
2195 | ||
2196 | /* Disable phy_sw_coma register and re-enable JAGCore clocks */ | |
2197 | pmcsr |= ET_PMCSR_INIT; | |
2198 | pmcsr &= ~ET_PM_PHY_SW_COMA; | |
2199 | writel(pmcsr, &adapter->regs->global.pm_csr); | |
2200 | ||
2201 | /* Restore the GbE PHY speed and duplex modes; | |
2202 | * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY | |
2203 | */ | |
2204 | /* TODO - when PM is re-enabled, check if we need to | |
2205 | * perform a similar task as this - | |
2206 | * adapter->ai_force_speed = adapter->pdown_speed; | |
2207 | * adapter->ai_force_duplex = adapter->pdown_duplex; | |
2208 | */ | |
2209 | ||
2210 | /* Re-initialize the send structures */ | |
2211 | et131x_init_send(adapter); | |
2212 | ||
d2796743 ME |
2213 | /* Bring the device back to the state it was during init prior to |
2214 | * autonegotiation being complete. This way, when we get the auto-neg | |
2215 | * complete interrupt, we can complete init by calling ConfigMacREGS2. | |
2216 | */ | |
2217 | et131x_soft_reset(adapter); | |
2218 | ||
2219 | /* setup et1310 as per the documentation ?? */ | |
2220 | et131x_adapter_setup(adapter); | |
2221 | ||
2222 | /* Allow Tx to restart */ | |
2223 | adapter->flags &= ~fMP_ADAPTER_LOWER_POWER; | |
2224 | ||
2225 | et131x_enable_txrx(adapter->netdev); | |
2226 | } | |
2227 | ||
d2796743 ME |
2228 | static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit) |
2229 | { | |
2230 | u32 tmp_free_buff_ring = *free_buff_ring; | |
2231 | tmp_free_buff_ring++; | |
2232 | /* This works for all cases where limit < 1024. The 1023 case | |
2233 | works because 1023++ is 1024 which means the if condition is not | |
2234 | taken but the carry of the bit into the wrap bit toggles the wrap | |
2235 | value correctly */ | |
2236 | if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) { | |
2237 | tmp_free_buff_ring &= ~ET_DMA10_MASK; | |
2238 | tmp_free_buff_ring ^= ET_DMA10_WRAP; | |
2239 | } | |
2240 | /* For the 1023 case */ | |
2241 | tmp_free_buff_ring &= (ET_DMA10_MASK|ET_DMA10_WRAP); | |
2242 | *free_buff_ring = tmp_free_buff_ring; | |
2243 | return tmp_free_buff_ring; | |
2244 | } | |
2245 | ||
2246 | /** | |
2247 | * et131x_rx_dma_memory_alloc | |
2248 | * @adapter: pointer to our private adapter structure | |
2249 | * | |
2250 | * Returns 0 on success and errno on failure (as defined in errno.h) | |
2251 | * | |
2252 | * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required, | |
2253 | * and the Packet Status Ring. | |
2254 | */ | |
eb7a6ca6 | 2255 | static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter) |
d2796743 | 2256 | { |
788ca84a | 2257 | u8 id; |
d2796743 ME |
2258 | u32 i, j; |
2259 | u32 bufsize; | |
87648933 ME |
2260 | u32 pktstat_ringsize; |
2261 | u32 fbr_chunksize; | |
d2796743 ME |
2262 | struct rx_ring *rx_ring; |
2263 | ||
2264 | /* Setup some convenience pointers */ | |
2265 | rx_ring = &adapter->rx_ring; | |
2266 | ||
2267 | /* Alloc memory for the lookup table */ | |
e592a9b0 | 2268 | rx_ring->fbr[0] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); |
f0ada678 | 2269 | rx_ring->fbr[1] = kmalloc(sizeof(struct fbr_lookup), GFP_KERNEL); |
d2796743 ME |
2270 | |
2271 | /* The first thing we will do is configure the sizes of the buffer | |
2272 | * rings. These will change based on jumbo packet support. Larger | |
2273 | * jumbo packets increases the size of each entry in FBR0, and the | |
2274 | * number of entries in FBR0, while at the same time decreasing the | |
2275 | * number of entries in FBR1. | |
2276 | * | |
2277 | * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1 | |
2278 | * entries are huge in order to accommodate a "jumbo" frame, then it | |
2279 | * will have less entries. Conversely, FBR1 will now be relied upon | |
2280 | * to carry more "normal" frames, thus it's entry size also increases | |
2281 | * and the number of entries goes up too (since it now carries | |
2282 | * "small" + "regular" packets. | |
2283 | * | |
2284 | * In this scheme, we try to maintain 512 entries between the two | |
2285 | * rings. Also, FBR1 remains a constant size - when it's size doubles | |
2286 | * the number of entries halves. FBR0 increases in size, however. | |
2287 | */ | |
2288 | ||
2289 | if (adapter->registry_jumbo_packet < 2048) { | |
f0ada678 | 2290 | rx_ring->fbr[0]->buffsize = 256; |
e592a9b0 | 2291 | rx_ring->fbr[0]->num_entries = 512; |
f0ada678 ME |
2292 | rx_ring->fbr[1]->buffsize = 2048; |
2293 | rx_ring->fbr[1]->num_entries = 512; | |
d2796743 | 2294 | } else if (adapter->registry_jumbo_packet < 4096) { |
f0ada678 ME |
2295 | rx_ring->fbr[0]->buffsize = 512; |
2296 | rx_ring->fbr[0]->num_entries = 1024; | |
2297 | rx_ring->fbr[1]->buffsize = 4096; | |
2298 | rx_ring->fbr[1]->num_entries = 512; | |
d2796743 | 2299 | } else { |
f0ada678 ME |
2300 | rx_ring->fbr[0]->buffsize = 1024; |
2301 | rx_ring->fbr[0]->num_entries = 768; | |
2302 | rx_ring->fbr[1]->buffsize = 16384; | |
2303 | rx_ring->fbr[1]->num_entries = 128; | |
d2796743 ME |
2304 | } |
2305 | ||
09a3fc2b | 2306 | adapter->rx_ring.psr_num_entries = |
f0ada678 ME |
2307 | adapter->rx_ring.fbr[0]->num_entries + |
2308 | adapter->rx_ring.fbr[1]->num_entries; | |
d2796743 | 2309 | |
788ca84a ME |
2310 | for (id = 0; id < NUM_FBRS; id++) { |
2311 | /* Allocate an area of memory for Free Buffer Ring */ | |
3781683e ME |
2312 | bufsize = |
2313 | (sizeof(struct fbr_desc) * rx_ring->fbr[id]->num_entries); | |
788ca84a ME |
2314 | rx_ring->fbr[id]->ring_virtaddr = |
2315 | dma_alloc_coherent(&adapter->pdev->dev, | |
0d1b7a84 | 2316 | bufsize, |
788ca84a | 2317 | &rx_ring->fbr[id]->ring_physaddr, |
0d1b7a84 | 2318 | GFP_KERNEL); |
788ca84a | 2319 | if (!rx_ring->fbr[id]->ring_virtaddr) { |
d2796743 | 2320 | dev_err(&adapter->pdev->dev, |
788ca84a | 2321 | "Cannot alloc memory for Free Buffer Ring %d\n", id); |
d2796743 ME |
2322 | return -ENOMEM; |
2323 | } | |
d2796743 ME |
2324 | } |
2325 | ||
788ca84a | 2326 | for (id = 0; id < NUM_FBRS; id++) { |
d3c75e8d | 2327 | fbr_chunksize = (FBR_CHUNKS * rx_ring->fbr[id]->buffsize); |
87648933 | 2328 | |
3781683e ME |
2329 | for (i = 0; |
2330 | i < (rx_ring->fbr[id]->num_entries / FBR_CHUNKS); i++) { | |
788ca84a | 2331 | dma_addr_t fbr_tmp_physaddr; |
788ca84a | 2332 | |
788ca84a ME |
2333 | rx_ring->fbr[id]->mem_virtaddrs[i] = dma_alloc_coherent( |
2334 | &adapter->pdev->dev, fbr_chunksize, | |
2335 | &rx_ring->fbr[id]->mem_physaddrs[i], | |
2336 | GFP_KERNEL); | |
d2796743 | 2337 | |
788ca84a ME |
2338 | if (!rx_ring->fbr[id]->mem_virtaddrs[i]) { |
2339 | dev_err(&adapter->pdev->dev, | |
2340 | "Could not alloc memory\n"); | |
2341 | return -ENOMEM; | |
2342 | } | |
d2796743 | 2343 | |
788ca84a ME |
2344 | /* See NOTE in "Save Physical Address" comment above */ |
2345 | fbr_tmp_physaddr = rx_ring->fbr[id]->mem_physaddrs[i]; | |
2346 | ||
788ca84a ME |
2347 | for (j = 0; j < FBR_CHUNKS; j++) { |
2348 | u32 index = (i * FBR_CHUNKS) + j; | |
2349 | ||
2350 | /* Save the Virtual address of this index for | |
2351 | * quick access later | |
2352 | */ | |
2353 | rx_ring->fbr[id]->virt[index] = | |
2354 | (u8 *) rx_ring->fbr[id]->mem_virtaddrs[i] + | |
d3c75e8d | 2355 | (j * rx_ring->fbr[id]->buffsize); |
788ca84a ME |
2356 | |
2357 | /* now store the physical address in the | |
2358 | * descriptor so the device can access it | |
2359 | */ | |
2360 | rx_ring->fbr[id]->bus_high[index] = | |
2361 | upper_32_bits(fbr_tmp_physaddr); | |
2362 | rx_ring->fbr[id]->bus_low[index] = | |
2363 | lower_32_bits(fbr_tmp_physaddr); | |
2364 | ||
2365 | fbr_tmp_physaddr += rx_ring->fbr[id]->buffsize; | |
788ca84a | 2366 | } |
d2796743 ME |
2367 | } |
2368 | } | |
d2796743 ME |
2369 | |
2370 | /* Allocate an area of memory for FIFO of Packet Status ring entries */ | |
2371 | pktstat_ringsize = | |
2372 | sizeof(struct pkt_stat_desc) * adapter->rx_ring.psr_num_entries; | |
2373 | ||
0d1b7a84 | 2374 | rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev, |
d2796743 | 2375 | pktstat_ringsize, |
0d1b7a84 ME |
2376 | &rx_ring->ps_ring_physaddr, |
2377 | GFP_KERNEL); | |
d2796743 ME |
2378 | |
2379 | if (!rx_ring->ps_ring_virtaddr) { | |
2380 | dev_err(&adapter->pdev->dev, | |
2381 | "Cannot alloc memory for Packet Status Ring\n"); | |
2382 | return -ENOMEM; | |
2383 | } | |
e58b89da TY |
2384 | pr_info("Packet Status Ring %llx\n", |
2385 | (unsigned long long) rx_ring->ps_ring_physaddr); | |
d2796743 ME |
2386 | |
2387 | /* | |
26dc751e | 2388 | * NOTE : dma_alloc_coherent(), used above to alloc DMA regions, |
d2796743 ME |
2389 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
2390 | * are ever returned, make sure the high part is retrieved here before | |
2391 | * storing the adjusted address. | |
2392 | */ | |
2393 | ||
2394 | /* Allocate an area of memory for writeback of status information */ | |
0d1b7a84 | 2395 | rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev, |
d2796743 | 2396 | sizeof(struct rx_status_block), |
0d1b7a84 ME |
2397 | &rx_ring->rx_status_bus, |
2398 | GFP_KERNEL); | |
d2796743 ME |
2399 | if (!rx_ring->rx_status_block) { |
2400 | dev_err(&adapter->pdev->dev, | |
2401 | "Cannot alloc memory for Status Block\n"); | |
2402 | return -ENOMEM; | |
2403 | } | |
2404 | rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD; | |
e58b89da | 2405 | pr_info("PRS %llx\n", (unsigned long long)rx_ring->rx_status_bus); |
d2796743 | 2406 | |
d2796743 ME |
2407 | /* The RFDs are going to be put on lists later on, so initialize the |
2408 | * lists now. | |
2409 | */ | |
2410 | INIT_LIST_HEAD(&rx_ring->recv_list); | |
2411 | return 0; | |
2412 | } | |
2413 | ||
2414 | /** | |
2415 | * et131x_rx_dma_memory_free - Free all memory allocated within this module. | |
2416 | * @adapter: pointer to our private adapter structure | |
2417 | */ | |
eb7a6ca6 | 2418 | static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter) |
d2796743 | 2419 | { |
788ca84a | 2420 | u8 id; |
d2796743 ME |
2421 | u32 index; |
2422 | u32 bufsize; | |
2423 | u32 pktstat_ringsize; | |
2424 | struct rfd *rfd; | |
2425 | struct rx_ring *rx_ring; | |
2426 | ||
2427 | /* Setup some convenience pointers */ | |
2428 | rx_ring = &adapter->rx_ring; | |
2429 | ||
2430 | /* Free RFDs and associated packet descriptors */ | |
2431 | WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd); | |
2432 | ||
2433 | while (!list_empty(&rx_ring->recv_list)) { | |
2434 | rfd = (struct rfd *) list_entry(rx_ring->recv_list.next, | |
2435 | struct rfd, list_node); | |
2436 | ||
2437 | list_del(&rfd->list_node); | |
2438 | rfd->skb = NULL; | |
d959df0a | 2439 | kfree(rfd); |
d2796743 ME |
2440 | } |
2441 | ||
788ca84a ME |
2442 | /* Free Free Buffer Rings */ |
2443 | for (id = 0; id < NUM_FBRS; id++) { | |
823bb2e8 ME |
2444 | if (!rx_ring->fbr[id]->ring_virtaddr) |
2445 | continue; | |
d2796743 | 2446 | |
823bb2e8 ME |
2447 | /* First the packet memory */ |
2448 | for (index = 0; | |
2449 | index < (rx_ring->fbr[id]->num_entries / FBR_CHUNKS); | |
2450 | index++) { | |
2451 | if (rx_ring->fbr[id]->mem_virtaddrs[index]) { | |
3781683e ME |
2452 | bufsize = |
2453 | rx_ring->fbr[id]->buffsize * FBR_CHUNKS; | |
d2796743 | 2454 | |
823bb2e8 ME |
2455 | dma_free_coherent(&adapter->pdev->dev, |
2456 | bufsize, | |
2457 | rx_ring->fbr[id]->mem_virtaddrs[index], | |
2458 | rx_ring->fbr[id]->mem_physaddrs[index]); | |
d2796743 | 2459 | |
823bb2e8 ME |
2460 | rx_ring->fbr[id]->mem_virtaddrs[index] = NULL; |
2461 | } | |
d2796743 | 2462 | } |
823bb2e8 ME |
2463 | |
2464 | bufsize = | |
2465 | sizeof(struct fbr_desc) * rx_ring->fbr[id]->num_entries; | |
2466 | ||
2467 | dma_free_coherent(&adapter->pdev->dev, bufsize, | |
2468 | rx_ring->fbr[id]->ring_virtaddr, | |
2469 | rx_ring->fbr[id]->ring_physaddr); | |
2470 | ||
2471 | rx_ring->fbr[id]->ring_virtaddr = NULL; | |
d2796743 | 2472 | } |
d2796743 ME |
2473 | |
2474 | /* Free Packet Status Ring */ | |
2475 | if (rx_ring->ps_ring_virtaddr) { | |
242187aa ME |
2476 | pktstat_ringsize = sizeof(struct pkt_stat_desc) * |
2477 | adapter->rx_ring.psr_num_entries; | |
d2796743 | 2478 | |
675c8f68 | 2479 | dma_free_coherent(&adapter->pdev->dev, pktstat_ringsize, |
d2796743 ME |
2480 | rx_ring->ps_ring_virtaddr, |
2481 | rx_ring->ps_ring_physaddr); | |
2482 | ||
2483 | rx_ring->ps_ring_virtaddr = NULL; | |
2484 | } | |
2485 | ||
2486 | /* Free area of memory for the writeback of status information */ | |
2487 | if (rx_ring->rx_status_block) { | |
675c8f68 | 2488 | dma_free_coherent(&adapter->pdev->dev, |
d2796743 ME |
2489 | sizeof(struct rx_status_block), |
2490 | rx_ring->rx_status_block, rx_ring->rx_status_bus); | |
2491 | rx_ring->rx_status_block = NULL; | |
2492 | } | |
2493 | ||
d2796743 | 2494 | /* Free the FBR Lookup Table */ |
e592a9b0 | 2495 | kfree(rx_ring->fbr[0]); |
f0ada678 | 2496 | kfree(rx_ring->fbr[1]); |
d2796743 ME |
2497 | |
2498 | /* Reset Counters */ | |
2499 | rx_ring->num_ready_recv = 0; | |
2500 | } | |
2501 | ||
2502 | /** | |
2503 | * et131x_init_recv - Initialize receive data structures. | |
2504 | * @adapter: pointer to our private adapter structure | |
2505 | * | |
2506 | * Returns 0 on success and errno on failure (as defined in errno.h) | |
2507 | */ | |
eb7a6ca6 | 2508 | static int et131x_init_recv(struct et131x_adapter *adapter) |
d2796743 | 2509 | { |
d959df0a | 2510 | struct rfd *rfd; |
d2796743 ME |
2511 | u32 rfdct; |
2512 | u32 numrfd = 0; | |
2513 | struct rx_ring *rx_ring; | |
2514 | ||
2515 | /* Setup some convenience pointers */ | |
2516 | rx_ring = &adapter->rx_ring; | |
2517 | ||
2518 | /* Setup each RFD */ | |
2519 | for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) { | |
d959df0a | 2520 | rfd = kzalloc(sizeof(struct rfd), GFP_ATOMIC | GFP_DMA); |
d2796743 ME |
2521 | |
2522 | if (!rfd) { | |
d959df0a ME |
2523 | dev_err(&adapter->pdev->dev, "Couldn't alloc RFD\n"); |
2524 | return -ENOMEM; | |
d2796743 ME |
2525 | } |
2526 | ||
2527 | rfd->skb = NULL; | |
2528 | ||
2529 | /* Add this RFD to the recv_list */ | |
2530 | list_add_tail(&rfd->list_node, &rx_ring->recv_list); | |
2531 | ||
2532 | /* Increment both the available RFD's, and the total RFD's. */ | |
2533 | rx_ring->num_ready_recv++; | |
2534 | numrfd++; | |
2535 | } | |
2536 | ||
d959df0a | 2537 | return 0; |
d2796743 ME |
2538 | } |
2539 | ||
d2796743 ME |
2540 | /** |
2541 | * et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate. | |
2542 | * @adapter: pointer to our adapter structure | |
2543 | */ | |
eb7a6ca6 | 2544 | static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter) |
d2796743 ME |
2545 | { |
2546 | struct phy_device *phydev = adapter->phydev; | |
2547 | ||
2548 | if (!phydev) | |
2549 | return; | |
2550 | ||
2551 | /* For version B silicon, we do not use the RxDMA timer for 10 and 100 | |
2552 | * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing. | |
2553 | */ | |
2554 | if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) { | |
2555 | writel(0, &adapter->regs->rxdma.max_pkt_time); | |
2556 | writel(1, &adapter->regs->rxdma.num_pkt_done); | |
2557 | } | |
2558 | } | |
2559 | ||
2560 | /** | |
2561 | * NICReturnRFD - Recycle a RFD and put it back onto the receive list | |
2562 | * @adapter: pointer to our adapter | |
2563 | * @rfd: pointer to the RFD | |
2564 | */ | |
2565 | static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd) | |
2566 | { | |
2567 | struct rx_ring *rx_local = &adapter->rx_ring; | |
2568 | struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma; | |
2569 | u16 buff_index = rfd->bufferindex; | |
2570 | u8 ring_index = rfd->ringindex; | |
2571 | unsigned long flags; | |
2572 | ||
2573 | /* We don't use any of the OOB data besides status. Otherwise, we | |
2574 | * need to clean up OOB data | |
2575 | */ | |
f0ada678 | 2576 | if (buff_index < rx_local->fbr[ring_index]->num_entries) { |
788ca84a | 2577 | u32 *offset; |
788ca84a ME |
2578 | struct fbr_desc *next; |
2579 | ||
d2796743 ME |
2580 | spin_lock_irqsave(&adapter->fbr_lock, flags); |
2581 | ||
f0ada678 | 2582 | if (ring_index == 0) |
788ca84a | 2583 | offset = &rx_dma->fbr0_full_offset; |
f0ada678 ME |
2584 | else |
2585 | offset = &rx_dma->fbr1_full_offset; | |
788ca84a | 2586 | |
3781683e ME |
2587 | next = (struct fbr_desc *) |
2588 | (rx_local->fbr[ring_index]->ring_virtaddr) + | |
f0ada678 | 2589 | INDEX10(rx_local->fbr[ring_index]->local_full); |
788ca84a ME |
2590 | |
2591 | /* Handle the Free Buffer Ring advancement here. Write | |
2592 | * the PA / Buffer Index for the returned buffer into | |
2593 | * the oldest (next to be freed)FBR entry | |
2594 | */ | |
f0ada678 ME |
2595 | next->addr_hi = rx_local->fbr[ring_index]->bus_high[buff_index]; |
2596 | next->addr_lo = rx_local->fbr[ring_index]->bus_low[buff_index]; | |
788ca84a ME |
2597 | next->word2 = buff_index; |
2598 | ||
3781683e ME |
2599 | writel(bump_free_buff_ring( |
2600 | &rx_local->fbr[ring_index]->local_full, | |
2601 | rx_local->fbr[ring_index]->num_entries - 1), | |
2602 | offset); | |
788ca84a | 2603 | |
d2796743 ME |
2604 | spin_unlock_irqrestore(&adapter->fbr_lock, flags); |
2605 | } else { | |
2606 | dev_err(&adapter->pdev->dev, | |
2607 | "%s illegal Buffer Index returned\n", __func__); | |
2608 | } | |
2609 | ||
2610 | /* The processing on this RFD is done, so put it back on the tail of | |
2611 | * our list | |
2612 | */ | |
2613 | spin_lock_irqsave(&adapter->rcv_lock, flags); | |
2614 | list_add_tail(&rfd->list_node, &rx_local->recv_list); | |
2615 | rx_local->num_ready_recv++; | |
2616 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); | |
2617 | ||
2618 | WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd); | |
2619 | } | |
2620 | ||
54dbf04f ME |
2621 | /** |
2622 | * nic_rx_pkts - Checks the hardware for available packets | |
2623 | * @adapter: pointer to our adapter | |
2624 | * | |
2625 | * Returns rfd, a pointer to our MPRFD. | |
2626 | * | |
2627 | * Checks the hardware for available packets, using completion ring | |
2628 | * If packets are available, it gets an RFD from the recv_list, attaches | |
2629 | * the packet to it, puts the RFD in the RecvPendList, and also returns | |
2630 | * the pointer to the RFD. | |
2631 | */ | |
d2796743 ME |
2632 | static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter) |
2633 | { | |
2634 | struct rx_ring *rx_local = &adapter->rx_ring; | |
2635 | struct rx_status_block *status; | |
2636 | struct pkt_stat_desc *psr; | |
186c426d | 2637 | struct rfd *rfd; |
d2796743 ME |
2638 | u32 i; |
2639 | u8 *buf; | |
2640 | unsigned long flags; | |
2641 | struct list_head *element; | |
2642 | u8 ring_index; | |
2643 | u16 buff_index; | |
2644 | u32 len; | |
2645 | u32 word0; | |
2646 | u32 word1; | |
186c426d | 2647 | struct sk_buff *skb; |
d2796743 ME |
2648 | |
2649 | /* RX Status block is written by the DMA engine prior to every | |
2650 | * interrupt. It contains the next to be used entry in the Packet | |
2651 | * Status Ring, and also the two Free Buffer rings. | |
2652 | */ | |
2653 | status = rx_local->rx_status_block; | |
2654 | word1 = status->word1 >> 16; /* Get the useful bits */ | |
2655 | ||
2656 | /* Check the PSR and wrap bits do not match */ | |
2657 | if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF)) | |
242187aa | 2658 | return NULL; /* Looks like this ring is not updated yet */ |
d2796743 ME |
2659 | |
2660 | /* The packet status ring indicates that data is available. */ | |
2661 | psr = (struct pkt_stat_desc *) (rx_local->ps_ring_virtaddr) + | |
2662 | (rx_local->local_psr_full & 0xFFF); | |
2663 | ||
242187aa ME |
2664 | /* Grab any information that is required once the PSR is advanced, |
2665 | * since we can no longer rely on the memory being accurate | |
d2796743 ME |
2666 | */ |
2667 | len = psr->word1 & 0xFFFF; | |
2668 | ring_index = (psr->word1 >> 26) & 0x03; | |
2669 | buff_index = (psr->word1 >> 16) & 0x3FF; | |
2670 | word0 = psr->word0; | |
2671 | ||
2672 | /* Indicate that we have used this PSR entry. */ | |
2673 | /* FIXME wrap 12 */ | |
2674 | add_12bit(&rx_local->local_psr_full, 1); | |
2675 | if ( | |
2676 | (rx_local->local_psr_full & 0xFFF) > rx_local->psr_num_entries - 1) { | |
2677 | /* Clear psr full and toggle the wrap bit */ | |
2678 | rx_local->local_psr_full &= ~0xFFF; | |
2679 | rx_local->local_psr_full ^= 0x1000; | |
2680 | } | |
2681 | ||
242187aa | 2682 | writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset); |
d2796743 | 2683 | |
d2796743 | 2684 | if (ring_index > 1 || |
f0ada678 | 2685 | buff_index > rx_local->fbr[ring_index]->num_entries - 1) { |
d2796743 ME |
2686 | /* Illegal buffer or ring index cannot be used by S/W*/ |
2687 | dev_err(&adapter->pdev->dev, | |
242187aa ME |
2688 | "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n", |
2689 | rx_local->local_psr_full & 0xFFF, len, buff_index); | |
d2796743 ME |
2690 | return NULL; |
2691 | } | |
2692 | ||
2693 | /* Get and fill the RFD. */ | |
2694 | spin_lock_irqsave(&adapter->rcv_lock, flags); | |
2695 | ||
d2796743 ME |
2696 | element = rx_local->recv_list.next; |
2697 | rfd = (struct rfd *) list_entry(element, struct rfd, list_node); | |
2698 | ||
242187aa | 2699 | if (!rfd) { |
d2796743 ME |
2700 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); |
2701 | return NULL; | |
2702 | } | |
2703 | ||
2704 | list_del(&rfd->list_node); | |
2705 | rx_local->num_ready_recv--; | |
2706 | ||
2707 | spin_unlock_irqrestore(&adapter->rcv_lock, flags); | |
2708 | ||
2709 | rfd->bufferindex = buff_index; | |
2710 | rfd->ringindex = ring_index; | |
2711 | ||
242187aa ME |
2712 | /* In V1 silicon, there is a bug which screws up filtering of runt |
2713 | * packets. Therefore runt packet filtering is disabled in the MAC and | |
2714 | * the packets are dropped here. They are also counted here. | |
d2796743 ME |
2715 | */ |
2716 | if (len < (NIC_MIN_PACKET_SIZE + 4)) { | |
2717 | adapter->stats.rx_other_errs++; | |
2718 | len = 0; | |
2719 | } | |
2720 | ||
242187aa ME |
2721 | if (len == 0) { |
2722 | rfd->len = 0; | |
2723 | goto out; | |
2724 | } | |
2725 | ||
2726 | /* Determine if this is a multicast packet coming in */ | |
2727 | if ((word0 & ALCATEL_MULTICAST_PKT) && | |
2728 | !(word0 & ALCATEL_BROADCAST_PKT)) { | |
2729 | /* Promiscuous mode and Multicast mode are not mutually | |
2730 | * exclusive as was first thought. I guess Promiscuous is just | |
2731 | * considered a super-set of the other filters. Generally filter | |
2732 | * is 0x2b when in promiscuous mode. | |
2733 | */ | |
2734 | if ((adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) | |
2735 | && !(adapter->packet_filter & ET131X_PACKET_TYPE_PROMISCUOUS) | |
2736 | && !(adapter->packet_filter & | |
d2796743 | 2737 | ET131X_PACKET_TYPE_ALL_MULTICAST)) { |
f0ada678 | 2738 | buf = rx_local->fbr[ring_index]->virt[buff_index]; |
d2796743 | 2739 | |
242187aa ME |
2740 | /* Loop through our list to see if the destination |
2741 | * address of this packet matches one in our list. | |
2742 | */ | |
2743 | for (i = 0; i < adapter->multicast_addr_count; i++) { | |
2744 | if (buf[0] == adapter->multicast_list[i][0] | |
2745 | && buf[1] == adapter->multicast_list[i][1] | |
2746 | && buf[2] == adapter->multicast_list[i][2] | |
2747 | && buf[3] == adapter->multicast_list[i][3] | |
2748 | && buf[4] == adapter->multicast_list[i][4] | |
2749 | && buf[5] == adapter->multicast_list[i][5]) { | |
2750 | break; | |
d2796743 | 2751 | } |
d2796743 ME |
2752 | } |
2753 | ||
242187aa ME |
2754 | /* If our index is equal to the number of Multicast |
2755 | * address we have, then this means we did not find this | |
2756 | * packet's matching address in our list. Set the len to | |
2757 | * zero, so we free our RFD when we return from this | |
2758 | * function. | |
d2796743 | 2759 | */ |
242187aa ME |
2760 | if (i == adapter->multicast_addr_count) |
2761 | len = 0; | |
2762 | } | |
d2796743 | 2763 | |
242187aa ME |
2764 | if (len > 0) |
2765 | adapter->stats.multicast_pkts_rcvd++; | |
2766 | } else if (word0 & ALCATEL_BROADCAST_PKT) { | |
2767 | adapter->stats.broadcast_pkts_rcvd++; | |
2768 | } else { | |
2769 | /* Not sure what this counter measures in promiscuous mode. | |
2770 | * Perhaps we should check the MAC address to see if it is | |
2771 | * directed to us in promiscuous mode. | |
2772 | */ | |
2773 | adapter->stats.unicast_pkts_rcvd++; | |
2774 | } | |
d2796743 | 2775 | |
242187aa ME |
2776 | if (len == 0) { |
2777 | rfd->len = 0; | |
2778 | goto out; | |
2779 | } | |
d2796743 | 2780 | |
242187aa | 2781 | rfd->len = len; |
d2796743 | 2782 | |
242187aa ME |
2783 | skb = dev_alloc_skb(rfd->len + 2); |
2784 | if (!skb) { | |
2785 | dev_err(&adapter->pdev->dev, "Couldn't alloc an SKB for Rx\n"); | |
2786 | return NULL; | |
2787 | } | |
d2796743 | 2788 | |
242187aa | 2789 | adapter->net_stats.rx_bytes += rfd->len; |
d2796743 | 2790 | |
242187aa | 2791 | memcpy(skb_put(skb, rfd->len), |
f0ada678 | 2792 | rx_local->fbr[ring_index]->virt[buff_index], |
242187aa | 2793 | rfd->len); |
d2796743 | 2794 | |
242187aa ME |
2795 | skb->dev = adapter->netdev; |
2796 | skb->protocol = eth_type_trans(skb, adapter->netdev); | |
2797 | skb->ip_summed = CHECKSUM_NONE; | |
2798 | netif_rx_ni(skb); | |
d2796743 | 2799 | |
242187aa | 2800 | out: |
d2796743 ME |
2801 | nic_return_rfd(adapter, rfd); |
2802 | return rfd; | |
2803 | } | |
2804 | ||
d2796743 ME |
2805 | /** |
2806 | * et131x_handle_recv_interrupt - Interrupt handler for receive processing | |
2807 | * @adapter: pointer to our adapter | |
2808 | * | |
2809 | * Assumption, Rcv spinlock has been acquired. | |
2810 | */ | |
eb7a6ca6 | 2811 | static void et131x_handle_recv_interrupt(struct et131x_adapter *adapter) |
d2796743 ME |
2812 | { |
2813 | struct rfd *rfd = NULL; | |
2814 | u32 count = 0; | |
2815 | bool done = true; | |
2816 | ||
2817 | /* Process up to available RFD's */ | |
2818 | while (count < NUM_PACKETS_HANDLED) { | |
2819 | if (list_empty(&adapter->rx_ring.recv_list)) { | |
2820 | WARN_ON(adapter->rx_ring.num_ready_recv != 0); | |
2821 | done = false; | |
2822 | break; | |
2823 | } | |
2824 | ||
2825 | rfd = nic_rx_pkts(adapter); | |
2826 | ||
2827 | if (rfd == NULL) | |
2828 | break; | |
2829 | ||
2830 | /* Do not receive any packets until a filter has been set. | |
2831 | * Do not receive any packets until we have link. | |
2832 | * If length is zero, return the RFD in order to advance the | |
2833 | * Free buffer ring. | |
2834 | */ | |
2835 | if (!adapter->packet_filter || | |
2836 | !netif_carrier_ok(adapter->netdev) || | |
2837 | rfd->len == 0) | |
2838 | continue; | |
2839 | ||
2840 | /* Increment the number of packets we received */ | |
2841 | adapter->net_stats.rx_packets++; | |
2842 | ||
2843 | /* Set the status on the packet, either resources or success */ | |
2844 | if (adapter->rx_ring.num_ready_recv < RFD_LOW_WATER_MARK) { | |
2845 | dev_warn(&adapter->pdev->dev, | |
2846 | "RFD's are running out\n"); | |
2847 | } | |
2848 | count++; | |
2849 | } | |
2850 | ||
2851 | if (count == NUM_PACKETS_HANDLED || !done) { | |
2852 | adapter->rx_ring.unfinished_receives = true; | |
2853 | writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO, | |
2854 | &adapter->regs->global.watchdog_timer); | |
2855 | } else | |
2856 | /* Watchdog timer will disable itself if appropriate. */ | |
2857 | adapter->rx_ring.unfinished_receives = false; | |
2858 | } | |
2859 | ||
d2796743 ME |
2860 | /** |
2861 | * et131x_tx_dma_memory_alloc | |
2862 | * @adapter: pointer to our private adapter structure | |
2863 | * | |
2864 | * Returns 0 on success and errno on failure (as defined in errno.h). | |
2865 | * | |
2866 | * Allocates memory that will be visible both to the device and to the CPU. | |
2867 | * The OS will pass us packets, pointers to which we will insert in the Tx | |
2868 | * Descriptor queue. The device will read this queue to find the packets in | |
2869 | * memory. The device will update the "status" in memory each time it xmits a | |
2870 | * packet. | |
2871 | */ | |
eb7a6ca6 | 2872 | static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter) |
d2796743 ME |
2873 | { |
2874 | int desc_size = 0; | |
2875 | struct tx_ring *tx_ring = &adapter->tx_ring; | |
2876 | ||
2877 | /* Allocate memory for the TCB's (Transmit Control Block) */ | |
2878 | adapter->tx_ring.tcb_ring = | |
2879 | kcalloc(NUM_TCB, sizeof(struct tcb), GFP_ATOMIC | GFP_DMA); | |
2880 | if (!adapter->tx_ring.tcb_ring) { | |
2881 | dev_err(&adapter->pdev->dev, "Cannot alloc memory for TCBs\n"); | |
2882 | return -ENOMEM; | |
2883 | } | |
2884 | ||
d3c75e8d | 2885 | desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX); |
d2796743 | 2886 | tx_ring->tx_desc_ring = |
09a3fc2b ME |
2887 | (struct tx_desc *) dma_alloc_coherent(&adapter->pdev->dev, |
2888 | desc_size, | |
2889 | &tx_ring->tx_desc_ring_pa, | |
2890 | GFP_KERNEL); | |
d2796743 ME |
2891 | if (!adapter->tx_ring.tx_desc_ring) { |
2892 | dev_err(&adapter->pdev->dev, | |
09a3fc2b | 2893 | "Cannot alloc memory for Tx Ring\n"); |
d2796743 ME |
2894 | return -ENOMEM; |
2895 | } | |
2896 | ||
2897 | /* Save physical address | |
2898 | * | |
26dc751e | 2899 | * NOTE: dma_alloc_coherent(), used above to alloc DMA regions, |
d2796743 ME |
2900 | * ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses |
2901 | * are ever returned, make sure the high part is retrieved here before | |
2902 | * storing the adjusted address. | |
2903 | */ | |
2904 | /* Allocate memory for the Tx status block */ | |
0d1b7a84 | 2905 | tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev, |
d2796743 | 2906 | sizeof(u32), |
0d1b7a84 ME |
2907 | &tx_ring->tx_status_pa, |
2908 | GFP_KERNEL); | |
d2796743 ME |
2909 | if (!adapter->tx_ring.tx_status_pa) { |
2910 | dev_err(&adapter->pdev->dev, | |
2911 | "Cannot alloc memory for Tx status block\n"); | |
2912 | return -ENOMEM; | |
2913 | } | |
2914 | return 0; | |
2915 | } | |
2916 | ||
2917 | /** | |
2918 | * et131x_tx_dma_memory_free - Free all memory allocated within this module | |
2919 | * @adapter: pointer to our private adapter structure | |
2920 | * | |
2921 | * Returns 0 on success and errno on failure (as defined in errno.h). | |
2922 | */ | |
eb7a6ca6 | 2923 | static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter) |
d2796743 ME |
2924 | { |
2925 | int desc_size = 0; | |
2926 | ||
2927 | if (adapter->tx_ring.tx_desc_ring) { | |
2928 | /* Free memory relating to Tx rings here */ | |
d3c75e8d | 2929 | desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX); |
675c8f68 | 2930 | dma_free_coherent(&adapter->pdev->dev, |
d2796743 ME |
2931 | desc_size, |
2932 | adapter->tx_ring.tx_desc_ring, | |
2933 | adapter->tx_ring.tx_desc_ring_pa); | |
2934 | adapter->tx_ring.tx_desc_ring = NULL; | |
2935 | } | |
2936 | ||
2937 | /* Free memory for the Tx status block */ | |
2938 | if (adapter->tx_ring.tx_status) { | |
675c8f68 | 2939 | dma_free_coherent(&adapter->pdev->dev, |
d2796743 ME |
2940 | sizeof(u32), |
2941 | adapter->tx_ring.tx_status, | |
2942 | adapter->tx_ring.tx_status_pa); | |
2943 | ||
2944 | adapter->tx_ring.tx_status = NULL; | |
2945 | } | |
2946 | /* Free the memory for the tcb structures */ | |
2947 | kfree(adapter->tx_ring.tcb_ring); | |
2948 | } | |
2949 | ||
d2796743 ME |
2950 | /** |
2951 | * nic_send_packet - NIC specific send handler for version B silicon. | |
2952 | * @adapter: pointer to our adapter | |
2953 | * @tcb: pointer to struct tcb | |
2954 | * | |
2955 | * Returns 0 or errno. | |
2956 | */ | |
2957 | static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb) | |
2958 | { | |
2959 | u32 i; | |
2960 | struct tx_desc desc[24]; /* 24 x 16 byte */ | |
2961 | u32 frag = 0; | |
2962 | u32 thiscopy, remainder; | |
2963 | struct sk_buff *skb = tcb->skb; | |
2964 | u32 nr_frags = skb_shinfo(skb)->nr_frags + 1; | |
2965 | struct skb_frag_struct *frags = &skb_shinfo(skb)->frags[0]; | |
2966 | unsigned long flags; | |
2967 | struct phy_device *phydev = adapter->phydev; | |
998f6dfb | 2968 | dma_addr_t dma_addr; |
d2796743 ME |
2969 | |
2970 | /* Part of the optimizations of this send routine restrict us to | |
2971 | * sending 24 fragments at a pass. In practice we should never see | |
2972 | * more than 5 fragments. | |
2973 | * | |
2974 | * NOTE: The older version of this function (below) can handle any | |
2975 | * number of fragments. If needed, we can call this function, | |
2976 | * although it is less efficient. | |
2977 | */ | |
2978 | if (nr_frags > 23) | |
2979 | return -EIO; | |
2980 | ||
2981 | memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1)); | |
2982 | ||
2983 | for (i = 0; i < nr_frags; i++) { | |
2984 | /* If there is something in this element, lets get a | |
2985 | * descriptor from the ring and get the necessary data | |
2986 | */ | |
2987 | if (i == 0) { | |
2988 | /* If the fragments are smaller than a standard MTU, | |
2989 | * then map them to a single descriptor in the Tx | |
2990 | * Desc ring. However, if they're larger, as is | |
2991 | * possible with support for jumbo packets, then | |
2992 | * split them each across 2 descriptors. | |
2993 | * | |
2994 | * This will work until we determine why the hardware | |
2995 | * doesn't seem to like large fragments. | |
2996 | */ | |
f1b540b9 | 2997 | if (skb_headlen(skb) <= 1514) { |
d2796743 ME |
2998 | /* Low 16bits are length, high is vlan and |
2999 | unused currently so zero */ | |
f1b540b9 | 3000 | desc[frag].len_vlan = skb_headlen(skb); |
998f6dfb ME |
3001 | dma_addr = dma_map_single(&adapter->pdev->dev, |
3002 | skb->data, | |
3003 | skb_headlen(skb), | |
3004 | DMA_TO_DEVICE); | |
3005 | desc[frag].addr_lo = lower_32_bits(dma_addr); | |
3006 | desc[frag].addr_hi = upper_32_bits(dma_addr); | |
3007 | frag++; | |
d2796743 | 3008 | } else { |
f1b540b9 | 3009 | desc[frag].len_vlan = skb_headlen(skb) / 2; |
998f6dfb | 3010 | dma_addr = dma_map_single(&adapter->pdev->dev, |
3781683e ME |
3011 | skb->data, |
3012 | (skb_headlen(skb) / 2), | |
3013 | DMA_TO_DEVICE); | |
998f6dfb ME |
3014 | desc[frag].addr_lo = lower_32_bits(dma_addr); |
3015 | desc[frag].addr_hi = upper_32_bits(dma_addr); | |
3016 | frag++; | |
d2796743 | 3017 | |
f1b540b9 | 3018 | desc[frag].len_vlan = skb_headlen(skb) / 2; |
998f6dfb | 3019 | dma_addr = dma_map_single(&adapter->pdev->dev, |
3781683e ME |
3020 | skb->data + |
3021 | (skb_headlen(skb) / 2), | |
3022 | (skb_headlen(skb) / 2), | |
3023 | DMA_TO_DEVICE); | |
998f6dfb ME |
3024 | desc[frag].addr_lo = lower_32_bits(dma_addr); |
3025 | desc[frag].addr_hi = upper_32_bits(dma_addr); | |
3026 | frag++; | |
d2796743 ME |
3027 | } |
3028 | } else { | |
998f6dfb ME |
3029 | desc[frag].len_vlan = frags[i - 1].size; |
3030 | dma_addr = skb_frag_dma_map(&adapter->pdev->dev, | |
3031 | &frags[i - 1], | |
3032 | 0, | |
3033 | frags[i - 1].size, | |
3034 | DMA_TO_DEVICE); | |
3035 | desc[frag].addr_lo = lower_32_bits(dma_addr); | |
3036 | desc[frag].addr_hi = upper_32_bits(dma_addr); | |
3037 | frag++; | |
d2796743 ME |
3038 | } |
3039 | } | |
3040 | ||
d2796743 ME |
3041 | if (phydev && phydev->speed == SPEED_1000) { |
3042 | if (++adapter->tx_ring.since_irq == PARM_TX_NUM_BUFS_DEF) { | |
3043 | /* Last element & Interrupt flag */ | |
a129be84 | 3044 | desc[frag - 1].flags = TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT; |
d2796743 ME |
3045 | adapter->tx_ring.since_irq = 0; |
3046 | } else { /* Last element */ | |
a129be84 | 3047 | desc[frag - 1].flags = TXDESC_FLAG_LASTPKT; |
d2796743 ME |
3048 | } |
3049 | } else | |
a129be84 | 3050 | desc[frag - 1].flags = TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT; |
d2796743 | 3051 | |
a129be84 | 3052 | desc[0].flags |= TXDESC_FLAG_FIRSTPKT; |
d2796743 ME |
3053 | |
3054 | tcb->index_start = adapter->tx_ring.send_idx; | |
3055 | tcb->stale = 0; | |
3056 | ||
3057 | spin_lock_irqsave(&adapter->send_hw_lock, flags); | |
3058 | ||
a129be84 | 3059 | thiscopy = NUM_DESC_PER_RING_TX - INDEX10(adapter->tx_ring.send_idx); |
d2796743 ME |
3060 | |
3061 | if (thiscopy >= frag) { | |
3062 | remainder = 0; | |
3063 | thiscopy = frag; | |
3064 | } else { | |
3065 | remainder = frag - thiscopy; | |
3066 | } | |
3067 | ||
3068 | memcpy(adapter->tx_ring.tx_desc_ring + | |
3069 | INDEX10(adapter->tx_ring.send_idx), desc, | |
3070 | sizeof(struct tx_desc) * thiscopy); | |
3071 | ||
3072 | add_10bit(&adapter->tx_ring.send_idx, thiscopy); | |
3073 | ||
3074 | if (INDEX10(adapter->tx_ring.send_idx) == 0 || | |
3075 | INDEX10(adapter->tx_ring.send_idx) == NUM_DESC_PER_RING_TX) { | |
3076 | adapter->tx_ring.send_idx &= ~ET_DMA10_MASK; | |
3077 | adapter->tx_ring.send_idx ^= ET_DMA10_WRAP; | |
3078 | } | |
3079 | ||
3080 | if (remainder) { | |
3081 | memcpy(adapter->tx_ring.tx_desc_ring, | |
3082 | desc + thiscopy, | |
3083 | sizeof(struct tx_desc) * remainder); | |
3084 | ||
3085 | add_10bit(&adapter->tx_ring.send_idx, remainder); | |
3086 | } | |
3087 | ||
3088 | if (INDEX10(adapter->tx_ring.send_idx) == 0) { | |
3089 | if (adapter->tx_ring.send_idx) | |
3090 | tcb->index = NUM_DESC_PER_RING_TX - 1; | |
3091 | else | |
3092 | tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1); | |
3093 | } else | |
3094 | tcb->index = adapter->tx_ring.send_idx - 1; | |
3095 | ||
3096 | spin_lock(&adapter->tcb_send_qlock); | |
3097 | ||
3098 | if (adapter->tx_ring.send_tail) | |
3099 | adapter->tx_ring.send_tail->next = tcb; | |
3100 | else | |
3101 | adapter->tx_ring.send_head = tcb; | |
3102 | ||
3103 | adapter->tx_ring.send_tail = tcb; | |
3104 | ||
3105 | WARN_ON(tcb->next != NULL); | |
3106 | ||
3107 | adapter->tx_ring.used++; | |
3108 | ||
3109 | spin_unlock(&adapter->tcb_send_qlock); | |
3110 | ||
3111 | /* Write the new write pointer back to the device. */ | |
3112 | writel(adapter->tx_ring.send_idx, | |
3113 | &adapter->regs->txdma.service_request); | |
3114 | ||
3115 | /* For Gig only, we use Tx Interrupt coalescing. Enable the software | |
3116 | * timer to wake us up if this packet isn't followed by N more. | |
3117 | */ | |
3118 | if (phydev && phydev->speed == SPEED_1000) { | |
3119 | writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO, | |
3120 | &adapter->regs->global.watchdog_timer); | |
3121 | } | |
3122 | spin_unlock_irqrestore(&adapter->send_hw_lock, flags); | |
3123 | ||
3124 | return 0; | |
3125 | } | |
3126 | ||
3127 | /** | |
3128 | * send_packet - Do the work to send a packet | |
3129 | * @skb: the packet(s) to send | |
3130 | * @adapter: a pointer to the device's private adapter structure | |
3131 | * | |
3132 | * Return 0 in almost all cases; non-zero value in extreme hard failure only. | |
3133 | * | |
3134 | * Assumption: Send spinlock has been acquired | |
3135 | */ | |
3136 | static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter) | |
3137 | { | |
3138 | int status; | |
3139 | struct tcb *tcb = NULL; | |
3140 | u16 *shbufva; | |
3141 | unsigned long flags; | |
3142 | ||
3143 | /* All packets must have at least a MAC address and a protocol type */ | |
3144 | if (skb->len < ETH_HLEN) | |
3145 | return -EIO; | |
3146 | ||
3147 | /* Get a TCB for this packet */ | |
3148 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); | |
3149 | ||
3150 | tcb = adapter->tx_ring.tcb_qhead; | |
3151 | ||
3152 | if (tcb == NULL) { | |
3153 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); | |
3154 | return -ENOMEM; | |
3155 | } | |
3156 | ||
3157 | adapter->tx_ring.tcb_qhead = tcb->next; | |
3158 | ||
3159 | if (adapter->tx_ring.tcb_qhead == NULL) | |
3160 | adapter->tx_ring.tcb_qtail = NULL; | |
3161 | ||
3162 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); | |
3163 | ||
3164 | tcb->skb = skb; | |
3165 | ||
f1b540b9 | 3166 | if (skb->data != NULL && skb_headlen(skb) >= 6) { |
d2796743 ME |
3167 | shbufva = (u16 *) skb->data; |
3168 | ||
3169 | if ((shbufva[0] == 0xffff) && | |
3170 | (shbufva[1] == 0xffff) && (shbufva[2] == 0xffff)) { | |
3171 | tcb->flags |= fMP_DEST_BROAD; | |
3172 | } else if ((shbufva[0] & 0x3) == 0x0001) { | |
3173 | tcb->flags |= fMP_DEST_MULTI; | |
3174 | } | |
3175 | } | |
3176 | ||
3177 | tcb->next = NULL; | |
3178 | ||
3179 | /* Call the NIC specific send handler. */ | |
3180 | status = nic_send_packet(adapter, tcb); | |
3181 | ||
3182 | if (status != 0) { | |
3183 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); | |
3184 | ||
3185 | if (adapter->tx_ring.tcb_qtail) | |
3186 | adapter->tx_ring.tcb_qtail->next = tcb; | |
3187 | else | |
3188 | /* Apparently ready Q is empty. */ | |
3189 | adapter->tx_ring.tcb_qhead = tcb; | |
3190 | ||
3191 | adapter->tx_ring.tcb_qtail = tcb; | |
3192 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); | |
3193 | return status; | |
3194 | } | |
3195 | WARN_ON(adapter->tx_ring.used > NUM_TCB); | |
3196 | return 0; | |
3197 | } | |
3198 | ||
3199 | /** | |
3200 | * et131x_send_packets - This function is called by the OS to send packets | |
3201 | * @skb: the packet(s) to send | |
3202 | * @netdev:device on which to TX the above packet(s) | |
3203 | * | |
3204 | * Return 0 in almost all cases; non-zero value in extreme hard failure only | |
3205 | */ | |
eb7a6ca6 | 3206 | static int et131x_send_packets(struct sk_buff *skb, struct net_device *netdev) |
d2796743 ME |
3207 | { |
3208 | int status = 0; | |
06709e96 | 3209 | struct et131x_adapter *adapter = netdev_priv(netdev); |
d2796743 ME |
3210 | |
3211 | /* Send these packets | |
3212 | * | |
3213 | * NOTE: The Linux Tx entry point is only given one packet at a time | |
3214 | * to Tx, so the PacketCount and it's array used makes no sense here | |
3215 | */ | |
3216 | ||
3217 | /* TCB is not available */ | |
3218 | if (adapter->tx_ring.used >= NUM_TCB) { | |
3219 | /* NOTE: If there's an error on send, no need to queue the | |
3220 | * packet under Linux; if we just send an error up to the | |
3221 | * netif layer, it will resend the skb to us. | |
3222 | */ | |
3223 | status = -ENOMEM; | |
3224 | } else { | |
3225 | /* We need to see if the link is up; if it's not, make the | |
3226 | * netif layer think we're good and drop the packet | |
3227 | */ | |
3228 | if ((adapter->flags & fMP_ADAPTER_FAIL_SEND_MASK) || | |
3229 | !netif_carrier_ok(netdev)) { | |
3230 | dev_kfree_skb_any(skb); | |
3231 | skb = NULL; | |
3232 | ||
3233 | adapter->net_stats.tx_dropped++; | |
3234 | } else { | |
3235 | status = send_packet(skb, adapter); | |
3236 | if (status != 0 && status != -ENOMEM) { | |
3237 | /* On any other error, make netif think we're | |
3238 | * OK and drop the packet | |
3239 | */ | |
3240 | dev_kfree_skb_any(skb); | |
3241 | skb = NULL; | |
3242 | adapter->net_stats.tx_dropped++; | |
3243 | } | |
3244 | } | |
3245 | } | |
3246 | return status; | |
3247 | } | |
3248 | ||
3249 | /** | |
3250 | * free_send_packet - Recycle a struct tcb | |
3251 | * @adapter: pointer to our adapter | |
3252 | * @tcb: pointer to struct tcb | |
3253 | * | |
3254 | * Complete the packet if necessary | |
3255 | * Assumption - Send spinlock has been acquired | |
3256 | */ | |
3257 | static inline void free_send_packet(struct et131x_adapter *adapter, | |
3258 | struct tcb *tcb) | |
3259 | { | |
3260 | unsigned long flags; | |
3261 | struct tx_desc *desc = NULL; | |
3262 | struct net_device_stats *stats = &adapter->net_stats; | |
983e4b35 | 3263 | u64 dma_addr; |
d2796743 ME |
3264 | |
3265 | if (tcb->flags & fMP_DEST_BROAD) | |
3266 | atomic_inc(&adapter->stats.broadcast_pkts_xmtd); | |
3267 | else if (tcb->flags & fMP_DEST_MULTI) | |
3268 | atomic_inc(&adapter->stats.multicast_pkts_xmtd); | |
3269 | else | |
3270 | atomic_inc(&adapter->stats.unicast_pkts_xmtd); | |
3271 | ||
3272 | if (tcb->skb) { | |
3273 | stats->tx_bytes += tcb->skb->len; | |
3274 | ||
3275 | /* Iterate through the TX descriptors on the ring | |
3276 | * corresponding to this packet and umap the fragments | |
3277 | * they point to | |
3278 | */ | |
3279 | do { | |
3280 | desc = (struct tx_desc *) | |
3281 | (adapter->tx_ring.tx_desc_ring + | |
3282 | INDEX10(tcb->index_start)); | |
3283 | ||
998f6dfb | 3284 | dma_addr = desc->addr_lo; |
983e4b35 | 3285 | dma_addr |= (u64)desc->addr_hi << 32; |
998f6dfb | 3286 | |
26dc751e | 3287 | dma_unmap_single(&adapter->pdev->dev, |
998f6dfb | 3288 | dma_addr, |
26dc751e | 3289 | desc->len_vlan, DMA_TO_DEVICE); |
d2796743 ME |
3290 | |
3291 | add_10bit(&tcb->index_start, 1); | |
3292 | if (INDEX10(tcb->index_start) >= | |
3293 | NUM_DESC_PER_RING_TX) { | |
3294 | tcb->index_start &= ~ET_DMA10_MASK; | |
3295 | tcb->index_start ^= ET_DMA10_WRAP; | |
3296 | } | |
3297 | } while (desc != (adapter->tx_ring.tx_desc_ring + | |
3298 | INDEX10(tcb->index))); | |
3299 | ||
3300 | dev_kfree_skb_any(tcb->skb); | |
3301 | } | |
3302 | ||
3303 | memset(tcb, 0, sizeof(struct tcb)); | |
3304 | ||
3305 | /* Add the TCB to the Ready Q */ | |
3306 | spin_lock_irqsave(&adapter->tcb_ready_qlock, flags); | |
3307 | ||
3308 | adapter->net_stats.tx_packets++; | |
3309 | ||
3310 | if (adapter->tx_ring.tcb_qtail) | |
3311 | adapter->tx_ring.tcb_qtail->next = tcb; | |
3312 | else | |
3313 | /* Apparently ready Q is empty. */ | |
3314 | adapter->tx_ring.tcb_qhead = tcb; | |
3315 | ||
3316 | adapter->tx_ring.tcb_qtail = tcb; | |
3317 | ||
3318 | spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags); | |
3319 | WARN_ON(adapter->tx_ring.used < 0); | |
3320 | } | |
3321 | ||
3322 | /** | |
3323 | * et131x_free_busy_send_packets - Free and complete the stopped active sends | |
3324 | * @adapter: pointer to our adapter | |
3325 | * | |
3326 | * Assumption - Send spinlock has been acquired | |
3327 | */ | |
eb7a6ca6 | 3328 | static void et131x_free_busy_send_packets(struct et131x_adapter *adapter) |
d2796743 ME |
3329 | { |
3330 | struct tcb *tcb; | |
3331 | unsigned long flags; | |
3332 | u32 freed = 0; | |
3333 | ||
3334 | /* Any packets being sent? Check the first TCB on the send list */ | |
3335 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); | |
3336 | ||
3337 | tcb = adapter->tx_ring.send_head; | |
3338 | ||
3339 | while (tcb != NULL && freed < NUM_TCB) { | |
3340 | struct tcb *next = tcb->next; | |
3341 | ||
3342 | adapter->tx_ring.send_head = next; | |
3343 | ||
3344 | if (next == NULL) | |
3345 | adapter->tx_ring.send_tail = NULL; | |
3346 | ||
3347 | adapter->tx_ring.used--; | |
3348 | ||
3349 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); | |
3350 | ||
3351 | freed++; | |
3352 | free_send_packet(adapter, tcb); | |
3353 | ||
3354 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); | |
3355 | ||
3356 | tcb = adapter->tx_ring.send_head; | |
3357 | } | |
3358 | ||
3359 | WARN_ON(freed == NUM_TCB); | |
3360 | ||
3361 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); | |
3362 | ||
3363 | adapter->tx_ring.used = 0; | |
3364 | } | |
3365 | ||
3366 | /** | |
3367 | * et131x_handle_send_interrupt - Interrupt handler for sending processing | |
3368 | * @adapter: pointer to our adapter | |
3369 | * | |
3370 | * Re-claim the send resources, complete sends and get more to send from | |
3371 | * the send wait queue. | |
3372 | * | |
3373 | * Assumption - Send spinlock has been acquired | |
3374 | */ | |
eb7a6ca6 | 3375 | static void et131x_handle_send_interrupt(struct et131x_adapter *adapter) |
d2796743 ME |
3376 | { |
3377 | unsigned long flags; | |
3378 | u32 serviced; | |
3379 | struct tcb *tcb; | |
3380 | u32 index; | |
3381 | ||
3382 | serviced = readl(&adapter->regs->txdma.new_service_complete); | |
3383 | index = INDEX10(serviced); | |
3384 | ||
3385 | /* Has the ring wrapped? Process any descriptors that do not have | |
3386 | * the same "wrap" indicator as the current completion indicator | |
3387 | */ | |
3388 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); | |
3389 | ||
3390 | tcb = adapter->tx_ring.send_head; | |
3391 | ||
3392 | while (tcb && | |
3393 | ((serviced ^ tcb->index) & ET_DMA10_WRAP) && | |
3394 | index < INDEX10(tcb->index)) { | |
3395 | adapter->tx_ring.used--; | |
3396 | adapter->tx_ring.send_head = tcb->next; | |
3397 | if (tcb->next == NULL) | |
3398 | adapter->tx_ring.send_tail = NULL; | |
3399 | ||
3400 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); | |
3401 | free_send_packet(adapter, tcb); | |
3402 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); | |
3403 | ||
3404 | /* Goto the next packet */ | |
3405 | tcb = adapter->tx_ring.send_head; | |
3406 | } | |
3407 | while (tcb && | |
3408 | !((serviced ^ tcb->index) & ET_DMA10_WRAP) | |
3409 | && index > (tcb->index & ET_DMA10_MASK)) { | |
3410 | adapter->tx_ring.used--; | |
3411 | adapter->tx_ring.send_head = tcb->next; | |
3412 | if (tcb->next == NULL) | |
3413 | adapter->tx_ring.send_tail = NULL; | |
3414 | ||
3415 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); | |
3416 | free_send_packet(adapter, tcb); | |
3417 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); | |
3418 | ||
3419 | /* Goto the next packet */ | |
3420 | tcb = adapter->tx_ring.send_head; | |
3421 | } | |
3422 | ||
3423 | /* Wake up the queue when we hit a low-water mark */ | |
3424 | if (adapter->tx_ring.used <= NUM_TCB / 3) | |
3425 | netif_wake_queue(adapter->netdev); | |
3426 | ||
3427 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); | |
3428 | } | |
3429 | ||
d2796743 ME |
3430 | static int et131x_get_settings(struct net_device *netdev, |
3431 | struct ethtool_cmd *cmd) | |
3432 | { | |
3433 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
3434 | ||
3435 | return phy_ethtool_gset(adapter->phydev, cmd); | |
3436 | } | |
3437 | ||
3438 | static int et131x_set_settings(struct net_device *netdev, | |
3439 | struct ethtool_cmd *cmd) | |
3440 | { | |
3441 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
3442 | ||
3443 | return phy_ethtool_sset(adapter->phydev, cmd); | |
3444 | } | |
3445 | ||
3446 | static int et131x_get_regs_len(struct net_device *netdev) | |
3447 | { | |
3448 | #define ET131X_REGS_LEN 256 | |
3449 | return ET131X_REGS_LEN * sizeof(u32); | |
3450 | } | |
3451 | ||
3452 | static void et131x_get_regs(struct net_device *netdev, | |
3453 | struct ethtool_regs *regs, void *regs_data) | |
3454 | { | |
3455 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
3456 | struct address_map __iomem *aregs = adapter->regs; | |
3457 | u32 *regs_buff = regs_data; | |
3458 | u32 num = 0; | |
3459 | ||
3460 | memset(regs_data, 0, et131x_get_regs_len(netdev)); | |
3461 | ||
3462 | regs->version = (1 << 24) | (adapter->pdev->revision << 16) | | |
3463 | adapter->pdev->device; | |
3464 | ||
3465 | /* PHY regs */ | |
3466 | et131x_mii_read(adapter, MII_BMCR, (u16 *)®s_buff[num++]); | |
3467 | et131x_mii_read(adapter, MII_BMSR, (u16 *)®s_buff[num++]); | |
3468 | et131x_mii_read(adapter, MII_PHYSID1, (u16 *)®s_buff[num++]); | |
3469 | et131x_mii_read(adapter, MII_PHYSID2, (u16 *)®s_buff[num++]); | |
3470 | et131x_mii_read(adapter, MII_ADVERTISE, (u16 *)®s_buff[num++]); | |
3471 | et131x_mii_read(adapter, MII_LPA, (u16 *)®s_buff[num++]); | |
3472 | et131x_mii_read(adapter, MII_EXPANSION, (u16 *)®s_buff[num++]); | |
3473 | /* Autoneg next page transmit reg */ | |
3474 | et131x_mii_read(adapter, 0x07, (u16 *)®s_buff[num++]); | |
3475 | /* Link partner next page reg */ | |
3476 | et131x_mii_read(adapter, 0x08, (u16 *)®s_buff[num++]); | |
3477 | et131x_mii_read(adapter, MII_CTRL1000, (u16 *)®s_buff[num++]); | |
3478 | et131x_mii_read(adapter, MII_STAT1000, (u16 *)®s_buff[num++]); | |
01e14a4c ME |
3479 | et131x_mii_read(adapter, 0x0b, (u16 *)®s_buff[num++]); |
3480 | et131x_mii_read(adapter, 0x0c, (u16 *)®s_buff[num++]); | |
3481 | et131x_mii_read(adapter, MII_MMD_CTRL, (u16 *)®s_buff[num++]); | |
3482 | et131x_mii_read(adapter, MII_MMD_DATA, (u16 *)®s_buff[num++]); | |
d2796743 | 3483 | et131x_mii_read(adapter, MII_ESTATUS, (u16 *)®s_buff[num++]); |
01e14a4c | 3484 | |
d2796743 ME |
3485 | et131x_mii_read(adapter, PHY_INDEX_REG, (u16 *)®s_buff[num++]); |
3486 | et131x_mii_read(adapter, PHY_DATA_REG, (u16 *)®s_buff[num++]); | |
3487 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, | |
3488 | (u16 *)®s_buff[num++]); | |
3489 | et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, | |
3490 | (u16 *)®s_buff[num++]); | |
3491 | et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL+1, | |
3492 | (u16 *)®s_buff[num++]); | |
01e14a4c | 3493 | |
d2796743 ME |
3494 | et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, |
3495 | (u16 *)®s_buff[num++]); | |
3496 | et131x_mii_read(adapter, PHY_CONFIG, (u16 *)®s_buff[num++]); | |
3497 | et131x_mii_read(adapter, PHY_PHY_CONTROL, (u16 *)®s_buff[num++]); | |
3498 | et131x_mii_read(adapter, PHY_INTERRUPT_MASK, (u16 *)®s_buff[num++]); | |
3499 | et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, | |
3500 | (u16 *)®s_buff[num++]); | |
3501 | et131x_mii_read(adapter, PHY_PHY_STATUS, (u16 *)®s_buff[num++]); | |
3502 | et131x_mii_read(adapter, PHY_LED_1, (u16 *)®s_buff[num++]); | |
3503 | et131x_mii_read(adapter, PHY_LED_2, (u16 *)®s_buff[num++]); | |
3504 | ||
3505 | /* Global regs */ | |
3506 | regs_buff[num++] = readl(&aregs->global.txq_start_addr); | |
3507 | regs_buff[num++] = readl(&aregs->global.txq_end_addr); | |
3508 | regs_buff[num++] = readl(&aregs->global.rxq_start_addr); | |
3509 | regs_buff[num++] = readl(&aregs->global.rxq_end_addr); | |
3510 | regs_buff[num++] = readl(&aregs->global.pm_csr); | |
3511 | regs_buff[num++] = adapter->stats.interrupt_status; | |
3512 | regs_buff[num++] = readl(&aregs->global.int_mask); | |
3513 | regs_buff[num++] = readl(&aregs->global.int_alias_clr_en); | |
3514 | regs_buff[num++] = readl(&aregs->global.int_status_alias); | |
3515 | regs_buff[num++] = readl(&aregs->global.sw_reset); | |
3516 | regs_buff[num++] = readl(&aregs->global.slv_timer); | |
3517 | regs_buff[num++] = readl(&aregs->global.msi_config); | |
3518 | regs_buff[num++] = readl(&aregs->global.loopback); | |
3519 | regs_buff[num++] = readl(&aregs->global.watchdog_timer); | |
3520 | ||
3521 | /* TXDMA regs */ | |
3522 | regs_buff[num++] = readl(&aregs->txdma.csr); | |
3523 | regs_buff[num++] = readl(&aregs->txdma.pr_base_hi); | |
3524 | regs_buff[num++] = readl(&aregs->txdma.pr_base_lo); | |
3525 | regs_buff[num++] = readl(&aregs->txdma.pr_num_des); | |
3526 | regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr); | |
3527 | regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext); | |
3528 | regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr); | |
3529 | regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi); | |
3530 | regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo); | |
3531 | regs_buff[num++] = readl(&aregs->txdma.service_request); | |
3532 | regs_buff[num++] = readl(&aregs->txdma.service_complete); | |
3533 | regs_buff[num++] = readl(&aregs->txdma.cache_rd_index); | |
3534 | regs_buff[num++] = readl(&aregs->txdma.cache_wr_index); | |
3535 | regs_buff[num++] = readl(&aregs->txdma.tx_dma_error); | |
3536 | regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt); | |
3537 | regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt); | |
3538 | regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt); | |
3539 | regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt); | |
3540 | regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt); | |
3541 | regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt); | |
3542 | regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt); | |
3543 | regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt); | |
3544 | regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt); | |
3545 | regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt); | |
3546 | regs_buff[num++] = readl(&aregs->txdma.new_service_complete); | |
3547 | regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt); | |
3548 | ||
3549 | /* RXDMA regs */ | |
3550 | regs_buff[num++] = readl(&aregs->rxdma.csr); | |
3551 | regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi); | |
3552 | regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo); | |
3553 | regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done); | |
3554 | regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time); | |
3555 | regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr); | |
3556 | regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext); | |
3557 | regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr); | |
3558 | regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi); | |
3559 | regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo); | |
3560 | regs_buff[num++] = readl(&aregs->rxdma.psr_num_des); | |
3561 | regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset); | |
3562 | regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset); | |
3563 | regs_buff[num++] = readl(&aregs->rxdma.psr_access_index); | |
3564 | regs_buff[num++] = readl(&aregs->rxdma.psr_min_des); | |
3565 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo); | |
3566 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi); | |
3567 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des); | |
3568 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset); | |
3569 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset); | |
3570 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index); | |
3571 | regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des); | |
3572 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo); | |
3573 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi); | |
3574 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des); | |
3575 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset); | |
3576 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset); | |
3577 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index); | |
3578 | regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des); | |
3579 | } | |
3580 | ||
3581 | #define ET131X_DRVINFO_LEN 32 /* value from ethtool.h */ | |
3582 | static void et131x_get_drvinfo(struct net_device *netdev, | |
3583 | struct ethtool_drvinfo *info) | |
3584 | { | |
3585 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
3586 | ||
3587 | strncpy(info->driver, DRIVER_NAME, ET131X_DRVINFO_LEN); | |
3588 | strncpy(info->version, DRIVER_VERSION, ET131X_DRVINFO_LEN); | |
3589 | strncpy(info->bus_info, pci_name(adapter->pdev), ET131X_DRVINFO_LEN); | |
3590 | } | |
3591 | ||
3592 | static struct ethtool_ops et131x_ethtool_ops = { | |
3593 | .get_settings = et131x_get_settings, | |
3594 | .set_settings = et131x_set_settings, | |
3595 | .get_drvinfo = et131x_get_drvinfo, | |
3596 | .get_regs_len = et131x_get_regs_len, | |
3597 | .get_regs = et131x_get_regs, | |
242187aa | 3598 | .get_link = ethtool_op_get_link, |
d2796743 | 3599 | }; |
d2796743 ME |
3600 | /** |
3601 | * et131x_hwaddr_init - set up the MAC Address on the ET1310 | |
3602 | * @adapter: pointer to our private adapter structure | |
3603 | */ | |
eb7a6ca6 | 3604 | static void et131x_hwaddr_init(struct et131x_adapter *adapter) |
d2796743 ME |
3605 | { |
3606 | /* If have our default mac from init and no mac address from | |
3607 | * EEPROM then we need to generate the last octet and set it on the | |
3608 | * device | |
3609 | */ | |
c14d01b8 | 3610 | if (is_zero_ether_addr(adapter->rom_addr)) { |
d2796743 ME |
3611 | /* |
3612 | * We need to randomly generate the last octet so we | |
3613 | * decrease our chances of setting the mac address to | |
3614 | * same as another one of our cards in the system | |
3615 | */ | |
3616 | get_random_bytes(&adapter->addr[5], 1); | |
3617 | /* | |
3618 | * We have the default value in the register we are | |
3619 | * working with so we need to copy the current | |
3620 | * address into the permanent address | |
3621 | */ | |
3622 | memcpy(adapter->rom_addr, | |
3623 | adapter->addr, ETH_ALEN); | |
3624 | } else { | |
3625 | /* We do not have an override address, so set the | |
3626 | * current address to the permanent address and add | |
3627 | * it to the device | |
3628 | */ | |
3629 | memcpy(adapter->addr, | |
3630 | adapter->rom_addr, ETH_ALEN); | |
3631 | } | |
3632 | } | |
3633 | ||
3634 | /** | |
3635 | * et131x_pci_init - initial PCI setup | |
3636 | * @adapter: pointer to our private adapter structure | |
3637 | * @pdev: our PCI device | |
3638 | * | |
3639 | * Perform the initial setup of PCI registers and if possible initialise | |
3640 | * the MAC address. At this point the I/O registers have yet to be mapped | |
3641 | */ | |
3642 | static int et131x_pci_init(struct et131x_adapter *adapter, | |
3643 | struct pci_dev *pdev) | |
3644 | { | |
d14e3d05 | 3645 | u16 max_payload; |
d14e3d05 FR |
3646 | int i, rc; |
3647 | ||
3648 | rc = et131x_init_eeprom(adapter); | |
3649 | if (rc < 0) | |
3650 | goto out; | |
3651 | ||
532c5f69 | 3652 | if (!pci_is_pcie(pdev)) { |
d14e3d05 FR |
3653 | dev_err(&pdev->dev, "Missing PCIe capabilities\n"); |
3654 | goto err_out; | |
3655 | } | |
bf3313a1 | 3656 | |
d2796743 ME |
3657 | /* Let's set up the PORT LOGIC Register. First we need to know what |
3658 | * the max_payload_size is | |
3659 | */ | |
532c5f69 | 3660 | if (pcie_capability_read_word(pdev, PCI_EXP_DEVCAP, &max_payload)) { |
d2796743 ME |
3661 | dev_err(&pdev->dev, |
3662 | "Could not read PCI config space for Max Payload Size\n"); | |
d14e3d05 | 3663 | goto err_out; |
d2796743 ME |
3664 | } |
3665 | ||
3666 | /* Program the Ack/Nak latency and replay timers */ | |
d14e3d05 | 3667 | max_payload &= 0x07; |
d2796743 ME |
3668 | |
3669 | if (max_payload < 2) { | |
3670 | static const u16 acknak[2] = { 0x76, 0xD0 }; | |
3671 | static const u16 replay[2] = { 0x1E0, 0x2ED }; | |
3672 | ||
3673 | if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK, | |
3674 | acknak[max_payload])) { | |
3675 | dev_err(&pdev->dev, | |
3676 | "Could not write PCI config space for ACK/NAK\n"); | |
d14e3d05 | 3677 | goto err_out; |
d2796743 ME |
3678 | } |
3679 | if (pci_write_config_word(pdev, ET1310_PCI_REPLAY, | |
3680 | replay[max_payload])) { | |
3681 | dev_err(&pdev->dev, | |
3682 | "Could not write PCI config space for Replay Timer\n"); | |
d14e3d05 | 3683 | goto err_out; |
d2796743 ME |
3684 | } |
3685 | } | |
3686 | ||
3687 | /* l0s and l1 latency timers. We are using default values. | |
3688 | * Representing 001 for L0s and 010 for L1 | |
3689 | */ | |
3690 | if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) { | |
3691 | dev_err(&pdev->dev, | |
3692 | "Could not write PCI config space for Latency Timers\n"); | |
d14e3d05 | 3693 | goto err_out; |
d2796743 ME |
3694 | } |
3695 | ||
3696 | /* Change the max read size to 2k */ | |
532c5f69 JL |
3697 | if (pcie_capability_clear_and_set_word(pdev, PCI_EXP_DEVCTL, |
3698 | PCI_EXP_DEVCTL_READRQ, 0x4 << 12)) { | |
d2796743 | 3699 | dev_err(&pdev->dev, |
532c5f69 | 3700 | "Couldn't change PCI config space for Max read size\n"); |
d14e3d05 | 3701 | goto err_out; |
d2796743 ME |
3702 | } |
3703 | ||
3704 | /* Get MAC address from config space if an eeprom exists, otherwise | |
3705 | * the MAC address there will not be valid | |
3706 | */ | |
3707 | if (!adapter->has_eeprom) { | |
3708 | et131x_hwaddr_init(adapter); | |
3709 | return 0; | |
3710 | } | |
3711 | ||
3712 | for (i = 0; i < ETH_ALEN; i++) { | |
3713 | if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i, | |
3714 | adapter->rom_addr + i)) { | |
3715 | dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n"); | |
d14e3d05 | 3716 | goto err_out; |
d2796743 ME |
3717 | } |
3718 | } | |
3719 | memcpy(adapter->addr, adapter->rom_addr, ETH_ALEN); | |
d14e3d05 FR |
3720 | out: |
3721 | return rc; | |
3722 | err_out: | |
3723 | rc = -EIO; | |
3724 | goto out; | |
d2796743 ME |
3725 | } |
3726 | ||
3727 | /** | |
3728 | * et131x_error_timer_handler | |
3729 | * @data: timer-specific variable; here a pointer to our adapter structure | |
3730 | * | |
3731 | * The routine called when the error timer expires, to track the number of | |
3732 | * recurring errors. | |
3733 | */ | |
eb7a6ca6 | 3734 | static void et131x_error_timer_handler(unsigned long data) |
d2796743 ME |
3735 | { |
3736 | struct et131x_adapter *adapter = (struct et131x_adapter *) data; | |
3737 | struct phy_device *phydev = adapter->phydev; | |
3738 | ||
3739 | if (et1310_in_phy_coma(adapter)) { | |
3740 | /* Bring the device immediately out of coma, to | |
3741 | * prevent it from sleeping indefinitely, this | |
3742 | * mechanism could be improved! */ | |
3743 | et1310_disable_phy_coma(adapter); | |
3744 | adapter->boot_coma = 20; | |
3745 | } else { | |
3746 | et1310_update_macstat_host_counters(adapter); | |
3747 | } | |
3748 | ||
3749 | if (!phydev->link && adapter->boot_coma < 11) | |
3750 | adapter->boot_coma++; | |
3751 | ||
3752 | if (adapter->boot_coma == 10) { | |
3753 | if (!phydev->link) { | |
3754 | if (!et1310_in_phy_coma(adapter)) { | |
3755 | /* NOTE - This was originally a 'sync with | |
3756 | * interrupt'. How to do that under Linux? | |
3757 | */ | |
3758 | et131x_enable_interrupts(adapter); | |
3759 | et1310_enable_phy_coma(adapter); | |
3760 | } | |
3761 | } | |
3762 | } | |
3763 | ||
3764 | /* This is a periodic timer, so reschedule */ | |
242187aa | 3765 | mod_timer(&adapter->error_timer, jiffies + TX_ERROR_PERIOD * HZ / 1000); |
d2796743 ME |
3766 | } |
3767 | ||
d959df0a ME |
3768 | /** |
3769 | * et131x_adapter_memory_free - Free all memory allocated for use by Tx & Rx | |
3770 | * @adapter: pointer to our private adapter structure | |
3771 | */ | |
3772 | static void et131x_adapter_memory_free(struct et131x_adapter *adapter) | |
3773 | { | |
3774 | /* Free DMA memory */ | |
3775 | et131x_tx_dma_memory_free(adapter); | |
3776 | et131x_rx_dma_memory_free(adapter); | |
3777 | } | |
3778 | ||
d2796743 ME |
3779 | /** |
3780 | * et131x_adapter_memory_alloc | |
3781 | * @adapter: pointer to our private adapter structure | |
3782 | * | |
3783 | * Returns 0 on success, errno on failure (as defined in errno.h). | |
3784 | * | |
3785 | * Allocate all the memory blocks for send, receive and others. | |
3786 | */ | |
eb7a6ca6 | 3787 | static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter) |
d2796743 ME |
3788 | { |
3789 | int status; | |
3790 | ||
3791 | /* Allocate memory for the Tx Ring */ | |
3792 | status = et131x_tx_dma_memory_alloc(adapter); | |
3793 | if (status != 0) { | |
3794 | dev_err(&adapter->pdev->dev, | |
3795 | "et131x_tx_dma_memory_alloc FAILED\n"); | |
3796 | return status; | |
3797 | } | |
3798 | /* Receive buffer memory allocation */ | |
3799 | status = et131x_rx_dma_memory_alloc(adapter); | |
3800 | if (status != 0) { | |
3801 | dev_err(&adapter->pdev->dev, | |
3802 | "et131x_rx_dma_memory_alloc FAILED\n"); | |
3803 | et131x_tx_dma_memory_free(adapter); | |
3804 | return status; | |
3805 | } | |
3806 | ||
3807 | /* Init receive data structures */ | |
3808 | status = et131x_init_recv(adapter); | |
d959df0a | 3809 | if (status) { |
d2796743 ME |
3810 | dev_err(&adapter->pdev->dev, |
3811 | "et131x_init_recv FAILED\n"); | |
d959df0a | 3812 | et131x_adapter_memory_free(adapter); |
d2796743 ME |
3813 | } |
3814 | return status; | |
3815 | } | |
3816 | ||
d2796743 ME |
3817 | static void et131x_adjust_link(struct net_device *netdev) |
3818 | { | |
3819 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
3820 | struct phy_device *phydev = adapter->phydev; | |
3821 | ||
d2796743 ME |
3822 | if (phydev && phydev->link != adapter->link) { |
3823 | /* | |
3824 | * Check to see if we are in coma mode and if | |
3825 | * so, disable it because we will not be able | |
3826 | * to read PHY values until we are out. | |
3827 | */ | |
3828 | if (et1310_in_phy_coma(adapter)) | |
3829 | et1310_disable_phy_coma(adapter); | |
3830 | ||
6903098c ME |
3831 | adapter->link = phydev->link; |
3832 | phy_print_status(phydev); | |
3833 | ||
d2796743 ME |
3834 | if (phydev->link) { |
3835 | adapter->boot_coma = 20; | |
6903098c ME |
3836 | if (phydev && phydev->speed == SPEED_10) { |
3837 | /* | |
3838 | * NOTE - Is there a way to query this without | |
3839 | * TruePHY? | |
3840 | * && TRU_QueryCoreType(adapter->hTruePhy, 0)== | |
3841 | * EMI_TRUEPHY_A13O) { | |
3842 | */ | |
3843 | u16 register18; | |
3844 | ||
3845 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, | |
3846 | ®ister18); | |
3847 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, | |
3848 | register18 | 0x4); | |
3849 | et131x_mii_write(adapter, PHY_INDEX_REG, | |
3850 | register18 | 0x8402); | |
3851 | et131x_mii_write(adapter, PHY_DATA_REG, | |
3852 | register18 | 511); | |
3853 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, | |
3854 | register18); | |
3855 | } | |
3856 | ||
3857 | et1310_config_flow_control(adapter); | |
3858 | ||
3859 | if (phydev && phydev->speed == SPEED_1000 && | |
3860 | adapter->registry_jumbo_packet > 2048) { | |
3861 | u16 reg; | |
3862 | ||
3863 | et131x_mii_read(adapter, PHY_CONFIG, ®); | |
3864 | reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH; | |
3865 | reg |= ET_PHY_CONFIG_FIFO_DEPTH_32; | |
3866 | et131x_mii_write(adapter, PHY_CONFIG, reg); | |
3867 | } | |
3868 | ||
3869 | et131x_set_rx_dma_timer(adapter); | |
3870 | et1310_config_mac_regs2(adapter); | |
d2796743 | 3871 | } else { |
d2796743 ME |
3872 | adapter->boot_coma = 0; |
3873 | ||
3874 | if (phydev->speed == SPEED_10) { | |
3875 | /* NOTE - Is there a way to query this without | |
3876 | * TruePHY? | |
3877 | * && TRU_QueryCoreType(adapter->hTruePhy, 0) == | |
3878 | * EMI_TRUEPHY_A13O) | |
3879 | */ | |
3880 | u16 register18; | |
3881 | ||
3882 | et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, | |
3883 | ®ister18); | |
3884 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, | |
3885 | register18 | 0x4); | |
3886 | et131x_mii_write(adapter, PHY_INDEX_REG, | |
3887 | register18 | 0x8402); | |
3888 | et131x_mii_write(adapter, PHY_DATA_REG, | |
3889 | register18 | 511); | |
3890 | et131x_mii_write(adapter, PHY_MPHY_CONTROL_REG, | |
3891 | register18); | |
3892 | } | |
3893 | ||
3894 | /* Free the packets being actively sent & stopped */ | |
3895 | et131x_free_busy_send_packets(adapter); | |
3896 | ||
3897 | /* Re-initialize the send structures */ | |
3898 | et131x_init_send(adapter); | |
3899 | ||
d2796743 ME |
3900 | /* |
3901 | * Bring the device back to the state it was during | |
3902 | * init prior to autonegotiation being complete. This | |
3903 | * way, when we get the auto-neg complete interrupt, | |
3904 | * we can complete init by calling config_mac_regs2. | |
3905 | */ | |
3906 | et131x_soft_reset(adapter); | |
3907 | ||
3908 | /* Setup ET1310 as per the documentation */ | |
3909 | et131x_adapter_setup(adapter); | |
3910 | ||
3911 | /* perform reset of tx/rx */ | |
3912 | et131x_disable_txrx(netdev); | |
3913 | et131x_enable_txrx(netdev); | |
3914 | } | |
3915 | ||
d2796743 ME |
3916 | } |
3917 | } | |
3918 | ||
3919 | static int et131x_mii_probe(struct net_device *netdev) | |
3920 | { | |
3921 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
3922 | struct phy_device *phydev = NULL; | |
3923 | ||
3924 | phydev = phy_find_first(adapter->mii_bus); | |
3925 | if (!phydev) { | |
3926 | dev_err(&adapter->pdev->dev, "no PHY found\n"); | |
3927 | return -ENODEV; | |
3928 | } | |
3929 | ||
3930 | phydev = phy_connect(netdev, dev_name(&phydev->dev), | |
3931 | &et131x_adjust_link, 0, PHY_INTERFACE_MODE_MII); | |
3932 | ||
3933 | if (IS_ERR(phydev)) { | |
3934 | dev_err(&adapter->pdev->dev, "Could not attach to PHY\n"); | |
3935 | return PTR_ERR(phydev); | |
3936 | } | |
3937 | ||
3938 | phydev->supported &= (SUPPORTED_10baseT_Half | |
3939 | | SUPPORTED_10baseT_Full | |
3940 | | SUPPORTED_100baseT_Half | |
3941 | | SUPPORTED_100baseT_Full | |
3942 | | SUPPORTED_Autoneg | |
3943 | | SUPPORTED_MII | |
3944 | | SUPPORTED_TP); | |
3945 | ||
3946 | if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST) | |
3947 | phydev->supported |= SUPPORTED_1000baseT_Full; | |
3948 | ||
3949 | phydev->advertising = phydev->supported; | |
3950 | adapter->phydev = phydev; | |
3951 | ||
397d3e60 | 3952 | dev_info(&adapter->pdev->dev, "attached PHY driver [%s] (mii_bus:phy_addr=%s)\n", |
d2796743 ME |
3953 | phydev->drv->name, dev_name(&phydev->dev)); |
3954 | ||
3955 | return 0; | |
3956 | } | |
3957 | ||
3958 | /** | |
3959 | * et131x_adapter_init | |
3960 | * @adapter: pointer to the private adapter struct | |
3961 | * @pdev: pointer to the PCI device | |
3962 | * | |
3963 | * Initialize the data structures for the et131x_adapter object and link | |
3964 | * them together with the platform provided device structures. | |
3965 | */ | |
3966 | static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev, | |
3967 | struct pci_dev *pdev) | |
3968 | { | |
3969 | static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 }; | |
3970 | ||
3971 | struct et131x_adapter *adapter; | |
3972 | ||
3973 | /* Allocate private adapter struct and copy in relevant information */ | |
3974 | adapter = netdev_priv(netdev); | |
3975 | adapter->pdev = pci_dev_get(pdev); | |
3976 | adapter->netdev = netdev; | |
3977 | ||
d2796743 ME |
3978 | /* Initialize spinlocks here */ |
3979 | spin_lock_init(&adapter->lock); | |
3980 | spin_lock_init(&adapter->tcb_send_qlock); | |
3981 | spin_lock_init(&adapter->tcb_ready_qlock); | |
3982 | spin_lock_init(&adapter->send_hw_lock); | |
3983 | spin_lock_init(&adapter->rcv_lock); | |
3984 | spin_lock_init(&adapter->rcv_pend_lock); | |
3985 | spin_lock_init(&adapter->fbr_lock); | |
3986 | spin_lock_init(&adapter->phy_lock); | |
3987 | ||
3988 | adapter->registry_jumbo_packet = 1514; /* 1514-9216 */ | |
3989 | ||
3990 | /* Set the MAC address to a default */ | |
3991 | memcpy(adapter->addr, default_mac, ETH_ALEN); | |
3992 | ||
3993 | return adapter; | |
3994 | } | |
3995 | ||
d2796743 ME |
3996 | /** |
3997 | * et131x_pci_remove | |
3998 | * @pdev: a pointer to the device's pci_dev structure | |
3999 | * | |
4000 | * Registered in the pci_driver structure, this function is called when the | |
4001 | * PCI subsystem detects that a PCI device which matches the information | |
4002 | * contained in the pci_device_id table has been removed. | |
4003 | */ | |
596c5dd3 | 4004 | static void et131x_pci_remove(struct pci_dev *pdev) |
d2796743 ME |
4005 | { |
4006 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4007 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4008 | ||
4009 | unregister_netdev(netdev); | |
fa9f0a65 | 4010 | phy_disconnect(adapter->phydev); |
d2796743 ME |
4011 | mdiobus_unregister(adapter->mii_bus); |
4012 | kfree(adapter->mii_bus->irq); | |
4013 | mdiobus_free(adapter->mii_bus); | |
4014 | ||
4015 | et131x_adapter_memory_free(adapter); | |
4016 | iounmap(adapter->regs); | |
4017 | pci_dev_put(pdev); | |
4018 | ||
4019 | free_netdev(netdev); | |
4020 | pci_release_regions(pdev); | |
4021 | pci_disable_device(pdev); | |
4022 | } | |
4023 | ||
a4d444bd ME |
4024 | /** |
4025 | * et131x_up - Bring up a device for use. | |
4026 | * @netdev: device to be opened | |
4027 | */ | |
eb7a6ca6 | 4028 | static void et131x_up(struct net_device *netdev) |
a4d444bd ME |
4029 | { |
4030 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4031 | ||
4032 | et131x_enable_txrx(netdev); | |
4033 | phy_start(adapter->phydev); | |
4034 | } | |
4035 | ||
4036 | /** | |
4037 | * et131x_down - Bring down the device | |
ac399bc0 | 4038 | * @netdev: device to be brought down |
a4d444bd | 4039 | */ |
eb7a6ca6 | 4040 | static void et131x_down(struct net_device *netdev) |
a4d444bd ME |
4041 | { |
4042 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4043 | ||
4044 | /* Save the timestamp for the TX watchdog, prevent a timeout */ | |
4045 | netdev->trans_start = jiffies; | |
4046 | ||
4047 | phy_stop(adapter->phydev); | |
4048 | et131x_disable_txrx(netdev); | |
4049 | } | |
4050 | ||
d2796743 ME |
4051 | #ifdef CONFIG_PM_SLEEP |
4052 | static int et131x_suspend(struct device *dev) | |
4053 | { | |
4054 | struct pci_dev *pdev = to_pci_dev(dev); | |
4055 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4056 | ||
4057 | if (netif_running(netdev)) { | |
4058 | netif_device_detach(netdev); | |
4059 | et131x_down(netdev); | |
4060 | pci_save_state(pdev); | |
4061 | } | |
4062 | ||
4063 | return 0; | |
4064 | } | |
4065 | ||
4066 | static int et131x_resume(struct device *dev) | |
4067 | { | |
4068 | struct pci_dev *pdev = to_pci_dev(dev); | |
4069 | struct net_device *netdev = pci_get_drvdata(pdev); | |
4070 | ||
4071 | if (netif_running(netdev)) { | |
4072 | pci_restore_state(pdev); | |
4073 | et131x_up(netdev); | |
4074 | netif_device_attach(netdev); | |
4075 | } | |
4076 | ||
4077 | return 0; | |
4078 | } | |
4079 | ||
2e9ff8d9 ME |
4080 | static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume); |
4081 | #define ET131X_PM_OPS (&et131x_pm_ops) | |
4082 | #else | |
4083 | #define ET131X_PM_OPS NULL | |
4084 | #endif | |
4085 | ||
d2796743 ME |
4086 | /** |
4087 | * et131x_isr - The Interrupt Service Routine for the driver. | |
4088 | * @irq: the IRQ on which the interrupt was received. | |
4089 | * @dev_id: device-specific info (here a pointer to a net_device struct) | |
4090 | * | |
4091 | * Returns a value indicating if the interrupt was handled. | |
4092 | */ | |
4093 | irqreturn_t et131x_isr(int irq, void *dev_id) | |
4094 | { | |
4095 | bool handled = true; | |
4096 | struct net_device *netdev = (struct net_device *)dev_id; | |
4097 | struct et131x_adapter *adapter = NULL; | |
4098 | u32 status; | |
4099 | ||
4100 | if (!netif_device_present(netdev)) { | |
4101 | handled = false; | |
4102 | goto out; | |
4103 | } | |
4104 | ||
4105 | adapter = netdev_priv(netdev); | |
4106 | ||
4107 | /* If the adapter is in low power state, then it should not | |
4108 | * recognize any interrupt | |
4109 | */ | |
4110 | ||
4111 | /* Disable Device Interrupts */ | |
4112 | et131x_disable_interrupts(adapter); | |
4113 | ||
4114 | /* Get a copy of the value in the interrupt status register | |
4115 | * so we can process the interrupting section | |
4116 | */ | |
4117 | status = readl(&adapter->regs->global.int_status); | |
4118 | ||
4119 | if (adapter->flowcontrol == FLOW_TXONLY || | |
4120 | adapter->flowcontrol == FLOW_BOTH) { | |
4121 | status &= ~INT_MASK_ENABLE; | |
4122 | } else { | |
4123 | status &= ~INT_MASK_ENABLE_NO_FLOW; | |
4124 | } | |
4125 | ||
4126 | /* Make sure this is our interrupt */ | |
4127 | if (!status) { | |
4128 | handled = false; | |
4129 | et131x_enable_interrupts(adapter); | |
4130 | goto out; | |
4131 | } | |
4132 | ||
4133 | /* This is our interrupt, so process accordingly */ | |
4134 | ||
4135 | if (status & ET_INTR_WATCHDOG) { | |
4136 | struct tcb *tcb = adapter->tx_ring.send_head; | |
4137 | ||
4138 | if (tcb) | |
4139 | if (++tcb->stale > 1) | |
4140 | status |= ET_INTR_TXDMA_ISR; | |
4141 | ||
4142 | if (adapter->rx_ring.unfinished_receives) | |
4143 | status |= ET_INTR_RXDMA_XFR_DONE; | |
4144 | else if (tcb == NULL) | |
4145 | writel(0, &adapter->regs->global.watchdog_timer); | |
4146 | ||
4147 | status &= ~ET_INTR_WATCHDOG; | |
4148 | } | |
4149 | ||
4150 | if (status == 0) { | |
4151 | /* This interrupt has in some way been "handled" by | |
4152 | * the ISR. Either it was a spurious Rx interrupt, or | |
4153 | * it was a Tx interrupt that has been filtered by | |
4154 | * the ISR. | |
4155 | */ | |
4156 | et131x_enable_interrupts(adapter); | |
4157 | goto out; | |
4158 | } | |
4159 | ||
4160 | /* We need to save the interrupt status value for use in our | |
4161 | * DPC. We will clear the software copy of that in that | |
4162 | * routine. | |
4163 | */ | |
4164 | adapter->stats.interrupt_status = status; | |
4165 | ||
4166 | /* Schedule the ISR handler as a bottom-half task in the | |
4167 | * kernel's tq_immediate queue, and mark the queue for | |
4168 | * execution | |
4169 | */ | |
4170 | schedule_work(&adapter->task); | |
4171 | out: | |
4172 | return IRQ_RETVAL(handled); | |
4173 | } | |
4174 | ||
4175 | /** | |
4176 | * et131x_isr_handler - The ISR handler | |
4177 | * @p_adapter, a pointer to the device's private adapter structure | |
4178 | * | |
4179 | * scheduled to run in a deferred context by the ISR. This is where the ISR's | |
4180 | * work actually gets done. | |
4181 | */ | |
eb7a6ca6 | 4182 | static void et131x_isr_handler(struct work_struct *work) |
d2796743 ME |
4183 | { |
4184 | struct et131x_adapter *adapter = | |
4185 | container_of(work, struct et131x_adapter, task); | |
4186 | u32 status = adapter->stats.interrupt_status; | |
4187 | struct address_map __iomem *iomem = adapter->regs; | |
4188 | ||
4189 | /* | |
4190 | * These first two are by far the most common. Once handled, we clear | |
4191 | * their two bits in the status word. If the word is now zero, we | |
4192 | * exit. | |
4193 | */ | |
4194 | /* Handle all the completed Transmit interrupts */ | |
4195 | if (status & ET_INTR_TXDMA_ISR) | |
4196 | et131x_handle_send_interrupt(adapter); | |
4197 | ||
4198 | /* Handle all the completed Receives interrupts */ | |
4199 | if (status & ET_INTR_RXDMA_XFR_DONE) | |
4200 | et131x_handle_recv_interrupt(adapter); | |
4201 | ||
4202 | status &= 0xffffffd7; | |
4203 | ||
15ffde4d ME |
4204 | if (!status) |
4205 | goto out; | |
d2796743 | 4206 | |
15ffde4d ME |
4207 | /* Handle the TXDMA Error interrupt */ |
4208 | if (status & ET_INTR_TXDMA_ERR) { | |
4209 | u32 txdma_err; | |
d2796743 | 4210 | |
15ffde4d ME |
4211 | /* Following read also clears the register (COR) */ |
4212 | txdma_err = readl(&iomem->txdma.tx_dma_error); | |
d2796743 | 4213 | |
15ffde4d ME |
4214 | dev_warn(&adapter->pdev->dev, |
4215 | "TXDMA_ERR interrupt, error = %d\n", | |
4216 | txdma_err); | |
4217 | } | |
d2796743 | 4218 | |
15ffde4d ME |
4219 | /* Handle Free Buffer Ring 0 and 1 Low interrupt */ |
4220 | if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) { | |
4221 | /* | |
4222 | * This indicates the number of unused buffers in RXDMA free | |
4223 | * buffer ring 0 is <= the limit you programmed. Free buffer | |
4224 | * resources need to be returned. Free buffers are consumed as | |
4225 | * packets are passed from the network to the host. The host | |
4226 | * becomes aware of the packets from the contents of the packet | |
4227 | * status ring. This ring is queried when the packet done | |
4228 | * interrupt occurs. Packets are then passed to the OS. When | |
4229 | * the OS is done with the packets the resources can be | |
4230 | * returned to the ET1310 for re-use. This interrupt is one | |
4231 | * method of returning resources. | |
4232 | */ | |
d2796743 | 4233 | |
15ffde4d ME |
4234 | /* |
4235 | * If the user has flow control on, then we will | |
4236 | * send a pause packet, otherwise just exit | |
4237 | */ | |
4238 | if (adapter->flowcontrol == FLOW_TXONLY || | |
4239 | adapter->flowcontrol == FLOW_BOTH) { | |
4240 | u32 pm_csr; | |
d2796743 ME |
4241 | |
4242 | /* | |
15ffde4d ME |
4243 | * Tell the device to send a pause packet via the back |
4244 | * pressure register (bp req and bp xon/xoff) | |
d2796743 | 4245 | */ |
15ffde4d ME |
4246 | pm_csr = readl(&iomem->global.pm_csr); |
4247 | if (!et1310_in_phy_coma(adapter)) | |
4248 | writel(3, &iomem->txmac.bp_ctrl); | |
d2796743 | 4249 | } |
15ffde4d | 4250 | } |
d2796743 | 4251 | |
15ffde4d ME |
4252 | /* Handle Packet Status Ring Low Interrupt */ |
4253 | if (status & ET_INTR_RXDMA_STAT_LOW) { | |
4254 | /* | |
4255 | * Same idea as with the two Free Buffer Rings. Packets going | |
4256 | * from the network to the host each consume a free buffer | |
4257 | * resource and a packet status resource. These resoures are | |
4258 | * passed to the OS. When the OS is done with the resources, | |
4259 | * they need to be returned to the ET1310. This is one method | |
4260 | * of returning the resources. | |
4261 | */ | |
4262 | } | |
d2796743 | 4263 | |
15ffde4d ME |
4264 | /* Handle RXDMA Error Interrupt */ |
4265 | if (status & ET_INTR_RXDMA_ERR) { | |
4266 | /* | |
4267 | * The rxdma_error interrupt is sent when a time-out on a | |
4268 | * request issued by the JAGCore has occurred or a completion is | |
4269 | * returned with an un-successful status. In both cases the | |
4270 | * request is considered complete. The JAGCore will | |
4271 | * automatically re-try the request in question. Normally | |
4272 | * information on events like these are sent to the host using | |
4273 | * the "Advanced Error Reporting" capability. This interrupt is | |
4274 | * another way of getting similar information. The only thing | |
4275 | * required is to clear the interrupt by reading the ISR in the | |
4276 | * global resources. The JAGCore will do a re-try on the | |
4277 | * request. Normally you should never see this interrupt. If | |
4278 | * you start to see this interrupt occurring frequently then | |
4279 | * something bad has occurred. A reset might be the thing to do. | |
4280 | */ | |
4281 | /* TRAP();*/ | |
d2796743 | 4282 | |
15ffde4d ME |
4283 | dev_warn(&adapter->pdev->dev, |
4284 | "RxDMA_ERR interrupt, error %x\n", | |
4285 | readl(&iomem->txmac.tx_test)); | |
4286 | } | |
d2796743 | 4287 | |
15ffde4d ME |
4288 | /* Handle the Wake on LAN Event */ |
4289 | if (status & ET_INTR_WOL) { | |
4290 | /* | |
4291 | * This is a secondary interrupt for wake on LAN. The driver | |
4292 | * should never see this, if it does, something serious is | |
4293 | * wrong. We will TRAP the message when we are in DBG mode, | |
4294 | * otherwise we will ignore it. | |
4295 | */ | |
4296 | dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n"); | |
4297 | } | |
d2796743 | 4298 | |
15ffde4d ME |
4299 | /* Let's move on to the TxMac */ |
4300 | if (status & ET_INTR_TXMAC) { | |
4301 | u32 err = readl(&iomem->txmac.err); | |
d2796743 | 4302 | |
15ffde4d ME |
4303 | /* |
4304 | * When any of the errors occur and TXMAC generates an | |
4305 | * interrupt to report these errors, it usually means that | |
4306 | * TXMAC has detected an error in the data stream retrieved | |
4307 | * from the on-chip Tx Q. All of these errors are catastrophic | |
4308 | * and TXMAC won't be able to recover data when these errors | |
4309 | * occur. In a nutshell, the whole Tx path will have to be reset | |
4310 | * and re-configured afterwards. | |
4311 | */ | |
4312 | dev_warn(&adapter->pdev->dev, | |
4313 | "TXMAC interrupt, error 0x%08x\n", | |
4314 | err); | |
d2796743 | 4315 | |
15ffde4d ME |
4316 | /* |
4317 | * If we are debugging, we want to see this error, otherwise we | |
4318 | * just want the device to be reset and continue | |
4319 | */ | |
4320 | } | |
d2796743 | 4321 | |
15ffde4d ME |
4322 | /* Handle RXMAC Interrupt */ |
4323 | if (status & ET_INTR_RXMAC) { | |
4324 | /* | |
4325 | * These interrupts are catastrophic to the device, what we need | |
4326 | * to do is disable the interrupts and set the flag to cause us | |
4327 | * to reset so we can solve this issue. | |
4328 | */ | |
4329 | /* MP_SET_FLAG( adapter, fMP_ADAPTER_HARDWARE_ERROR); */ | |
d2796743 | 4330 | |
15ffde4d ME |
4331 | dev_warn(&adapter->pdev->dev, |
4332 | "RXMAC interrupt, error 0x%08x. Requesting reset\n", | |
4333 | readl(&iomem->rxmac.err_reg)); | |
d2796743 | 4334 | |
15ffde4d ME |
4335 | dev_warn(&adapter->pdev->dev, |
4336 | "Enable 0x%08x, Diag 0x%08x\n", | |
4337 | readl(&iomem->rxmac.ctrl), | |
4338 | readl(&iomem->rxmac.rxq_diag)); | |
d2796743 | 4339 | |
15ffde4d ME |
4340 | /* |
4341 | * If we are debugging, we want to see this error, otherwise we | |
4342 | * just want the device to be reset and continue | |
4343 | */ | |
4344 | } | |
d2796743 | 4345 | |
15ffde4d ME |
4346 | /* Handle MAC_STAT Interrupt */ |
4347 | if (status & ET_INTR_MAC_STAT) { | |
4348 | /* | |
4349 | * This means at least one of the un-masked counters in the | |
4350 | * MAC_STAT block has rolled over. Use this to maintain the top, | |
4351 | * software managed bits of the counter(s). | |
4352 | */ | |
4353 | et1310_handle_macstat_interrupt(adapter); | |
d2796743 | 4354 | } |
15ffde4d ME |
4355 | |
4356 | /* Handle SLV Timeout Interrupt */ | |
4357 | if (status & ET_INTR_SLV_TIMEOUT) { | |
4358 | /* | |
4359 | * This means a timeout has occurred on a read or write request | |
4360 | * to one of the JAGCore registers. The Global Resources block | |
4361 | * has terminated the request and on a read request, returned a | |
4362 | * "fake" value. The most likely reasons are: Bad Address or the | |
4363 | * addressed module is in a power-down state and can't respond. | |
4364 | */ | |
4365 | } | |
4366 | out: | |
d2796743 ME |
4367 | et131x_enable_interrupts(adapter); |
4368 | } | |
4369 | ||
d2796743 ME |
4370 | /** |
4371 | * et131x_stats - Return the current device statistics. | |
4372 | * @netdev: device whose stats are being queried | |
4373 | * | |
4374 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
4375 | */ | |
4376 | static struct net_device_stats *et131x_stats(struct net_device *netdev) | |
4377 | { | |
4378 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4379 | struct net_device_stats *stats = &adapter->net_stats; | |
4380 | struct ce_stats *devstat = &adapter->stats; | |
4381 | ||
4382 | stats->rx_errors = devstat->rx_length_errs + | |
4383 | devstat->rx_align_errs + | |
4384 | devstat->rx_crc_errs + | |
4385 | devstat->rx_code_violations + | |
4386 | devstat->rx_other_errs; | |
4387 | stats->tx_errors = devstat->tx_max_pkt_errs; | |
4388 | stats->multicast = devstat->multicast_pkts_rcvd; | |
4389 | stats->collisions = devstat->tx_collisions; | |
4390 | ||
4391 | stats->rx_length_errors = devstat->rx_length_errs; | |
4392 | stats->rx_over_errors = devstat->rx_overflows; | |
4393 | stats->rx_crc_errors = devstat->rx_crc_errs; | |
4394 | ||
4395 | /* NOTE: These stats don't have corresponding values in CE_STATS, | |
4396 | * so we're going to have to update these directly from within the | |
4397 | * TX/RX code | |
4398 | */ | |
4399 | /* stats->rx_bytes = 20; devstat->; */ | |
4400 | /* stats->tx_bytes = 20; devstat->; */ | |
4401 | /* stats->rx_dropped = devstat->; */ | |
4402 | /* stats->tx_dropped = devstat->; */ | |
4403 | ||
4404 | /* NOTE: Not used, can't find analogous statistics */ | |
4405 | /* stats->rx_frame_errors = devstat->; */ | |
4406 | /* stats->rx_fifo_errors = devstat->; */ | |
4407 | /* stats->rx_missed_errors = devstat->; */ | |
4408 | ||
4409 | /* stats->tx_aborted_errors = devstat->; */ | |
4410 | /* stats->tx_carrier_errors = devstat->; */ | |
4411 | /* stats->tx_fifo_errors = devstat->; */ | |
4412 | /* stats->tx_heartbeat_errors = devstat->; */ | |
4413 | /* stats->tx_window_errors = devstat->; */ | |
4414 | return stats; | |
4415 | } | |
4416 | ||
d2796743 ME |
4417 | /** |
4418 | * et131x_open - Open the device for use. | |
4419 | * @netdev: device to be opened | |
4420 | * | |
4421 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
4422 | */ | |
eb7a6ca6 | 4423 | static int et131x_open(struct net_device *netdev) |
d2796743 | 4424 | { |
d2796743 | 4425 | struct et131x_adapter *adapter = netdev_priv(netdev); |
5f3eb881 FR |
4426 | struct pci_dev *pdev = adapter->pdev; |
4427 | unsigned int irq = pdev->irq; | |
4428 | int result; | |
d2796743 ME |
4429 | |
4430 | /* Start the timer to track NIC errors */ | |
4431 | init_timer(&adapter->error_timer); | |
4432 | adapter->error_timer.expires = jiffies + TX_ERROR_PERIOD * HZ / 1000; | |
4433 | adapter->error_timer.function = et131x_error_timer_handler; | |
4434 | adapter->error_timer.data = (unsigned long)adapter; | |
4435 | add_timer(&adapter->error_timer); | |
4436 | ||
bf3313a1 | 4437 | result = request_irq(irq, et131x_isr, |
4438 | IRQF_SHARED, netdev->name, netdev); | |
d2796743 | 4439 | if (result) { |
5f3eb881 | 4440 | dev_err(&pdev->dev, "could not register IRQ %d\n", irq); |
d2796743 ME |
4441 | return result; |
4442 | } | |
4443 | ||
4444 | adapter->flags |= fMP_ADAPTER_INTERRUPT_IN_USE; | |
4445 | ||
4446 | et131x_up(netdev); | |
4447 | ||
4448 | return result; | |
4449 | } | |
4450 | ||
d2796743 ME |
4451 | /** |
4452 | * et131x_close - Close the device | |
4453 | * @netdev: device to be closed | |
4454 | * | |
4455 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
4456 | */ | |
eb7a6ca6 | 4457 | static int et131x_close(struct net_device *netdev) |
d2796743 ME |
4458 | { |
4459 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4460 | ||
4461 | et131x_down(netdev); | |
4462 | ||
4463 | adapter->flags &= ~fMP_ADAPTER_INTERRUPT_IN_USE; | |
5f3eb881 | 4464 | free_irq(adapter->pdev->irq, netdev); |
d2796743 ME |
4465 | |
4466 | /* Stop the error timer */ | |
4467 | return del_timer_sync(&adapter->error_timer); | |
4468 | } | |
4469 | ||
4470 | /** | |
4471 | * et131x_ioctl - The I/O Control handler for the driver | |
4472 | * @netdev: device on which the control request is being made | |
4473 | * @reqbuf: a pointer to the IOCTL request buffer | |
4474 | * @cmd: the IOCTL command code | |
4475 | * | |
4476 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
4477 | */ | |
09a3fc2b ME |
4478 | static int et131x_ioctl(struct net_device *netdev, struct ifreq *reqbuf, |
4479 | int cmd) | |
d2796743 ME |
4480 | { |
4481 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4482 | ||
4483 | if (!adapter->phydev) | |
4484 | return -EINVAL; | |
4485 | ||
4486 | return phy_mii_ioctl(adapter->phydev, reqbuf, cmd); | |
4487 | } | |
4488 | ||
4489 | /** | |
4490 | * et131x_set_packet_filter - Configures the Rx Packet filtering on the device | |
4491 | * @adapter: pointer to our private adapter structure | |
4492 | * | |
4493 | * FIXME: lot of dups with MAC code | |
4494 | * | |
4495 | * Returns 0 on success, errno on failure | |
4496 | */ | |
4497 | static int et131x_set_packet_filter(struct et131x_adapter *adapter) | |
4498 | { | |
834d0ee3 | 4499 | int filter = adapter->packet_filter; |
d2796743 | 4500 | int status = 0; |
d2796743 ME |
4501 | u32 ctrl; |
4502 | u32 pf_ctrl; | |
4503 | ||
4504 | ctrl = readl(&adapter->regs->rxmac.ctrl); | |
4505 | pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl); | |
4506 | ||
4507 | /* Default to disabled packet filtering. Enable it in the individual | |
4508 | * case statements that require the device to filter something | |
4509 | */ | |
4510 | ctrl |= 0x04; | |
4511 | ||
4512 | /* Set us to be in promiscuous mode so we receive everything, this | |
4513 | * is also true when we get a packet filter of 0 | |
4514 | */ | |
4515 | if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0) | |
4516 | pf_ctrl &= ~7; /* Clear filter bits */ | |
4517 | else { | |
4518 | /* | |
4519 | * Set us up with Multicast packet filtering. Three cases are | |
4520 | * possible - (1) we have a multi-cast list, (2) we receive ALL | |
4521 | * multicast entries or (3) we receive none. | |
4522 | */ | |
4523 | if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST) | |
4524 | pf_ctrl &= ~2; /* Multicast filter bit */ | |
4525 | else { | |
4526 | et1310_setup_device_for_multicast(adapter); | |
4527 | pf_ctrl |= 2; | |
4528 | ctrl &= ~0x04; | |
4529 | } | |
4530 | ||
4531 | /* Set us up with Unicast packet filtering */ | |
4532 | if (filter & ET131X_PACKET_TYPE_DIRECTED) { | |
4533 | et1310_setup_device_for_unicast(adapter); | |
4534 | pf_ctrl |= 4; | |
4535 | ctrl &= ~0x04; | |
4536 | } | |
4537 | ||
4538 | /* Set us up with Broadcast packet filtering */ | |
4539 | if (filter & ET131X_PACKET_TYPE_BROADCAST) { | |
4540 | pf_ctrl |= 1; /* Broadcast filter bit */ | |
4541 | ctrl &= ~0x04; | |
4542 | } else | |
4543 | pf_ctrl &= ~1; | |
4544 | ||
4545 | /* Setup the receive mac configuration registers - Packet | |
4546 | * Filter control + the enable / disable for packet filter | |
4547 | * in the control reg. | |
4548 | */ | |
4549 | writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl); | |
4550 | writel(ctrl, &adapter->regs->rxmac.ctrl); | |
4551 | } | |
4552 | return status; | |
4553 | } | |
4554 | ||
4555 | /** | |
4556 | * et131x_multicast - The handler to configure multicasting on the interface | |
4557 | * @netdev: a pointer to a net_device struct representing the device | |
4558 | */ | |
4559 | static void et131x_multicast(struct net_device *netdev) | |
4560 | { | |
4561 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
834d0ee3 | 4562 | int packet_filter; |
d2796743 ME |
4563 | unsigned long flags; |
4564 | struct netdev_hw_addr *ha; | |
4565 | int i; | |
4566 | ||
4567 | spin_lock_irqsave(&adapter->lock, flags); | |
4568 | ||
4569 | /* Before we modify the platform-independent filter flags, store them | |
4570 | * locally. This allows us to determine if anything's changed and if | |
4571 | * we even need to bother the hardware | |
4572 | */ | |
4573 | packet_filter = adapter->packet_filter; | |
4574 | ||
4575 | /* Clear the 'multicast' flag locally; because we only have a single | |
4576 | * flag to check multicast, and multiple multicast addresses can be | |
4577 | * set, this is the easiest way to determine if more than one | |
4578 | * multicast address is being set. | |
4579 | */ | |
4580 | packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST; | |
4581 | ||
4582 | /* Check the net_device flags and set the device independent flags | |
4583 | * accordingly | |
4584 | */ | |
4585 | ||
4586 | if (netdev->flags & IFF_PROMISC) | |
4587 | adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS; | |
4588 | else | |
4589 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS; | |
4590 | ||
4591 | if (netdev->flags & IFF_ALLMULTI) | |
4592 | adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST; | |
4593 | ||
4594 | if (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST) | |
4595 | adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST; | |
4596 | ||
4597 | if (netdev_mc_count(netdev) < 1) { | |
4598 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST; | |
4599 | adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST; | |
4600 | } else | |
4601 | adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST; | |
4602 | ||
4603 | /* Set values in the private adapter struct */ | |
4604 | i = 0; | |
4605 | netdev_for_each_mc_addr(ha, netdev) { | |
4606 | if (i == NIC_MAX_MCAST_LIST) | |
4607 | break; | |
4608 | memcpy(adapter->multicast_list[i++], ha->addr, ETH_ALEN); | |
4609 | } | |
4610 | adapter->multicast_addr_count = i; | |
4611 | ||
4612 | /* Are the new flags different from the previous ones? If not, then no | |
4613 | * action is required | |
4614 | * | |
4615 | * NOTE - This block will always update the multicast_list with the | |
4616 | * hardware, even if the addresses aren't the same. | |
4617 | */ | |
4618 | if (packet_filter != adapter->packet_filter) { | |
4619 | /* Call the device's filter function */ | |
4620 | et131x_set_packet_filter(adapter); | |
4621 | } | |
4622 | spin_unlock_irqrestore(&adapter->lock, flags); | |
4623 | } | |
4624 | ||
4625 | /** | |
4626 | * et131x_tx - The handler to tx a packet on the device | |
4627 | * @skb: data to be Tx'd | |
4628 | * @netdev: device on which data is to be Tx'd | |
4629 | * | |
4630 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
4631 | */ | |
4632 | static int et131x_tx(struct sk_buff *skb, struct net_device *netdev) | |
4633 | { | |
4634 | int status = 0; | |
06709e96 ME |
4635 | struct et131x_adapter *adapter = netdev_priv(netdev); |
4636 | ||
4637 | /* stop the queue if it's getting full */ | |
09a3fc2b ME |
4638 | if (adapter->tx_ring.used >= NUM_TCB - 1 && |
4639 | !netif_queue_stopped(netdev)) | |
06709e96 | 4640 | netif_stop_queue(netdev); |
d2796743 ME |
4641 | |
4642 | /* Save the timestamp for the TX timeout watchdog */ | |
4643 | netdev->trans_start = jiffies; | |
4644 | ||
4645 | /* Call the device-specific data Tx routine */ | |
4646 | status = et131x_send_packets(skb, netdev); | |
4647 | ||
4648 | /* Check status and manage the netif queue if necessary */ | |
4649 | if (status != 0) { | |
09a3fc2b | 4650 | if (status == -ENOMEM) |
d2796743 | 4651 | status = NETDEV_TX_BUSY; |
09a3fc2b | 4652 | else |
d2796743 | 4653 | status = NETDEV_TX_OK; |
d2796743 ME |
4654 | } |
4655 | return status; | |
4656 | } | |
4657 | ||
4658 | /** | |
4659 | * et131x_tx_timeout - Timeout handler | |
4660 | * @netdev: a pointer to a net_device struct representing the device | |
4661 | * | |
4662 | * The handler called when a Tx request times out. The timeout period is | |
4663 | * specified by the 'tx_timeo" element in the net_device structure (see | |
4664 | * et131x_alloc_device() to see how this value is set). | |
4665 | */ | |
4666 | static void et131x_tx_timeout(struct net_device *netdev) | |
4667 | { | |
4668 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4669 | struct tcb *tcb; | |
4670 | unsigned long flags; | |
4671 | ||
4672 | /* If the device is closed, ignore the timeout */ | |
4673 | if (~(adapter->flags & fMP_ADAPTER_INTERRUPT_IN_USE)) | |
4674 | return; | |
4675 | ||
4676 | /* Any nonrecoverable hardware error? | |
4677 | * Checks adapter->flags for any failure in phy reading | |
4678 | */ | |
4679 | if (adapter->flags & fMP_ADAPTER_NON_RECOVER_ERROR) | |
4680 | return; | |
4681 | ||
4682 | /* Hardware failure? */ | |
4683 | if (adapter->flags & fMP_ADAPTER_HARDWARE_ERROR) { | |
4684 | dev_err(&adapter->pdev->dev, "hardware error - reset\n"); | |
4685 | return; | |
4686 | } | |
4687 | ||
4688 | /* Is send stuck? */ | |
4689 | spin_lock_irqsave(&adapter->tcb_send_qlock, flags); | |
4690 | ||
4691 | tcb = adapter->tx_ring.send_head; | |
4692 | ||
4693 | if (tcb != NULL) { | |
4694 | tcb->count++; | |
4695 | ||
4696 | if (tcb->count > NIC_SEND_HANG_THRESHOLD) { | |
4697 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, | |
4698 | flags); | |
4699 | ||
4700 | dev_warn(&adapter->pdev->dev, | |
4701 | "Send stuck - reset. tcb->WrIndex %x, flags 0x%08x\n", | |
4702 | tcb->index, | |
4703 | tcb->flags); | |
4704 | ||
4705 | adapter->net_stats.tx_errors++; | |
4706 | ||
4707 | /* perform reset of tx/rx */ | |
4708 | et131x_disable_txrx(netdev); | |
4709 | et131x_enable_txrx(netdev); | |
4710 | return; | |
4711 | } | |
4712 | } | |
4713 | ||
4714 | spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags); | |
4715 | } | |
4716 | ||
4717 | /** | |
4718 | * et131x_change_mtu - The handler called to change the MTU for the device | |
4719 | * @netdev: device whose MTU is to be changed | |
4720 | * @new_mtu: the desired MTU | |
4721 | * | |
4722 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
4723 | */ | |
4724 | static int et131x_change_mtu(struct net_device *netdev, int new_mtu) | |
4725 | { | |
4726 | int result = 0; | |
4727 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4728 | ||
4729 | /* Make sure the requested MTU is valid */ | |
4730 | if (new_mtu < 64 || new_mtu > 9216) | |
4731 | return -EINVAL; | |
4732 | ||
4733 | et131x_disable_txrx(netdev); | |
4734 | et131x_handle_send_interrupt(adapter); | |
4735 | et131x_handle_recv_interrupt(adapter); | |
4736 | ||
4737 | /* Set the new MTU */ | |
4738 | netdev->mtu = new_mtu; | |
4739 | ||
4740 | /* Free Rx DMA memory */ | |
4741 | et131x_adapter_memory_free(adapter); | |
4742 | ||
4743 | /* Set the config parameter for Jumbo Packet support */ | |
4744 | adapter->registry_jumbo_packet = new_mtu + 14; | |
4745 | et131x_soft_reset(adapter); | |
4746 | ||
4747 | /* Alloc and init Rx DMA memory */ | |
4748 | result = et131x_adapter_memory_alloc(adapter); | |
4749 | if (result != 0) { | |
4750 | dev_warn(&adapter->pdev->dev, | |
4751 | "Change MTU failed; couldn't re-alloc DMA memory\n"); | |
4752 | return result; | |
4753 | } | |
4754 | ||
4755 | et131x_init_send(adapter); | |
4756 | ||
4757 | et131x_hwaddr_init(adapter); | |
4758 | memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN); | |
4759 | ||
4760 | /* Init the device with the new settings */ | |
4761 | et131x_adapter_setup(adapter); | |
4762 | ||
4763 | et131x_enable_txrx(netdev); | |
4764 | ||
4765 | return result; | |
4766 | } | |
4767 | ||
4768 | /** | |
4769 | * et131x_set_mac_addr - handler to change the MAC address for the device | |
4770 | * @netdev: device whose MAC is to be changed | |
4771 | * @new_mac: the desired MAC address | |
4772 | * | |
4773 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
4774 | * | |
4775 | * IMPLEMENTED BY : blux http://berndlux.de 22.01.2007 21:14 | |
4776 | */ | |
4777 | static int et131x_set_mac_addr(struct net_device *netdev, void *new_mac) | |
4778 | { | |
4779 | int result = 0; | |
4780 | struct et131x_adapter *adapter = netdev_priv(netdev); | |
4781 | struct sockaddr *address = new_mac; | |
4782 | ||
4783 | /* begin blux */ | |
4784 | ||
4785 | if (adapter == NULL) | |
4786 | return -ENODEV; | |
4787 | ||
4788 | /* Make sure the requested MAC is valid */ | |
4789 | if (!is_valid_ether_addr(address->sa_data)) | |
d8aa3e26 | 4790 | return -EADDRNOTAVAIL; |
d2796743 ME |
4791 | |
4792 | et131x_disable_txrx(netdev); | |
4793 | et131x_handle_send_interrupt(adapter); | |
4794 | et131x_handle_recv_interrupt(adapter); | |
4795 | ||
4796 | /* Set the new MAC */ | |
4797 | /* netdev->set_mac_address = &new_mac; */ | |
4798 | ||
4799 | memcpy(netdev->dev_addr, address->sa_data, netdev->addr_len); | |
4800 | ||
e58b89da TY |
4801 | netdev_info(netdev, "Setting MAC address to %pM\n", |
4802 | netdev->dev_addr); | |
d2796743 ME |
4803 | |
4804 | /* Free Rx DMA memory */ | |
4805 | et131x_adapter_memory_free(adapter); | |
4806 | ||
4807 | et131x_soft_reset(adapter); | |
4808 | ||
4809 | /* Alloc and init Rx DMA memory */ | |
4810 | result = et131x_adapter_memory_alloc(adapter); | |
4811 | if (result != 0) { | |
4812 | dev_err(&adapter->pdev->dev, | |
4813 | "Change MAC failed; couldn't re-alloc DMA memory\n"); | |
4814 | return result; | |
4815 | } | |
4816 | ||
4817 | et131x_init_send(adapter); | |
4818 | ||
4819 | et131x_hwaddr_init(adapter); | |
4820 | ||
4821 | /* Init the device with the new settings */ | |
4822 | et131x_adapter_setup(adapter); | |
4823 | ||
4824 | et131x_enable_txrx(netdev); | |
4825 | ||
4826 | return result; | |
4827 | } | |
4828 | ||
4829 | static const struct net_device_ops et131x_netdev_ops = { | |
4830 | .ndo_open = et131x_open, | |
4831 | .ndo_stop = et131x_close, | |
4832 | .ndo_start_xmit = et131x_tx, | |
aa77677e | 4833 | .ndo_set_rx_mode = et131x_multicast, |
d2796743 ME |
4834 | .ndo_tx_timeout = et131x_tx_timeout, |
4835 | .ndo_change_mtu = et131x_change_mtu, | |
4836 | .ndo_set_mac_address = et131x_set_mac_addr, | |
4837 | .ndo_validate_addr = eth_validate_addr, | |
4838 | .ndo_get_stats = et131x_stats, | |
4839 | .ndo_do_ioctl = et131x_ioctl, | |
4840 | }; | |
4841 | ||
5da2b158 ME |
4842 | /** |
4843 | * et131x_pci_setup - Perform device initialization | |
4844 | * @pdev: a pointer to the device's pci_dev structure | |
4845 | * @ent: this device's entry in the pci_device_id table | |
4846 | * | |
4847 | * Returns 0 on success, errno on failure (as defined in errno.h) | |
4848 | * | |
4849 | * Registered in the pci_driver structure, this function is called when the | |
4850 | * PCI subsystem finds a new PCI device which matches the information | |
4851 | * contained in the pci_device_id table. This routine is the equivalent to | |
4852 | * a device insertion routine. | |
4853 | */ | |
fe5c49b3 | 4854 | static int et131x_pci_setup(struct pci_dev *pdev, |
5da2b158 ME |
4855 | const struct pci_device_id *ent) |
4856 | { | |
5da2b158 ME |
4857 | struct net_device *netdev; |
4858 | struct et131x_adapter *adapter; | |
fa9f0a65 | 4859 | int rc; |
5da2b158 ME |
4860 | int ii; |
4861 | ||
fa9f0a65 FR |
4862 | rc = pci_enable_device(pdev); |
4863 | if (rc < 0) { | |
5da2b158 | 4864 | dev_err(&pdev->dev, "pci_enable_device() failed\n"); |
fa9f0a65 | 4865 | goto out; |
5da2b158 ME |
4866 | } |
4867 | ||
4868 | /* Perform some basic PCI checks */ | |
4869 | if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) { | |
4870 | dev_err(&pdev->dev, "Can't find PCI device's base address\n"); | |
fa9f0a65 | 4871 | rc = -ENODEV; |
5da2b158 ME |
4872 | goto err_disable; |
4873 | } | |
4874 | ||
fa9f0a65 FR |
4875 | rc = pci_request_regions(pdev, DRIVER_NAME); |
4876 | if (rc < 0) { | |
5da2b158 ME |
4877 | dev_err(&pdev->dev, "Can't get PCI resources\n"); |
4878 | goto err_disable; | |
4879 | } | |
4880 | ||
4881 | pci_set_master(pdev); | |
4882 | ||
4883 | /* Check the DMA addressing support of this device */ | |
4884 | if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) { | |
fa9f0a65 FR |
4885 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64)); |
4886 | if (rc < 0) { | |
5da2b158 ME |
4887 | dev_err(&pdev->dev, |
4888 | "Unable to obtain 64 bit DMA for consistent allocations\n"); | |
4889 | goto err_release_res; | |
4890 | } | |
4891 | } else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32))) { | |
fa9f0a65 FR |
4892 | rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32)); |
4893 | if (rc < 0) { | |
5da2b158 ME |
4894 | dev_err(&pdev->dev, |
4895 | "Unable to obtain 32 bit DMA for consistent allocations\n"); | |
4896 | goto err_release_res; | |
4897 | } | |
4898 | } else { | |
4899 | dev_err(&pdev->dev, "No usable DMA addressing method\n"); | |
fa9f0a65 | 4900 | rc = -EIO; |
5da2b158 ME |
4901 | goto err_release_res; |
4902 | } | |
4903 | ||
4904 | /* Allocate netdev and private adapter structs */ | |
fa9f0a65 | 4905 | netdev = alloc_etherdev(sizeof(struct et131x_adapter)); |
5da2b158 ME |
4906 | if (!netdev) { |
4907 | dev_err(&pdev->dev, "Couldn't alloc netdev struct\n"); | |
fa9f0a65 | 4908 | rc = -ENOMEM; |
5da2b158 ME |
4909 | goto err_release_res; |
4910 | } | |
4911 | ||
fa9f0a65 FR |
4912 | netdev->watchdog_timeo = ET131X_TX_TIMEOUT; |
4913 | netdev->netdev_ops = &et131x_netdev_ops; | |
4914 | ||
5da2b158 | 4915 | SET_NETDEV_DEV(netdev, &pdev->dev); |
a6e28b34 | 4916 | SET_ETHTOOL_OPS(netdev, &et131x_ethtool_ops); |
5da2b158 ME |
4917 | |
4918 | adapter = et131x_adapter_init(netdev, pdev); | |
4919 | ||
fa9f0a65 FR |
4920 | rc = et131x_pci_init(adapter, pdev); |
4921 | if (rc < 0) | |
4922 | goto err_free_dev; | |
5da2b158 ME |
4923 | |
4924 | /* Map the bus-relative registers to system virtual memory */ | |
4925 | adapter->regs = pci_ioremap_bar(pdev, 0); | |
4926 | if (!adapter->regs) { | |
4927 | dev_err(&pdev->dev, "Cannot map device registers\n"); | |
fa9f0a65 | 4928 | rc = -ENOMEM; |
5da2b158 ME |
4929 | goto err_free_dev; |
4930 | } | |
4931 | ||
4932 | /* If Phy COMA mode was enabled when we went down, disable it here. */ | |
4933 | writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr); | |
4934 | ||
4935 | /* Issue a global reset to the et1310 */ | |
4936 | et131x_soft_reset(adapter); | |
4937 | ||
4938 | /* Disable all interrupts (paranoid) */ | |
4939 | et131x_disable_interrupts(adapter); | |
4940 | ||
4941 | /* Allocate DMA memory */ | |
fa9f0a65 FR |
4942 | rc = et131x_adapter_memory_alloc(adapter); |
4943 | if (rc < 0) { | |
5da2b158 ME |
4944 | dev_err(&pdev->dev, "Could not alloc adapater memory (DMA)\n"); |
4945 | goto err_iounmap; | |
4946 | } | |
4947 | ||
4948 | /* Init send data structures */ | |
4949 | et131x_init_send(adapter); | |
4950 | ||
4951 | /* Set up the task structure for the ISR's deferred handler */ | |
4952 | INIT_WORK(&adapter->task, et131x_isr_handler); | |
4953 | ||
4954 | /* Copy address into the net_device struct */ | |
4955 | memcpy(netdev->dev_addr, adapter->addr, ETH_ALEN); | |
4956 | ||
4957 | /* Init variable for counting how long we do not have link status */ | |
4958 | adapter->boot_coma = 0; | |
4959 | et1310_disable_phy_coma(adapter); | |
4960 | ||
fa9f0a65 FR |
4961 | rc = -ENOMEM; |
4962 | ||
5da2b158 ME |
4963 | /* Setup the mii_bus struct */ |
4964 | adapter->mii_bus = mdiobus_alloc(); | |
4965 | if (!adapter->mii_bus) { | |
4966 | dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n"); | |
4967 | goto err_mem_free; | |
4968 | } | |
4969 | ||
4970 | adapter->mii_bus->name = "et131x_eth_mii"; | |
4971 | snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x", | |
4972 | (adapter->pdev->bus->number << 8) | adapter->pdev->devfn); | |
4973 | adapter->mii_bus->priv = netdev; | |
4974 | adapter->mii_bus->read = et131x_mdio_read; | |
4975 | adapter->mii_bus->write = et131x_mdio_write; | |
4976 | adapter->mii_bus->reset = et131x_mdio_reset; | |
4977 | adapter->mii_bus->irq = kmalloc(sizeof(int)*PHY_MAX_ADDR, GFP_KERNEL); | |
4978 | if (!adapter->mii_bus->irq) { | |
4979 | dev_err(&pdev->dev, "mii_bus irq allocation failed\n"); | |
4980 | goto err_mdio_free; | |
4981 | } | |
4982 | ||
4983 | for (ii = 0; ii < PHY_MAX_ADDR; ii++) | |
4984 | adapter->mii_bus->irq[ii] = PHY_POLL; | |
4985 | ||
fa9f0a65 FR |
4986 | rc = mdiobus_register(adapter->mii_bus); |
4987 | if (rc < 0) { | |
5da2b158 | 4988 | dev_err(&pdev->dev, "failed to register MII bus\n"); |
5da2b158 ME |
4989 | goto err_mdio_free_irq; |
4990 | } | |
4991 | ||
fa9f0a65 FR |
4992 | rc = et131x_mii_probe(netdev); |
4993 | if (rc < 0) { | |
5da2b158 ME |
4994 | dev_err(&pdev->dev, "failed to probe MII bus\n"); |
4995 | goto err_mdio_unregister; | |
4996 | } | |
4997 | ||
4998 | /* Setup et1310 as per the documentation */ | |
4999 | et131x_adapter_setup(adapter); | |
5000 | ||
5001 | /* We can enable interrupts now | |
5002 | * | |
5003 | * NOTE - Because registration of interrupt handler is done in the | |
5004 | * device's open(), defer enabling device interrupts to that | |
5005 | * point | |
5006 | */ | |
5007 | ||
5008 | /* Register the net_device struct with the Linux network layer */ | |
fa9f0a65 FR |
5009 | rc = register_netdev(netdev); |
5010 | if (rc < 0) { | |
5da2b158 | 5011 | dev_err(&pdev->dev, "register_netdev() failed\n"); |
fa9f0a65 | 5012 | goto err_phy_disconnect; |
5da2b158 ME |
5013 | } |
5014 | ||
5015 | /* Register the net_device struct with the PCI subsystem. Save a copy | |
5016 | * of the PCI config space for this device now that the device has | |
5017 | * been initialized, just in case it needs to be quickly restored. | |
5018 | */ | |
5019 | pci_set_drvdata(pdev, netdev); | |
fa9f0a65 FR |
5020 | out: |
5021 | return rc; | |
5da2b158 | 5022 | |
fa9f0a65 FR |
5023 | err_phy_disconnect: |
5024 | phy_disconnect(adapter->phydev); | |
5da2b158 ME |
5025 | err_mdio_unregister: |
5026 | mdiobus_unregister(adapter->mii_bus); | |
5027 | err_mdio_free_irq: | |
5028 | kfree(adapter->mii_bus->irq); | |
5029 | err_mdio_free: | |
5030 | mdiobus_free(adapter->mii_bus); | |
5031 | err_mem_free: | |
5032 | et131x_adapter_memory_free(adapter); | |
5033 | err_iounmap: | |
5034 | iounmap(adapter->regs); | |
5035 | err_free_dev: | |
5036 | pci_dev_put(pdev); | |
5037 | free_netdev(netdev); | |
5038 | err_release_res: | |
5039 | pci_release_regions(pdev); | |
5040 | err_disable: | |
5041 | pci_disable_device(pdev); | |
fa9f0a65 | 5042 | goto out; |
5da2b158 ME |
5043 | } |
5044 | ||
5da2b158 ME |
5045 | static DEFINE_PCI_DEVICE_TABLE(et131x_pci_table) = { |
5046 | { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL}, | |
5047 | { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL}, | |
5048 | {0,} | |
5049 | }; | |
5050 | MODULE_DEVICE_TABLE(pci, et131x_pci_table); | |
5051 | ||
5052 | static struct pci_driver et131x_driver = { | |
5053 | .name = DRIVER_NAME, | |
5054 | .id_table = et131x_pci_table, | |
5055 | .probe = et131x_pci_setup, | |
0b5e4092 | 5056 | .remove = et131x_pci_remove, |
5da2b158 ME |
5057 | .driver.pm = ET131X_PM_OPS, |
5058 | }; | |
5059 | ||
89812b1f | 5060 | module_pci_driver(et131x_driver); |