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7a27b042 MH |
1 | /* |
2 | * AD7190 AD7192 AD7195 SPI ADC driver | |
3 | * | |
4 | * Copyright 2011 Analog Devices Inc. | |
5 | * | |
6 | * Licensed under the GPL-2. | |
7 | */ | |
8 | ||
9 | #include <linux/interrupt.h> | |
10 | #include <linux/device.h> | |
11 | #include <linux/kernel.h> | |
12 | #include <linux/slab.h> | |
13 | #include <linux/sysfs.h> | |
14 | #include <linux/spi/spi.h> | |
15 | #include <linux/regulator/consumer.h> | |
16 | #include <linux/err.h> | |
17 | #include <linux/sched.h> | |
18 | #include <linux/delay.h> | |
19 | ||
06458e27 JC |
20 | #include <linux/iio/iio.h> |
21 | #include <linux/iio/sysfs.h> | |
22 | #include <linux/iio/buffer.h> | |
7a27b042 | 23 | #include "../ring_sw.h" |
06458e27 JC |
24 | #include <linux/iio/trigger.h> |
25 | #include <linux/iio/trigger_consumer.h> | |
7a27b042 MH |
26 | |
27 | #include "ad7192.h" | |
28 | ||
29 | /* Registers */ | |
30 | #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */ | |
31 | #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */ | |
32 | #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */ | |
33 | #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */ | |
34 | #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */ | |
35 | #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */ | |
36 | #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */ | |
37 | #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit | |
38 | * (AD7792)/24-bit (AD7192)) */ | |
39 | #define AD7192_REG_FULLSALE 7 /* Full-Scale Register | |
40 | * (RW, 16-bit (AD7792)/24-bit (AD7192)) */ | |
41 | ||
42 | /* Communications Register Bit Designations (AD7192_REG_COMM) */ | |
43 | #define AD7192_COMM_WEN (1 << 7) /* Write Enable */ | |
44 | #define AD7192_COMM_WRITE (0 << 6) /* Write Operation */ | |
45 | #define AD7192_COMM_READ (1 << 6) /* Read Operation */ | |
46 | #define AD7192_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */ | |
47 | #define AD7192_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */ | |
48 | ||
49 | /* Status Register Bit Designations (AD7192_REG_STAT) */ | |
50 | #define AD7192_STAT_RDY (1 << 7) /* Ready */ | |
51 | #define AD7192_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */ | |
52 | #define AD7192_STAT_NOREF (1 << 5) /* Error no external reference */ | |
53 | #define AD7192_STAT_PARITY (1 << 4) /* Parity */ | |
54 | #define AD7192_STAT_CH3 (1 << 2) /* Channel 3 */ | |
55 | #define AD7192_STAT_CH2 (1 << 1) /* Channel 2 */ | |
56 | #define AD7192_STAT_CH1 (1 << 0) /* Channel 1 */ | |
57 | ||
58 | /* Mode Register Bit Designations (AD7192_REG_MODE) */ | |
59 | #define AD7192_MODE_SEL(x) (((x) & 0x7) << 21) /* Operation Mode Select */ | |
60 | #define AD7192_MODE_DAT_STA (1 << 20) /* Status Register transmission */ | |
61 | #define AD7192_MODE_CLKSRC(x) (((x) & 0x3) << 18) /* Clock Source Select */ | |
62 | #define AD7192_MODE_SINC3 (1 << 15) /* SINC3 Filter Select */ | |
63 | #define AD7192_MODE_ACX (1 << 14) /* AC excitation enable(AD7195 only)*/ | |
64 | #define AD7192_MODE_ENPAR (1 << 13) /* Parity Enable */ | |
65 | #define AD7192_MODE_CLKDIV (1 << 12) /* Clock divide by 2 (AD7190/2 only)*/ | |
66 | #define AD7192_MODE_SCYCLE (1 << 11) /* Single cycle conversion */ | |
67 | #define AD7192_MODE_REJ60 (1 << 10) /* 50/60Hz notch filter */ | |
68 | #define AD7192_MODE_RATE(x) ((x) & 0x3FF) /* Filter Update Rate Select */ | |
69 | ||
70 | /* Mode Register: AD7192_MODE_SEL options */ | |
71 | #define AD7192_MODE_CONT 0 /* Continuous Conversion Mode */ | |
72 | #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */ | |
73 | #define AD7192_MODE_IDLE 2 /* Idle Mode */ | |
74 | #define AD7192_MODE_PWRDN 3 /* Power-Down Mode */ | |
75 | #define AD7192_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */ | |
76 | #define AD7192_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */ | |
77 | #define AD7192_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */ | |
78 | #define AD7192_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */ | |
79 | ||
80 | /* Mode Register: AD7192_MODE_CLKSRC options */ | |
81 | #define AD7192_CLK_EXT_MCLK1_2 0 /* External 4.92 MHz Clock connected | |
82 | * from MCLK1 to MCLK2 */ | |
83 | #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */ | |
84 | #define AD7192_CLK_INT 2 /* Internal 4.92 MHz Clock not | |
85 | * available at the MCLK2 pin */ | |
86 | #define AD7192_CLK_INT_CO 3 /* Internal 4.92 MHz Clock available | |
87 | * at the MCLK2 pin */ | |
88 | ||
89 | ||
90 | /* Configuration Register Bit Designations (AD7192_REG_CONF) */ | |
91 | ||
92 | #define AD7192_CONF_CHOP (1 << 23) /* CHOP enable */ | |
93 | #define AD7192_CONF_REFSEL (1 << 20) /* REFIN1/REFIN2 Reference Select */ | |
94 | #define AD7192_CONF_CHAN(x) (((x) & 0xFF) << 8) /* Channel select */ | |
95 | #define AD7192_CONF_BURN (1 << 7) /* Burnout current enable */ | |
96 | #define AD7192_CONF_REFDET (1 << 6) /* Reference detect enable */ | |
97 | #define AD7192_CONF_BUF (1 << 4) /* Buffered Mode Enable */ | |
98 | #define AD7192_CONF_UNIPOLAR (1 << 3) /* Unipolar/Bipolar Enable */ | |
99 | #define AD7192_CONF_GAIN(x) ((x) & 0x7) /* Gain Select */ | |
100 | ||
101 | #define AD7192_CH_AIN1P_AIN2M 0 /* AIN1(+) - AIN2(-) */ | |
102 | #define AD7192_CH_AIN3P_AIN4M 1 /* AIN3(+) - AIN4(-) */ | |
103 | #define AD7192_CH_TEMP 2 /* Temp Sensor */ | |
104 | #define AD7192_CH_AIN2P_AIN2M 3 /* AIN2(+) - AIN2(-) */ | |
105 | #define AD7192_CH_AIN1 4 /* AIN1 - AINCOM */ | |
106 | #define AD7192_CH_AIN2 5 /* AIN2 - AINCOM */ | |
107 | #define AD7192_CH_AIN3 6 /* AIN3 - AINCOM */ | |
108 | #define AD7192_CH_AIN4 7 /* AIN4 - AINCOM */ | |
109 | ||
110 | /* ID Register Bit Designations (AD7192_REG_ID) */ | |
111 | #define ID_AD7190 0x4 | |
112 | #define ID_AD7192 0x0 | |
113 | #define ID_AD7195 0x6 | |
114 | #define AD7192_ID_MASK 0x0F | |
115 | ||
116 | /* GPOCON Register Bit Designations (AD7192_REG_GPOCON) */ | |
117 | #define AD7192_GPOCON_BPDSW (1 << 6) /* Bridge power-down switch enable */ | |
118 | #define AD7192_GPOCON_GP32EN (1 << 5) /* Digital Output P3 and P2 enable */ | |
119 | #define AD7192_GPOCON_GP10EN (1 << 4) /* Digital Output P1 and P0 enable */ | |
120 | #define AD7192_GPOCON_P3DAT (1 << 3) /* P3 state */ | |
121 | #define AD7192_GPOCON_P2DAT (1 << 2) /* P2 state */ | |
122 | #define AD7192_GPOCON_P1DAT (1 << 1) /* P1 state */ | |
123 | #define AD7192_GPOCON_P0DAT (1 << 0) /* P0 state */ | |
124 | ||
125 | #define AD7192_INT_FREQ_MHz 4915200 | |
126 | ||
127 | /* NOTE: | |
128 | * The AD7190/2/5 features a dual use data out ready DOUT/RDY output. | |
129 | * In order to avoid contentions on the SPI bus, it's therefore necessary | |
130 | * to use spi bus locking. | |
131 | * | |
132 | * The DOUT/RDY output must also be wired to an interrupt capable GPIO. | |
133 | */ | |
134 | ||
135 | struct ad7192_state { | |
136 | struct spi_device *spi; | |
137 | struct iio_trigger *trig; | |
138 | struct regulator *reg; | |
139 | struct ad7192_platform_data *pdata; | |
140 | wait_queue_head_t wq_data_avail; | |
141 | bool done; | |
142 | bool irq_dis; | |
143 | u16 int_vref_mv; | |
144 | u32 mclk; | |
145 | u32 f_order; | |
146 | u32 mode; | |
147 | u32 conf; | |
148 | u32 scale_avail[8][2]; | |
32b5eeca | 149 | long available_scan_masks[9]; |
7a27b042 MH |
150 | u8 gpocon; |
151 | u8 devid; | |
152 | /* | |
153 | * DMA (thus cache coherency maintenance) requires the | |
154 | * transfer buffers to live in their own cache lines. | |
155 | */ | |
156 | u8 data[4] ____cacheline_aligned; | |
157 | }; | |
158 | ||
159 | static int __ad7192_write_reg(struct ad7192_state *st, bool locked, | |
160 | bool cs_change, unsigned char reg, | |
161 | unsigned size, unsigned val) | |
162 | { | |
163 | u8 *data = st->data; | |
164 | struct spi_transfer t = { | |
165 | .tx_buf = data, | |
166 | .len = size + 1, | |
167 | .cs_change = cs_change, | |
168 | }; | |
169 | struct spi_message m; | |
170 | ||
171 | data[0] = AD7192_COMM_WRITE | AD7192_COMM_ADDR(reg); | |
172 | ||
173 | switch (size) { | |
174 | case 3: | |
175 | data[1] = val >> 16; | |
176 | data[2] = val >> 8; | |
177 | data[3] = val; | |
178 | break; | |
179 | case 2: | |
180 | data[1] = val >> 8; | |
181 | data[2] = val; | |
182 | break; | |
183 | case 1: | |
184 | data[1] = val; | |
185 | break; | |
186 | default: | |
187 | return -EINVAL; | |
188 | } | |
189 | ||
190 | spi_message_init(&m); | |
191 | spi_message_add_tail(&t, &m); | |
192 | ||
193 | if (locked) | |
194 | return spi_sync_locked(st->spi, &m); | |
195 | else | |
196 | return spi_sync(st->spi, &m); | |
197 | } | |
198 | ||
199 | static int ad7192_write_reg(struct ad7192_state *st, | |
200 | unsigned reg, unsigned size, unsigned val) | |
201 | { | |
202 | return __ad7192_write_reg(st, false, false, reg, size, val); | |
203 | } | |
204 | ||
205 | static int __ad7192_read_reg(struct ad7192_state *st, bool locked, | |
206 | bool cs_change, unsigned char reg, | |
207 | int *val, unsigned size) | |
208 | { | |
209 | u8 *data = st->data; | |
210 | int ret; | |
211 | struct spi_transfer t[] = { | |
212 | { | |
213 | .tx_buf = data, | |
214 | .len = 1, | |
215 | }, { | |
216 | .rx_buf = data, | |
217 | .len = size, | |
218 | .cs_change = cs_change, | |
219 | }, | |
220 | }; | |
221 | struct spi_message m; | |
222 | ||
223 | data[0] = AD7192_COMM_READ | AD7192_COMM_ADDR(reg); | |
224 | ||
225 | spi_message_init(&m); | |
226 | spi_message_add_tail(&t[0], &m); | |
227 | spi_message_add_tail(&t[1], &m); | |
228 | ||
229 | if (locked) | |
230 | ret = spi_sync_locked(st->spi, &m); | |
231 | else | |
232 | ret = spi_sync(st->spi, &m); | |
233 | ||
234 | if (ret < 0) | |
235 | return ret; | |
236 | ||
237 | switch (size) { | |
238 | case 3: | |
239 | *val = data[0] << 16 | data[1] << 8 | data[2]; | |
240 | break; | |
241 | case 2: | |
242 | *val = data[0] << 8 | data[1]; | |
243 | break; | |
244 | case 1: | |
245 | *val = data[0]; | |
246 | break; | |
247 | default: | |
248 | return -EINVAL; | |
249 | } | |
250 | ||
251 | return 0; | |
252 | } | |
253 | ||
254 | static int ad7192_read_reg(struct ad7192_state *st, | |
255 | unsigned reg, int *val, unsigned size) | |
256 | { | |
257 | return __ad7192_read_reg(st, 0, 0, reg, val, size); | |
258 | } | |
259 | ||
260 | static int ad7192_read(struct ad7192_state *st, unsigned ch, | |
261 | unsigned len, int *val) | |
262 | { | |
263 | int ret; | |
264 | st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | | |
265 | AD7192_CONF_CHAN(1 << ch); | |
266 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | | |
267 | AD7192_MODE_SEL(AD7192_MODE_SINGLE); | |
268 | ||
269 | ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); | |
270 | ||
271 | spi_bus_lock(st->spi->master); | |
272 | st->done = false; | |
273 | ||
274 | ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode); | |
275 | if (ret < 0) | |
276 | goto out; | |
277 | ||
278 | st->irq_dis = false; | |
279 | enable_irq(st->spi->irq); | |
280 | wait_event_interruptible(st->wq_data_avail, st->done); | |
281 | ||
282 | ret = __ad7192_read_reg(st, 1, 0, AD7192_REG_DATA, val, len); | |
283 | out: | |
284 | spi_bus_unlock(st->spi->master); | |
285 | ||
286 | return ret; | |
287 | } | |
288 | ||
289 | static int ad7192_calibrate(struct ad7192_state *st, unsigned mode, unsigned ch) | |
290 | { | |
291 | int ret; | |
292 | ||
293 | st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | | |
294 | AD7192_CONF_CHAN(1 << ch); | |
295 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | AD7192_MODE_SEL(mode); | |
296 | ||
297 | ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); | |
298 | ||
299 | spi_bus_lock(st->spi->master); | |
300 | st->done = false; | |
301 | ||
302 | ret = __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, | |
303 | (st->devid != ID_AD7195) ? | |
304 | st->mode | AD7192_MODE_CLKDIV : | |
305 | st->mode); | |
306 | if (ret < 0) | |
307 | goto out; | |
308 | ||
309 | st->irq_dis = false; | |
310 | enable_irq(st->spi->irq); | |
311 | wait_event_interruptible(st->wq_data_avail, st->done); | |
312 | ||
313 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | | |
314 | AD7192_MODE_SEL(AD7192_MODE_IDLE); | |
315 | ||
316 | ret = __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode); | |
317 | out: | |
318 | spi_bus_unlock(st->spi->master); | |
319 | ||
320 | return ret; | |
321 | } | |
322 | ||
323 | static const u8 ad7192_calib_arr[8][2] = { | |
324 | {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN1}, | |
325 | {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN1}, | |
326 | {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN2}, | |
327 | {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN2}, | |
328 | {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN3}, | |
329 | {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN3}, | |
330 | {AD7192_MODE_CAL_INT_ZERO, AD7192_CH_AIN4}, | |
331 | {AD7192_MODE_CAL_INT_FULL, AD7192_CH_AIN4} | |
332 | }; | |
333 | ||
334 | static int ad7192_calibrate_all(struct ad7192_state *st) | |
335 | { | |
336 | int i, ret; | |
337 | ||
338 | for (i = 0; i < ARRAY_SIZE(ad7192_calib_arr); i++) { | |
339 | ret = ad7192_calibrate(st, ad7192_calib_arr[i][0], | |
340 | ad7192_calib_arr[i][1]); | |
341 | if (ret) | |
342 | goto out; | |
343 | } | |
344 | ||
345 | return 0; | |
346 | out: | |
347 | dev_err(&st->spi->dev, "Calibration failed\n"); | |
348 | return ret; | |
349 | } | |
350 | ||
351 | static int ad7192_setup(struct ad7192_state *st) | |
352 | { | |
353 | struct iio_dev *indio_dev = spi_get_drvdata(st->spi); | |
354 | struct ad7192_platform_data *pdata = st->pdata; | |
355 | unsigned long long scale_uv; | |
356 | int i, ret, id; | |
357 | u8 ones[6]; | |
358 | ||
359 | /* reset the serial interface */ | |
360 | memset(&ones, 0xFF, 6); | |
361 | ret = spi_write(st->spi, &ones, 6); | |
362 | if (ret < 0) | |
363 | goto out; | |
364 | msleep(1); /* Wait for at least 500us */ | |
365 | ||
366 | /* write/read test for device presence */ | |
367 | ret = ad7192_read_reg(st, AD7192_REG_ID, &id, 1); | |
368 | if (ret) | |
369 | goto out; | |
370 | ||
371 | id &= AD7192_ID_MASK; | |
372 | ||
373 | if (id != st->devid) | |
374 | dev_warn(&st->spi->dev, "device ID query failed (0x%X)\n", id); | |
375 | ||
376 | switch (pdata->clock_source_sel) { | |
377 | case AD7192_CLK_EXT_MCLK1_2: | |
378 | case AD7192_CLK_EXT_MCLK2: | |
379 | st->mclk = AD7192_INT_FREQ_MHz; | |
380 | break; | |
381 | case AD7192_CLK_INT: | |
382 | case AD7192_CLK_INT_CO: | |
383 | if (pdata->ext_clk_Hz) | |
384 | st->mclk = pdata->ext_clk_Hz; | |
385 | else | |
386 | st->mclk = AD7192_INT_FREQ_MHz; | |
387 | break; | |
388 | default: | |
389 | ret = -EINVAL; | |
390 | goto out; | |
391 | } | |
392 | ||
393 | st->mode = AD7192_MODE_SEL(AD7192_MODE_IDLE) | | |
394 | AD7192_MODE_CLKSRC(pdata->clock_source_sel) | | |
395 | AD7192_MODE_RATE(480); | |
396 | ||
397 | st->conf = AD7192_CONF_GAIN(0); | |
398 | ||
399 | if (pdata->rej60_en) | |
400 | st->mode |= AD7192_MODE_REJ60; | |
401 | ||
402 | if (pdata->sinc3_en) | |
403 | st->mode |= AD7192_MODE_SINC3; | |
404 | ||
405 | if (pdata->refin2_en && (st->devid != ID_AD7195)) | |
406 | st->conf |= AD7192_CONF_REFSEL; | |
407 | ||
408 | if (pdata->chop_en) { | |
409 | st->conf |= AD7192_CONF_CHOP; | |
410 | if (pdata->sinc3_en) | |
411 | st->f_order = 3; /* SINC 3rd order */ | |
412 | else | |
413 | st->f_order = 4; /* SINC 4th order */ | |
414 | } else { | |
415 | st->f_order = 1; | |
416 | } | |
417 | ||
418 | if (pdata->buf_en) | |
419 | st->conf |= AD7192_CONF_BUF; | |
420 | ||
421 | if (pdata->unipolar_en) | |
422 | st->conf |= AD7192_CONF_UNIPOLAR; | |
423 | ||
424 | if (pdata->burnout_curr_en) | |
425 | st->conf |= AD7192_CONF_BURN; | |
426 | ||
427 | ret = ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode); | |
428 | if (ret) | |
429 | goto out; | |
430 | ||
431 | ret = ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); | |
432 | if (ret) | |
433 | goto out; | |
434 | ||
435 | ret = ad7192_calibrate_all(st); | |
436 | if (ret) | |
437 | goto out; | |
438 | ||
439 | /* Populate available ADC input ranges */ | |
440 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { | |
441 | scale_uv = ((u64)st->int_vref_mv * 100000000) | |
442 | >> (indio_dev->channels[0].scan_type.realbits - | |
443 | ((st->conf & AD7192_CONF_UNIPOLAR) ? 0 : 1)); | |
444 | scale_uv >>= i; | |
445 | ||
446 | st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; | |
447 | st->scale_avail[i][0] = scale_uv; | |
448 | } | |
449 | ||
450 | return 0; | |
451 | out: | |
452 | dev_err(&st->spi->dev, "setup failed\n"); | |
453 | return ret; | |
454 | } | |
455 | ||
7a27b042 MH |
456 | static int ad7192_ring_preenable(struct iio_dev *indio_dev) |
457 | { | |
458 | struct ad7192_state *st = iio_priv(indio_dev); | |
7a27b042 | 459 | unsigned channel; |
2150489f | 460 | int ret; |
7a27b042 | 461 | |
550268ca | 462 | if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) |
7a27b042 MH |
463 | return -EINVAL; |
464 | ||
2150489f JC |
465 | ret = iio_sw_buffer_preenable(indio_dev); |
466 | if (ret < 0) | |
467 | return ret; | |
468 | ||
550268ca JC |
469 | channel = find_first_bit(indio_dev->active_scan_mask, |
470 | indio_dev->masklength); | |
7a27b042 | 471 | |
7a27b042 MH |
472 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | |
473 | AD7192_MODE_SEL(AD7192_MODE_CONT); | |
474 | st->conf = (st->conf & ~AD7192_CONF_CHAN(-1)) | | |
475 | AD7192_CONF_CHAN(1 << indio_dev->channels[channel].address); | |
476 | ||
477 | ad7192_write_reg(st, AD7192_REG_CONF, 3, st->conf); | |
478 | ||
479 | spi_bus_lock(st->spi->master); | |
480 | __ad7192_write_reg(st, 1, 1, AD7192_REG_MODE, 3, st->mode); | |
481 | ||
482 | st->irq_dis = false; | |
483 | enable_irq(st->spi->irq); | |
484 | ||
485 | return 0; | |
486 | } | |
487 | ||
488 | static int ad7192_ring_postdisable(struct iio_dev *indio_dev) | |
489 | { | |
490 | struct ad7192_state *st = iio_priv(indio_dev); | |
491 | ||
492 | st->mode = (st->mode & ~AD7192_MODE_SEL(-1)) | | |
493 | AD7192_MODE_SEL(AD7192_MODE_IDLE); | |
494 | ||
495 | st->done = false; | |
496 | wait_event_interruptible(st->wq_data_avail, st->done); | |
497 | ||
498 | if (!st->irq_dis) | |
499 | disable_irq_nosync(st->spi->irq); | |
500 | ||
501 | __ad7192_write_reg(st, 1, 0, AD7192_REG_MODE, 3, st->mode); | |
502 | ||
503 | return spi_bus_unlock(st->spi->master); | |
504 | } | |
505 | ||
506 | /** | |
507 | * ad7192_trigger_handler() bh of trigger launched polling to ring buffer | |
508 | **/ | |
509 | static irqreturn_t ad7192_trigger_handler(int irq, void *p) | |
510 | { | |
511 | struct iio_poll_func *pf = p; | |
e65bc6ac | 512 | struct iio_dev *indio_dev = pf->indio_dev; |
14555b14 | 513 | struct iio_buffer *ring = indio_dev->buffer; |
7a27b042 MH |
514 | struct ad7192_state *st = iio_priv(indio_dev); |
515 | s64 dat64[2]; | |
516 | s32 *dat32 = (s32 *)dat64; | |
517 | ||
550268ca | 518 | if (!bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength)) |
7a27b042 MH |
519 | __ad7192_read_reg(st, 1, 1, AD7192_REG_DATA, |
520 | dat32, | |
521 | indio_dev->channels[0].scan_type.realbits/8); | |
522 | ||
523 | /* Guaranteed to be aligned with 8 byte boundary */ | |
fd6487f8 | 524 | if (indio_dev->scan_timestamp) |
7a27b042 MH |
525 | dat64[1] = pf->timestamp; |
526 | ||
527 | ring->access->store_to(ring, (u8 *)dat64, pf->timestamp); | |
528 | ||
529 | iio_trigger_notify_done(indio_dev->trig); | |
530 | st->irq_dis = false; | |
531 | enable_irq(st->spi->irq); | |
532 | ||
533 | return IRQ_HANDLED; | |
534 | } | |
535 | ||
14555b14 | 536 | static const struct iio_buffer_setup_ops ad7192_ring_setup_ops = { |
7a27b042 | 537 | .preenable = &ad7192_ring_preenable, |
3b99fb76 JC |
538 | .postenable = &iio_triggered_buffer_postenable, |
539 | .predisable = &iio_triggered_buffer_predisable, | |
7a27b042 MH |
540 | .postdisable = &ad7192_ring_postdisable, |
541 | }; | |
542 | ||
543 | static int ad7192_register_ring_funcs_and_init(struct iio_dev *indio_dev) | |
544 | { | |
545 | int ret; | |
546 | ||
14555b14 JC |
547 | indio_dev->buffer = iio_sw_rb_allocate(indio_dev); |
548 | if (!indio_dev->buffer) { | |
7a27b042 MH |
549 | ret = -ENOMEM; |
550 | goto error_ret; | |
551 | } | |
7a27b042 MH |
552 | indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time, |
553 | &ad7192_trigger_handler, | |
554 | IRQF_ONESHOT, | |
555 | indio_dev, | |
556 | "ad7192_consumer%d", | |
557 | indio_dev->id); | |
558 | if (indio_dev->pollfunc == NULL) { | |
559 | ret = -ENOMEM; | |
560 | goto error_deallocate_sw_rb; | |
561 | } | |
562 | ||
563 | /* Ring buffer functions - here trigger setup related */ | |
1612244f | 564 | indio_dev->setup_ops = &ad7192_ring_setup_ops; |
7a27b042 MH |
565 | |
566 | /* Flag that polled ring buffering is possible */ | |
ec3afa40 | 567 | indio_dev->modes |= INDIO_BUFFER_TRIGGERED; |
7a27b042 MH |
568 | return 0; |
569 | ||
570 | error_deallocate_sw_rb: | |
14555b14 | 571 | iio_sw_rb_free(indio_dev->buffer); |
7a27b042 MH |
572 | error_ret: |
573 | return ret; | |
574 | } | |
575 | ||
576 | static void ad7192_ring_cleanup(struct iio_dev *indio_dev) | |
577 | { | |
7a27b042 | 578 | iio_dealloc_pollfunc(indio_dev->pollfunc); |
14555b14 | 579 | iio_sw_rb_free(indio_dev->buffer); |
7a27b042 MH |
580 | } |
581 | ||
582 | /** | |
583 | * ad7192_data_rdy_trig_poll() the event handler for the data rdy trig | |
584 | **/ | |
585 | static irqreturn_t ad7192_data_rdy_trig_poll(int irq, void *private) | |
586 | { | |
587 | struct ad7192_state *st = iio_priv(private); | |
588 | ||
589 | st->done = true; | |
590 | wake_up_interruptible(&st->wq_data_avail); | |
591 | disable_irq_nosync(irq); | |
592 | st->irq_dis = true; | |
593 | iio_trigger_poll(st->trig, iio_get_time_ns()); | |
594 | ||
595 | return IRQ_HANDLED; | |
596 | } | |
597 | ||
8324e860 JC |
598 | static struct iio_trigger_ops ad7192_trigger_ops = { |
599 | .owner = THIS_MODULE, | |
600 | }; | |
601 | ||
7a27b042 MH |
602 | static int ad7192_probe_trigger(struct iio_dev *indio_dev) |
603 | { | |
604 | struct ad7192_state *st = iio_priv(indio_dev); | |
605 | int ret; | |
606 | ||
607 | st->trig = iio_allocate_trigger("%s-dev%d", | |
608 | spi_get_device_id(st->spi)->name, | |
609 | indio_dev->id); | |
610 | if (st->trig == NULL) { | |
611 | ret = -ENOMEM; | |
612 | goto error_ret; | |
613 | } | |
8324e860 | 614 | st->trig->ops = &ad7192_trigger_ops; |
7a27b042 MH |
615 | ret = request_irq(st->spi->irq, |
616 | ad7192_data_rdy_trig_poll, | |
617 | IRQF_TRIGGER_LOW, | |
618 | spi_get_device_id(st->spi)->name, | |
619 | indio_dev); | |
620 | if (ret) | |
621 | goto error_free_trig; | |
622 | ||
623 | disable_irq_nosync(st->spi->irq); | |
624 | st->irq_dis = true; | |
625 | st->trig->dev.parent = &st->spi->dev; | |
7a27b042 MH |
626 | st->trig->private_data = indio_dev; |
627 | ||
628 | ret = iio_trigger_register(st->trig); | |
629 | ||
630 | /* select default trigger */ | |
631 | indio_dev->trig = st->trig; | |
632 | if (ret) | |
633 | goto error_free_irq; | |
634 | ||
635 | return 0; | |
636 | ||
637 | error_free_irq: | |
638 | free_irq(st->spi->irq, indio_dev); | |
639 | error_free_trig: | |
640 | iio_free_trigger(st->trig); | |
641 | error_ret: | |
642 | return ret; | |
643 | } | |
644 | ||
645 | static void ad7192_remove_trigger(struct iio_dev *indio_dev) | |
646 | { | |
647 | struct ad7192_state *st = iio_priv(indio_dev); | |
648 | ||
649 | iio_trigger_unregister(st->trig); | |
650 | free_irq(st->spi->irq, indio_dev); | |
651 | iio_free_trigger(st->trig); | |
652 | } | |
653 | ||
654 | static ssize_t ad7192_read_frequency(struct device *dev, | |
655 | struct device_attribute *attr, | |
656 | char *buf) | |
657 | { | |
658 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
659 | struct ad7192_state *st = iio_priv(indio_dev); | |
660 | ||
661 | return sprintf(buf, "%d\n", st->mclk / | |
662 | (st->f_order * 1024 * AD7192_MODE_RATE(st->mode))); | |
663 | } | |
664 | ||
665 | static ssize_t ad7192_write_frequency(struct device *dev, | |
666 | struct device_attribute *attr, | |
667 | const char *buf, | |
668 | size_t len) | |
669 | { | |
670 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
671 | struct ad7192_state *st = iio_priv(indio_dev); | |
672 | unsigned long lval; | |
673 | int div, ret; | |
674 | ||
675 | ret = strict_strtoul(buf, 10, &lval); | |
676 | if (ret) | |
677 | return ret; | |
678 | ||
679 | mutex_lock(&indio_dev->mlock); | |
14555b14 | 680 | if (iio_buffer_enabled(indio_dev)) { |
7a27b042 MH |
681 | mutex_unlock(&indio_dev->mlock); |
682 | return -EBUSY; | |
683 | } | |
684 | ||
685 | div = st->mclk / (lval * st->f_order * 1024); | |
686 | if (div < 1 || div > 1023) { | |
687 | ret = -EINVAL; | |
688 | goto out; | |
689 | } | |
690 | ||
691 | st->mode &= ~AD7192_MODE_RATE(-1); | |
692 | st->mode |= AD7192_MODE_RATE(div); | |
693 | ad7192_write_reg(st, AD7192_REG_MODE, 3, st->mode); | |
694 | ||
695 | out: | |
696 | mutex_unlock(&indio_dev->mlock); | |
697 | ||
698 | return ret ? ret : len; | |
699 | } | |
700 | ||
701 | static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO, | |
702 | ad7192_read_frequency, | |
703 | ad7192_write_frequency); | |
704 | ||
705 | ||
706 | static ssize_t ad7192_show_scale_available(struct device *dev, | |
707 | struct device_attribute *attr, char *buf) | |
708 | { | |
709 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
710 | struct ad7192_state *st = iio_priv(indio_dev); | |
711 | int i, len = 0; | |
712 | ||
713 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) | |
714 | len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0], | |
715 | st->scale_avail[i][1]); | |
716 | ||
717 | len += sprintf(buf + len, "\n"); | |
718 | ||
719 | return len; | |
720 | } | |
721 | ||
322c9563 JC |
722 | static IIO_DEVICE_ATTR_NAMED(in_v_m_v_scale_available, |
723 | in_voltage-voltage_scale_available, | |
7a27b042 MH |
724 | S_IRUGO, ad7192_show_scale_available, NULL, 0); |
725 | ||
322c9563 | 726 | static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO, |
7a27b042 MH |
727 | ad7192_show_scale_available, NULL, 0); |
728 | ||
729 | static ssize_t ad7192_show_ac_excitation(struct device *dev, | |
730 | struct device_attribute *attr, | |
731 | char *buf) | |
732 | { | |
733 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
734 | struct ad7192_state *st = iio_priv(indio_dev); | |
735 | ||
736 | return sprintf(buf, "%d\n", !!(st->mode & AD7192_MODE_ACX)); | |
737 | } | |
738 | ||
739 | static ssize_t ad7192_show_bridge_switch(struct device *dev, | |
740 | struct device_attribute *attr, | |
741 | char *buf) | |
742 | { | |
743 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
744 | struct ad7192_state *st = iio_priv(indio_dev); | |
745 | ||
746 | return sprintf(buf, "%d\n", !!(st->gpocon & AD7192_GPOCON_BPDSW)); | |
747 | } | |
748 | ||
749 | static ssize_t ad7192_set(struct device *dev, | |
750 | struct device_attribute *attr, | |
751 | const char *buf, | |
752 | size_t len) | |
753 | { | |
754 | struct iio_dev *indio_dev = dev_get_drvdata(dev); | |
755 | struct ad7192_state *st = iio_priv(indio_dev); | |
756 | struct iio_dev_attr *this_attr = to_iio_dev_attr(attr); | |
757 | int ret; | |
758 | bool val; | |
759 | ||
760 | ret = strtobool(buf, &val); | |
761 | if (ret < 0) | |
762 | return ret; | |
763 | ||
764 | mutex_lock(&indio_dev->mlock); | |
14555b14 | 765 | if (iio_buffer_enabled(indio_dev)) { |
7a27b042 MH |
766 | mutex_unlock(&indio_dev->mlock); |
767 | return -EBUSY; | |
768 | } | |
769 | ||
e15fbc91 | 770 | switch ((u32) this_attr->address) { |
7a27b042 MH |
771 | case AD7192_REG_GPOCON: |
772 | if (val) | |
773 | st->gpocon |= AD7192_GPOCON_BPDSW; | |
774 | else | |
775 | st->gpocon &= ~AD7192_GPOCON_BPDSW; | |
776 | ||
777 | ad7192_write_reg(st, AD7192_REG_GPOCON, 1, st->gpocon); | |
778 | break; | |
779 | case AD7192_REG_MODE: | |
780 | if (val) | |
781 | st->mode |= AD7192_MODE_ACX; | |
782 | else | |
783 | st->mode &= ~AD7192_MODE_ACX; | |
784 | ||
785 | ad7192_write_reg(st, AD7192_REG_GPOCON, 3, st->mode); | |
786 | break; | |
787 | default: | |
788 | ret = -EINVAL; | |
789 | } | |
790 | ||
791 | mutex_unlock(&indio_dev->mlock); | |
792 | ||
793 | return ret ? ret : len; | |
794 | } | |
795 | ||
796 | static IIO_DEVICE_ATTR(bridge_switch_en, S_IRUGO | S_IWUSR, | |
797 | ad7192_show_bridge_switch, ad7192_set, | |
798 | AD7192_REG_GPOCON); | |
799 | ||
800 | static IIO_DEVICE_ATTR(ac_excitation_en, S_IRUGO | S_IWUSR, | |
801 | ad7192_show_ac_excitation, ad7192_set, | |
802 | AD7192_REG_MODE); | |
803 | ||
804 | static struct attribute *ad7192_attributes[] = { | |
805 | &iio_dev_attr_sampling_frequency.dev_attr.attr, | |
322c9563 JC |
806 | &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr, |
807 | &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, | |
7a27b042 MH |
808 | &iio_dev_attr_bridge_switch_en.dev_attr.attr, |
809 | &iio_dev_attr_ac_excitation_en.dev_attr.attr, | |
810 | NULL | |
811 | }; | |
812 | ||
7a27b042 MH |
813 | static const struct attribute_group ad7192_attribute_group = { |
814 | .attrs = ad7192_attributes, | |
15bbb779 JC |
815 | }; |
816 | ||
817 | static struct attribute *ad7195_attributes[] = { | |
818 | &iio_dev_attr_sampling_frequency.dev_attr.attr, | |
819 | &iio_dev_attr_in_v_m_v_scale_available.dev_attr.attr, | |
820 | &iio_dev_attr_in_voltage_scale_available.dev_attr.attr, | |
821 | &iio_dev_attr_bridge_switch_en.dev_attr.attr, | |
822 | NULL | |
823 | }; | |
824 | ||
825 | static const struct attribute_group ad7195_attribute_group = { | |
826 | .attrs = ad7195_attributes, | |
7a27b042 MH |
827 | }; |
828 | ||
829 | static int ad7192_read_raw(struct iio_dev *indio_dev, | |
830 | struct iio_chan_spec const *chan, | |
831 | int *val, | |
832 | int *val2, | |
833 | long m) | |
834 | { | |
835 | struct ad7192_state *st = iio_priv(indio_dev); | |
836 | int ret, smpl = 0; | |
837 | bool unipolar = !!(st->conf & AD7192_CONF_UNIPOLAR); | |
838 | ||
839 | switch (m) { | |
b11f98ff | 840 | case IIO_CHAN_INFO_RAW: |
7a27b042 | 841 | mutex_lock(&indio_dev->mlock); |
14555b14 | 842 | if (iio_buffer_enabled(indio_dev)) |
e0f0ddad | 843 | ret = -EBUSY; |
7a27b042 MH |
844 | else |
845 | ret = ad7192_read(st, chan->address, | |
846 | chan->scan_type.realbits / 8, &smpl); | |
847 | mutex_unlock(&indio_dev->mlock); | |
848 | ||
849 | if (ret < 0) | |
850 | return ret; | |
851 | ||
852 | *val = (smpl >> chan->scan_type.shift) & | |
853 | ((1 << (chan->scan_type.realbits)) - 1); | |
854 | ||
855 | switch (chan->type) { | |
ade7ef7b | 856 | case IIO_VOLTAGE: |
7a27b042 MH |
857 | if (!unipolar) |
858 | *val -= (1 << (chan->scan_type.realbits - 1)); | |
859 | break; | |
860 | case IIO_TEMP: | |
861 | *val -= 0x800000; | |
862 | *val /= 2815; /* temp Kelvin */ | |
863 | *val -= 273; /* temp Celsius */ | |
864 | break; | |
865 | default: | |
866 | return -EINVAL; | |
867 | } | |
868 | return IIO_VAL_INT; | |
869 | ||
c8a9f805 JC |
870 | case IIO_CHAN_INFO_SCALE: |
871 | switch (chan->type) { | |
872 | case IIO_VOLTAGE: | |
873 | mutex_lock(&indio_dev->mlock); | |
874 | *val = st->scale_avail[AD7192_CONF_GAIN(st->conf)][0]; | |
875 | *val2 = st->scale_avail[AD7192_CONF_GAIN(st->conf)][1]; | |
876 | mutex_unlock(&indio_dev->mlock); | |
877 | return IIO_VAL_INT_PLUS_NANO; | |
878 | case IIO_TEMP: | |
879 | *val = 1000; | |
880 | return IIO_VAL_INT; | |
881 | default: | |
882 | return -EINVAL; | |
883 | } | |
7a27b042 MH |
884 | } |
885 | ||
886 | return -EINVAL; | |
887 | } | |
888 | ||
889 | static int ad7192_write_raw(struct iio_dev *indio_dev, | |
890 | struct iio_chan_spec const *chan, | |
891 | int val, | |
892 | int val2, | |
893 | long mask) | |
894 | { | |
895 | struct ad7192_state *st = iio_priv(indio_dev); | |
896 | int ret, i; | |
897 | unsigned int tmp; | |
898 | ||
899 | mutex_lock(&indio_dev->mlock); | |
14555b14 | 900 | if (iio_buffer_enabled(indio_dev)) { |
7a27b042 MH |
901 | mutex_unlock(&indio_dev->mlock); |
902 | return -EBUSY; | |
903 | } | |
904 | ||
905 | switch (mask) { | |
c8a9f805 | 906 | case IIO_CHAN_INFO_SCALE: |
7a27b042 MH |
907 | ret = -EINVAL; |
908 | for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) | |
909 | if (val2 == st->scale_avail[i][1]) { | |
910 | tmp = st->conf; | |
911 | st->conf &= ~AD7192_CONF_GAIN(-1); | |
912 | st->conf |= AD7192_CONF_GAIN(i); | |
913 | ||
914 | if (tmp != st->conf) { | |
915 | ad7192_write_reg(st, AD7192_REG_CONF, | |
916 | 3, st->conf); | |
917 | ad7192_calibrate_all(st); | |
918 | } | |
919 | ret = 0; | |
920 | } | |
921 | ||
922 | default: | |
923 | ret = -EINVAL; | |
924 | } | |
925 | ||
926 | mutex_unlock(&indio_dev->mlock); | |
927 | ||
928 | return ret; | |
929 | } | |
930 | ||
931 | static int ad7192_validate_trigger(struct iio_dev *indio_dev, | |
932 | struct iio_trigger *trig) | |
933 | { | |
934 | if (indio_dev->trig != trig) | |
935 | return -EINVAL; | |
936 | ||
937 | return 0; | |
938 | } | |
939 | ||
940 | static int ad7192_write_raw_get_fmt(struct iio_dev *indio_dev, | |
941 | struct iio_chan_spec const *chan, | |
942 | long mask) | |
943 | { | |
944 | return IIO_VAL_INT_PLUS_NANO; | |
945 | } | |
946 | ||
947 | static const struct iio_info ad7192_info = { | |
948 | .read_raw = &ad7192_read_raw, | |
949 | .write_raw = &ad7192_write_raw, | |
950 | .write_raw_get_fmt = &ad7192_write_raw_get_fmt, | |
951 | .attrs = &ad7192_attribute_group, | |
952 | .validate_trigger = ad7192_validate_trigger, | |
953 | .driver_module = THIS_MODULE, | |
954 | }; | |
955 | ||
15bbb779 JC |
956 | static const struct iio_info ad7195_info = { |
957 | .read_raw = &ad7192_read_raw, | |
958 | .write_raw = &ad7192_write_raw, | |
959 | .write_raw_get_fmt = &ad7192_write_raw_get_fmt, | |
960 | .attrs = &ad7195_attribute_group, | |
961 | .validate_trigger = ad7192_validate_trigger, | |
962 | .driver_module = THIS_MODULE, | |
963 | }; | |
964 | ||
7a27b042 | 965 | #define AD7192_CHAN_DIFF(_chan, _chan2, _name, _address, _si) \ |
ade7ef7b JC |
966 | { .type = IIO_VOLTAGE, \ |
967 | .differential = 1, \ | |
7a27b042 MH |
968 | .indexed = 1, \ |
969 | .extend_name = _name, \ | |
970 | .channel = _chan, \ | |
971 | .channel2 = _chan2, \ | |
b11f98ff JC |
972 | .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \ |
973 | IIO_CHAN_INFO_SCALE_SHARED_BIT, \ | |
7a27b042 MH |
974 | .address = _address, \ |
975 | .scan_index = _si, \ | |
976 | .scan_type = IIO_ST('s', 24, 32, 0)} | |
977 | ||
978 | #define AD7192_CHAN(_chan, _address, _si) \ | |
ade7ef7b | 979 | { .type = IIO_VOLTAGE, \ |
7a27b042 MH |
980 | .indexed = 1, \ |
981 | .channel = _chan, \ | |
b11f98ff JC |
982 | .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \ |
983 | IIO_CHAN_INFO_SCALE_SHARED_BIT, \ | |
7a27b042 MH |
984 | .address = _address, \ |
985 | .scan_index = _si, \ | |
986 | .scan_type = IIO_ST('s', 24, 32, 0)} | |
987 | ||
988 | #define AD7192_CHAN_TEMP(_chan, _address, _si) \ | |
989 | { .type = IIO_TEMP, \ | |
990 | .indexed = 1, \ | |
991 | .channel = _chan, \ | |
b11f98ff JC |
992 | .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT | \ |
993 | IIO_CHAN_INFO_SCALE_SEPARATE_BIT, \ | |
7a27b042 MH |
994 | .address = _address, \ |
995 | .scan_index = _si, \ | |
996 | .scan_type = IIO_ST('s', 24, 32, 0)} | |
997 | ||
998 | static struct iio_chan_spec ad7192_channels[] = { | |
999 | AD7192_CHAN_DIFF(1, 2, NULL, AD7192_CH_AIN1P_AIN2M, 0), | |
1000 | AD7192_CHAN_DIFF(3, 4, NULL, AD7192_CH_AIN3P_AIN4M, 1), | |
1001 | AD7192_CHAN_TEMP(0, AD7192_CH_TEMP, 2), | |
1002 | AD7192_CHAN_DIFF(2, 2, "shorted", AD7192_CH_AIN2P_AIN2M, 3), | |
1003 | AD7192_CHAN(1, AD7192_CH_AIN1, 4), | |
1004 | AD7192_CHAN(2, AD7192_CH_AIN2, 5), | |
1005 | AD7192_CHAN(3, AD7192_CH_AIN3, 6), | |
1006 | AD7192_CHAN(4, AD7192_CH_AIN4, 7), | |
1007 | IIO_CHAN_SOFT_TIMESTAMP(8), | |
1008 | }; | |
1009 | ||
1010 | static int __devinit ad7192_probe(struct spi_device *spi) | |
1011 | { | |
1012 | struct ad7192_platform_data *pdata = spi->dev.platform_data; | |
1013 | struct ad7192_state *st; | |
1014 | struct iio_dev *indio_dev; | |
d2fffd6c | 1015 | int ret, i , voltage_uv = 0; |
7a27b042 MH |
1016 | |
1017 | if (!pdata) { | |
1018 | dev_err(&spi->dev, "no platform data?\n"); | |
1019 | return -ENODEV; | |
1020 | } | |
1021 | ||
1022 | if (!spi->irq) { | |
1023 | dev_err(&spi->dev, "no IRQ?\n"); | |
1024 | return -ENODEV; | |
1025 | } | |
1026 | ||
1027 | indio_dev = iio_allocate_device(sizeof(*st)); | |
1028 | if (indio_dev == NULL) | |
1029 | return -ENOMEM; | |
1030 | ||
1031 | st = iio_priv(indio_dev); | |
1032 | ||
1033 | st->reg = regulator_get(&spi->dev, "vcc"); | |
1034 | if (!IS_ERR(st->reg)) { | |
1035 | ret = regulator_enable(st->reg); | |
1036 | if (ret) | |
1037 | goto error_put_reg; | |
1038 | ||
1039 | voltage_uv = regulator_get_voltage(st->reg); | |
1040 | } | |
1041 | ||
1042 | st->pdata = pdata; | |
1043 | ||
1044 | if (pdata && pdata->vref_mv) | |
1045 | st->int_vref_mv = pdata->vref_mv; | |
1046 | else if (voltage_uv) | |
1047 | st->int_vref_mv = voltage_uv / 1000; | |
1048 | else | |
1049 | dev_warn(&spi->dev, "reference voltage undefined\n"); | |
1050 | ||
1051 | spi_set_drvdata(spi, indio_dev); | |
1052 | st->spi = spi; | |
1053 | st->devid = spi_get_device_id(spi)->driver_data; | |
1054 | indio_dev->dev.parent = &spi->dev; | |
1055 | indio_dev->name = spi_get_device_id(spi)->name; | |
1056 | indio_dev->modes = INDIO_DIRECT_MODE; | |
1057 | indio_dev->channels = ad7192_channels; | |
1058 | indio_dev->num_channels = ARRAY_SIZE(ad7192_channels); | |
1059 | indio_dev->available_scan_masks = st->available_scan_masks; | |
15bbb779 JC |
1060 | if (st->devid == ID_AD7195) |
1061 | indio_dev->info = &ad7195_info; | |
1062 | else | |
1063 | indio_dev->info = &ad7192_info; | |
7a27b042 MH |
1064 | |
1065 | for (i = 0; i < indio_dev->num_channels; i++) | |
1066 | st->available_scan_masks[i] = (1 << i) | (1 << | |
1067 | indio_dev->channels[indio_dev->num_channels - 1]. | |
1068 | scan_index); | |
1069 | ||
1070 | init_waitqueue_head(&st->wq_data_avail); | |
1071 | ||
1072 | ret = ad7192_register_ring_funcs_and_init(indio_dev); | |
1073 | if (ret) | |
1074 | goto error_disable_reg; | |
1075 | ||
7a27b042 MH |
1076 | ret = ad7192_probe_trigger(indio_dev); |
1077 | if (ret) | |
d2fffd6c | 1078 | goto error_ring_cleanup; |
7a27b042 | 1079 | |
14555b14 JC |
1080 | ret = iio_buffer_register(indio_dev, |
1081 | indio_dev->channels, | |
1082 | indio_dev->num_channels); | |
7a27b042 MH |
1083 | if (ret) |
1084 | goto error_remove_trigger; | |
1085 | ||
1086 | ret = ad7192_setup(st); | |
1087 | if (ret) | |
d2fffd6c | 1088 | goto error_unreg_ring; |
7a27b042 | 1089 | |
d2fffd6c JC |
1090 | ret = iio_device_register(indio_dev); |
1091 | if (ret < 0) | |
1092 | goto error_unreg_ring; | |
7a27b042 MH |
1093 | return 0; |
1094 | ||
d2fffd6c | 1095 | error_unreg_ring: |
14555b14 | 1096 | iio_buffer_unregister(indio_dev); |
7a27b042 MH |
1097 | error_remove_trigger: |
1098 | ad7192_remove_trigger(indio_dev); | |
d2fffd6c | 1099 | error_ring_cleanup: |
7a27b042 MH |
1100 | ad7192_ring_cleanup(indio_dev); |
1101 | error_disable_reg: | |
1102 | if (!IS_ERR(st->reg)) | |
1103 | regulator_disable(st->reg); | |
1104 | error_put_reg: | |
1105 | if (!IS_ERR(st->reg)) | |
1106 | regulator_put(st->reg); | |
1107 | ||
d2fffd6c | 1108 | iio_free_device(indio_dev); |
7a27b042 MH |
1109 | |
1110 | return ret; | |
1111 | } | |
1112 | ||
1113 | static int ad7192_remove(struct spi_device *spi) | |
1114 | { | |
1115 | struct iio_dev *indio_dev = spi_get_drvdata(spi); | |
1116 | struct ad7192_state *st = iio_priv(indio_dev); | |
1117 | ||
d2fffd6c | 1118 | iio_device_unregister(indio_dev); |
14555b14 | 1119 | iio_buffer_unregister(indio_dev); |
7a27b042 MH |
1120 | ad7192_remove_trigger(indio_dev); |
1121 | ad7192_ring_cleanup(indio_dev); | |
1122 | ||
1123 | if (!IS_ERR(st->reg)) { | |
1124 | regulator_disable(st->reg); | |
1125 | regulator_put(st->reg); | |
1126 | } | |
1127 | ||
7a27b042 MH |
1128 | return 0; |
1129 | } | |
1130 | ||
1131 | static const struct spi_device_id ad7192_id[] = { | |
1132 | {"ad7190", ID_AD7190}, | |
1133 | {"ad7192", ID_AD7192}, | |
1134 | {"ad7195", ID_AD7195}, | |
1135 | {} | |
1136 | }; | |
55e4390c | 1137 | MODULE_DEVICE_TABLE(spi, ad7192_id); |
7a27b042 MH |
1138 | |
1139 | static struct spi_driver ad7192_driver = { | |
1140 | .driver = { | |
1141 | .name = "ad7192", | |
1142 | .owner = THIS_MODULE, | |
1143 | }, | |
1144 | .probe = ad7192_probe, | |
1145 | .remove = __devexit_p(ad7192_remove), | |
1146 | .id_table = ad7192_id, | |
1147 | }; | |
ae6ae6fe | 1148 | module_spi_driver(ad7192_driver); |
7a27b042 MH |
1149 | |
1150 | MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>"); | |
1151 | MODULE_DESCRIPTION("Analog Devices AD7190, AD7192, AD7195 ADC"); | |
1152 | MODULE_LICENSE("GPL v2"); |