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staging/iio: Use correct argument for sizeof
[deliverable/linux.git] / drivers / staging / iio / adc / mxs-lradc.c
CommitLineData
bc2c90c9
MV		 1/*
2 * Freescale i.MX28 LRADC driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Marek Vasut <marex@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/interrupt.h>
19#include <linux/device.h>
20#include <linux/kernel.h>
21#include <linux/slab.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/sysfs.h>
25#include <linux/list.h>
26#include <linux/io.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/spinlock.h>
30#include <linux/wait.h>
31#include <linux/sched.h>
32#include <linux/stmp_device.h>
33#include <linux/bitops.h>
34#include <linux/completion.h>
06ddd353
MV		 35#include <linux/delay.h>
36#include <linux/input.h>
bc2c90c9
MV		 37
38#include <mach/mxs.h>
39#include <mach/common.h>
40
41#include <linux/iio/iio.h>
42#include <linux/iio/buffer.h>
43#include <linux/iio/trigger.h>
44#include <linux/iio/trigger_consumer.h>
45#include <linux/iio/triggered_buffer.h>
46
47#define DRIVER_NAME "mxs-lradc"
48
49#define LRADC_MAX_DELAY_CHANS 4
50#define LRADC_MAX_MAPPED_CHANS 8
51#define LRADC_MAX_TOTAL_CHANS 16
52
53#define LRADC_DELAY_TIMER_HZ 2000
54
55/*
56 * Make this runtime configurable if necessary. Currently, if the buffered mode
57 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
58 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
59 * seconds. The result is that the samples arrive every 500mS.
60 */
61#define LRADC_DELAY_TIMER_PER 200
62#define LRADC_DELAY_TIMER_LOOP 5
63
06ddd353
MV		 64/*
65 * Once the pen touches the touchscreen, the touchscreen switches from
66 * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
67 * is realized by worker thread, which is called every 20 or so milliseconds.
68 * This gives the touchscreen enough fluence and does not strain the system
69 * too much.
70 */
71#define LRADC_TS_SAMPLE_DELAY_MS 5
72
73/*
74 * The LRADC reads the following amount of samples from each touchscreen
75 * channel and the driver then computes avarage of these.
76 */
77#define LRADC_TS_SAMPLE_AMOUNT 4
78
bc2c90c9
MV		 79static const char * const mxs_lradc_irq_name[] = {
80 "mxs-lradc-touchscreen",
81 "mxs-lradc-thresh0",
82 "mxs-lradc-thresh1",
83 "mxs-lradc-channel0",
84 "mxs-lradc-channel1",
85 "mxs-lradc-channel2",
86 "mxs-lradc-channel3",
87 "mxs-lradc-channel4",
88 "mxs-lradc-channel5",
89 "mxs-lradc-channel6",
90 "mxs-lradc-channel7",
91 "mxs-lradc-button0",
92 "mxs-lradc-button1",
93};
94
06ddd353
MV		 95enum mxs_lradc_ts {
96 MXS_LRADC_TOUCHSCREEN_NONE = 0,
97 MXS_LRADC_TOUCHSCREEN_4WIRE,
98 MXS_LRADC_TOUCHSCREEN_5WIRE,
99};
100
bc2c90c9
MV		 101struct mxs_lradc {
102 struct device *dev;
103 void __iomem *base;
104 int irq[13];
105
106 uint32_t *buffer;
107 struct iio_trigger *trig;
108
109 struct mutex lock;
110
bc2c90c9 111 struct completion completion;
06ddd353
MV		 112
113 /*
114 * Touchscreen LRADC channels receives a private slot in the CTRL4
115 * register, the slot #7. Therefore only 7 slots instead of 8 in the
116 * CTRL4 register can be mapped to LRADC channels when using the
117 * touchscreen.
118 *
119 * Furthermore, certain LRADC channels are shared between touchscreen
120 * and/or touch-buttons and generic LRADC block. Therefore when using
121 * either of these, these channels are not available for the regular
122 * sampling. The shared channels are as follows:
123 *
124 * CH0 -- Touch button #0
125 * CH1 -- Touch button #1
126 * CH2 -- Touch screen XPUL
127 * CH3 -- Touch screen YPLL
128 * CH4 -- Touch screen XNUL
129 * CH5 -- Touch screen YNLR
130 * CH6 -- Touch screen WIPER (5-wire only)
131 *
132 * The bitfields below represents which parts of the LRADC block are
133 * switched into special mode of operation. These channels can not
134 * be sampled as regular LRADC channels. The driver will refuse any
135 * attempt to sample these channels.
136 */
137#define CHAN_MASK_TOUCHBUTTON (0x3 << 0)
138#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
139#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
140 enum mxs_lradc_ts use_touchscreen;
141 bool stop_touchscreen;
142 bool use_touchbutton;
143
144 struct input_dev *ts_input;
145 struct work_struct ts_work;
bc2c90c9
MV		 146};
147
148#define LRADC_CTRL0 0x00
06ddd353
MV		 149#define LRADC_CTRL0_TOUCH_DETECT_ENABLE (1 << 23)
150#define LRADC_CTRL0_TOUCH_SCREEN_TYPE (1 << 22)
151#define LRADC_CTRL0_YNNSW /* YM */ (1 << 21)
152#define LRADC_CTRL0_YPNSW /* YP */ (1 << 20)
153#define LRADC_CTRL0_YPPSW /* YP */ (1 << 19)
154#define LRADC_CTRL0_XNNSW /* XM */ (1 << 18)
155#define LRADC_CTRL0_XNPSW /* XM */ (1 << 17)
156#define LRADC_CTRL0_XPPSW /* XP */ (1 << 16)
157#define LRADC_CTRL0_PLATE_MASK (0x3f << 16)
bc2c90c9
MV		 158
159#define LRADC_CTRL1 0x10
06ddd353 160#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24)
bc2c90c9
MV		 161#define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
162#define LRADC_CTRL1_LRADC_IRQ_EN_MASK (0x1fff << 16)
06ddd353
MV		 163#define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
164#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8)
165#define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
166#define LRADC_CTRL1_LRADC_IRQ_MASK 0x1fff
167#define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
bc2c90c9
MV		 168
169#define LRADC_CTRL2 0x20
170#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
171
06ddd353
MV		 172#define LRADC_STATUS 0x40
173#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0)
174
bc2c90c9
MV		 175#define LRADC_CH(n) (0x50 + (0x10 * (n)))
176#define LRADC_CH_ACCUMULATE (1 << 29)
177#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
178#define LRADC_CH_NUM_SAMPLES_OFFSET 24
179#define LRADC_CH_VALUE_MASK 0x3ffff
180#define LRADC_CH_VALUE_OFFSET 0
181
182#define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
183#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
184#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
185#define LRADC_DELAY_KICK (1 << 20)
186#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
187#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
188#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
189#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
190#define LRADC_DELAY_DELAY_MASK 0x7ff
191#define LRADC_DELAY_DELAY_OFFSET 0
192
193#define LRADC_CTRL4 0x140
194#define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
195#define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
196
197/*
198 * Raw I/O operations
199 */
200static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
201 const struct iio_chan_spec *chan,
202 int *val, int *val2, long m)
203{
204 struct mxs_lradc *lradc = iio_priv(iio_dev);
205 int ret;
06ddd353 206 unsigned long mask;
bc2c90c9
MV		 207
208 if (m != IIO_CHAN_INFO_RAW)
209 return -EINVAL;
210
211 /* Check for invalid channel */
212 if (chan->channel > LRADC_MAX_TOTAL_CHANS)
213 return -EINVAL;
214
06ddd353
MV		 215 /* Validate the channel if it doesn't intersect with reserved chans. */
216 bitmap_set(&mask, chan->channel, 1);
217 ret = iio_validate_scan_mask_onehot(iio_dev, &mask);
218 if (ret)
219 return -EINVAL;
220
bc2c90c9
MV		 221 /*
222 * See if there is no buffered operation in progess. If there is, simply
223 * bail out. This can be improved to support both buffered and raw IO at
224 * the same time, yet the code becomes horribly complicated. Therefore I
225 * applied KISS principle here.
226 */
227 ret = mutex_trylock(&lradc->lock);
228 if (!ret)
229 return -EBUSY;
230
231 INIT_COMPLETION(lradc->completion);
232
233 /*
234 * No buffered operation in progress, map the channel and trigger it.
235 * Virtual channel 0 is always used here as the others are always not
236 * used if doing raw sampling.
237 */
238 writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
239 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
240 writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
241
06ddd353
MV		 242 /* Clean the slot's previous content, then set new one. */
243 writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
244 lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
245 writel(chan->channel, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
246
bc2c90c9
MV		 247 writel(0, lradc->base + LRADC_CH(0));
248
249 /* Enable the IRQ and start sampling the channel. */
250 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
251 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
252 writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
253
254 /* Wait for completion on the channel, 1 second max. */
255 ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
256 if (!ret)
257 ret = -ETIMEDOUT;
258 if (ret < 0)
259 goto err;
260
261 /* Read the data. */
262 *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
263 ret = IIO_VAL_INT;
264
265err:
266 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
267 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
268
269 mutex_unlock(&lradc->lock);
270
271 return ret;
272}
273
274static const struct iio_info mxs_lradc_iio_info = {
275 .driver_module = THIS_MODULE,
276 .read_raw = mxs_lradc_read_raw,
277};
278
06ddd353
MV		 279/*
280 * Touchscreen handling
281 */
282enum lradc_ts_plate {
283 LRADC_SAMPLE_X,
284 LRADC_SAMPLE_Y,
285 LRADC_SAMPLE_PRESSURE,
286};
287
288static int mxs_lradc_ts_touched(struct mxs_lradc *lradc)
289{
290 uint32_t reg;
291
292 /* Enable touch detection. */
293 writel(LRADC_CTRL0_PLATE_MASK,
294 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
295 writel(LRADC_CTRL0_TOUCH_DETECT_ENABLE,
296 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
297
298 msleep(LRADC_TS_SAMPLE_DELAY_MS);
299
300 reg = readl(lradc->base + LRADC_STATUS);
301
302 return reg & LRADC_STATUS_TOUCH_DETECT_RAW;
303}
304
305static int32_t mxs_lradc_ts_sample(struct mxs_lradc *lradc,
306 enum lradc_ts_plate plate, int change)
307{
308 unsigned long delay, jiff;
309 uint32_t reg, ctrl0 = 0, chan = 0;
310 /* The touchscreen always uses CTRL4 slot #7. */
311 const uint8_t slot = 7;
312 uint32_t val;
313
314 /*
315 * There are three correct configurations of the controller sampling
316 * the touchscreen, each of these configuration provides different
317 * information from the touchscreen.
318 *
319 * The following table describes the sampling configurations:
320 * +-------------+-------+-------+-------+
321 * | Wire \ Axis | X | Y | Z |
322 * +---------------------+-------+-------+
323 * | X+ (CH2) | HI | TS | TS |
324 * +-------------+-------+-------+-------+
325 * | X- (CH4) | LO | SH | HI |
326 * +-------------+-------+-------+-------+
327 * | Y+ (CH3) | SH | HI | HI |
328 * +-------------+-------+-------+-------+
329 * | Y- (CH5) | TS | LO | SH |
330 * +-------------+-------+-------+-------+
331 *
332 * HI ... strong '1' ; LO ... strong '0'
333 * SH ... sample here ; TS ... tri-state
334 *
335 * There are a few other ways of obtaining the Z coordinate
336 * (aka. pressure), but the one in the table seems to be the
337 * most reliable one.
338 */
339 switch (plate) {
340 case LRADC_SAMPLE_X:
341 ctrl0 = LRADC_CTRL0_XPPSW | LRADC_CTRL0_XNNSW;
342 chan = 3;
343 break;
344 case LRADC_SAMPLE_Y:
345 ctrl0 = LRADC_CTRL0_YPPSW | LRADC_CTRL0_YNNSW;
346 chan = 4;
347 break;
348 case LRADC_SAMPLE_PRESSURE:
349 ctrl0 = LRADC_CTRL0_YPPSW | LRADC_CTRL0_XNNSW;
350 chan = 5;
351 break;
352 }
353
354 if (change) {
355 writel(LRADC_CTRL0_PLATE_MASK,
356 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
357 writel(ctrl0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
358
359 writel(LRADC_CTRL4_LRADCSELECT_MASK(slot),
360 lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
361 writel(chan << LRADC_CTRL4_LRADCSELECT_OFFSET(slot),
362 lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
363 }
364
365 writel(0xffffffff, lradc->base + LRADC_CH(slot) + STMP_OFFSET_REG_CLR);
366 writel(1 << slot, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
367
368 delay = jiffies + msecs_to_jiffies(LRADC_TS_SAMPLE_DELAY_MS);
369 do {
370 jiff = jiffies;
371 reg = readl_relaxed(lradc->base + LRADC_CTRL1);
372 if (reg & LRADC_CTRL1_LRADC_IRQ(slot))
373 break;
374 } while (time_before(jiff, delay));
375
376 writel(LRADC_CTRL1_LRADC_IRQ(slot),
377 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
378
379 if (time_after_eq(jiff, delay))
380 return -ETIMEDOUT;
381
382 val = readl(lradc->base + LRADC_CH(slot));
383 val &= LRADC_CH_VALUE_MASK;
384
385 return val;
386}
387
388static int32_t mxs_lradc_ts_sample_filter(struct mxs_lradc *lradc,
389 enum lradc_ts_plate plate)
390{
391 int32_t val, tot = 0;
392 int i;
393
394 val = mxs_lradc_ts_sample(lradc, plate, 1);
395
396 /* Delay a bit so the touchscreen is stable. */
397 mdelay(2);
398
399 for (i = 0; i < LRADC_TS_SAMPLE_AMOUNT; i++) {
400 val = mxs_lradc_ts_sample(lradc, plate, 0);
401 tot += val;
402 }
403
404 return tot / LRADC_TS_SAMPLE_AMOUNT;
405}
406
407static void mxs_lradc_ts_work(struct work_struct *ts_work)
408{
409 struct mxs_lradc *lradc = container_of(ts_work,
410 struct mxs_lradc, ts_work);
411 int val_x, val_y, val_p;
412 bool valid = false;
413
414 while (mxs_lradc_ts_touched(lradc)) {
415 /* Disable touch detector so we can sample the touchscreen. */
416 writel(LRADC_CTRL0_TOUCH_DETECT_ENABLE,
417 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
418
419 if (likely(valid)) {
420 input_report_abs(lradc->ts_input, ABS_X, val_x);
421 input_report_abs(lradc->ts_input, ABS_Y, val_y);
422 input_report_abs(lradc->ts_input, ABS_PRESSURE, val_p);
423 input_report_key(lradc->ts_input, BTN_TOUCH, 1);
424 input_sync(lradc->ts_input);
425 }
426
427 valid = false;
428
429 val_x = mxs_lradc_ts_sample_filter(lradc, LRADC_SAMPLE_X);
430 if (val_x < 0)
431 continue;
432 val_y = mxs_lradc_ts_sample_filter(lradc, LRADC_SAMPLE_Y);
433 if (val_y < 0)
434 continue;
435 val_p = mxs_lradc_ts_sample_filter(lradc, LRADC_SAMPLE_PRESSURE);
436 if (val_p < 0)
437 continue;
438
439 valid = true;
440 }
441
442 input_report_abs(lradc->ts_input, ABS_PRESSURE, 0);
443 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
444 input_sync(lradc->ts_input);
445
446 /* Do not restart the TS IRQ if the driver is shutting down. */
447 if (lradc->stop_touchscreen)
448 return;
449
450 /* Restart the touchscreen interrupts. */
451 writel(LRADC_CTRL1_TOUCH_DETECT_IRQ,
452 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
453 writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
454 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
455}
456
457static int mxs_lradc_ts_open(struct input_dev *dev)
458{
459 struct mxs_lradc *lradc = input_get_drvdata(dev);
460
461 /* The touchscreen is starting. */
462 lradc->stop_touchscreen = false;
463
464 /* Enable the touch-detect circuitry. */
465 writel(LRADC_CTRL0_TOUCH_DETECT_ENABLE,
466 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
467
468 /* Enable the touch-detect IRQ. */
469 writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
470 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
471
472 return 0;
473}
474
475static void mxs_lradc_ts_close(struct input_dev *dev)
476{
477 struct mxs_lradc *lradc = input_get_drvdata(dev);
478
479 /* Indicate the touchscreen is stopping. */
480 lradc->stop_touchscreen = true;
481 mb();
482
483 /* Wait until touchscreen thread finishes any possible remnants. */
484 cancel_work_sync(&lradc->ts_work);
485
486 /* Disable touchscreen touch-detect IRQ. */
487 writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
488 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
489
490 /* Power-down touchscreen touch-detect circuitry. */
491 writel(LRADC_CTRL0_TOUCH_DETECT_ENABLE,
492 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
493}
494
495static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
496{
497 struct input_dev *input;
498 struct device *dev = lradc->dev;
499 int ret;
500
501 if (!lradc->use_touchscreen)
502 return 0;
503
504 input = input_allocate_device();
505 if (!input) {
506 dev_err(dev, "Failed to allocate TS device!\n");
507 return -ENOMEM;
508 }
509
510 input->name = DRIVER_NAME;
511 input->id.bustype = BUS_HOST;
512 input->dev.parent = dev;
513 input->open = mxs_lradc_ts_open;
514 input->close = mxs_lradc_ts_close;
515
516 __set_bit(EV_ABS, input->evbit);
517 __set_bit(EV_KEY, input->evbit);
518 __set_bit(BTN_TOUCH, input->keybit);
519 input_set_abs_params(input, ABS_X, 0, LRADC_CH_VALUE_MASK, 0, 0);
520 input_set_abs_params(input, ABS_Y, 0, LRADC_CH_VALUE_MASK, 0, 0);
521 input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_CH_VALUE_MASK, 0, 0);
522
523 lradc->ts_input = input;
524 input_set_drvdata(input, lradc);
525 ret = input_register_device(input);
526 if (ret)
527 input_free_device(lradc->ts_input);
528
529 return ret;
530}
531
532static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
533{
534 if (!lradc->use_touchscreen)
535 return;
536
537 cancel_work_sync(&lradc->ts_work);
538
539 input_unregister_device(lradc->ts_input);
540}
541
bc2c90c9
MV		 542/*
543 * IRQ Handling
544 */
545static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
546{
547 struct iio_dev *iio = data;
548 struct mxs_lradc *lradc = iio_priv(iio);
549 unsigned long reg = readl(lradc->base + LRADC_CTRL1);
06ddd353
MV		 550 const uint32_t ts_irq_mask =
551 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
552 LRADC_CTRL1_TOUCH_DETECT_IRQ;
bc2c90c9
MV		 553
554 if (!(reg & LRADC_CTRL1_LRADC_IRQ_MASK))
555 return IRQ_NONE;
556
557 /*
06ddd353
MV		 558 * Touchscreen IRQ handling code has priority and therefore
559 * is placed here. In case touchscreen IRQ arrives, disable
560 * it ASAP
bc2c90c9 561 */
06ddd353
MV		 562 if (reg & LRADC_CTRL1_TOUCH_DETECT_IRQ) {
563 writel(ts_irq_mask,
564 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
565 if (!lradc->stop_touchscreen)
566 schedule_work(&lradc->ts_work);
567 }
bc2c90c9
MV		 568
569 if (iio_buffer_enabled(iio))
570 iio_trigger_poll(iio->trig, iio_get_time_ns());
571 else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
572 complete(&lradc->completion);
573
574 writel(reg & LRADC_CTRL1_LRADC_IRQ_MASK,
575 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
576
577 return IRQ_HANDLED;
578}
579
580/*
581 * Trigger handling
582 */
583static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
584{
585 struct iio_poll_func *pf = p;
586 struct iio_dev *iio = pf->indio_dev;
587 struct mxs_lradc *lradc = iio_priv(iio);
bc2c90c9
MV		 588 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
589 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
7b7a4efe 590 unsigned int i, j = 0;
bc2c90c9
MV		 591
592 for_each_set_bit(i, iio->active_scan_mask, iio->masklength) {
593 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
594 writel(chan_value, lradc->base + LRADC_CH(j));
595 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
596 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
597 j++;
598 }
599
600 if (iio->scan_timestamp) {
601 s64 *timestamp = (s64 *)((u8 *)lradc->buffer +
602 ALIGN(j, sizeof(s64)));
603 *timestamp = pf->timestamp;
604 }
605
84b36ce5 606 iio_push_to_buffers(iio, (u8 *)lradc->buffer);
bc2c90c9
MV		 607
608 iio_trigger_notify_done(iio->trig);
609
610 return IRQ_HANDLED;
611}
612
613static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
614{
615 struct iio_dev *iio = trig->private_data;
616 struct mxs_lradc *lradc = iio_priv(iio);
617 const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
618
619 writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st);
620
621 return 0;
622}
623
624static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
625 .owner = THIS_MODULE,
626 .set_trigger_state = &mxs_lradc_configure_trigger,
627};
628
629static int mxs_lradc_trigger_init(struct iio_dev *iio)
630{
631 int ret;
632 struct iio_trigger *trig;
633
634 trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
635 if (trig == NULL)
636 return -ENOMEM;
637
638 trig->dev.parent = iio->dev.parent;
639 trig->private_data = iio;
640 trig->ops = &mxs_lradc_trigger_ops;
641
642 ret = iio_trigger_register(trig);
643 if (ret) {
644 iio_trigger_free(trig);
645 return ret;
646 }
647
648 iio->trig = trig;
649
650 return 0;
651}
652
653static void mxs_lradc_trigger_remove(struct iio_dev *iio)
654{
655 iio_trigger_unregister(iio->trig);
656 iio_trigger_free(iio->trig);
657}
658
659static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
660{
661 struct mxs_lradc *lradc = iio_priv(iio);
662 struct iio_buffer *buffer = iio->buffer;
06ddd353
MV		 663 int ret = 0, chan, ofs = 0;
664 unsigned long enable = 0;
665 uint32_t ctrl4_set = 0;
666 uint32_t ctrl4_clr = 0;
bc2c90c9
MV		 667 uint32_t ctrl1_irq = 0;
668 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
669 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
670 const int len = bitmap_weight(buffer->scan_mask, LRADC_MAX_TOTAL_CHANS);
671
672 if (!len)
673 return -EINVAL;
674
675 /*
676 * Lock the driver so raw access can not be done during buffered
677 * operation. This simplifies the code a lot.
678 */
679 ret = mutex_trylock(&lradc->lock);
680 if (!ret)
681 return -EBUSY;
682
683 lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
684 if (!lradc->buffer) {
685 ret = -ENOMEM;
686 goto err_mem;
687 }
688
689 ret = iio_sw_buffer_preenable(iio);
690 if (ret < 0)
691 goto err_buf;
692
693 writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
694 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
695 writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
696
697 for_each_set_bit(chan, buffer->scan_mask, LRADC_MAX_TOTAL_CHANS) {
06ddd353
MV		 698 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
699 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
bc2c90c9
MV		 700 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
701 writel(chan_value, lradc->base + LRADC_CH(ofs));
06ddd353 702 bitmap_set(&enable, ofs, 1);
bc2c90c9 703 ofs++;
73327b4c 704 }
bc2c90c9
MV		 705
706 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
707 lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
708
06ddd353
MV		 709 writel(ctrl4_clr, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
710 writel(ctrl4_set, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
711
bc2c90c9
MV		 712 writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
713
714 writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
715 lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
716
717 return 0;
718
719err_buf:
720 kfree(lradc->buffer);
721err_mem:
722 mutex_unlock(&lradc->lock);
723 return ret;
724}
725
726static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
727{
728 struct mxs_lradc *lradc = iio_priv(iio);
729
730 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
731 lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
732
733 writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
734 writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
735 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
736
737 kfree(lradc->buffer);
738 mutex_unlock(&lradc->lock);
739
740 return 0;
741}
742
743static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
744 const unsigned long *mask)
745{
06ddd353
MV		 746 struct mxs_lradc *lradc = iio_priv(iio);
747 const int len = iio->masklength;
748 const int map_chans = bitmap_weight(mask, len);
749 int rsvd_chans = 0;
750 unsigned long rsvd_mask = 0;
751
752 if (lradc->use_touchbutton)
753 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
754 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
755 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
756 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
757 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
758
759 if (lradc->use_touchbutton)
760 rsvd_chans++;
761 if (lradc->use_touchscreen)
762 rsvd_chans++;
763
764 /* Test for attempts to map channels with special mode of operation. */
765 if (bitmap_intersects(mask, &rsvd_mask, len))
766 return false;
767
768 /* Test for attempts to map more channels then available slots. */
769 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
770 return false;
771
772 return true;
bc2c90c9
MV		 773}
774
775static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
776 .preenable = &mxs_lradc_buffer_preenable,
777 .postenable = &iio_triggered_buffer_postenable,
778 .predisable = &iio_triggered_buffer_predisable,
779 .postdisable = &mxs_lradc_buffer_postdisable,
780 .validate_scan_mask = &mxs_lradc_validate_scan_mask,
781};
782
783/*
784 * Driver initialization
785 */
786
787#define MXS_ADC_CHAN(idx, chan_type) { \
788 .type = (chan_type), \
789 .indexed = 1, \
790 .scan_index = (idx), \
791 .info_mask = IIO_CHAN_INFO_RAW_SEPARATE_BIT, \
792 .channel = (idx), \
793 .scan_type = { \
794 .sign = 'u', \
795 .realbits = 18, \
796 .storagebits = 32, \
797 }, \
798}
799
800static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
801 MXS_ADC_CHAN(0, IIO_VOLTAGE),
802 MXS_ADC_CHAN(1, IIO_VOLTAGE),
803 MXS_ADC_CHAN(2, IIO_VOLTAGE),
804 MXS_ADC_CHAN(3, IIO_VOLTAGE),
805 MXS_ADC_CHAN(4, IIO_VOLTAGE),
806 MXS_ADC_CHAN(5, IIO_VOLTAGE),
807 MXS_ADC_CHAN(6, IIO_VOLTAGE),
808 MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */
809 MXS_ADC_CHAN(8, IIO_TEMP), /* Temp sense 0 */
810 MXS_ADC_CHAN(9, IIO_TEMP), /* Temp sense 1 */
811 MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */
812 MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */
813 MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */
814 MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */
815 MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */
816 MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */
817};
818
819static void mxs_lradc_hw_init(struct mxs_lradc *lradc)
820{
06ddd353
MV		 821 /* The ADC always uses DELAY CHANNEL 0. */
822 const uint32_t adc_cfg =
823 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
bc2c90c9
MV		 824 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
825
826 stmp_reset_block(lradc->base);
827
06ddd353
MV		 828 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
829 writel(adc_cfg, lradc->base + LRADC_DELAY(0));
830
831 /* Disable remaining DELAY CHANNELs */
832 writel(0, lradc->base + LRADC_DELAY(1));
833 writel(0, lradc->base + LRADC_DELAY(2));
834 writel(0, lradc->base + LRADC_DELAY(3));
835
836 /* Configure the touchscreen type */
837 writel(LRADC_CTRL0_TOUCH_SCREEN_TYPE,
838 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
839
840 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE) {
841 writel(LRADC_CTRL0_TOUCH_SCREEN_TYPE,
842 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
843 }
bc2c90c9
MV		 844
845 /* Start internal temperature sensing. */
846 writel(0, lradc->base + LRADC_CTRL2);
847}
848
849static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
850{
851 int i;
852
853 writel(LRADC_CTRL1_LRADC_IRQ_EN_MASK,
854 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
855
856 for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
857 writel(0, lradc->base + LRADC_DELAY(i));
858}
859
4ae1c61f 860static int mxs_lradc_probe(struct platform_device *pdev)
bc2c90c9
MV		 861{
862 struct device *dev = &pdev->dev;
06ddd353 863 struct device_node *node = dev->of_node;
bc2c90c9
MV		 864 struct mxs_lradc *lradc;
865 struct iio_dev *iio;
866 struct resource *iores;
06ddd353 867 uint32_t ts_wires = 0;
bc2c90c9
MV		 868 int ret = 0;
869 int i;
870
871 /* Allocate the IIO device. */
872 iio = iio_device_alloc(sizeof(*lradc));
873 if (!iio) {
874 dev_err(dev, "Failed to allocate IIO device\n");
875 return -ENOMEM;
876 }
877
878 lradc = iio_priv(iio);
879
880 /* Grab the memory area */
881 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
882 lradc->dev = &pdev->dev;
883 lradc->base = devm_request_and_ioremap(dev, iores);
884 if (!lradc->base) {
885 ret = -EADDRNOTAVAIL;
886 goto err_addr;
887 }
888
06ddd353
MV		 889 INIT_WORK(&lradc->ts_work, mxs_lradc_ts_work);
890
891 /* Check if touchscreen is enabled in DT. */
892 ret = of_property_read_u32(node, "fsl,lradc-touchscreen-wires",
893 &ts_wires);
894 if (ret)
895 dev_info(dev, "Touchscreen not enabled.\n");
896 else if (ts_wires == 4)
897 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
898 else if (ts_wires == 5)
899 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
900 else
901 dev_warn(dev, "Unsupported number of touchscreen wires (%d)\n",
902 ts_wires);
903
bc2c90c9
MV		 904 /* Grab all IRQ sources */
905 for (i = 0; i < 13; i++) {
906 lradc->irq[i] = platform_get_irq(pdev, i);
907 if (lradc->irq[i] < 0) {
908 ret = -EINVAL;
909 goto err_addr;
910 }
911
912 ret = devm_request_irq(dev, lradc->irq[i],
913 mxs_lradc_handle_irq, 0,
914 mxs_lradc_irq_name[i], iio);
915 if (ret)
916 goto err_addr;
917 }
918
919 platform_set_drvdata(pdev, iio);
920
921 init_completion(&lradc->completion);
922 mutex_init(&lradc->lock);
923
924 iio->name = pdev->name;
925 iio->dev.parent = &pdev->dev;
926 iio->info = &mxs_lradc_iio_info;
927 iio->modes = INDIO_DIRECT_MODE;
928 iio->channels = mxs_lradc_chan_spec;
929 iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
930
931 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
932 &mxs_lradc_trigger_handler,
933 &mxs_lradc_buffer_ops);
934 if (ret)
935 goto err_addr;
936
937 ret = mxs_lradc_trigger_init(iio);
938 if (ret)
939 goto err_trig;
940
06ddd353
MV		 941 /* Register the touchscreen input device. */
942 ret = mxs_lradc_ts_register(lradc);
943 if (ret)
944 goto err_dev;
945
bc2c90c9
MV		 946 /* Register IIO device. */
947 ret = iio_device_register(iio);
948 if (ret) {
949 dev_err(dev, "Failed to register IIO device\n");
06ddd353 950 goto err_ts;
bc2c90c9
MV		 951 }
952
953 /* Configure the hardware. */
954 mxs_lradc_hw_init(lradc);
955
956 return 0;
957
06ddd353
MV		 958err_ts:
959 mxs_lradc_ts_unregister(lradc);
bc2c90c9
MV		 960err_dev:
961 mxs_lradc_trigger_remove(iio);
962err_trig:
963 iio_triggered_buffer_cleanup(iio);
964err_addr:
965 iio_device_free(iio);
966 return ret;
967}
968
447d4f29 969static int mxs_lradc_remove(struct platform_device *pdev)
bc2c90c9
MV		 970{
971 struct iio_dev *iio = platform_get_drvdata(pdev);
972 struct mxs_lradc *lradc = iio_priv(iio);
973
06ddd353
MV		 974 mxs_lradc_ts_unregister(lradc);
975
bc2c90c9
MV		 976 mxs_lradc_hw_stop(lradc);
977
978 iio_device_unregister(iio);
979 iio_triggered_buffer_cleanup(iio);
980 mxs_lradc_trigger_remove(iio);
981 iio_device_free(iio);
982
983 return 0;
984}
985
986static const struct of_device_id mxs_lradc_dt_ids[] = {
987 { .compatible = "fsl,imx28-lradc", },
988 { /* sentinel */ }
989};
990MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
991
992static struct platform_driver mxs_lradc_driver = {
993 .driver = {
994 .name = DRIVER_NAME,
995 .owner = THIS_MODULE,
996 .of_match_table = mxs_lradc_dt_ids,
997 },
998 .probe = mxs_lradc_probe,
e543acf0 999 .remove = mxs_lradc_remove,
bc2c90c9
MV		 1000};
1001
1002module_platform_driver(mxs_lradc_driver);
1003
1004MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1005MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
1006MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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