Staging/iio/adc/touchscreen/MXS: separate i.MX28 specific register bits
[deliverable/linux.git] / drivers / staging / iio / adc / mxs-lradc.c
CommitLineData
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1/*
2 * Freescale i.MX28 LRADC driver
3 *
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Marek Vasut <marex@denx.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
97f4be60 18#include <linux/err.h>
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19#include <linux/interrupt.h>
20#include <linux/device.h>
21#include <linux/kernel.h>
22#include <linux/slab.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/sysfs.h>
26#include <linux/list.h>
27#include <linux/io.h>
28#include <linux/module.h>
29#include <linux/platform_device.h>
30#include <linux/spinlock.h>
31#include <linux/wait.h>
32#include <linux/sched.h>
33#include <linux/stmp_device.h>
34#include <linux/bitops.h>
35#include <linux/completion.h>
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36#include <linux/delay.h>
37#include <linux/input.h>
18da755d 38#include <linux/clk.h>
bc2c90c9 39
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40#include <linux/iio/iio.h>
41#include <linux/iio/buffer.h>
42#include <linux/iio/trigger.h>
43#include <linux/iio/trigger_consumer.h>
44#include <linux/iio/triggered_buffer.h>
45
46#define DRIVER_NAME "mxs-lradc"
47
48#define LRADC_MAX_DELAY_CHANS 4
49#define LRADC_MAX_MAPPED_CHANS 8
50#define LRADC_MAX_TOTAL_CHANS 16
51
52#define LRADC_DELAY_TIMER_HZ 2000
53
54/*
55 * Make this runtime configurable if necessary. Currently, if the buffered mode
56 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
57 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
58 * seconds. The result is that the samples arrive every 500mS.
59 */
60#define LRADC_DELAY_TIMER_PER 200
61#define LRADC_DELAY_TIMER_LOOP 5
62
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63/*
64 * Once the pen touches the touchscreen, the touchscreen switches from
65 * IRQ-driven mode to polling mode to prevent interrupt storm. The polling
66 * is realized by worker thread, which is called every 20 or so milliseconds.
67 * This gives the touchscreen enough fluence and does not strain the system
68 * too much.
69 */
70#define LRADC_TS_SAMPLE_DELAY_MS 5
71
72/*
73 * The LRADC reads the following amount of samples from each touchscreen
74 * channel and the driver then computes avarage of these.
75 */
76#define LRADC_TS_SAMPLE_AMOUNT 4
77
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78enum mxs_lradc_id {
79 IMX23_LRADC,
80 IMX28_LRADC,
81};
82
83static const char * const mx23_lradc_irq_names[] = {
84 "mxs-lradc-touchscreen",
85 "mxs-lradc-channel0",
86 "mxs-lradc-channel1",
87 "mxs-lradc-channel2",
88 "mxs-lradc-channel3",
89 "mxs-lradc-channel4",
90 "mxs-lradc-channel5",
91 "mxs-lradc-channel6",
92 "mxs-lradc-channel7",
93};
94
95static const char * const mx28_lradc_irq_names[] = {
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96 "mxs-lradc-touchscreen",
97 "mxs-lradc-thresh0",
98 "mxs-lradc-thresh1",
99 "mxs-lradc-channel0",
100 "mxs-lradc-channel1",
101 "mxs-lradc-channel2",
102 "mxs-lradc-channel3",
103 "mxs-lradc-channel4",
104 "mxs-lradc-channel5",
105 "mxs-lradc-channel6",
106 "mxs-lradc-channel7",
107 "mxs-lradc-button0",
108 "mxs-lradc-button1",
109};
110
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111struct mxs_lradc_of_config {
112 const int irq_count;
113 const char * const *irq_name;
114};
115
ad76fda7 116static const struct mxs_lradc_of_config mxs_lradc_of_config[] = {
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117 [IMX23_LRADC] = {
118 .irq_count = ARRAY_SIZE(mx23_lradc_irq_names),
119 .irq_name = mx23_lradc_irq_names,
120 },
121 [IMX28_LRADC] = {
122 .irq_count = ARRAY_SIZE(mx28_lradc_irq_names),
123 .irq_name = mx28_lradc_irq_names,
124 },
125};
126
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127enum mxs_lradc_ts {
128 MXS_LRADC_TOUCHSCREEN_NONE = 0,
129 MXS_LRADC_TOUCHSCREEN_4WIRE,
130 MXS_LRADC_TOUCHSCREEN_5WIRE,
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131};
132
133struct mxs_lradc {
134 struct device *dev;
135 void __iomem *base;
136 int irq[13];
137
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138 struct clk *clk;
139
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140 uint32_t *buffer;
141 struct iio_trigger *trig;
142
143 struct mutex lock;
144
bc2c90c9 145 struct completion completion;
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146
147 /*
148 * Touchscreen LRADC channels receives a private slot in the CTRL4
149 * register, the slot #7. Therefore only 7 slots instead of 8 in the
150 * CTRL4 register can be mapped to LRADC channels when using the
151 * touchscreen.
152 *
153 * Furthermore, certain LRADC channels are shared between touchscreen
154 * and/or touch-buttons and generic LRADC block. Therefore when using
155 * either of these, these channels are not available for the regular
156 * sampling. The shared channels are as follows:
157 *
158 * CH0 -- Touch button #0
159 * CH1 -- Touch button #1
160 * CH2 -- Touch screen XPUL
161 * CH3 -- Touch screen YPLL
162 * CH4 -- Touch screen XNUL
163 * CH5 -- Touch screen YNLR
164 * CH6 -- Touch screen WIPER (5-wire only)
165 *
166 * The bitfields below represents which parts of the LRADC block are
167 * switched into special mode of operation. These channels can not
168 * be sampled as regular LRADC channels. The driver will refuse any
169 * attempt to sample these channels.
170 */
171#define CHAN_MASK_TOUCHBUTTON (0x3 << 0)
172#define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2)
173#define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2)
174 enum mxs_lradc_ts use_touchscreen;
175 bool stop_touchscreen;
176 bool use_touchbutton;
177
178 struct input_dev *ts_input;
179 struct work_struct ts_work;
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180
181 enum mxs_lradc_id soc;
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182};
183
184#define LRADC_CTRL0 0x00
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185# define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE (1 << 23)
186# define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE (1 << 22)
187# define LRADC_CTRL0_MX28_YNNSW /* YM */ (1 << 21)
188# define LRADC_CTRL0_MX28_YPNSW /* YP */ (1 << 20)
189# define LRADC_CTRL0_MX28_YPPSW /* YP */ (1 << 19)
190# define LRADC_CTRL0_MX28_XNNSW /* XM */ (1 << 18)
191# define LRADC_CTRL0_MX28_XNPSW /* XM */ (1 << 17)
192# define LRADC_CTRL0_MX28_XPPSW /* XP */ (1 << 16)
193
194# define LRADC_CTRL0_MX28_PLATE_MASK \
195 (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \
196 LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \
197 LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \
198 LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW)
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199
200#define LRADC_CTRL1 0x10
06ddd353 201#define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24)
bc2c90c9 202#define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16))
7e4d4a6f 203#define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16)
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204#define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16
205#define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8)
206#define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n))
7e4d4a6f 207#define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff
06ddd353 208#define LRADC_CTRL1_LRADC_IRQ_OFFSET 0
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209
210#define LRADC_CTRL2 0x20
211#define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15)
212
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213#define LRADC_STATUS 0x40
214#define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0)
215
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216#define LRADC_CH(n) (0x50 + (0x10 * (n)))
217#define LRADC_CH_ACCUMULATE (1 << 29)
218#define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24)
219#define LRADC_CH_NUM_SAMPLES_OFFSET 24
220#define LRADC_CH_VALUE_MASK 0x3ffff
221#define LRADC_CH_VALUE_OFFSET 0
222
223#define LRADC_DELAY(n) (0xd0 + (0x10 * (n)))
224#define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24)
225#define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24
226#define LRADC_DELAY_KICK (1 << 20)
227#define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
228#define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16
229#define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11)
230#define LRADC_DELAY_LOOP_COUNT_OFFSET 11
231#define LRADC_DELAY_DELAY_MASK 0x7ff
232#define LRADC_DELAY_DELAY_OFFSET 0
233
234#define LRADC_CTRL4 0x140
235#define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4))
236#define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4)
237
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238#define LRADC_RESOLUTION 12
239#define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1)
240
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241/*
242 * Raw I/O operations
243 */
244static int mxs_lradc_read_raw(struct iio_dev *iio_dev,
245 const struct iio_chan_spec *chan,
246 int *val, int *val2, long m)
247{
248 struct mxs_lradc *lradc = iio_priv(iio_dev);
249 int ret;
250
251 if (m != IIO_CHAN_INFO_RAW)
252 return -EINVAL;
253
254 /* Check for invalid channel */
255 if (chan->channel > LRADC_MAX_TOTAL_CHANS)
256 return -EINVAL;
257
258 /*
259 * See if there is no buffered operation in progess. If there is, simply
260 * bail out. This can be improved to support both buffered and raw IO at
261 * the same time, yet the code becomes horribly complicated. Therefore I
262 * applied KISS principle here.
263 */
264 ret = mutex_trylock(&lradc->lock);
265 if (!ret)
266 return -EBUSY;
267
268 INIT_COMPLETION(lradc->completion);
269
270 /*
271 * No buffered operation in progress, map the channel and trigger it.
272 * Virtual channel 0 is always used here as the others are always not
273 * used if doing raw sampling.
274 */
7e4d4a6f 275 writel(LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
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276 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
277 writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
278
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279 /* Clean the slot's previous content, then set new one. */
280 writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
281 lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
282 writel(chan->channel, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
283
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284 writel(0, lradc->base + LRADC_CH(0));
285
286 /* Enable the IRQ and start sampling the channel. */
287 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
288 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
289 writel(1 << 0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
290
291 /* Wait for completion on the channel, 1 second max. */
292 ret = wait_for_completion_killable_timeout(&lradc->completion, HZ);
293 if (!ret)
294 ret = -ETIMEDOUT;
295 if (ret < 0)
296 goto err;
297
298 /* Read the data. */
299 *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
300 ret = IIO_VAL_INT;
301
302err:
303 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
304 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
305
306 mutex_unlock(&lradc->lock);
307
308 return ret;
309}
310
311static const struct iio_info mxs_lradc_iio_info = {
312 .driver_module = THIS_MODULE,
313 .read_raw = mxs_lradc_read_raw,
314};
315
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316/*
317 * Touchscreen handling
318 */
319enum lradc_ts_plate {
320 LRADC_SAMPLE_X,
321 LRADC_SAMPLE_Y,
322 LRADC_SAMPLE_PRESSURE,
323};
324
325static int mxs_lradc_ts_touched(struct mxs_lradc *lradc)
326{
327 uint32_t reg;
328
329 /* Enable touch detection. */
7e4d4a6f 330 writel(LRADC_CTRL0_MX28_PLATE_MASK,
06ddd353 331 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
7e4d4a6f 332 writel(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE,
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333 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
334
335 msleep(LRADC_TS_SAMPLE_DELAY_MS);
336
337 reg = readl(lradc->base + LRADC_STATUS);
338
339 return reg & LRADC_STATUS_TOUCH_DETECT_RAW;
340}
341
342static int32_t mxs_lradc_ts_sample(struct mxs_lradc *lradc,
343 enum lradc_ts_plate plate, int change)
344{
345 unsigned long delay, jiff;
346 uint32_t reg, ctrl0 = 0, chan = 0;
347 /* The touchscreen always uses CTRL4 slot #7. */
348 const uint8_t slot = 7;
349 uint32_t val;
350
351 /*
352 * There are three correct configurations of the controller sampling
353 * the touchscreen, each of these configuration provides different
354 * information from the touchscreen.
355 *
356 * The following table describes the sampling configurations:
357 * +-------------+-------+-------+-------+
358 * | Wire \ Axis | X | Y | Z |
359 * +---------------------+-------+-------+
360 * | X+ (CH2) | HI | TS | TS |
361 * +-------------+-------+-------+-------+
362 * | X- (CH4) | LO | SH | HI |
363 * +-------------+-------+-------+-------+
364 * | Y+ (CH3) | SH | HI | HI |
365 * +-------------+-------+-------+-------+
366 * | Y- (CH5) | TS | LO | SH |
367 * +-------------+-------+-------+-------+
368 *
369 * HI ... strong '1' ; LO ... strong '0'
370 * SH ... sample here ; TS ... tri-state
371 *
372 * There are a few other ways of obtaining the Z coordinate
373 * (aka. pressure), but the one in the table seems to be the
374 * most reliable one.
375 */
376 switch (plate) {
377 case LRADC_SAMPLE_X:
7e4d4a6f 378 ctrl0 = LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW;
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379 chan = 3;
380 break;
381 case LRADC_SAMPLE_Y:
7e4d4a6f 382 ctrl0 = LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW;
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383 chan = 4;
384 break;
385 case LRADC_SAMPLE_PRESSURE:
7e4d4a6f 386 ctrl0 = LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW;
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387 chan = 5;
388 break;
389 }
390
391 if (change) {
7e4d4a6f 392 writel(LRADC_CTRL0_MX28_PLATE_MASK,
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393 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
394 writel(ctrl0, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
395
396 writel(LRADC_CTRL4_LRADCSELECT_MASK(slot),
397 lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
398 writel(chan << LRADC_CTRL4_LRADCSELECT_OFFSET(slot),
399 lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
400 }
401
402 writel(0xffffffff, lradc->base + LRADC_CH(slot) + STMP_OFFSET_REG_CLR);
403 writel(1 << slot, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
404
405 delay = jiffies + msecs_to_jiffies(LRADC_TS_SAMPLE_DELAY_MS);
406 do {
407 jiff = jiffies;
408 reg = readl_relaxed(lradc->base + LRADC_CTRL1);
409 if (reg & LRADC_CTRL1_LRADC_IRQ(slot))
410 break;
411 } while (time_before(jiff, delay));
412
413 writel(LRADC_CTRL1_LRADC_IRQ(slot),
414 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
415
416 if (time_after_eq(jiff, delay))
417 return -ETIMEDOUT;
418
419 val = readl(lradc->base + LRADC_CH(slot));
420 val &= LRADC_CH_VALUE_MASK;
421
422 return val;
423}
424
425static int32_t mxs_lradc_ts_sample_filter(struct mxs_lradc *lradc,
426 enum lradc_ts_plate plate)
427{
428 int32_t val, tot = 0;
429 int i;
430
431 val = mxs_lradc_ts_sample(lradc, plate, 1);
432
433 /* Delay a bit so the touchscreen is stable. */
434 mdelay(2);
435
436 for (i = 0; i < LRADC_TS_SAMPLE_AMOUNT; i++) {
437 val = mxs_lradc_ts_sample(lradc, plate, 0);
438 tot += val;
439 }
440
441 return tot / LRADC_TS_SAMPLE_AMOUNT;
442}
443
444static void mxs_lradc_ts_work(struct work_struct *ts_work)
445{
446 struct mxs_lradc *lradc = container_of(ts_work,
447 struct mxs_lradc, ts_work);
448 int val_x, val_y, val_p;
449 bool valid = false;
450
451 while (mxs_lradc_ts_touched(lradc)) {
452 /* Disable touch detector so we can sample the touchscreen. */
7e4d4a6f 453 writel(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE,
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454 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
455
456 if (likely(valid)) {
457 input_report_abs(lradc->ts_input, ABS_X, val_x);
458 input_report_abs(lradc->ts_input, ABS_Y, val_y);
459 input_report_abs(lradc->ts_input, ABS_PRESSURE, val_p);
460 input_report_key(lradc->ts_input, BTN_TOUCH, 1);
461 input_sync(lradc->ts_input);
462 }
463
464 valid = false;
465
466 val_x = mxs_lradc_ts_sample_filter(lradc, LRADC_SAMPLE_X);
467 if (val_x < 0)
468 continue;
469 val_y = mxs_lradc_ts_sample_filter(lradc, LRADC_SAMPLE_Y);
470 if (val_y < 0)
471 continue;
472 val_p = mxs_lradc_ts_sample_filter(lradc, LRADC_SAMPLE_PRESSURE);
473 if (val_p < 0)
474 continue;
475
476 valid = true;
477 }
478
479 input_report_abs(lradc->ts_input, ABS_PRESSURE, 0);
480 input_report_key(lradc->ts_input, BTN_TOUCH, 0);
481 input_sync(lradc->ts_input);
482
483 /* Do not restart the TS IRQ if the driver is shutting down. */
484 if (lradc->stop_touchscreen)
485 return;
486
487 /* Restart the touchscreen interrupts. */
488 writel(LRADC_CTRL1_TOUCH_DETECT_IRQ,
489 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
490 writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
491 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
492}
493
494static int mxs_lradc_ts_open(struct input_dev *dev)
495{
496 struct mxs_lradc *lradc = input_get_drvdata(dev);
497
498 /* The touchscreen is starting. */
499 lradc->stop_touchscreen = false;
500
501 /* Enable the touch-detect circuitry. */
7e4d4a6f 502 writel(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE,
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503 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
504
505 /* Enable the touch-detect IRQ. */
506 writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
507 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
508
509 return 0;
510}
511
512static void mxs_lradc_ts_close(struct input_dev *dev)
513{
514 struct mxs_lradc *lradc = input_get_drvdata(dev);
515
516 /* Indicate the touchscreen is stopping. */
517 lradc->stop_touchscreen = true;
518 mb();
519
520 /* Wait until touchscreen thread finishes any possible remnants. */
521 cancel_work_sync(&lradc->ts_work);
522
523 /* Disable touchscreen touch-detect IRQ. */
524 writel(LRADC_CTRL1_TOUCH_DETECT_IRQ_EN,
525 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
526
527 /* Power-down touchscreen touch-detect circuitry. */
7e4d4a6f 528 writel(LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE,
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529 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
530}
531
532static int mxs_lradc_ts_register(struct mxs_lradc *lradc)
533{
534 struct input_dev *input;
535 struct device *dev = lradc->dev;
536 int ret;
537
538 if (!lradc->use_touchscreen)
539 return 0;
540
541 input = input_allocate_device();
542 if (!input) {
543 dev_err(dev, "Failed to allocate TS device!\n");
544 return -ENOMEM;
545 }
546
547 input->name = DRIVER_NAME;
548 input->id.bustype = BUS_HOST;
549 input->dev.parent = dev;
550 input->open = mxs_lradc_ts_open;
551 input->close = mxs_lradc_ts_close;
552
553 __set_bit(EV_ABS, input->evbit);
554 __set_bit(EV_KEY, input->evbit);
555 __set_bit(BTN_TOUCH, input->keybit);
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556 input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
557 input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0);
558 input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK,
559 0, 0);
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560
561 lradc->ts_input = input;
562 input_set_drvdata(input, lradc);
563 ret = input_register_device(input);
564 if (ret)
565 input_free_device(lradc->ts_input);
566
567 return ret;
568}
569
570static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc)
571{
572 if (!lradc->use_touchscreen)
573 return;
574
575 cancel_work_sync(&lradc->ts_work);
576
577 input_unregister_device(lradc->ts_input);
578}
579
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580/*
581 * IRQ Handling
582 */
583static irqreturn_t mxs_lradc_handle_irq(int irq, void *data)
584{
585 struct iio_dev *iio = data;
586 struct mxs_lradc *lradc = iio_priv(iio);
587 unsigned long reg = readl(lradc->base + LRADC_CTRL1);
06ddd353
MV
588 const uint32_t ts_irq_mask =
589 LRADC_CTRL1_TOUCH_DETECT_IRQ_EN |
590 LRADC_CTRL1_TOUCH_DETECT_IRQ;
bc2c90c9 591
7e4d4a6f 592 if (!(reg & LRADC_CTRL1_MX28_LRADC_IRQ_MASK))
bc2c90c9
MV
593 return IRQ_NONE;
594
595 /*
06ddd353
MV
596 * Touchscreen IRQ handling code has priority and therefore
597 * is placed here. In case touchscreen IRQ arrives, disable
598 * it ASAP
bc2c90c9 599 */
06ddd353
MV
600 if (reg & LRADC_CTRL1_TOUCH_DETECT_IRQ) {
601 writel(ts_irq_mask,
602 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
603 if (!lradc->stop_touchscreen)
604 schedule_work(&lradc->ts_work);
605 }
bc2c90c9
MV
606
607 if (iio_buffer_enabled(iio))
608 iio_trigger_poll(iio->trig, iio_get_time_ns());
609 else if (reg & LRADC_CTRL1_LRADC_IRQ(0))
610 complete(&lradc->completion);
611
7e4d4a6f 612 writel(reg & LRADC_CTRL1_MX28_LRADC_IRQ_MASK,
bc2c90c9
MV
613 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
614
615 return IRQ_HANDLED;
616}
617
618/*
619 * Trigger handling
620 */
621static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p)
622{
623 struct iio_poll_func *pf = p;
624 struct iio_dev *iio = pf->indio_dev;
625 struct mxs_lradc *lradc = iio_priv(iio);
bc2c90c9
MV
626 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
627 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
7b7a4efe 628 unsigned int i, j = 0;
bc2c90c9 629
f4914e5e 630 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
bc2c90c9
MV
631 lradc->buffer[j] = readl(lradc->base + LRADC_CH(j));
632 writel(chan_value, lradc->base + LRADC_CH(j));
633 lradc->buffer[j] &= LRADC_CH_VALUE_MASK;
634 lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
635 j++;
636 }
637
4fa10de6 638 iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp);
bc2c90c9
MV
639
640 iio_trigger_notify_done(iio->trig);
641
642 return IRQ_HANDLED;
643}
644
645static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state)
646{
1e9663c6 647 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
bc2c90c9
MV
648 struct mxs_lradc *lradc = iio_priv(iio);
649 const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
650
651 writel(LRADC_DELAY_KICK, lradc->base + LRADC_DELAY(0) + st);
652
653 return 0;
654}
655
656static const struct iio_trigger_ops mxs_lradc_trigger_ops = {
657 .owner = THIS_MODULE,
658 .set_trigger_state = &mxs_lradc_configure_trigger,
659};
660
661static int mxs_lradc_trigger_init(struct iio_dev *iio)
662{
663 int ret;
664 struct iio_trigger *trig;
e1b1fa66 665 struct mxs_lradc *lradc = iio_priv(iio);
bc2c90c9
MV
666
667 trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id);
668 if (trig == NULL)
669 return -ENOMEM;
670
e1b1fa66 671 trig->dev.parent = lradc->dev;
1e9663c6 672 iio_trigger_set_drvdata(trig, iio);
bc2c90c9
MV
673 trig->ops = &mxs_lradc_trigger_ops;
674
675 ret = iio_trigger_register(trig);
676 if (ret) {
677 iio_trigger_free(trig);
678 return ret;
679 }
680
e1b1fa66 681 lradc->trig = trig;
bc2c90c9
MV
682
683 return 0;
684}
685
686static void mxs_lradc_trigger_remove(struct iio_dev *iio)
687{
e1b1fa66
MV
688 struct mxs_lradc *lradc = iio_priv(iio);
689
690 iio_trigger_unregister(lradc->trig);
691 iio_trigger_free(lradc->trig);
bc2c90c9
MV
692}
693
694static int mxs_lradc_buffer_preenable(struct iio_dev *iio)
695{
696 struct mxs_lradc *lradc = iio_priv(iio);
06ddd353
MV
697 int ret = 0, chan, ofs = 0;
698 unsigned long enable = 0;
699 uint32_t ctrl4_set = 0;
700 uint32_t ctrl4_clr = 0;
bc2c90c9
MV
701 uint32_t ctrl1_irq = 0;
702 const uint32_t chan_value = LRADC_CH_ACCUMULATE |
703 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
c80712c7 704 const int len = bitmap_weight(iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS);
bc2c90c9
MV
705
706 if (!len)
707 return -EINVAL;
708
709 /*
710 * Lock the driver so raw access can not be done during buffered
711 * operation. This simplifies the code a lot.
712 */
713 ret = mutex_trylock(&lradc->lock);
714 if (!ret)
715 return -EBUSY;
716
717 lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL);
718 if (!lradc->buffer) {
719 ret = -ENOMEM;
720 goto err_mem;
721 }
722
723 ret = iio_sw_buffer_preenable(iio);
724 if (ret < 0)
725 goto err_buf;
726
7e4d4a6f 727 writel(LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
bc2c90c9
MV
728 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
729 writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
730
c80712c7 731 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
06ddd353
MV
732 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
733 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
bc2c90c9
MV
734 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
735 writel(chan_value, lradc->base + LRADC_CH(ofs));
06ddd353 736 bitmap_set(&enable, ofs, 1);
bc2c90c9 737 ofs++;
73327b4c 738 }
bc2c90c9
MV
739
740 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
741 lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
742
06ddd353
MV
743 writel(ctrl4_clr, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
744 writel(ctrl4_set, lradc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
745
bc2c90c9
MV
746 writel(ctrl1_irq, lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
747
748 writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
749 lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
750
751 return 0;
752
753err_buf:
754 kfree(lradc->buffer);
755err_mem:
756 mutex_unlock(&lradc->lock);
757 return ret;
758}
759
760static int mxs_lradc_buffer_postdisable(struct iio_dev *iio)
761{
762 struct mxs_lradc *lradc = iio_priv(iio);
763
764 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
765 lradc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
766
767 writel(0xff, lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
7e4d4a6f 768 writel(LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
bc2c90c9
MV
769 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
770
771 kfree(lradc->buffer);
772 mutex_unlock(&lradc->lock);
773
774 return 0;
775}
776
777static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio,
778 const unsigned long *mask)
779{
06ddd353 780 struct mxs_lradc *lradc = iio_priv(iio);
f4914e5e 781 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
06ddd353
MV
782 int rsvd_chans = 0;
783 unsigned long rsvd_mask = 0;
784
785 if (lradc->use_touchbutton)
786 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
787 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE)
788 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
789 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE)
790 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
791
792 if (lradc->use_touchbutton)
793 rsvd_chans++;
794 if (lradc->use_touchscreen)
795 rsvd_chans++;
796
797 /* Test for attempts to map channels with special mode of operation. */
f4914e5e 798 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
06ddd353
MV
799 return false;
800
801 /* Test for attempts to map more channels then available slots. */
802 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
803 return false;
804
805 return true;
bc2c90c9
MV
806}
807
808static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = {
809 .preenable = &mxs_lradc_buffer_preenable,
810 .postenable = &iio_triggered_buffer_postenable,
811 .predisable = &iio_triggered_buffer_predisable,
812 .postdisable = &mxs_lradc_buffer_postdisable,
813 .validate_scan_mask = &mxs_lradc_validate_scan_mask,
814};
815
816/*
817 * Driver initialization
818 */
819
820#define MXS_ADC_CHAN(idx, chan_type) { \
821 .type = (chan_type), \
822 .indexed = 1, \
823 .scan_index = (idx), \
78a5fa67 824 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
bc2c90c9
MV
825 .channel = (idx), \
826 .scan_type = { \
827 .sign = 'u', \
1eb70a97 828 .realbits = LRADC_RESOLUTION, \
bc2c90c9
MV
829 .storagebits = 32, \
830 }, \
831}
832
833static const struct iio_chan_spec mxs_lradc_chan_spec[] = {
834 MXS_ADC_CHAN(0, IIO_VOLTAGE),
835 MXS_ADC_CHAN(1, IIO_VOLTAGE),
836 MXS_ADC_CHAN(2, IIO_VOLTAGE),
837 MXS_ADC_CHAN(3, IIO_VOLTAGE),
838 MXS_ADC_CHAN(4, IIO_VOLTAGE),
839 MXS_ADC_CHAN(5, IIO_VOLTAGE),
840 MXS_ADC_CHAN(6, IIO_VOLTAGE),
841 MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */
842 MXS_ADC_CHAN(8, IIO_TEMP), /* Temp sense 0 */
843 MXS_ADC_CHAN(9, IIO_TEMP), /* Temp sense 1 */
844 MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */
845 MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */
846 MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */
847 MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */
848 MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */
849 MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */
850};
851
947123d5 852static int mxs_lradc_hw_init(struct mxs_lradc *lradc)
bc2c90c9 853{
06ddd353
MV
854 /* The ADC always uses DELAY CHANNEL 0. */
855 const uint32_t adc_cfg =
856 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
bc2c90c9
MV
857 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
858
947123d5
FE
859 int ret = stmp_reset_block(lradc->base);
860 if (ret)
861 return ret;
bc2c90c9 862
06ddd353
MV
863 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
864 writel(adc_cfg, lradc->base + LRADC_DELAY(0));
865
866 /* Disable remaining DELAY CHANNELs */
867 writel(0, lradc->base + LRADC_DELAY(1));
868 writel(0, lradc->base + LRADC_DELAY(2));
869 writel(0, lradc->base + LRADC_DELAY(3));
870
871 /* Configure the touchscreen type */
7e4d4a6f 872 writel(LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
06ddd353
MV
873 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
874
875 if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE) {
7e4d4a6f 876 writel(LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE,
06ddd353
MV
877 lradc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
878 }
bc2c90c9
MV
879
880 /* Start internal temperature sensing. */
881 writel(0, lradc->base + LRADC_CTRL2);
947123d5
FE
882
883 return 0;
bc2c90c9
MV
884}
885
886static void mxs_lradc_hw_stop(struct mxs_lradc *lradc)
887{
888 int i;
889
7e4d4a6f 890 writel(LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK,
bc2c90c9
MV
891 lradc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
892
893 for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++)
894 writel(0, lradc->base + LRADC_DELAY(i));
895}
896
5e1f9aca
MV
897static const struct of_device_id mxs_lradc_dt_ids[] = {
898 { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, },
899 { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, },
900 { /* sentinel */ }
901};
902MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids);
903
4ae1c61f 904static int mxs_lradc_probe(struct platform_device *pdev)
bc2c90c9 905{
5e1f9aca
MV
906 const struct of_device_id *of_id =
907 of_match_device(mxs_lradc_dt_ids, &pdev->dev);
908 const struct mxs_lradc_of_config *of_cfg =
909 &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data];
bc2c90c9 910 struct device *dev = &pdev->dev;
06ddd353 911 struct device_node *node = dev->of_node;
bc2c90c9
MV
912 struct mxs_lradc *lradc;
913 struct iio_dev *iio;
914 struct resource *iores;
06ddd353 915 uint32_t ts_wires = 0;
bc2c90c9
MV
916 int ret = 0;
917 int i;
918
919 /* Allocate the IIO device. */
073c33d5 920 iio = devm_iio_device_alloc(dev, sizeof(*lradc));
bc2c90c9
MV
921 if (!iio) {
922 dev_err(dev, "Failed to allocate IIO device\n");
923 return -ENOMEM;
924 }
925
926 lradc = iio_priv(iio);
ccff5297 927 lradc->soc = (enum mxs_lradc_id)of_id->data;
bc2c90c9
MV
928
929 /* Grab the memory area */
930 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
931 lradc->dev = &pdev->dev;
97f4be60 932 lradc->base = devm_ioremap_resource(dev, iores);
073c33d5
SK
933 if (IS_ERR(lradc->base))
934 return PTR_ERR(lradc->base);
bc2c90c9 935
18da755d
JB
936 lradc->clk = devm_clk_get(&pdev->dev, NULL);
937 if (IS_ERR(lradc->clk)) {
938 dev_err(dev, "Failed to get the delay unit clock\n");
939 return PTR_ERR(lradc->clk);
940 }
941 ret = clk_prepare_enable(lradc->clk);
942 if (ret != 0) {
943 dev_err(dev, "Failed to enable the delay unit clock\n");
944 return ret;
945 }
946
06ddd353
MV
947 INIT_WORK(&lradc->ts_work, mxs_lradc_ts_work);
948
949 /* Check if touchscreen is enabled in DT. */
950 ret = of_property_read_u32(node, "fsl,lradc-touchscreen-wires",
951 &ts_wires);
952 if (ret)
953 dev_info(dev, "Touchscreen not enabled.\n");
954 else if (ts_wires == 4)
955 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE;
956 else if (ts_wires == 5)
957 lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE;
958 else
959 dev_warn(dev, "Unsupported number of touchscreen wires (%d)\n",
960 ts_wires);
961
bc2c90c9 962 /* Grab all IRQ sources */
5e1f9aca 963 for (i = 0; i < of_cfg->irq_count; i++) {
bc2c90c9 964 lradc->irq[i] = platform_get_irq(pdev, i);
073c33d5
SK
965 if (lradc->irq[i] < 0)
966 return -EINVAL;
bc2c90c9
MV
967
968 ret = devm_request_irq(dev, lradc->irq[i],
969 mxs_lradc_handle_irq, 0,
5e1f9aca 970 of_cfg->irq_name[i], iio);
bc2c90c9 971 if (ret)
073c33d5 972 return ret;
bc2c90c9
MV
973 }
974
975 platform_set_drvdata(pdev, iio);
976
977 init_completion(&lradc->completion);
978 mutex_init(&lradc->lock);
979
980 iio->name = pdev->name;
981 iio->dev.parent = &pdev->dev;
982 iio->info = &mxs_lradc_iio_info;
983 iio->modes = INDIO_DIRECT_MODE;
984 iio->channels = mxs_lradc_chan_spec;
985 iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec);
f4914e5e 986 iio->masklength = LRADC_MAX_TOTAL_CHANS;
bc2c90c9
MV
987
988 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
989 &mxs_lradc_trigger_handler,
990 &mxs_lradc_buffer_ops);
991 if (ret)
073c33d5 992 return ret;
bc2c90c9
MV
993
994 ret = mxs_lradc_trigger_init(iio);
995 if (ret)
996 goto err_trig;
997
f6e8a968 998 /* Configure the hardware. */
947123d5
FE
999 ret = mxs_lradc_hw_init(lradc);
1000 if (ret)
1001 goto err_dev;
f6e8a968 1002
06ddd353
MV
1003 /* Register the touchscreen input device. */
1004 ret = mxs_lradc_ts_register(lradc);
1005 if (ret)
a0ef6db7 1006 goto err_ts_register;
06ddd353 1007
bc2c90c9
MV
1008 /* Register IIO device. */
1009 ret = iio_device_register(iio);
1010 if (ret) {
1011 dev_err(dev, "Failed to register IIO device\n");
06ddd353 1012 goto err_ts;
bc2c90c9
MV
1013 }
1014
bc2c90c9
MV
1015 return 0;
1016
06ddd353
MV
1017err_ts:
1018 mxs_lradc_ts_unregister(lradc);
a0ef6db7
FE
1019err_ts_register:
1020 mxs_lradc_hw_stop(lradc);
bc2c90c9
MV
1021err_dev:
1022 mxs_lradc_trigger_remove(iio);
1023err_trig:
1024 iio_triggered_buffer_cleanup(iio);
bc2c90c9
MV
1025 return ret;
1026}
1027
447d4f29 1028static int mxs_lradc_remove(struct platform_device *pdev)
bc2c90c9
MV
1029{
1030 struct iio_dev *iio = platform_get_drvdata(pdev);
1031 struct mxs_lradc *lradc = iio_priv(iio);
1032
a0ef6db7 1033 iio_device_unregister(iio);
06ddd353 1034 mxs_lradc_ts_unregister(lradc);
bc2c90c9 1035 mxs_lradc_hw_stop(lradc);
bc2c90c9 1036 mxs_lradc_trigger_remove(iio);
a0ef6db7 1037 iio_triggered_buffer_cleanup(iio);
bc2c90c9 1038
18da755d 1039 clk_disable_unprepare(lradc->clk);
bc2c90c9
MV
1040 return 0;
1041}
1042
bc2c90c9
MV
1043static struct platform_driver mxs_lradc_driver = {
1044 .driver = {
1045 .name = DRIVER_NAME,
1046 .owner = THIS_MODULE,
1047 .of_match_table = mxs_lradc_dt_ids,
1048 },
1049 .probe = mxs_lradc_probe,
e543acf0 1050 .remove = mxs_lradc_remove,
bc2c90c9
MV
1051};
1052
1053module_platform_driver(mxs_lradc_driver);
1054
1055MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
1056MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver");
1057MODULE_LICENSE("GPL v2");
8c4a8c9d 1058MODULE_ALIAS("platform:" DRIVER_NAME);
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