Commit | Line | Data |
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bc2c90c9 MV |
1 | /* |
2 | * Freescale i.MX28 LRADC driver | |
3 | * | |
4 | * Copyright (c) 2012 DENX Software Engineering, GmbH. | |
5 | * Marek Vasut <marex@denx.de> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; either version 2 of the License, or | |
10 | * (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | */ | |
17 | ||
97f4be60 | 18 | #include <linux/err.h> |
bc2c90c9 MV |
19 | #include <linux/interrupt.h> |
20 | #include <linux/device.h> | |
21 | #include <linux/kernel.h> | |
22 | #include <linux/slab.h> | |
23 | #include <linux/of.h> | |
24 | #include <linux/of_device.h> | |
25 | #include <linux/sysfs.h> | |
26 | #include <linux/list.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
29 | #include <linux/platform_device.h> | |
30 | #include <linux/spinlock.h> | |
31 | #include <linux/wait.h> | |
32 | #include <linux/sched.h> | |
33 | #include <linux/stmp_device.h> | |
34 | #include <linux/bitops.h> | |
35 | #include <linux/completion.h> | |
06ddd353 MV |
36 | #include <linux/delay.h> |
37 | #include <linux/input.h> | |
18da755d | 38 | #include <linux/clk.h> |
bc2c90c9 | 39 | |
bc2c90c9 | 40 | #include <linux/iio/iio.h> |
d5acf594 | 41 | #include <linux/iio/sysfs.h> |
bc2c90c9 MV |
42 | #include <linux/iio/buffer.h> |
43 | #include <linux/iio/trigger.h> | |
44 | #include <linux/iio/trigger_consumer.h> | |
45 | #include <linux/iio/triggered_buffer.h> | |
46 | ||
47 | #define DRIVER_NAME "mxs-lradc" | |
48 | ||
49 | #define LRADC_MAX_DELAY_CHANS 4 | |
50 | #define LRADC_MAX_MAPPED_CHANS 8 | |
51 | #define LRADC_MAX_TOTAL_CHANS 16 | |
52 | ||
53 | #define LRADC_DELAY_TIMER_HZ 2000 | |
54 | ||
55 | /* | |
56 | * Make this runtime configurable if necessary. Currently, if the buffered mode | |
57 | * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before | |
58 | * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000) | |
59 | * seconds. The result is that the samples arrive every 500mS. | |
60 | */ | |
61 | #define LRADC_DELAY_TIMER_PER 200 | |
62 | #define LRADC_DELAY_TIMER_LOOP 5 | |
63 | ||
06ddd353 MV |
64 | /* |
65 | * Once the pen touches the touchscreen, the touchscreen switches from | |
66 | * IRQ-driven mode to polling mode to prevent interrupt storm. The polling | |
67 | * is realized by worker thread, which is called every 20 or so milliseconds. | |
68 | * This gives the touchscreen enough fluence and does not strain the system | |
69 | * too much. | |
70 | */ | |
71 | #define LRADC_TS_SAMPLE_DELAY_MS 5 | |
72 | ||
73 | /* | |
74 | * The LRADC reads the following amount of samples from each touchscreen | |
75 | * channel and the driver then computes avarage of these. | |
76 | */ | |
77 | #define LRADC_TS_SAMPLE_AMOUNT 4 | |
78 | ||
5e1f9aca MV |
79 | enum mxs_lradc_id { |
80 | IMX23_LRADC, | |
81 | IMX28_LRADC, | |
82 | }; | |
83 | ||
84 | static const char * const mx23_lradc_irq_names[] = { | |
85 | "mxs-lradc-touchscreen", | |
86 | "mxs-lradc-channel0", | |
87 | "mxs-lradc-channel1", | |
88 | "mxs-lradc-channel2", | |
89 | "mxs-lradc-channel3", | |
90 | "mxs-lradc-channel4", | |
91 | "mxs-lradc-channel5", | |
92 | "mxs-lradc-channel6", | |
93 | "mxs-lradc-channel7", | |
94 | }; | |
95 | ||
96 | static const char * const mx28_lradc_irq_names[] = { | |
bc2c90c9 MV |
97 | "mxs-lradc-touchscreen", |
98 | "mxs-lradc-thresh0", | |
99 | "mxs-lradc-thresh1", | |
100 | "mxs-lradc-channel0", | |
101 | "mxs-lradc-channel1", | |
102 | "mxs-lradc-channel2", | |
103 | "mxs-lradc-channel3", | |
104 | "mxs-lradc-channel4", | |
105 | "mxs-lradc-channel5", | |
106 | "mxs-lradc-channel6", | |
107 | "mxs-lradc-channel7", | |
108 | "mxs-lradc-button0", | |
109 | "mxs-lradc-button1", | |
110 | }; | |
111 | ||
5e1f9aca MV |
112 | struct mxs_lradc_of_config { |
113 | const int irq_count; | |
114 | const char * const *irq_name; | |
f6db68a4 HP |
115 | const uint32_t *vref_mv; |
116 | }; | |
117 | ||
118 | #define VREF_MV_BASE 1850 | |
119 | ||
120 | static const uint32_t mx23_vref_mv[LRADC_MAX_TOTAL_CHANS] = { | |
121 | VREF_MV_BASE, /* CH0 */ | |
122 | VREF_MV_BASE, /* CH1 */ | |
123 | VREF_MV_BASE, /* CH2 */ | |
124 | VREF_MV_BASE, /* CH3 */ | |
125 | VREF_MV_BASE, /* CH4 */ | |
126 | VREF_MV_BASE, /* CH5 */ | |
127 | VREF_MV_BASE * 2, /* CH6 VDDIO */ | |
128 | VREF_MV_BASE * 4, /* CH7 VBATT */ | |
129 | VREF_MV_BASE, /* CH8 Temp sense 0 */ | |
130 | VREF_MV_BASE, /* CH9 Temp sense 1 */ | |
131 | VREF_MV_BASE, /* CH10 */ | |
132 | VREF_MV_BASE, /* CH11 */ | |
133 | VREF_MV_BASE, /* CH12 USB_DP */ | |
134 | VREF_MV_BASE, /* CH13 USB_DN */ | |
135 | VREF_MV_BASE, /* CH14 VBG */ | |
136 | VREF_MV_BASE * 4, /* CH15 VDD5V */ | |
137 | }; | |
138 | ||
139 | static const uint32_t mx28_vref_mv[LRADC_MAX_TOTAL_CHANS] = { | |
140 | VREF_MV_BASE, /* CH0 */ | |
141 | VREF_MV_BASE, /* CH1 */ | |
142 | VREF_MV_BASE, /* CH2 */ | |
143 | VREF_MV_BASE, /* CH3 */ | |
144 | VREF_MV_BASE, /* CH4 */ | |
145 | VREF_MV_BASE, /* CH5 */ | |
146 | VREF_MV_BASE, /* CH6 */ | |
147 | VREF_MV_BASE * 4, /* CH7 VBATT */ | |
148 | VREF_MV_BASE, /* CH8 Temp sense 0 */ | |
149 | VREF_MV_BASE, /* CH9 Temp sense 1 */ | |
150 | VREF_MV_BASE * 2, /* CH10 VDDIO */ | |
151 | VREF_MV_BASE, /* CH11 VTH */ | |
152 | VREF_MV_BASE * 2, /* CH12 VDDA */ | |
153 | VREF_MV_BASE, /* CH13 VDDD */ | |
154 | VREF_MV_BASE, /* CH14 VBG */ | |
155 | VREF_MV_BASE * 4, /* CH15 VDD5V */ | |
5e1f9aca MV |
156 | }; |
157 | ||
ad76fda7 | 158 | static const struct mxs_lradc_of_config mxs_lradc_of_config[] = { |
5e1f9aca MV |
159 | [IMX23_LRADC] = { |
160 | .irq_count = ARRAY_SIZE(mx23_lradc_irq_names), | |
161 | .irq_name = mx23_lradc_irq_names, | |
f6db68a4 | 162 | .vref_mv = mx23_vref_mv, |
5e1f9aca MV |
163 | }, |
164 | [IMX28_LRADC] = { | |
165 | .irq_count = ARRAY_SIZE(mx28_lradc_irq_names), | |
166 | .irq_name = mx28_lradc_irq_names, | |
f6db68a4 | 167 | .vref_mv = mx28_vref_mv, |
5e1f9aca MV |
168 | }, |
169 | }; | |
170 | ||
06ddd353 MV |
171 | enum mxs_lradc_ts { |
172 | MXS_LRADC_TOUCHSCREEN_NONE = 0, | |
173 | MXS_LRADC_TOUCHSCREEN_4WIRE, | |
174 | MXS_LRADC_TOUCHSCREEN_5WIRE, | |
bc2c90c9 MV |
175 | }; |
176 | ||
dee05308 JB |
177 | /* |
178 | * Touchscreen handling | |
179 | */ | |
180 | enum lradc_ts_plate { | |
181 | LRADC_TOUCH = 0, | |
182 | LRADC_SAMPLE_X, | |
183 | LRADC_SAMPLE_Y, | |
184 | LRADC_SAMPLE_PRESSURE, | |
185 | LRADC_SAMPLE_VALID, | |
186 | }; | |
187 | ||
aba70f2a HP |
188 | enum mxs_lradc_divbytwo { |
189 | MXS_LRADC_DIV_DISABLED = 0, | |
190 | MXS_LRADC_DIV_ENABLED, | |
191 | }; | |
192 | ||
d5acf594 HP |
193 | struct mxs_lradc_scale { |
194 | unsigned int integer; | |
195 | unsigned int nano; | |
196 | }; | |
197 | ||
bc2c90c9 MV |
198 | struct mxs_lradc { |
199 | struct device *dev; | |
200 | void __iomem *base; | |
201 | int irq[13]; | |
202 | ||
18da755d JB |
203 | struct clk *clk; |
204 | ||
bc2c90c9 MV |
205 | uint32_t *buffer; |
206 | struct iio_trigger *trig; | |
207 | ||
208 | struct mutex lock; | |
209 | ||
bc2c90c9 | 210 | struct completion completion; |
06ddd353 | 211 | |
f6db68a4 | 212 | const uint32_t *vref_mv; |
d5acf594 | 213 | struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2]; |
38125b2c | 214 | unsigned long is_divided; |
f6db68a4 | 215 | |
06ddd353 MV |
216 | /* |
217 | * Touchscreen LRADC channels receives a private slot in the CTRL4 | |
218 | * register, the slot #7. Therefore only 7 slots instead of 8 in the | |
219 | * CTRL4 register can be mapped to LRADC channels when using the | |
220 | * touchscreen. | |
221 | * | |
222 | * Furthermore, certain LRADC channels are shared between touchscreen | |
223 | * and/or touch-buttons and generic LRADC block. Therefore when using | |
224 | * either of these, these channels are not available for the regular | |
225 | * sampling. The shared channels are as follows: | |
226 | * | |
227 | * CH0 -- Touch button #0 | |
228 | * CH1 -- Touch button #1 | |
229 | * CH2 -- Touch screen XPUL | |
230 | * CH3 -- Touch screen YPLL | |
231 | * CH4 -- Touch screen XNUL | |
232 | * CH5 -- Touch screen YNLR | |
233 | * CH6 -- Touch screen WIPER (5-wire only) | |
234 | * | |
235 | * The bitfields below represents which parts of the LRADC block are | |
236 | * switched into special mode of operation. These channels can not | |
237 | * be sampled as regular LRADC channels. The driver will refuse any | |
238 | * attempt to sample these channels. | |
239 | */ | |
240 | #define CHAN_MASK_TOUCHBUTTON (0x3 << 0) | |
241 | #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 2) | |
242 | #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 2) | |
243 | enum mxs_lradc_ts use_touchscreen; | |
06ddd353 MV |
244 | bool use_touchbutton; |
245 | ||
246 | struct input_dev *ts_input; | |
ccff5297 JB |
247 | |
248 | enum mxs_lradc_id soc; | |
dee05308 JB |
249 | enum lradc_ts_plate cur_plate; /* statemachine */ |
250 | bool ts_valid; | |
251 | unsigned ts_x_pos; | |
252 | unsigned ts_y_pos; | |
253 | unsigned ts_pressure; | |
254 | ||
255 | /* handle touchscreen's physical behaviour */ | |
256 | /* samples per coordinate */ | |
257 | unsigned over_sample_cnt; | |
258 | /* time clocks between samples */ | |
259 | unsigned over_sample_delay; | |
260 | /* time in clocks to wait after the plates where switched */ | |
261 | unsigned settling_delay; | |
bc2c90c9 MV |
262 | }; |
263 | ||
264 | #define LRADC_CTRL0 0x00 | |
7e4d4a6f JB |
265 | # define LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE (1 << 23) |
266 | # define LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE (1 << 22) | |
267 | # define LRADC_CTRL0_MX28_YNNSW /* YM */ (1 << 21) | |
268 | # define LRADC_CTRL0_MX28_YPNSW /* YP */ (1 << 20) | |
269 | # define LRADC_CTRL0_MX28_YPPSW /* YP */ (1 << 19) | |
270 | # define LRADC_CTRL0_MX28_XNNSW /* XM */ (1 << 18) | |
271 | # define LRADC_CTRL0_MX28_XNPSW /* XM */ (1 << 17) | |
272 | # define LRADC_CTRL0_MX28_XPPSW /* XP */ (1 << 16) | |
273 | ||
8c06f714 JB |
274 | # define LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE (1 << 20) |
275 | # define LRADC_CTRL0_MX23_YM (1 << 19) | |
276 | # define LRADC_CTRL0_MX23_XM (1 << 18) | |
277 | # define LRADC_CTRL0_MX23_YP (1 << 17) | |
278 | # define LRADC_CTRL0_MX23_XP (1 << 16) | |
279 | ||
7e4d4a6f JB |
280 | # define LRADC_CTRL0_MX28_PLATE_MASK \ |
281 | (LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE | \ | |
282 | LRADC_CTRL0_MX28_YNNSW | LRADC_CTRL0_MX28_YPNSW | \ | |
283 | LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW | \ | |
284 | LRADC_CTRL0_MX28_XNPSW | LRADC_CTRL0_MX28_XPPSW) | |
bc2c90c9 | 285 | |
8c06f714 JB |
286 | # define LRADC_CTRL0_MX23_PLATE_MASK \ |
287 | (LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE | \ | |
288 | LRADC_CTRL0_MX23_YM | LRADC_CTRL0_MX23_XM | \ | |
289 | LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XP) | |
290 | ||
bc2c90c9 | 291 | #define LRADC_CTRL1 0x10 |
06ddd353 | 292 | #define LRADC_CTRL1_TOUCH_DETECT_IRQ_EN (1 << 24) |
bc2c90c9 | 293 | #define LRADC_CTRL1_LRADC_IRQ_EN(n) (1 << ((n) + 16)) |
7e4d4a6f | 294 | #define LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK (0x1fff << 16) |
8c06f714 | 295 | #define LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK (0x01ff << 16) |
06ddd353 MV |
296 | #define LRADC_CTRL1_LRADC_IRQ_EN_OFFSET 16 |
297 | #define LRADC_CTRL1_TOUCH_DETECT_IRQ (1 << 8) | |
298 | #define LRADC_CTRL1_LRADC_IRQ(n) (1 << (n)) | |
7e4d4a6f | 299 | #define LRADC_CTRL1_MX28_LRADC_IRQ_MASK 0x1fff |
8c06f714 | 300 | #define LRADC_CTRL1_MX23_LRADC_IRQ_MASK 0x01ff |
06ddd353 | 301 | #define LRADC_CTRL1_LRADC_IRQ_OFFSET 0 |
bc2c90c9 MV |
302 | |
303 | #define LRADC_CTRL2 0x20 | |
aba70f2a | 304 | #define LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET 24 |
bc2c90c9 MV |
305 | #define LRADC_CTRL2_TEMPSENSE_PWD (1 << 15) |
306 | ||
06ddd353 MV |
307 | #define LRADC_STATUS 0x40 |
308 | #define LRADC_STATUS_TOUCH_DETECT_RAW (1 << 0) | |
309 | ||
bc2c90c9 MV |
310 | #define LRADC_CH(n) (0x50 + (0x10 * (n))) |
311 | #define LRADC_CH_ACCUMULATE (1 << 29) | |
312 | #define LRADC_CH_NUM_SAMPLES_MASK (0x1f << 24) | |
313 | #define LRADC_CH_NUM_SAMPLES_OFFSET 24 | |
dee05308 JB |
314 | #define LRADC_CH_NUM_SAMPLES(x) \ |
315 | ((x) << LRADC_CH_NUM_SAMPLES_OFFSET) | |
bc2c90c9 MV |
316 | #define LRADC_CH_VALUE_MASK 0x3ffff |
317 | #define LRADC_CH_VALUE_OFFSET 0 | |
318 | ||
319 | #define LRADC_DELAY(n) (0xd0 + (0x10 * (n))) | |
320 | #define LRADC_DELAY_TRIGGER_LRADCS_MASK (0xff << 24) | |
321 | #define LRADC_DELAY_TRIGGER_LRADCS_OFFSET 24 | |
dee05308 JB |
322 | #define LRADC_DELAY_TRIGGER(x) \ |
323 | (((x) << LRADC_DELAY_TRIGGER_LRADCS_OFFSET) & \ | |
324 | LRADC_DELAY_TRIGGER_LRADCS_MASK) | |
bc2c90c9 MV |
325 | #define LRADC_DELAY_KICK (1 << 20) |
326 | #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16) | |
327 | #define LRADC_DELAY_TRIGGER_DELAYS_OFFSET 16 | |
dee05308 JB |
328 | #define LRADC_DELAY_TRIGGER_DELAYS(x) \ |
329 | (((x) << LRADC_DELAY_TRIGGER_DELAYS_OFFSET) & \ | |
330 | LRADC_DELAY_TRIGGER_DELAYS_MASK) | |
bc2c90c9 MV |
331 | #define LRADC_DELAY_LOOP_COUNT_MASK (0x1f << 11) |
332 | #define LRADC_DELAY_LOOP_COUNT_OFFSET 11 | |
dee05308 JB |
333 | #define LRADC_DELAY_LOOP(x) \ |
334 | (((x) << LRADC_DELAY_LOOP_COUNT_OFFSET) & \ | |
335 | LRADC_DELAY_LOOP_COUNT_MASK) | |
bc2c90c9 MV |
336 | #define LRADC_DELAY_DELAY_MASK 0x7ff |
337 | #define LRADC_DELAY_DELAY_OFFSET 0 | |
dee05308 JB |
338 | #define LRADC_DELAY_DELAY(x) \ |
339 | (((x) << LRADC_DELAY_DELAY_OFFSET) & \ | |
340 | LRADC_DELAY_DELAY_MASK) | |
bc2c90c9 MV |
341 | |
342 | #define LRADC_CTRL4 0x140 | |
343 | #define LRADC_CTRL4_LRADCSELECT_MASK(n) (0xf << ((n) * 4)) | |
344 | #define LRADC_CTRL4_LRADCSELECT_OFFSET(n) ((n) * 4) | |
345 | ||
1eb70a97 HP |
346 | #define LRADC_RESOLUTION 12 |
347 | #define LRADC_SINGLE_SAMPLE_MASK ((1 << LRADC_RESOLUTION) - 1) | |
348 | ||
f0b83cc8 JB |
349 | static void mxs_lradc_reg_set(struct mxs_lradc *lradc, u32 val, u32 reg) |
350 | { | |
351 | writel(val, lradc->base + reg + STMP_OFFSET_REG_SET); | |
352 | } | |
353 | ||
354 | static void mxs_lradc_reg_clear(struct mxs_lradc *lradc, u32 val, u32 reg) | |
355 | { | |
356 | writel(val, lradc->base + reg + STMP_OFFSET_REG_CLR); | |
357 | } | |
358 | ||
359 | static void mxs_lradc_reg_wrt(struct mxs_lradc *lradc, u32 val, u32 reg) | |
360 | { | |
361 | writel(val, lradc->base + reg); | |
362 | } | |
363 | ||
364 | static u32 mxs_lradc_plate_mask(struct mxs_lradc *lradc) | |
365 | { | |
8c06f714 JB |
366 | if (lradc->soc == IMX23_LRADC) |
367 | return LRADC_CTRL0_MX23_PLATE_MASK; | |
368 | else | |
369 | return LRADC_CTRL0_MX28_PLATE_MASK; | |
f0b83cc8 JB |
370 | } |
371 | ||
372 | static u32 mxs_lradc_irq_en_mask(struct mxs_lradc *lradc) | |
373 | { | |
8c06f714 JB |
374 | if (lradc->soc == IMX23_LRADC) |
375 | return LRADC_CTRL1_MX23_LRADC_IRQ_EN_MASK; | |
376 | else | |
377 | return LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK; | |
f0b83cc8 JB |
378 | } |
379 | ||
380 | static u32 mxs_lradc_irq_mask(struct mxs_lradc *lradc) | |
381 | { | |
8c06f714 JB |
382 | if (lradc->soc == IMX23_LRADC) |
383 | return LRADC_CTRL1_MX23_LRADC_IRQ_MASK; | |
384 | else | |
385 | return LRADC_CTRL1_MX28_LRADC_IRQ_MASK; | |
f0b83cc8 JB |
386 | } |
387 | ||
388 | static u32 mxs_lradc_touch_detect_bit(struct mxs_lradc *lradc) | |
389 | { | |
8c06f714 JB |
390 | if (lradc->soc == IMX23_LRADC) |
391 | return LRADC_CTRL0_MX23_TOUCH_DETECT_ENABLE; | |
392 | else | |
393 | return LRADC_CTRL0_MX28_TOUCH_DETECT_ENABLE; | |
f0b83cc8 JB |
394 | } |
395 | ||
396 | static u32 mxs_lradc_drive_x_plate(struct mxs_lradc *lradc) | |
397 | { | |
8c06f714 JB |
398 | if (lradc->soc == IMX23_LRADC) |
399 | return LRADC_CTRL0_MX23_XP | LRADC_CTRL0_MX23_XM; | |
400 | else | |
401 | return LRADC_CTRL0_MX28_XPPSW | LRADC_CTRL0_MX28_XNNSW; | |
f0b83cc8 JB |
402 | } |
403 | ||
404 | static u32 mxs_lradc_drive_y_plate(struct mxs_lradc *lradc) | |
405 | { | |
8c06f714 JB |
406 | if (lradc->soc == IMX23_LRADC) |
407 | return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_YM; | |
408 | else | |
409 | return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_YNNSW; | |
f0b83cc8 JB |
410 | } |
411 | ||
412 | static u32 mxs_lradc_drive_pressure(struct mxs_lradc *lradc) | |
413 | { | |
8c06f714 JB |
414 | if (lradc->soc == IMX23_LRADC) |
415 | return LRADC_CTRL0_MX23_YP | LRADC_CTRL0_MX23_XM; | |
416 | else | |
417 | return LRADC_CTRL0_MX28_YPPSW | LRADC_CTRL0_MX28_XNNSW; | |
f0b83cc8 JB |
418 | } |
419 | ||
dee05308 JB |
420 | static bool mxs_lradc_check_touch_event(struct mxs_lradc *lradc) |
421 | { | |
422 | return !!(readl(lradc->base + LRADC_STATUS) & | |
423 | LRADC_STATUS_TOUCH_DETECT_RAW); | |
424 | } | |
425 | ||
426 | static void mxs_lradc_setup_ts_channel(struct mxs_lradc *lradc, unsigned ch) | |
427 | { | |
428 | /* | |
429 | * prepare for oversampling conversion | |
430 | * | |
431 | * from the datasheet: | |
432 | * "The ACCUMULATE bit in the appropriate channel register | |
433 | * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0; | |
434 | * otherwise, the IRQs will not fire." | |
435 | */ | |
436 | mxs_lradc_reg_wrt(lradc, LRADC_CH_ACCUMULATE | | |
437 | LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1), | |
438 | LRADC_CH(ch)); | |
439 | ||
440 | /* from the datasheet: | |
441 | * "Software must clear this register in preparation for a | |
442 | * multi-cycle accumulation. | |
443 | */ | |
444 | mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch)); | |
445 | ||
446 | /* prepare the delay/loop unit according to the oversampling count */ | |
447 | mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch) | | |
448 | LRADC_DELAY_TRIGGER_DELAYS(0) | | |
449 | LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) | | |
450 | LRADC_DELAY_DELAY(lradc->over_sample_delay - 1), | |
451 | LRADC_DELAY(3)); | |
452 | ||
453 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) | | |
454 | LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) | | |
455 | LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1); | |
456 | ||
457 | /* wake us again, when the complete conversion is done */ | |
458 | mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch), LRADC_CTRL1); | |
459 | /* | |
460 | * after changing the touchscreen plates setting | |
461 | * the signals need some initial time to settle. Start the | |
462 | * SoC's delay unit and start the conversion later | |
463 | * and automatically. | |
464 | */ | |
465 | mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */ | |
466 | LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */ | |
467 | LRADC_DELAY_KICK | | |
468 | LRADC_DELAY_DELAY(lradc->settling_delay), | |
469 | LRADC_DELAY(2)); | |
470 | } | |
471 | ||
472 | /* | |
473 | * Pressure detection is special: | |
474 | * We want to do both required measurements for the pressure detection in | |
475 | * one turn. Use the hardware features to chain both conversions and let the | |
476 | * hardware report one interrupt if both conversions are done | |
477 | */ | |
478 | static void mxs_lradc_setup_ts_pressure(struct mxs_lradc *lradc, unsigned ch1, | |
479 | unsigned ch2) | |
480 | { | |
481 | u32 reg; | |
482 | ||
483 | /* | |
484 | * prepare for oversampling conversion | |
485 | * | |
486 | * from the datasheet: | |
487 | * "The ACCUMULATE bit in the appropriate channel register | |
488 | * HW_LRADC_CHn must be set to 1 if NUM_SAMPLES is greater then 0; | |
489 | * otherwise, the IRQs will not fire." | |
490 | */ | |
491 | reg = LRADC_CH_ACCUMULATE | | |
492 | LRADC_CH_NUM_SAMPLES(lradc->over_sample_cnt - 1); | |
493 | mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch1)); | |
494 | mxs_lradc_reg_wrt(lradc, reg, LRADC_CH(ch2)); | |
495 | ||
496 | /* from the datasheet: | |
497 | * "Software must clear this register in preparation for a | |
498 | * multi-cycle accumulation. | |
499 | */ | |
500 | mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch1)); | |
501 | mxs_lradc_reg_clear(lradc, LRADC_CH_VALUE_MASK, LRADC_CH(ch2)); | |
502 | ||
503 | /* prepare the delay/loop unit according to the oversampling count */ | |
504 | mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << ch1) | | |
505 | LRADC_DELAY_TRIGGER(1 << ch2) | /* start both channels */ | |
506 | LRADC_DELAY_TRIGGER_DELAYS(0) | | |
507 | LRADC_DELAY_LOOP(lradc->over_sample_cnt - 1) | | |
508 | LRADC_DELAY_DELAY(lradc->over_sample_delay - 1), | |
509 | LRADC_DELAY(3)); | |
510 | ||
511 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(2) | | |
512 | LRADC_CTRL1_LRADC_IRQ(3) | LRADC_CTRL1_LRADC_IRQ(4) | | |
513 | LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1); | |
514 | ||
515 | /* wake us again, when the conversions are done */ | |
516 | mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(ch2), LRADC_CTRL1); | |
517 | /* | |
518 | * after changing the touchscreen plates setting | |
519 | * the signals need some initial time to settle. Start the | |
520 | * SoC's delay unit and start the conversion later | |
521 | * and automatically. | |
522 | */ | |
523 | mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(0) | /* don't trigger ADC */ | |
524 | LRADC_DELAY_TRIGGER_DELAYS(1 << 3) | /* trigger DELAY unit#3 */ | |
525 | LRADC_DELAY_KICK | | |
526 | LRADC_DELAY_DELAY(lradc->settling_delay), LRADC_DELAY(2)); | |
527 | } | |
528 | ||
529 | static unsigned mxs_lradc_read_raw_channel(struct mxs_lradc *lradc, | |
530 | unsigned channel) | |
531 | { | |
532 | u32 reg; | |
533 | unsigned num_samples, val; | |
534 | ||
535 | reg = readl(lradc->base + LRADC_CH(channel)); | |
536 | if (reg & LRADC_CH_ACCUMULATE) | |
537 | num_samples = lradc->over_sample_cnt; | |
538 | else | |
539 | num_samples = 1; | |
540 | ||
541 | val = (reg & LRADC_CH_VALUE_MASK) >> LRADC_CH_VALUE_OFFSET; | |
542 | return val / num_samples; | |
543 | } | |
544 | ||
545 | static unsigned mxs_lradc_read_ts_pressure(struct mxs_lradc *lradc, | |
546 | unsigned ch1, unsigned ch2) | |
547 | { | |
548 | u32 reg, mask; | |
549 | unsigned pressure, m1, m2; | |
550 | ||
551 | mask = LRADC_CTRL1_LRADC_IRQ(ch1) | LRADC_CTRL1_LRADC_IRQ(ch2); | |
552 | reg = readl(lradc->base + LRADC_CTRL1) & mask; | |
553 | ||
554 | while (reg != mask) { | |
555 | reg = readl(lradc->base + LRADC_CTRL1) & mask; | |
556 | dev_dbg(lradc->dev, "One channel is still busy: %X\n", reg); | |
557 | } | |
558 | ||
559 | m1 = mxs_lradc_read_raw_channel(lradc, ch1); | |
560 | m2 = mxs_lradc_read_raw_channel(lradc, ch2); | |
561 | ||
562 | if (m2 == 0) { | |
563 | dev_warn(lradc->dev, "Cannot calculate pressure\n"); | |
564 | return 1 << (LRADC_RESOLUTION - 1); | |
565 | } | |
566 | ||
567 | /* simply scale the value from 0 ... max ADC resolution */ | |
568 | pressure = m1; | |
569 | pressure *= (1 << LRADC_RESOLUTION); | |
570 | pressure /= m2; | |
571 | ||
572 | dev_dbg(lradc->dev, "Pressure = %u\n", pressure); | |
573 | return pressure; | |
574 | } | |
575 | ||
576 | #define TS_CH_XP 2 | |
577 | #define TS_CH_YP 3 | |
578 | #define TS_CH_XM 4 | |
579 | #define TS_CH_YM 5 | |
580 | ||
581 | static int mxs_lradc_read_ts_channel(struct mxs_lradc *lradc) | |
582 | { | |
583 | u32 reg; | |
584 | int val; | |
585 | ||
586 | reg = readl(lradc->base + LRADC_CTRL1); | |
587 | ||
588 | /* only channels 3 to 5 are of interest here */ | |
589 | if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YP)) { | |
590 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YP) | | |
591 | LRADC_CTRL1_LRADC_IRQ(TS_CH_YP), LRADC_CTRL1); | |
592 | val = mxs_lradc_read_raw_channel(lradc, TS_CH_YP); | |
593 | } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_XM)) { | |
594 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_XM) | | |
595 | LRADC_CTRL1_LRADC_IRQ(TS_CH_XM), LRADC_CTRL1); | |
596 | val = mxs_lradc_read_raw_channel(lradc, TS_CH_XM); | |
597 | } else if (reg & LRADC_CTRL1_LRADC_IRQ(TS_CH_YM)) { | |
598 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(TS_CH_YM) | | |
599 | LRADC_CTRL1_LRADC_IRQ(TS_CH_YM), LRADC_CTRL1); | |
600 | val = mxs_lradc_read_raw_channel(lradc, TS_CH_YM); | |
601 | } else { | |
602 | return -EIO; | |
603 | } | |
604 | ||
605 | mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2)); | |
606 | mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3)); | |
607 | ||
608 | return val; | |
609 | } | |
610 | ||
611 | /* | |
612 | * YP(open)--+-------------+ | |
613 | * | |--+ | |
614 | * | | | | |
615 | * YM(-)--+-------------+ | | |
616 | * +--------------+ | |
617 | * | | | |
618 | * XP(weak+) XM(open) | |
619 | * | |
620 | * "weak+" means 200k Ohm VDDIO | |
621 | * (-) means GND | |
622 | */ | |
623 | static void mxs_lradc_setup_touch_detection(struct mxs_lradc *lradc) | |
624 | { | |
625 | /* | |
626 | * In order to detect a touch event the 'touch detect enable' bit | |
627 | * enables: | |
628 | * - a weak pullup to the X+ connector | |
629 | * - a strong ground at the Y- connector | |
630 | */ | |
631 | mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); | |
632 | mxs_lradc_reg_set(lradc, mxs_lradc_touch_detect_bit(lradc), | |
633 | LRADC_CTRL0); | |
634 | } | |
635 | ||
636 | /* | |
637 | * YP(meas)--+-------------+ | |
638 | * | |--+ | |
639 | * | | | | |
640 | * YM(open)--+-------------+ | | |
641 | * +--------------+ | |
642 | * | | | |
643 | * XP(+) XM(-) | |
644 | * | |
645 | * (+) means here 1.85 V | |
646 | * (-) means here GND | |
647 | */ | |
648 | static void mxs_lradc_prepare_x_pos(struct mxs_lradc *lradc) | |
649 | { | |
650 | mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); | |
651 | mxs_lradc_reg_set(lradc, mxs_lradc_drive_x_plate(lradc), LRADC_CTRL0); | |
652 | ||
653 | lradc->cur_plate = LRADC_SAMPLE_X; | |
654 | mxs_lradc_setup_ts_channel(lradc, TS_CH_YP); | |
655 | } | |
656 | ||
657 | /* | |
658 | * YP(+)--+-------------+ | |
659 | * | |--+ | |
660 | * | | | | |
661 | * YM(-)--+-------------+ | | |
662 | * +--------------+ | |
663 | * | | | |
664 | * XP(open) XM(meas) | |
665 | * | |
666 | * (+) means here 1.85 V | |
667 | * (-) means here GND | |
668 | */ | |
669 | static void mxs_lradc_prepare_y_pos(struct mxs_lradc *lradc) | |
670 | { | |
671 | mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); | |
672 | mxs_lradc_reg_set(lradc, mxs_lradc_drive_y_plate(lradc), LRADC_CTRL0); | |
673 | ||
674 | lradc->cur_plate = LRADC_SAMPLE_Y; | |
675 | mxs_lradc_setup_ts_channel(lradc, TS_CH_XM); | |
676 | } | |
677 | ||
678 | /* | |
679 | * YP(+)--+-------------+ | |
680 | * | |--+ | |
681 | * | | | | |
682 | * YM(meas)--+-------------+ | | |
683 | * +--------------+ | |
684 | * | | | |
685 | * XP(meas) XM(-) | |
686 | * | |
687 | * (+) means here 1.85 V | |
688 | * (-) means here GND | |
689 | */ | |
690 | static void mxs_lradc_prepare_pressure(struct mxs_lradc *lradc) | |
691 | { | |
692 | mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); | |
693 | mxs_lradc_reg_set(lradc, mxs_lradc_drive_pressure(lradc), LRADC_CTRL0); | |
694 | ||
695 | lradc->cur_plate = LRADC_SAMPLE_PRESSURE; | |
696 | mxs_lradc_setup_ts_pressure(lradc, TS_CH_XP, TS_CH_YM); | |
697 | } | |
698 | ||
699 | static void mxs_lradc_enable_touch_detection(struct mxs_lradc *lradc) | |
700 | { | |
701 | mxs_lradc_setup_touch_detection(lradc); | |
702 | ||
703 | lradc->cur_plate = LRADC_TOUCH; | |
704 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ | | |
705 | LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1); | |
706 | mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1); | |
707 | } | |
708 | ||
709 | static void mxs_lradc_report_ts_event(struct mxs_lradc *lradc) | |
710 | { | |
711 | input_report_abs(lradc->ts_input, ABS_X, lradc->ts_x_pos); | |
712 | input_report_abs(lradc->ts_input, ABS_Y, lradc->ts_y_pos); | |
713 | input_report_abs(lradc->ts_input, ABS_PRESSURE, lradc->ts_pressure); | |
714 | input_report_key(lradc->ts_input, BTN_TOUCH, 1); | |
715 | input_sync(lradc->ts_input); | |
716 | } | |
717 | ||
718 | static void mxs_lradc_complete_touch_event(struct mxs_lradc *lradc) | |
719 | { | |
720 | mxs_lradc_setup_touch_detection(lradc); | |
721 | lradc->cur_plate = LRADC_SAMPLE_VALID; | |
722 | /* | |
723 | * start a dummy conversion to burn time to settle the signals | |
724 | * note: we are not interested in the conversion's value | |
725 | */ | |
726 | mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(5)); | |
727 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ(5), LRADC_CTRL1); | |
728 | mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(5), LRADC_CTRL1); | |
729 | mxs_lradc_reg_wrt(lradc, LRADC_DELAY_TRIGGER(1 << 5) | | |
730 | LRADC_DELAY_KICK | LRADC_DELAY_DELAY(10), /* waste 5 ms */ | |
731 | LRADC_DELAY(2)); | |
732 | } | |
733 | ||
734 | /* | |
735 | * in order to avoid false measurements, report only samples where | |
736 | * the surface is still touched after the position measurement | |
737 | */ | |
738 | static void mxs_lradc_finish_touch_event(struct mxs_lradc *lradc, bool valid) | |
739 | { | |
740 | /* if it is still touched, report the sample */ | |
741 | if (valid && mxs_lradc_check_touch_event(lradc)) { | |
742 | lradc->ts_valid = true; | |
743 | mxs_lradc_report_ts_event(lradc); | |
744 | } | |
745 | ||
746 | /* if it is even still touched, continue with the next measurement */ | |
747 | if (mxs_lradc_check_touch_event(lradc)) { | |
748 | mxs_lradc_prepare_y_pos(lradc); | |
749 | return; | |
750 | } | |
751 | ||
752 | if (lradc->ts_valid) { | |
753 | /* signal the release */ | |
754 | lradc->ts_valid = false; | |
755 | input_report_key(lradc->ts_input, BTN_TOUCH, 0); | |
756 | input_sync(lradc->ts_input); | |
757 | } | |
758 | ||
759 | /* if it is released, wait for the next touch via IRQ */ | |
760dbe1d | 760 | lradc->cur_plate = LRADC_TOUCH; |
dee05308 JB |
761 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ, LRADC_CTRL1); |
762 | mxs_lradc_reg_set(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, LRADC_CTRL1); | |
763 | } | |
764 | ||
765 | /* touchscreen's state machine */ | |
766 | static void mxs_lradc_handle_touch(struct mxs_lradc *lradc) | |
767 | { | |
768 | int val; | |
769 | ||
770 | switch (lradc->cur_plate) { | |
771 | case LRADC_TOUCH: | |
772 | /* | |
773 | * start with the Y-pos, because it uses nearly the same plate | |
774 | * settings like the touch detection | |
775 | */ | |
776 | if (mxs_lradc_check_touch_event(lradc)) { | |
777 | mxs_lradc_reg_clear(lradc, | |
778 | LRADC_CTRL1_TOUCH_DETECT_IRQ_EN, | |
779 | LRADC_CTRL1); | |
780 | mxs_lradc_prepare_y_pos(lradc); | |
781 | } | |
782 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ, | |
783 | LRADC_CTRL1); | |
784 | return; | |
785 | ||
786 | case LRADC_SAMPLE_Y: | |
787 | val = mxs_lradc_read_ts_channel(lradc); | |
788 | if (val < 0) { | |
789 | mxs_lradc_enable_touch_detection(lradc); /* re-start */ | |
790 | return; | |
791 | } | |
792 | lradc->ts_y_pos = val; | |
793 | mxs_lradc_prepare_x_pos(lradc); | |
794 | return; | |
795 | ||
796 | case LRADC_SAMPLE_X: | |
797 | val = mxs_lradc_read_ts_channel(lradc); | |
798 | if (val < 0) { | |
799 | mxs_lradc_enable_touch_detection(lradc); /* re-start */ | |
800 | return; | |
801 | } | |
802 | lradc->ts_x_pos = val; | |
803 | mxs_lradc_prepare_pressure(lradc); | |
804 | return; | |
805 | ||
806 | case LRADC_SAMPLE_PRESSURE: | |
807 | lradc->ts_pressure = | |
808 | mxs_lradc_read_ts_pressure(lradc, TS_CH_XP, TS_CH_YM); | |
809 | mxs_lradc_complete_touch_event(lradc); | |
810 | return; | |
811 | ||
812 | case LRADC_SAMPLE_VALID: | |
813 | val = mxs_lradc_read_ts_channel(lradc); /* ignore the value */ | |
814 | mxs_lradc_finish_touch_event(lradc, 1); | |
815 | break; | |
816 | } | |
817 | } | |
818 | ||
bc2c90c9 MV |
819 | /* |
820 | * Raw I/O operations | |
821 | */ | |
c8231a9a | 822 | static int mxs_lradc_read_single(struct iio_dev *iio_dev, int chan, int *val) |
bc2c90c9 MV |
823 | { |
824 | struct mxs_lradc *lradc = iio_priv(iio_dev); | |
825 | int ret; | |
826 | ||
bc2c90c9 MV |
827 | /* |
828 | * See if there is no buffered operation in progess. If there is, simply | |
829 | * bail out. This can be improved to support both buffered and raw IO at | |
830 | * the same time, yet the code becomes horribly complicated. Therefore I | |
831 | * applied KISS principle here. | |
832 | */ | |
833 | ret = mutex_trylock(&lradc->lock); | |
834 | if (!ret) | |
835 | return -EBUSY; | |
836 | ||
16735d02 | 837 | reinit_completion(&lradc->completion); |
bc2c90c9 MV |
838 | |
839 | /* | |
840 | * No buffered operation in progress, map the channel and trigger it. | |
841 | * Virtual channel 0 is always used here as the others are always not | |
842 | * used if doing raw sampling. | |
843 | */ | |
8c06f714 JB |
844 | if (lradc->soc == IMX28_LRADC) |
845 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK, | |
f0b83cc8 JB |
846 | LRADC_CTRL1); |
847 | mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0); | |
bc2c90c9 | 848 | |
06ddd353 | 849 | /* Clean the slot's previous content, then set new one. */ |
f0b83cc8 | 850 | mxs_lradc_reg_clear(lradc, LRADC_CTRL4_LRADCSELECT_MASK(0), LRADC_CTRL4); |
c8231a9a | 851 | mxs_lradc_reg_set(lradc, chan, LRADC_CTRL4); |
06ddd353 | 852 | |
f0b83cc8 | 853 | mxs_lradc_reg_wrt(lradc, 0, LRADC_CH(0)); |
bc2c90c9 MV |
854 | |
855 | /* Enable the IRQ and start sampling the channel. */ | |
f0b83cc8 JB |
856 | mxs_lradc_reg_set(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1); |
857 | mxs_lradc_reg_set(lradc, 1 << 0, LRADC_CTRL0); | |
bc2c90c9 MV |
858 | |
859 | /* Wait for completion on the channel, 1 second max. */ | |
860 | ret = wait_for_completion_killable_timeout(&lradc->completion, HZ); | |
861 | if (!ret) | |
862 | ret = -ETIMEDOUT; | |
863 | if (ret < 0) | |
864 | goto err; | |
865 | ||
866 | /* Read the data. */ | |
867 | *val = readl(lradc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK; | |
868 | ret = IIO_VAL_INT; | |
869 | ||
870 | err: | |
f0b83cc8 | 871 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_LRADC_IRQ_EN(0), LRADC_CTRL1); |
bc2c90c9 MV |
872 | |
873 | mutex_unlock(&lradc->lock); | |
874 | ||
875 | return ret; | |
876 | } | |
877 | ||
c8231a9a AB |
878 | static int mxs_lradc_read_temp(struct iio_dev *iio_dev, int *val) |
879 | { | |
880 | int ret, min, max; | |
881 | ||
882 | ret = mxs_lradc_read_single(iio_dev, 8, &min); | |
883 | if (ret != IIO_VAL_INT) | |
884 | return ret; | |
885 | ||
886 | ret = mxs_lradc_read_single(iio_dev, 9, &max); | |
887 | if (ret != IIO_VAL_INT) | |
888 | return ret; | |
889 | ||
890 | *val = max - min; | |
891 | ||
892 | return IIO_VAL_INT; | |
893 | } | |
894 | ||
895 | static int mxs_lradc_read_raw(struct iio_dev *iio_dev, | |
896 | const struct iio_chan_spec *chan, | |
897 | int *val, int *val2, long m) | |
898 | { | |
f6db68a4 HP |
899 | struct mxs_lradc *lradc = iio_priv(iio_dev); |
900 | ||
c8231a9a AB |
901 | /* Check for invalid channel */ |
902 | if (chan->channel > LRADC_MAX_TOTAL_CHANS) | |
903 | return -EINVAL; | |
904 | ||
905 | switch (m) { | |
906 | case IIO_CHAN_INFO_RAW: | |
907 | if (chan->type == IIO_TEMP) | |
908 | return mxs_lradc_read_temp(iio_dev, val); | |
909 | ||
910 | return mxs_lradc_read_single(iio_dev, chan->channel, val); | |
911 | ||
912 | case IIO_CHAN_INFO_SCALE: | |
913 | if (chan->type == IIO_TEMP) { | |
914 | /* From the datasheet, we have to multiply by 1.012 and | |
915 | * divide by 4 | |
916 | */ | |
917 | *val = 0; | |
918 | *val2 = 253000; | |
919 | return IIO_VAL_INT_PLUS_MICRO; | |
920 | } | |
921 | ||
f6db68a4 | 922 | *val = lradc->vref_mv[chan->channel]; |
aba70f2a | 923 | *val2 = chan->scan_type.realbits - |
38125b2c | 924 | test_bit(chan->channel, &lradc->is_divided); |
f6db68a4 | 925 | return IIO_VAL_FRACTIONAL_LOG2; |
c8231a9a AB |
926 | |
927 | case IIO_CHAN_INFO_OFFSET: | |
928 | if (chan->type == IIO_TEMP) { | |
929 | /* The calculated value from the ADC is in Kelvin, we | |
930 | * want Celsius for hwmon so the offset is | |
931 | * -272.15 * scale | |
932 | */ | |
933 | *val = -1075; | |
934 | *val2 = 691699; | |
935 | ||
936 | return IIO_VAL_INT_PLUS_MICRO; | |
937 | } | |
938 | ||
939 | return -EINVAL; | |
940 | ||
941 | default: | |
942 | break; | |
943 | } | |
944 | ||
945 | return -EINVAL; | |
946 | } | |
947 | ||
aba70f2a HP |
948 | static int mxs_lradc_write_raw(struct iio_dev *iio_dev, |
949 | const struct iio_chan_spec *chan, | |
950 | int val, int val2, long m) | |
951 | { | |
952 | struct mxs_lradc *lradc = iio_priv(iio_dev); | |
953 | struct mxs_lradc_scale *scale_avail = | |
954 | lradc->scale_avail[chan->channel]; | |
955 | int ret; | |
956 | ||
957 | ret = mutex_trylock(&lradc->lock); | |
958 | if (!ret) | |
959 | return -EBUSY; | |
960 | ||
961 | switch (m) { | |
962 | case IIO_CHAN_INFO_SCALE: | |
963 | ret = -EINVAL; | |
964 | if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer && | |
965 | val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) { | |
966 | /* divider by two disabled */ | |
967 | writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, | |
968 | lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR); | |
38125b2c | 969 | clear_bit(chan->channel, &lradc->is_divided); |
aba70f2a HP |
970 | ret = 0; |
971 | } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer && | |
972 | val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) { | |
973 | /* divider by two enabled */ | |
974 | writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET, | |
975 | lradc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET); | |
38125b2c | 976 | set_bit(chan->channel, &lradc->is_divided); |
aba70f2a HP |
977 | ret = 0; |
978 | } | |
979 | ||
980 | break; | |
981 | default: | |
982 | ret = -EINVAL; | |
983 | break; | |
984 | } | |
985 | ||
986 | mutex_unlock(&lradc->lock); | |
987 | ||
988 | return ret; | |
989 | } | |
990 | ||
991 | static int mxs_lradc_write_raw_get_fmt(struct iio_dev *iio_dev, | |
992 | const struct iio_chan_spec *chan, | |
993 | long m) | |
994 | { | |
995 | return IIO_VAL_INT_PLUS_NANO; | |
996 | } | |
997 | ||
d5acf594 HP |
998 | static ssize_t mxs_lradc_show_scale_available_ch(struct device *dev, |
999 | struct device_attribute *attr, | |
1000 | char *buf, | |
1001 | int ch) | |
1002 | { | |
1003 | struct iio_dev *iio = dev_to_iio_dev(dev); | |
1004 | struct mxs_lradc *lradc = iio_priv(iio); | |
1005 | int i, len = 0; | |
1006 | ||
1007 | for (i = 0; i < ARRAY_SIZE(lradc->scale_avail[ch]); i++) | |
1008 | len += sprintf(buf + len, "%d.%09u ", | |
1009 | lradc->scale_avail[ch][i].integer, | |
1010 | lradc->scale_avail[ch][i].nano); | |
1011 | ||
1012 | len += sprintf(buf + len, "\n"); | |
1013 | ||
1014 | return len; | |
1015 | } | |
1016 | ||
1017 | static ssize_t mxs_lradc_show_scale_available(struct device *dev, | |
1018 | struct device_attribute *attr, | |
1019 | char *buf) | |
1020 | { | |
1021 | struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr); | |
1022 | ||
1023 | return mxs_lradc_show_scale_available_ch(dev, attr, buf, | |
1024 | iio_attr->address); | |
1025 | } | |
1026 | ||
1027 | #define SHOW_SCALE_AVAILABLE_ATTR(ch) \ | |
1028 | static IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, S_IRUGO, \ | |
1029 | mxs_lradc_show_scale_available, NULL, ch) | |
1030 | ||
1031 | SHOW_SCALE_AVAILABLE_ATTR(0); | |
1032 | SHOW_SCALE_AVAILABLE_ATTR(1); | |
1033 | SHOW_SCALE_AVAILABLE_ATTR(2); | |
1034 | SHOW_SCALE_AVAILABLE_ATTR(3); | |
1035 | SHOW_SCALE_AVAILABLE_ATTR(4); | |
1036 | SHOW_SCALE_AVAILABLE_ATTR(5); | |
1037 | SHOW_SCALE_AVAILABLE_ATTR(6); | |
1038 | SHOW_SCALE_AVAILABLE_ATTR(7); | |
d5acf594 HP |
1039 | SHOW_SCALE_AVAILABLE_ATTR(10); |
1040 | SHOW_SCALE_AVAILABLE_ATTR(11); | |
1041 | SHOW_SCALE_AVAILABLE_ATTR(12); | |
1042 | SHOW_SCALE_AVAILABLE_ATTR(13); | |
1043 | SHOW_SCALE_AVAILABLE_ATTR(14); | |
1044 | SHOW_SCALE_AVAILABLE_ATTR(15); | |
1045 | ||
1046 | static struct attribute *mxs_lradc_attributes[] = { | |
1047 | &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr, | |
1048 | &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr, | |
1049 | &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr, | |
1050 | &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr, | |
1051 | &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr, | |
1052 | &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr, | |
1053 | &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr, | |
1054 | &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr, | |
d5acf594 HP |
1055 | &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr, |
1056 | &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr, | |
1057 | &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr, | |
1058 | &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr, | |
1059 | &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr, | |
1060 | &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr, | |
1061 | NULL | |
1062 | }; | |
1063 | ||
1064 | static const struct attribute_group mxs_lradc_attribute_group = { | |
1065 | .attrs = mxs_lradc_attributes, | |
1066 | }; | |
1067 | ||
bc2c90c9 MV |
1068 | static const struct iio_info mxs_lradc_iio_info = { |
1069 | .driver_module = THIS_MODULE, | |
1070 | .read_raw = mxs_lradc_read_raw, | |
aba70f2a HP |
1071 | .write_raw = mxs_lradc_write_raw, |
1072 | .write_raw_get_fmt = mxs_lradc_write_raw_get_fmt, | |
d5acf594 | 1073 | .attrs = &mxs_lradc_attribute_group, |
bc2c90c9 MV |
1074 | }; |
1075 | ||
06ddd353 MV |
1076 | static int mxs_lradc_ts_open(struct input_dev *dev) |
1077 | { | |
1078 | struct mxs_lradc *lradc = input_get_drvdata(dev); | |
1079 | ||
06ddd353 | 1080 | /* Enable the touch-detect circuitry. */ |
dee05308 | 1081 | mxs_lradc_enable_touch_detection(lradc); |
06ddd353 MV |
1082 | |
1083 | return 0; | |
1084 | } | |
1085 | ||
dee05308 | 1086 | static void mxs_lradc_disable_ts(struct mxs_lradc *lradc) |
06ddd353 | 1087 | { |
dee05308 JB |
1088 | /* stop all interrupts from firing */ |
1089 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_TOUCH_DETECT_IRQ_EN | | |
1090 | LRADC_CTRL1_LRADC_IRQ_EN(2) | LRADC_CTRL1_LRADC_IRQ_EN(3) | | |
1091 | LRADC_CTRL1_LRADC_IRQ_EN(4) | LRADC_CTRL1_LRADC_IRQ_EN(5), | |
1092 | LRADC_CTRL1); | |
06ddd353 | 1093 | |
dee05308 JB |
1094 | /* Power-down touchscreen touch-detect circuitry. */ |
1095 | mxs_lradc_reg_clear(lradc, mxs_lradc_plate_mask(lradc), LRADC_CTRL0); | |
1096 | } | |
06ddd353 | 1097 | |
dee05308 JB |
1098 | static void mxs_lradc_ts_close(struct input_dev *dev) |
1099 | { | |
1100 | struct mxs_lradc *lradc = input_get_drvdata(dev); | |
06ddd353 | 1101 | |
dee05308 | 1102 | mxs_lradc_disable_ts(lradc); |
06ddd353 MV |
1103 | } |
1104 | ||
1105 | static int mxs_lradc_ts_register(struct mxs_lradc *lradc) | |
1106 | { | |
1107 | struct input_dev *input; | |
1108 | struct device *dev = lradc->dev; | |
1109 | int ret; | |
1110 | ||
1111 | if (!lradc->use_touchscreen) | |
1112 | return 0; | |
1113 | ||
1114 | input = input_allocate_device(); | |
f99a92c3 | 1115 | if (!input) |
06ddd353 | 1116 | return -ENOMEM; |
06ddd353 MV |
1117 | |
1118 | input->name = DRIVER_NAME; | |
1119 | input->id.bustype = BUS_HOST; | |
1120 | input->dev.parent = dev; | |
1121 | input->open = mxs_lradc_ts_open; | |
1122 | input->close = mxs_lradc_ts_close; | |
1123 | ||
1124 | __set_bit(EV_ABS, input->evbit); | |
1125 | __set_bit(EV_KEY, input->evbit); | |
1126 | __set_bit(BTN_TOUCH, input->keybit); | |
1eb70a97 HP |
1127 | input_set_abs_params(input, ABS_X, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0); |
1128 | input_set_abs_params(input, ABS_Y, 0, LRADC_SINGLE_SAMPLE_MASK, 0, 0); | |
1129 | input_set_abs_params(input, ABS_PRESSURE, 0, LRADC_SINGLE_SAMPLE_MASK, | |
1130 | 0, 0); | |
06ddd353 MV |
1131 | |
1132 | lradc->ts_input = input; | |
1133 | input_set_drvdata(input, lradc); | |
1134 | ret = input_register_device(input); | |
1135 | if (ret) | |
1136 | input_free_device(lradc->ts_input); | |
1137 | ||
1138 | return ret; | |
1139 | } | |
1140 | ||
1141 | static void mxs_lradc_ts_unregister(struct mxs_lradc *lradc) | |
1142 | { | |
1143 | if (!lradc->use_touchscreen) | |
1144 | return; | |
1145 | ||
dee05308 | 1146 | mxs_lradc_disable_ts(lradc); |
06ddd353 MV |
1147 | input_unregister_device(lradc->ts_input); |
1148 | } | |
1149 | ||
bc2c90c9 MV |
1150 | /* |
1151 | * IRQ Handling | |
1152 | */ | |
1153 | static irqreturn_t mxs_lradc_handle_irq(int irq, void *data) | |
1154 | { | |
1155 | struct iio_dev *iio = data; | |
1156 | struct mxs_lradc *lradc = iio_priv(iio); | |
1157 | unsigned long reg = readl(lradc->base + LRADC_CTRL1); | |
06ddd353 | 1158 | const uint32_t ts_irq_mask = |
dee05308 JB |
1159 | LRADC_CTRL1_TOUCH_DETECT_IRQ | |
1160 | LRADC_CTRL1_LRADC_IRQ(2) | | |
1161 | LRADC_CTRL1_LRADC_IRQ(3) | | |
1162 | LRADC_CTRL1_LRADC_IRQ(4) | | |
1163 | LRADC_CTRL1_LRADC_IRQ(5); | |
bc2c90c9 | 1164 | |
f0b83cc8 | 1165 | if (!(reg & mxs_lradc_irq_mask(lradc))) |
bc2c90c9 MV |
1166 | return IRQ_NONE; |
1167 | ||
dee05308 JB |
1168 | if (lradc->use_touchscreen && (reg & ts_irq_mask)) |
1169 | mxs_lradc_handle_touch(lradc); | |
bc2c90c9 MV |
1170 | |
1171 | if (iio_buffer_enabled(iio)) | |
1172 | iio_trigger_poll(iio->trig, iio_get_time_ns()); | |
1173 | else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) | |
1174 | complete(&lradc->completion); | |
1175 | ||
f0b83cc8 | 1176 | mxs_lradc_reg_clear(lradc, reg & mxs_lradc_irq_mask(lradc), LRADC_CTRL1); |
bc2c90c9 MV |
1177 | |
1178 | return IRQ_HANDLED; | |
1179 | } | |
1180 | ||
1181 | /* | |
1182 | * Trigger handling | |
1183 | */ | |
1184 | static irqreturn_t mxs_lradc_trigger_handler(int irq, void *p) | |
1185 | { | |
1186 | struct iio_poll_func *pf = p; | |
1187 | struct iio_dev *iio = pf->indio_dev; | |
1188 | struct mxs_lradc *lradc = iio_priv(iio); | |
bc2c90c9 MV |
1189 | const uint32_t chan_value = LRADC_CH_ACCUMULATE | |
1190 | ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); | |
7b7a4efe | 1191 | unsigned int i, j = 0; |
bc2c90c9 | 1192 | |
f4914e5e | 1193 | for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { |
bc2c90c9 | 1194 | lradc->buffer[j] = readl(lradc->base + LRADC_CH(j)); |
f0b83cc8 | 1195 | mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(j)); |
bc2c90c9 MV |
1196 | lradc->buffer[j] &= LRADC_CH_VALUE_MASK; |
1197 | lradc->buffer[j] /= LRADC_DELAY_TIMER_LOOP; | |
1198 | j++; | |
1199 | } | |
1200 | ||
4fa10de6 | 1201 | iio_push_to_buffers_with_timestamp(iio, lradc->buffer, pf->timestamp); |
bc2c90c9 MV |
1202 | |
1203 | iio_trigger_notify_done(iio->trig); | |
1204 | ||
1205 | return IRQ_HANDLED; | |
1206 | } | |
1207 | ||
1208 | static int mxs_lradc_configure_trigger(struct iio_trigger *trig, bool state) | |
1209 | { | |
1e9663c6 | 1210 | struct iio_dev *iio = iio_trigger_get_drvdata(trig); |
bc2c90c9 MV |
1211 | struct mxs_lradc *lradc = iio_priv(iio); |
1212 | const uint32_t st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR; | |
1213 | ||
f0b83cc8 | 1214 | mxs_lradc_reg_wrt(lradc, LRADC_DELAY_KICK, LRADC_DELAY(0) + st); |
bc2c90c9 MV |
1215 | |
1216 | return 0; | |
1217 | } | |
1218 | ||
1219 | static const struct iio_trigger_ops mxs_lradc_trigger_ops = { | |
1220 | .owner = THIS_MODULE, | |
1221 | .set_trigger_state = &mxs_lradc_configure_trigger, | |
1222 | }; | |
1223 | ||
1224 | static int mxs_lradc_trigger_init(struct iio_dev *iio) | |
1225 | { | |
1226 | int ret; | |
1227 | struct iio_trigger *trig; | |
e1b1fa66 | 1228 | struct mxs_lradc *lradc = iio_priv(iio); |
bc2c90c9 MV |
1229 | |
1230 | trig = iio_trigger_alloc("%s-dev%i", iio->name, iio->id); | |
1231 | if (trig == NULL) | |
1232 | return -ENOMEM; | |
1233 | ||
e1b1fa66 | 1234 | trig->dev.parent = lradc->dev; |
1e9663c6 | 1235 | iio_trigger_set_drvdata(trig, iio); |
bc2c90c9 MV |
1236 | trig->ops = &mxs_lradc_trigger_ops; |
1237 | ||
1238 | ret = iio_trigger_register(trig); | |
1239 | if (ret) { | |
1240 | iio_trigger_free(trig); | |
1241 | return ret; | |
1242 | } | |
1243 | ||
e1b1fa66 | 1244 | lradc->trig = trig; |
bc2c90c9 MV |
1245 | |
1246 | return 0; | |
1247 | } | |
1248 | ||
1249 | static void mxs_lradc_trigger_remove(struct iio_dev *iio) | |
1250 | { | |
e1b1fa66 MV |
1251 | struct mxs_lradc *lradc = iio_priv(iio); |
1252 | ||
1253 | iio_trigger_unregister(lradc->trig); | |
1254 | iio_trigger_free(lradc->trig); | |
bc2c90c9 MV |
1255 | } |
1256 | ||
1257 | static int mxs_lradc_buffer_preenable(struct iio_dev *iio) | |
1258 | { | |
1259 | struct mxs_lradc *lradc = iio_priv(iio); | |
06ddd353 MV |
1260 | int ret = 0, chan, ofs = 0; |
1261 | unsigned long enable = 0; | |
1262 | uint32_t ctrl4_set = 0; | |
1263 | uint32_t ctrl4_clr = 0; | |
bc2c90c9 MV |
1264 | uint32_t ctrl1_irq = 0; |
1265 | const uint32_t chan_value = LRADC_CH_ACCUMULATE | | |
1266 | ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET); | |
c80712c7 | 1267 | const int len = bitmap_weight(iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS); |
bc2c90c9 MV |
1268 | |
1269 | if (!len) | |
1270 | return -EINVAL; | |
1271 | ||
1272 | /* | |
1273 | * Lock the driver so raw access can not be done during buffered | |
1274 | * operation. This simplifies the code a lot. | |
1275 | */ | |
1276 | ret = mutex_trylock(&lradc->lock); | |
1277 | if (!ret) | |
1278 | return -EBUSY; | |
1279 | ||
1280 | lradc->buffer = kmalloc(len * sizeof(*lradc->buffer), GFP_KERNEL); | |
1281 | if (!lradc->buffer) { | |
1282 | ret = -ENOMEM; | |
1283 | goto err_mem; | |
1284 | } | |
1285 | ||
8c06f714 JB |
1286 | if (lradc->soc == IMX28_LRADC) |
1287 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK, | |
f0b83cc8 JB |
1288 | LRADC_CTRL1); |
1289 | mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0); | |
bc2c90c9 | 1290 | |
c80712c7 | 1291 | for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) { |
06ddd353 MV |
1292 | ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs); |
1293 | ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs); | |
bc2c90c9 | 1294 | ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs); |
f0b83cc8 | 1295 | mxs_lradc_reg_wrt(lradc, chan_value, LRADC_CH(ofs)); |
06ddd353 | 1296 | bitmap_set(&enable, ofs, 1); |
bc2c90c9 | 1297 | ofs++; |
73327b4c | 1298 | } |
bc2c90c9 | 1299 | |
f0b83cc8 JB |
1300 | mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK | |
1301 | LRADC_DELAY_KICK, LRADC_DELAY(0)); | |
1302 | mxs_lradc_reg_clear(lradc, ctrl4_clr, LRADC_CTRL4); | |
1303 | mxs_lradc_reg_set(lradc, ctrl4_set, LRADC_CTRL4); | |
1304 | mxs_lradc_reg_set(lradc, ctrl1_irq, LRADC_CTRL1); | |
1305 | mxs_lradc_reg_set(lradc, enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET, | |
1306 | LRADC_DELAY(0)); | |
bc2c90c9 MV |
1307 | |
1308 | return 0; | |
1309 | ||
bc2c90c9 MV |
1310 | err_mem: |
1311 | mutex_unlock(&lradc->lock); | |
1312 | return ret; | |
1313 | } | |
1314 | ||
1315 | static int mxs_lradc_buffer_postdisable(struct iio_dev *iio) | |
1316 | { | |
1317 | struct mxs_lradc *lradc = iio_priv(iio); | |
1318 | ||
f0b83cc8 JB |
1319 | mxs_lradc_reg_clear(lradc, LRADC_DELAY_TRIGGER_LRADCS_MASK | |
1320 | LRADC_DELAY_KICK, LRADC_DELAY(0)); | |
bc2c90c9 | 1321 | |
f0b83cc8 | 1322 | mxs_lradc_reg_clear(lradc, 0xff, LRADC_CTRL0); |
8c06f714 JB |
1323 | if (lradc->soc == IMX28_LRADC) |
1324 | mxs_lradc_reg_clear(lradc, LRADC_CTRL1_MX28_LRADC_IRQ_EN_MASK, | |
f0b83cc8 | 1325 | LRADC_CTRL1); |
bc2c90c9 MV |
1326 | |
1327 | kfree(lradc->buffer); | |
1328 | mutex_unlock(&lradc->lock); | |
1329 | ||
1330 | return 0; | |
1331 | } | |
1332 | ||
1333 | static bool mxs_lradc_validate_scan_mask(struct iio_dev *iio, | |
1334 | const unsigned long *mask) | |
1335 | { | |
06ddd353 | 1336 | struct mxs_lradc *lradc = iio_priv(iio); |
f4914e5e | 1337 | const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS); |
06ddd353 MV |
1338 | int rsvd_chans = 0; |
1339 | unsigned long rsvd_mask = 0; | |
1340 | ||
1341 | if (lradc->use_touchbutton) | |
1342 | rsvd_mask |= CHAN_MASK_TOUCHBUTTON; | |
1343 | if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_4WIRE) | |
1344 | rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE; | |
1345 | if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE) | |
1346 | rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE; | |
1347 | ||
1348 | if (lradc->use_touchbutton) | |
1349 | rsvd_chans++; | |
1350 | if (lradc->use_touchscreen) | |
1351 | rsvd_chans++; | |
1352 | ||
1353 | /* Test for attempts to map channels with special mode of operation. */ | |
f4914e5e | 1354 | if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS)) |
06ddd353 MV |
1355 | return false; |
1356 | ||
1357 | /* Test for attempts to map more channels then available slots. */ | |
1358 | if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS) | |
1359 | return false; | |
1360 | ||
1361 | return true; | |
bc2c90c9 MV |
1362 | } |
1363 | ||
1364 | static const struct iio_buffer_setup_ops mxs_lradc_buffer_ops = { | |
1365 | .preenable = &mxs_lradc_buffer_preenable, | |
1366 | .postenable = &iio_triggered_buffer_postenable, | |
1367 | .predisable = &iio_triggered_buffer_predisable, | |
1368 | .postdisable = &mxs_lradc_buffer_postdisable, | |
1369 | .validate_scan_mask = &mxs_lradc_validate_scan_mask, | |
1370 | }; | |
1371 | ||
1372 | /* | |
1373 | * Driver initialization | |
1374 | */ | |
1375 | ||
1376 | #define MXS_ADC_CHAN(idx, chan_type) { \ | |
1377 | .type = (chan_type), \ | |
1378 | .indexed = 1, \ | |
1379 | .scan_index = (idx), \ | |
f6db68a4 HP |
1380 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ |
1381 | BIT(IIO_CHAN_INFO_SCALE), \ | |
bc2c90c9 | 1382 | .channel = (idx), \ |
d5acf594 | 1383 | .address = (idx), \ |
bc2c90c9 MV |
1384 | .scan_type = { \ |
1385 | .sign = 'u', \ | |
1eb70a97 | 1386 | .realbits = LRADC_RESOLUTION, \ |
bc2c90c9 MV |
1387 | .storagebits = 32, \ |
1388 | }, \ | |
1389 | } | |
1390 | ||
1391 | static const struct iio_chan_spec mxs_lradc_chan_spec[] = { | |
1392 | MXS_ADC_CHAN(0, IIO_VOLTAGE), | |
1393 | MXS_ADC_CHAN(1, IIO_VOLTAGE), | |
1394 | MXS_ADC_CHAN(2, IIO_VOLTAGE), | |
1395 | MXS_ADC_CHAN(3, IIO_VOLTAGE), | |
1396 | MXS_ADC_CHAN(4, IIO_VOLTAGE), | |
1397 | MXS_ADC_CHAN(5, IIO_VOLTAGE), | |
1398 | MXS_ADC_CHAN(6, IIO_VOLTAGE), | |
1399 | MXS_ADC_CHAN(7, IIO_VOLTAGE), /* VBATT */ | |
c8231a9a AB |
1400 | /* Combined Temperature sensors */ |
1401 | { | |
1402 | .type = IIO_TEMP, | |
1403 | .indexed = 1, | |
1404 | .scan_index = 8, | |
1405 | .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | | |
1406 | BIT(IIO_CHAN_INFO_OFFSET) | | |
1407 | BIT(IIO_CHAN_INFO_SCALE), | |
1408 | .channel = 8, | |
1409 | .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,}, | |
1410 | }, | |
bc2c90c9 MV |
1411 | MXS_ADC_CHAN(10, IIO_VOLTAGE), /* VDDIO */ |
1412 | MXS_ADC_CHAN(11, IIO_VOLTAGE), /* VTH */ | |
1413 | MXS_ADC_CHAN(12, IIO_VOLTAGE), /* VDDA */ | |
1414 | MXS_ADC_CHAN(13, IIO_VOLTAGE), /* VDDD */ | |
1415 | MXS_ADC_CHAN(14, IIO_VOLTAGE), /* VBG */ | |
1416 | MXS_ADC_CHAN(15, IIO_VOLTAGE), /* VDD5V */ | |
1417 | }; | |
1418 | ||
947123d5 | 1419 | static int mxs_lradc_hw_init(struct mxs_lradc *lradc) |
bc2c90c9 | 1420 | { |
06ddd353 MV |
1421 | /* The ADC always uses DELAY CHANNEL 0. */ |
1422 | const uint32_t adc_cfg = | |
1423 | (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) | | |
bc2c90c9 MV |
1424 | (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET); |
1425 | ||
947123d5 FE |
1426 | int ret = stmp_reset_block(lradc->base); |
1427 | if (ret) | |
1428 | return ret; | |
bc2c90c9 | 1429 | |
06ddd353 | 1430 | /* Configure DELAY CHANNEL 0 for generic ADC sampling. */ |
f0b83cc8 | 1431 | mxs_lradc_reg_wrt(lradc, adc_cfg, LRADC_DELAY(0)); |
06ddd353 MV |
1432 | |
1433 | /* Disable remaining DELAY CHANNELs */ | |
f0b83cc8 JB |
1434 | mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(1)); |
1435 | mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(2)); | |
1436 | mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(3)); | |
06ddd353 MV |
1437 | |
1438 | /* Configure the touchscreen type */ | |
8c06f714 JB |
1439 | if (lradc->soc == IMX28_LRADC) { |
1440 | mxs_lradc_reg_clear(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE, | |
f0b83cc8 | 1441 | LRADC_CTRL0); |
06ddd353 | 1442 | |
f0b83cc8 JB |
1443 | if (lradc->use_touchscreen == MXS_LRADC_TOUCHSCREEN_5WIRE) |
1444 | mxs_lradc_reg_set(lradc, LRADC_CTRL0_MX28_TOUCH_SCREEN_TYPE, | |
1445 | LRADC_CTRL0); | |
06ddd353 | 1446 | } |
bc2c90c9 MV |
1447 | |
1448 | /* Start internal temperature sensing. */ | |
f0b83cc8 | 1449 | mxs_lradc_reg_wrt(lradc, 0, LRADC_CTRL2); |
947123d5 FE |
1450 | |
1451 | return 0; | |
bc2c90c9 MV |
1452 | } |
1453 | ||
1454 | static void mxs_lradc_hw_stop(struct mxs_lradc *lradc) | |
1455 | { | |
1456 | int i; | |
1457 | ||
f0b83cc8 | 1458 | mxs_lradc_reg_clear(lradc, mxs_lradc_irq_en_mask(lradc), LRADC_CTRL1); |
bc2c90c9 MV |
1459 | |
1460 | for (i = 0; i < LRADC_MAX_DELAY_CHANS; i++) | |
f0b83cc8 | 1461 | mxs_lradc_reg_wrt(lradc, 0, LRADC_DELAY(i)); |
bc2c90c9 MV |
1462 | } |
1463 | ||
5e1f9aca MV |
1464 | static const struct of_device_id mxs_lradc_dt_ids[] = { |
1465 | { .compatible = "fsl,imx23-lradc", .data = (void *)IMX23_LRADC, }, | |
1466 | { .compatible = "fsl,imx28-lradc", .data = (void *)IMX28_LRADC, }, | |
1467 | { /* sentinel */ } | |
1468 | }; | |
1469 | MODULE_DEVICE_TABLE(of, mxs_lradc_dt_ids); | |
1470 | ||
dee05308 JB |
1471 | static int mxs_lradc_probe_touchscreen(struct mxs_lradc *lradc, |
1472 | struct device_node *lradc_node) | |
1473 | { | |
e9c88fb5 JB |
1474 | int ret; |
1475 | u32 ts_wires = 0, adapt; | |
1476 | ||
1477 | ret = of_property_read_u32(lradc_node, "fsl,lradc-touchscreen-wires", | |
1478 | &ts_wires); | |
1479 | if (ret) | |
1480 | return -ENODEV; /* touchscreen feature disabled */ | |
1481 | ||
1482 | switch (ts_wires) { | |
1483 | case 4: | |
1484 | lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_4WIRE; | |
1485 | break; | |
1486 | case 5: | |
1487 | if (lradc->soc == IMX28_LRADC) { | |
1488 | lradc->use_touchscreen = MXS_LRADC_TOUCHSCREEN_5WIRE; | |
1489 | break; | |
1490 | } | |
1491 | /* fall through an error message for i.MX23 */ | |
1492 | default: | |
1493 | dev_err(lradc->dev, | |
1494 | "Unsupported number of touchscreen wires (%d)\n", | |
1495 | ts_wires); | |
1496 | return -EINVAL; | |
1497 | } | |
1498 | ||
dee05308 | 1499 | lradc->over_sample_cnt = 4; |
e9c88fb5 JB |
1500 | ret = of_property_read_u32(lradc_node, "fsl,ave-ctrl", &adapt); |
1501 | if (ret == 0) | |
1502 | lradc->over_sample_cnt = adapt; | |
1503 | ||
dee05308 | 1504 | lradc->over_sample_delay = 2; |
e9c88fb5 JB |
1505 | ret = of_property_read_u32(lradc_node, "fsl,ave-delay", &adapt); |
1506 | if (ret == 0) | |
1507 | lradc->over_sample_delay = adapt; | |
1508 | ||
dee05308 | 1509 | lradc->settling_delay = 10; |
e9c88fb5 JB |
1510 | ret = of_property_read_u32(lradc_node, "fsl,settling", &adapt); |
1511 | if (ret == 0) | |
1512 | lradc->settling_delay = adapt; | |
dee05308 JB |
1513 | |
1514 | return 0; | |
1515 | } | |
1516 | ||
4ae1c61f | 1517 | static int mxs_lradc_probe(struct platform_device *pdev) |
bc2c90c9 | 1518 | { |
5e1f9aca MV |
1519 | const struct of_device_id *of_id = |
1520 | of_match_device(mxs_lradc_dt_ids, &pdev->dev); | |
1521 | const struct mxs_lradc_of_config *of_cfg = | |
1522 | &mxs_lradc_of_config[(enum mxs_lradc_id)of_id->data]; | |
bc2c90c9 | 1523 | struct device *dev = &pdev->dev; |
06ddd353 | 1524 | struct device_node *node = dev->of_node; |
bc2c90c9 MV |
1525 | struct mxs_lradc *lradc; |
1526 | struct iio_dev *iio; | |
1527 | struct resource *iores; | |
dee05308 | 1528 | int ret = 0, touch_ret; |
d5acf594 HP |
1529 | int i, s; |
1530 | unsigned int scale_uv; | |
bc2c90c9 MV |
1531 | |
1532 | /* Allocate the IIO device. */ | |
073c33d5 | 1533 | iio = devm_iio_device_alloc(dev, sizeof(*lradc)); |
bc2c90c9 MV |
1534 | if (!iio) { |
1535 | dev_err(dev, "Failed to allocate IIO device\n"); | |
1536 | return -ENOMEM; | |
1537 | } | |
1538 | ||
1539 | lradc = iio_priv(iio); | |
ccff5297 | 1540 | lradc->soc = (enum mxs_lradc_id)of_id->data; |
bc2c90c9 MV |
1541 | |
1542 | /* Grab the memory area */ | |
1543 | iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
1544 | lradc->dev = &pdev->dev; | |
97f4be60 | 1545 | lradc->base = devm_ioremap_resource(dev, iores); |
073c33d5 SK |
1546 | if (IS_ERR(lradc->base)) |
1547 | return PTR_ERR(lradc->base); | |
bc2c90c9 | 1548 | |
18da755d JB |
1549 | lradc->clk = devm_clk_get(&pdev->dev, NULL); |
1550 | if (IS_ERR(lradc->clk)) { | |
1551 | dev_err(dev, "Failed to get the delay unit clock\n"); | |
1552 | return PTR_ERR(lradc->clk); | |
1553 | } | |
1554 | ret = clk_prepare_enable(lradc->clk); | |
1555 | if (ret != 0) { | |
1556 | dev_err(dev, "Failed to enable the delay unit clock\n"); | |
1557 | return ret; | |
1558 | } | |
1559 | ||
dee05308 | 1560 | touch_ret = mxs_lradc_probe_touchscreen(lradc, node); |
06ddd353 | 1561 | |
bc2c90c9 | 1562 | /* Grab all IRQ sources */ |
5e1f9aca | 1563 | for (i = 0; i < of_cfg->irq_count; i++) { |
bc2c90c9 | 1564 | lradc->irq[i] = platform_get_irq(pdev, i); |
073c33d5 SK |
1565 | if (lradc->irq[i] < 0) |
1566 | return -EINVAL; | |
bc2c90c9 MV |
1567 | |
1568 | ret = devm_request_irq(dev, lradc->irq[i], | |
1569 | mxs_lradc_handle_irq, 0, | |
5e1f9aca | 1570 | of_cfg->irq_name[i], iio); |
bc2c90c9 | 1571 | if (ret) |
073c33d5 | 1572 | return ret; |
bc2c90c9 MV |
1573 | } |
1574 | ||
f6db68a4 HP |
1575 | lradc->vref_mv = of_cfg->vref_mv; |
1576 | ||
bc2c90c9 MV |
1577 | platform_set_drvdata(pdev, iio); |
1578 | ||
1579 | init_completion(&lradc->completion); | |
1580 | mutex_init(&lradc->lock); | |
1581 | ||
1582 | iio->name = pdev->name; | |
1583 | iio->dev.parent = &pdev->dev; | |
1584 | iio->info = &mxs_lradc_iio_info; | |
1585 | iio->modes = INDIO_DIRECT_MODE; | |
1586 | iio->channels = mxs_lradc_chan_spec; | |
1587 | iio->num_channels = ARRAY_SIZE(mxs_lradc_chan_spec); | |
f4914e5e | 1588 | iio->masklength = LRADC_MAX_TOTAL_CHANS; |
bc2c90c9 MV |
1589 | |
1590 | ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time, | |
1591 | &mxs_lradc_trigger_handler, | |
1592 | &mxs_lradc_buffer_ops); | |
1593 | if (ret) | |
073c33d5 | 1594 | return ret; |
bc2c90c9 MV |
1595 | |
1596 | ret = mxs_lradc_trigger_init(iio); | |
1597 | if (ret) | |
1598 | goto err_trig; | |
1599 | ||
d5acf594 HP |
1600 | /* Populate available ADC input ranges */ |
1601 | for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) { | |
1602 | for (s = 0; s < ARRAY_SIZE(lradc->scale_avail[i]); s++) { | |
1603 | /* | |
1604 | * [s=0] = optional divider by two disabled (default) | |
1605 | * [s=1] = optional divider by two enabled | |
1606 | * | |
1607 | * The scale is calculated by doing: | |
1608 | * Vref >> (realbits - s) | |
1609 | * which multiplies by two on the second component | |
1610 | * of the array. | |
1611 | */ | |
1612 | scale_uv = ((u64)lradc->vref_mv[i] * 100000000) >> | |
d4bf105b | 1613 | (LRADC_RESOLUTION - s); |
d5acf594 HP |
1614 | lradc->scale_avail[i][s].nano = |
1615 | do_div(scale_uv, 100000000) * 10; | |
1616 | lradc->scale_avail[i][s].integer = scale_uv; | |
1617 | } | |
1618 | } | |
1619 | ||
f6e8a968 | 1620 | /* Configure the hardware. */ |
947123d5 FE |
1621 | ret = mxs_lradc_hw_init(lradc); |
1622 | if (ret) | |
1623 | goto err_dev; | |
f6e8a968 | 1624 | |
06ddd353 | 1625 | /* Register the touchscreen input device. */ |
dee05308 JB |
1626 | if (touch_ret == 0) { |
1627 | ret = mxs_lradc_ts_register(lradc); | |
1628 | if (ret) | |
1629 | goto err_ts_register; | |
1630 | } | |
06ddd353 | 1631 | |
bc2c90c9 MV |
1632 | /* Register IIO device. */ |
1633 | ret = iio_device_register(iio); | |
1634 | if (ret) { | |
1635 | dev_err(dev, "Failed to register IIO device\n"); | |
06ddd353 | 1636 | goto err_ts; |
bc2c90c9 MV |
1637 | } |
1638 | ||
bc2c90c9 MV |
1639 | return 0; |
1640 | ||
06ddd353 MV |
1641 | err_ts: |
1642 | mxs_lradc_ts_unregister(lradc); | |
a0ef6db7 FE |
1643 | err_ts_register: |
1644 | mxs_lradc_hw_stop(lradc); | |
bc2c90c9 MV |
1645 | err_dev: |
1646 | mxs_lradc_trigger_remove(iio); | |
1647 | err_trig: | |
1648 | iio_triggered_buffer_cleanup(iio); | |
bc2c90c9 MV |
1649 | return ret; |
1650 | } | |
1651 | ||
447d4f29 | 1652 | static int mxs_lradc_remove(struct platform_device *pdev) |
bc2c90c9 MV |
1653 | { |
1654 | struct iio_dev *iio = platform_get_drvdata(pdev); | |
1655 | struct mxs_lradc *lradc = iio_priv(iio); | |
1656 | ||
a0ef6db7 | 1657 | iio_device_unregister(iio); |
06ddd353 | 1658 | mxs_lradc_ts_unregister(lradc); |
bc2c90c9 | 1659 | mxs_lradc_hw_stop(lradc); |
bc2c90c9 | 1660 | mxs_lradc_trigger_remove(iio); |
a0ef6db7 | 1661 | iio_triggered_buffer_cleanup(iio); |
bc2c90c9 | 1662 | |
18da755d | 1663 | clk_disable_unprepare(lradc->clk); |
bc2c90c9 MV |
1664 | return 0; |
1665 | } | |
1666 | ||
bc2c90c9 MV |
1667 | static struct platform_driver mxs_lradc_driver = { |
1668 | .driver = { | |
1669 | .name = DRIVER_NAME, | |
1670 | .owner = THIS_MODULE, | |
1671 | .of_match_table = mxs_lradc_dt_ids, | |
1672 | }, | |
1673 | .probe = mxs_lradc_probe, | |
e543acf0 | 1674 | .remove = mxs_lradc_remove, |
bc2c90c9 MV |
1675 | }; |
1676 | ||
1677 | module_platform_driver(mxs_lradc_driver); | |
1678 | ||
1679 | MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); | |
1680 | MODULE_DESCRIPTION("Freescale i.MX28 LRADC driver"); | |
1681 | MODULE_LICENSE("GPL v2"); | |
8c4a8c9d | 1682 | MODULE_ALIAS("platform:" DRIVER_NAME); |