[deliverable/linux.git] / drivers / staging / iio / dds / ad9832.c

/*
 * AD9832 SPI DDS driver
 *
 * Copyright 2011 Analog Devices Inc.
 *
 * Licensed under the GPL-2.
 */

#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <asm/div64.h>

#include "../iio.h"
#include "../sysfs.h"
#include "dds.h"

#include "ad9832.h"

static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
{
	unsigned long long freqreg = (u64) fout *
				     (u64) ((u64) 1L << AD9832_FREQ_BITS);
	do_div(freqreg, mclk);
	return freqreg;
}

static int ad9832_write_frequency(struct ad9832_state *st,
				  unsigned addr, unsigned long fout)
{
	unsigned long regval;

	if (fout > (st->mclk / 2))
		return -EINVAL;

	regval = ad9832_calc_freqreg(st->mclk, fout);

	st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
					(addr << ADD_SHIFT) |
					((regval >> 24) & 0xFF));
	st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
					((addr - 1) << ADD_SHIFT) |
					((regval >> 16) & 0xFF));
	st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) |
					((addr - 2) << ADD_SHIFT) |
					((regval >> 8) & 0xFF));
	st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) |
					((addr - 3) << ADD_SHIFT) |
					((regval >> 0) & 0xFF));

	return spi_sync(st->spi, &st->freq_msg);;
}

static int ad9832_write_phase(struct ad9832_state *st,
				  unsigned long addr, unsigned long phase)
{
	if (phase > (1 << AD9832_PHASE_BITS))
		return -EINVAL;

	st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) |
					(addr << ADD_SHIFT) |
					((phase >> 8) & 0xFF));
	st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) |
					((addr - 1) << ADD_SHIFT) |
					(phase & 0xFF));

	return spi_sync(st->spi, &st->phase_msg);
}

static ssize_t ad9832_write(struct device *dev,
		struct device_attribute *attr,
		const char *buf,
		size_t len)
{
	struct iio_dev *dev_info = dev_get_drvdata(dev);
	struct ad9832_state *st = iio_priv(dev_info);
	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
	int ret;
	long val;

	ret = strict_strtoul(buf, 10, &val);
	if (ret)
		goto error_ret;

	mutex_lock(&dev_info->mlock);
	switch (this_attr->address) {
	case AD9832_FREQ0HM:
	case AD9832_FREQ1HM:
		ret = ad9832_write_frequency(st, this_attr->address, val);
		break;
	case AD9832_PHASE0H:
	case AD9832_PHASE1H:
	case AD9832_PHASE2H:
	case AD9832_PHASE3H:
		ret = ad9832_write_phase(st, this_attr->address, val);
		break;
	case AD9832_PINCTRL_EN:
		if (val)
			st->ctrl_ss &= ~AD9832_SELSRC;
		else
			st->ctrl_ss |= AD9832_SELSRC;
		st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) |
					st->ctrl_ss);
		ret = spi_sync(st->spi, &st->msg);
		break;
	case AD9832_FREQ_SYM:
		if (val == 1)
			st->ctrl_fp |= AD9832_FREQ;
		else if (val == 0)
			st->ctrl_fp &= ~AD9832_FREQ;
		else {
			ret = -EINVAL;
			break;
		}
		st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
					st->ctrl_fp);
		ret = spi_sync(st->spi, &st->msg);
		break;
	case AD9832_PHASE_SYM:
		if (val < 0 || val > 3) {
			ret = -EINVAL;
			break;
		}

		st->ctrl_fp &= ~AD9832_PHASE(3);
		st->ctrl_fp |= AD9832_PHASE(val);

		st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) |
					st->ctrl_fp);
		ret = spi_sync(st->spi, &st->msg);
		break;
	case AD9832_OUTPUT_EN:
		if (val)
			st->ctrl_src &= ~(AD9832_RESET | AD9832_SLEEP |
					AD9832_CLR);
		else
			st->ctrl_src |= AD9832_RESET;

		st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
					st->ctrl_src);
		ret = spi_sync(st->spi, &st->msg);
		break;
	default:
		ret = -ENODEV;
	}
	mutex_unlock(&dev_info->mlock);

error_ret:
	return ret ? ret : len;
}

/**
 * see dds.h for further information
 */

static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */

static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
				ad9832_write, AD9832_PHASE_SYM);
static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/

static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
				ad9832_write, AD9832_PINCTRL_EN);
static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
				ad9832_write, AD9832_OUTPUT_EN);

static struct attribute *ad9832_attributes[] = {
	&iio_dev_attr_dds0_freq0.dev_attr.attr,
	&iio_dev_attr_dds0_freq1.dev_attr.attr,
	&iio_const_attr_dds0_freq_scale.dev_attr.attr,
	&iio_dev_attr_dds0_phase0.dev_attr.attr,
	&iio_dev_attr_dds0_phase1.dev_attr.attr,
	&iio_dev_attr_dds0_phase2.dev_attr.attr,
	&iio_dev_attr_dds0_phase3.dev_attr.attr,
	&iio_const_attr_dds0_phase_scale.dev_attr.attr,
	&iio_dev_attr_dds0_pincontrol_en.dev_attr.attr,
	&iio_dev_attr_dds0_freqsymbol.dev_attr.attr,
	&iio_dev_attr_dds0_phasesymbol.dev_attr.attr,
	&iio_dev_attr_dds0_out_enable.dev_attr.attr,
	NULL,
};

static const struct attribute_group ad9832_attribute_group = {
	.attrs = ad9832_attributes,
};

static const struct iio_info ad9832_info = {
	.attrs = &ad9832_attribute_group,
	.driver_module = THIS_MODULE,
};

static int __devinit ad9832_probe(struct spi_device *spi)
{
	struct ad9832_platform_data *pdata = spi->dev.platform_data;
	struct iio_dev *indio_dev;
	struct ad9832_state *st;
	struct regulator *reg;
	int ret;

	if (!pdata) {
		dev_dbg(&spi->dev, "no platform data?\n");
		return -ENODEV;
	}

	reg = regulator_get(&spi->dev, "vcc");
	if (!IS_ERR(reg)) {
		ret = regulator_enable(reg);
		if (ret)
			goto error_put_reg;
	}

	indio_dev = iio_allocate_device(sizeof(*st));
	if (indio_dev == NULL) {
		ret = -ENOMEM;
		goto error_disable_reg;
	}
	spi_set_drvdata(spi, indio_dev);
	st = iio_priv(indio_dev);
	st->reg = reg;
	st->mclk = pdata->mclk;
	st->spi = spi;

	indio_dev->dev.parent = &spi->dev;
	indio_dev->name = spi_get_device_id(spi)->name;
	indio_dev->info = &ad9832_info;
	indio_dev->modes = INDIO_DIRECT_MODE;

	/* Setup default messages */

	st->xfer.tx_buf = &st->data;
	st->xfer.len = 2;

	spi_message_init(&st->msg);
	spi_message_add_tail(&st->xfer, &st->msg);

	st->freq_xfer[0].tx_buf = &st->freq_data[0];
	st->freq_xfer[0].len = 2;
	st->freq_xfer[0].cs_change = 1;
	st->freq_xfer[1].tx_buf = &st->freq_data[1];
	st->freq_xfer[1].len = 2;
	st->freq_xfer[1].cs_change = 1;
	st->freq_xfer[2].tx_buf = &st->freq_data[2];
	st->freq_xfer[2].len = 2;
	st->freq_xfer[2].cs_change = 1;
	st->freq_xfer[3].tx_buf = &st->freq_data[3];
	st->freq_xfer[3].len = 2;

	spi_message_init(&st->freq_msg);
	spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
	spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
	spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
	spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);

	st->phase_xfer[0].tx_buf = &st->phase_data[0];
	st->phase_xfer[0].len = 2;
	st->phase_xfer[0].cs_change = 1;
	st->phase_xfer[1].tx_buf = &st->phase_data[1];
	st->phase_xfer[1].len = 2;

	spi_message_init(&st->phase_msg);
	spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
	spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);

	st->ctrl_src = AD9832_SLEEP | AD9832_RESET | AD9832_CLR;
	st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) |
					st->ctrl_src);
	ret = spi_sync(st->spi, &st->msg);
	if (ret) {
		dev_err(&spi->dev, "device init failed\n");
		goto error_free_device;
	}

	ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
	if (ret)
		goto error_free_device;

	ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
	if (ret)
		goto error_free_device;

	ret = iio_device_register(indio_dev);
	if (ret)
		goto error_free_device;

	return 0;

error_free_device:
	iio_free_device(indio_dev);
error_disable_reg:
	if (!IS_ERR(reg))
		regulator_disable(reg);
error_put_reg:
	if (!IS_ERR(reg))
		regulator_put(reg);

	return ret;
}

static int __devexit ad9832_remove(struct spi_device *spi)
{
	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	struct ad9832_state *st = iio_priv(indio_dev);
	struct regulator *reg = st->reg;

	iio_device_unregister(indio_dev);
	if (!IS_ERR(reg)) {
		regulator_disable(reg);
		regulator_put(reg);
	}
	return 0;
}

static const struct spi_device_id ad9832_id[] = {
	{"ad9832", 0},
	{"ad9835", 0},
	{}
};

static struct spi_driver ad9832_driver = {
	.driver = {
		.name	= "ad9832",
		.bus	= &spi_bus_type,
		.owner	= THIS_MODULE,
	},
	.probe		= ad9832_probe,
	.remove		= __devexit_p(ad9832_remove),
	.id_table	= ad9832_id,
};

static int __init ad9832_init(void)
{
	return spi_register_driver(&ad9832_driver);
}
module_init(ad9832_init);

static void __exit ad9832_exit(void)
{
	spi_unregister_driver(&ad9832_driver);
}
module_exit(ad9832_exit);

MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:ad9832");
Commit	Line	Data
4a8e6c33	1	/*
ea707584	2	* AD9832 SPI DDS driver
4a8e6c33	3	*
ea707584	4	* Copyright 2011 Analog Devices Inc.
4a8e6c33	5	*
ea707584	6	* Licensed under the GPL-2.
4a8e6c33	7	*/
ea707584	8
4a8e6c33	9	#include <linux/device.h>
ea707584	10	#include <linux/kernel.h>
4a8e6c33 CC	11	#include <linux/slab.h>
4a8e6c33 CC	12	#include <linux/sysfs.h>
ea707584 MH	13	#include <linux/spi/spi.h>
	14	#include <linux/regulator/consumer.h>
	15	#include <linux/err.h>
	16	#include <asm/div64.h>
4a8e6c33 CC	17
	18	#include "../iio.h"
	19	#include "../sysfs.h"
ea707584	20	#include "dds.h"
4a8e6c33	21
ea707584	22	#include "ad9832.h"
4a8e6c33	23
ea707584	24	static unsigned long ad9832_calc_freqreg(unsigned long mclk, unsigned long fout)
4a8e6c33	25	{
ea707584 MH	26	unsigned long long freqreg = (u64) fout *
	27	(u64) ((u64) 1L << AD9832_FREQ_BITS);
	28	do_div(freqreg, mclk);
	29	return freqreg;
	30	}
4a8e6c33	31
ea707584 MH	32	static int ad9832_write_frequency(struct ad9832_state *st,
	33	unsigned addr, unsigned long fout)
	34	{
	35	unsigned long regval;
	36
	37	if (fout > (st->mclk / 2))
	38	return -EINVAL;
	39
	40	regval = ad9832_calc_freqreg(st->mclk, fout);
	41
	42	st->freq_data[0] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) \|
	43	(addr << ADD_SHIFT) \|
	44	((regval >> 24) & 0xFF));
	45	st->freq_data[1] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) \|
	46	((addr - 1) << ADD_SHIFT) \|
	47	((regval >> 16) & 0xFF));
	48	st->freq_data[2] = cpu_to_be16((AD9832_CMD_FRE8BITSW << CMD_SHIFT) \|
	49	((addr - 2) << ADD_SHIFT) \|
	50	((regval >> 8) & 0xFF));
	51	st->freq_data[3] = cpu_to_be16((AD9832_CMD_FRE16BITSW << CMD_SHIFT) \|
	52	((addr - 3) << ADD_SHIFT) \|
	53	((regval >> 0) & 0xFF));
	54
	55	return spi_sync(st->spi, &st->freq_msg);;
4a8e6c33 CC	56	}
4a8e6c33 CC	57
ea707584 MH	58	static int ad9832_write_phase(struct ad9832_state *st,
	59	unsigned long addr, unsigned long phase)
	60	{
	61	if (phase > (1 << AD9832_PHASE_BITS))
	62	return -EINVAL;
4a8e6c33	63
ea707584 MH	64	st->phase_data[0] = cpu_to_be16((AD9832_CMD_PHA8BITSW << CMD_SHIFT) \|
	65	(addr << ADD_SHIFT) \|
	66	((phase >> 8) & 0xFF));
	67	st->phase_data[1] = cpu_to_be16((AD9832_CMD_PHA16BITSW << CMD_SHIFT) \|
	68	((addr - 1) << ADD_SHIFT) \|
	69	(phase & 0xFF));
4a8e6c33	70
ea707584 MH	71	return spi_sync(st->spi, &st->phase_msg);
ea707584 MH	72	}
4a8e6c33	73
ea707584 MH	74	static ssize_t ad9832_write(struct device *dev,
	75	struct device_attribute *attr,
	76	const char *buf,
	77	size_t len)
4a8e6c33	78	{
ea707584	79	struct iio_dev *dev_info = dev_get_drvdata(dev);
39f3b32e	80	struct ad9832_state *st = iio_priv(dev_info);
ea707584	81	struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
4a8e6c33	82	int ret;
ea707584	83	long val;
4a8e6c33	84
ea707584	85	ret = strict_strtoul(buf, 10, &val);
4a8e6c33 CC	86	if (ret)
	87	goto error_ret;
	88
ea707584 MH	89	mutex_lock(&dev_info->mlock);
	90	switch (this_attr->address) {
	91	case AD9832_FREQ0HM:
	92	case AD9832_FREQ1HM:
	93	ret = ad9832_write_frequency(st, this_attr->address, val);
	94	break;
	95	case AD9832_PHASE0H:
	96	case AD9832_PHASE1H:
	97	case AD9832_PHASE2H:
	98	case AD9832_PHASE3H:
	99	ret = ad9832_write_phase(st, this_attr->address, val);
	100	break;
	101	case AD9832_PINCTRL_EN:
	102	if (val)
	103	st->ctrl_ss &= ~AD9832_SELSRC;
	104	else
	105	st->ctrl_ss \|= AD9832_SELSRC;
	106	st->data = cpu_to_be16((AD9832_CMD_SYNCSELSRC << CMD_SHIFT) \|
	107	st->ctrl_ss);
	108	ret = spi_sync(st->spi, &st->msg);
	109	break;
	110	case AD9832_FREQ_SYM:
	111	if (val == 1)
	112	st->ctrl_fp \|= AD9832_FREQ;
	113	else if (val == 0)
	114	st->ctrl_fp &= ~AD9832_FREQ;
	115	else {
	116	ret = -EINVAL;
	117	break;
	118	}
	119	st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) \|
	120	st->ctrl_fp);
	121	ret = spi_sync(st->spi, &st->msg);
	122	break;
	123	case AD9832_PHASE_SYM:
	124	if (val < 0 \|\| val > 3) {
	125	ret = -EINVAL;
	126	break;
	127	}
	128
	129	st->ctrl_fp &= ~AD9832_PHASE(3);
	130	st->ctrl_fp \|= AD9832_PHASE(val);
	131
	132	st->data = cpu_to_be16((AD9832_CMD_FPSELECT << CMD_SHIFT) \|
	133	st->ctrl_fp);
	134	ret = spi_sync(st->spi, &st->msg);
	135	break;
	136	case AD9832_OUTPUT_EN:
	137	if (val)
	138	st->ctrl_src &= ~(AD9832_RESET \| AD9832_SLEEP \|
	139	AD9832_CLR);
	140	else
	141	st->ctrl_src \|= AD9832_RESET;
	142
	143	st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) \|
	144	st->ctrl_src);
	145	ret = spi_sync(st->spi, &st->msg);
	146	break;
	147	default:
	148	ret = -ENODEV;
	149	}
	150	mutex_unlock(&dev_info->mlock);
4a8e6c33	151
ea707584 MH	152	error_ret:
	153	return ret ? ret : len;
	154	}
4a8e6c33	155
ea707584 MH	156	/**
	157	* see dds.h for further information
	158	*/
4a8e6c33	159
ea707584 MH	160	static IIO_DEV_ATTR_FREQ(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ0HM);
	161	static IIO_DEV_ATTR_FREQ(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_FREQ1HM);
	162	static IIO_DEV_ATTR_FREQSYMBOL(0, S_IWUSR, NULL, ad9832_write, AD9832_FREQ_SYM);
	163	static IIO_CONST_ATTR_FREQ_SCALE(0, "1"); /* 1Hz */
4a8e6c33	164
ea707584 MH	165	static IIO_DEV_ATTR_PHASE(0, 0, S_IWUSR, NULL, ad9832_write, AD9832_PHASE0H);
	166	static IIO_DEV_ATTR_PHASE(0, 1, S_IWUSR, NULL, ad9832_write, AD9832_PHASE1H);
	167	static IIO_DEV_ATTR_PHASE(0, 2, S_IWUSR, NULL, ad9832_write, AD9832_PHASE2H);
	168	static IIO_DEV_ATTR_PHASE(0, 3, S_IWUSR, NULL, ad9832_write, AD9832_PHASE3H);
	169	static IIO_DEV_ATTR_PHASESYMBOL(0, S_IWUSR, NULL,
	170	ad9832_write, AD9832_PHASE_SYM);
	171	static IIO_CONST_ATTR_PHASE_SCALE(0, "0.0015339808"); /* 2PI/2^12 rad*/
4a8e6c33	172
ea707584 MH	173	static IIO_DEV_ATTR_PINCONTROL_EN(0, S_IWUSR, NULL,
	174	ad9832_write, AD9832_PINCTRL_EN);
	175	static IIO_DEV_ATTR_OUT_ENABLE(0, S_IWUSR, NULL,
	176	ad9832_write, AD9832_OUTPUT_EN);
4a8e6c33	177
ea707584 MH	178	static struct attribute *ad9832_attributes[] = {
	179	&iio_dev_attr_dds0_freq0.dev_attr.attr,
	180	&iio_dev_attr_dds0_freq1.dev_attr.attr,
	181	&iio_const_attr_dds0_freq_scale.dev_attr.attr,
	182	&iio_dev_attr_dds0_phase0.dev_attr.attr,
	183	&iio_dev_attr_dds0_phase1.dev_attr.attr,
	184	&iio_dev_attr_dds0_phase2.dev_attr.attr,
	185	&iio_dev_attr_dds0_phase3.dev_attr.attr,
	186	&iio_const_attr_dds0_phase_scale.dev_attr.attr,
	187	&iio_dev_attr_dds0_pincontrol_en.dev_attr.attr,
	188	&iio_dev_attr_dds0_freqsymbol.dev_attr.attr,
	189	&iio_dev_attr_dds0_phasesymbol.dev_attr.attr,
	190	&iio_dev_attr_dds0_out_enable.dev_attr.attr,
ea707584 MH	191	NULL,
ea707584 MH	192	};
4a8e6c33	193
ea707584 MH	194	static const struct attribute_group ad9832_attribute_group = {
	195	.attrs = ad9832_attributes,
	196	};
4a8e6c33	197
6fe8135f JC	198	static const struct iio_info ad9832_info = {
	199	.attrs = &ad9832_attribute_group,
	200	.driver_module = THIS_MODULE,
	201	};
	202
4a8e6c33 CC	203	static int __devinit ad9832_probe(struct spi_device *spi)
4a8e6c33 CC	204	{
ea707584	205	struct ad9832_platform_data *pdata = spi->dev.platform_data;
39f3b32e	206	struct iio_dev *indio_dev;
4a8e6c33	207	struct ad9832_state *st;
39f3b32e	208	struct regulator *reg;
ea707584 MH	209	int ret;
	210
	211	if (!pdata) {
	212	dev_dbg(&spi->dev, "no platform data?\n");
	213	return -ENODEV;
	214	}
4a8e6c33	215
39f3b32e JC	216	reg = regulator_get(&spi->dev, "vcc");
	217	if (!IS_ERR(reg)) {
	218	ret = regulator_enable(reg);
ea707584 MH	219	if (ret)
	220	goto error_put_reg;
	221	}
	222
39f3b32e JC	223	indio_dev = iio_allocate_device(sizeof(*st));
39f3b32e JC	224	if (indio_dev == NULL) {
4a8e6c33	225	ret = -ENOMEM;
ea707584	226	goto error_disable_reg;
4a8e6c33	227	}
39f3b32e JC	228	spi_set_drvdata(spi, indio_dev);
	229	st = iio_priv(indio_dev);
	230	st->reg = reg;
	231	st->mclk = pdata->mclk;
	232	st->spi = spi;
4a8e6c33	233
39f3b32e JC	234	indio_dev->dev.parent = &spi->dev;
	235	indio_dev->name = spi_get_device_id(spi)->name;
	236	indio_dev->info = &ad9832_info;
	237	indio_dev->modes = INDIO_DIRECT_MODE;
ea707584 MH	238
	239	/* Setup default messages */
	240
	241	st->xfer.tx_buf = &st->data;
	242	st->xfer.len = 2;
	243
	244	spi_message_init(&st->msg);
	245	spi_message_add_tail(&st->xfer, &st->msg);
	246
	247	st->freq_xfer[0].tx_buf = &st->freq_data[0];
	248	st->freq_xfer[0].len = 2;
	249	st->freq_xfer[0].cs_change = 1;
	250	st->freq_xfer[1].tx_buf = &st->freq_data[1];
	251	st->freq_xfer[1].len = 2;
	252	st->freq_xfer[1].cs_change = 1;
	253	st->freq_xfer[2].tx_buf = &st->freq_data[2];
	254	st->freq_xfer[2].len = 2;
	255	st->freq_xfer[2].cs_change = 1;
	256	st->freq_xfer[3].tx_buf = &st->freq_data[3];
	257	st->freq_xfer[3].len = 2;
	258
	259	spi_message_init(&st->freq_msg);
	260	spi_message_add_tail(&st->freq_xfer[0], &st->freq_msg);
	261	spi_message_add_tail(&st->freq_xfer[1], &st->freq_msg);
	262	spi_message_add_tail(&st->freq_xfer[2], &st->freq_msg);
	263	spi_message_add_tail(&st->freq_xfer[3], &st->freq_msg);
	264
	265	st->phase_xfer[0].tx_buf = &st->phase_data[0];
	266	st->phase_xfer[0].len = 2;
	267	st->phase_xfer[0].cs_change = 1;
	268	st->phase_xfer[1].tx_buf = &st->phase_data[1];
	269	st->phase_xfer[1].len = 2;
	270
	271	spi_message_init(&st->phase_msg);
	272	spi_message_add_tail(&st->phase_xfer[0], &st->phase_msg);
	273	spi_message_add_tail(&st->phase_xfer[1], &st->phase_msg);
	274
	275	st->ctrl_src = AD9832_SLEEP \| AD9832_RESET \| AD9832_CLR;
	276	st->data = cpu_to_be16((AD9832_CMD_SLEEPRESCLR << CMD_SHIFT) \|
	277	st->ctrl_src);
	278	ret = spi_sync(st->spi, &st->msg);
	279	if (ret) {
	280	dev_err(&spi->dev, "device init failed\n");
	281	goto error_free_device;
	282	}
	283
	284	ret = ad9832_write_frequency(st, AD9832_FREQ0HM, pdata->freq0);
	285	if (ret)
	286	goto error_free_device;
	287
	288	ret = ad9832_write_frequency(st, AD9832_FREQ1HM, pdata->freq1);
	289	if (ret)
	290	goto error_free_device;
	291
	292	ret = ad9832_write_phase(st, AD9832_PHASE0H, pdata->phase0);
	293	if (ret)
	294	goto error_free_device;
	295
	296	ret = ad9832_write_phase(st, AD9832_PHASE1H, pdata->phase1);
	297	if (ret)
	298	goto error_free_device;
4a8e6c33	299
ea707584	300	ret = ad9832_write_phase(st, AD9832_PHASE2H, pdata->phase2);
4a8e6c33	301	if (ret)
ea707584 MH	302	goto error_free_device;
	303
	304	ret = ad9832_write_phase(st, AD9832_PHASE3H, pdata->phase3);
	305	if (ret)
	306	goto error_free_device;
	307
39f3b32e	308	ret = iio_device_register(indio_dev);
ea707584 MH	309	if (ret)
	310	goto error_free_device;
	311
4a8e6c33 CC	312	return 0;
4a8e6c33 CC	313
ea707584	314	error_free_device:
39f3b32e	315	iio_free_device(indio_dev);
ea707584	316	error_disable_reg:
39f3b32e JC	317	if (!IS_ERR(reg))
39f3b32e JC	318	regulator_disable(reg);
ea707584	319	error_put_reg:
39f3b32e JC	320	if (!IS_ERR(reg))
	321	regulator_put(reg);
	322
4a8e6c33 CC	323	return ret;
	324	}
	325
	326	static int __devexit ad9832_remove(struct spi_device *spi)
	327	{
39f3b32e JC	328	struct iio_dev *indio_dev = spi_get_drvdata(spi);
	329	struct ad9832_state *st = iio_priv(indio_dev);
	330	struct regulator *reg = st->reg;
	331
	332	iio_device_unregister(indio_dev);
	333	if (!IS_ERR(reg)) {
	334	regulator_disable(reg);
	335	regulator_put(reg);
ea707584	336	}
4a8e6c33 CC	337	return 0;
	338	}
	339
ea707584 MH	340	static const struct spi_device_id ad9832_id[] = {
	341	{"ad9832", 0},
	342	{"ad9835", 0},
	343	{}
	344	};
	345
4a8e6c33 CC	346	static struct spi_driver ad9832_driver = {
4a8e6c33 CC	347	.driver = {
ea707584 MH	348	.name = "ad9832",
	349	.bus = &spi_bus_type,
	350	.owner = THIS_MODULE,
4a8e6c33	351	},
ea707584 MH	352	.probe = ad9832_probe,
	353	.remove = __devexit_p(ad9832_remove),
	354	.id_table = ad9832_id,
4a8e6c33 CC	355	};
4a8e6c33 CC	356
ea707584	357	static int __init ad9832_init(void)
4a8e6c33 CC	358	{
	359	return spi_register_driver(&ad9832_driver);
	360	}
ea707584	361	module_init(ad9832_init);
4a8e6c33	362
ea707584	363	static void __exit ad9832_exit(void)
4a8e6c33 CC	364	{
	365	spi_unregister_driver(&ad9832_driver);
	366	}
ea707584	367	module_exit(ad9832_exit);
4a8e6c33	368
ea707584 MH	369	MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
ea707584 MH	370	MODULE_DESCRIPTION("Analog Devices AD9832/AD9835 DDS");
4a8e6c33	371	MODULE_LICENSE("GPL v2");
ea707584	372	MODULE_ALIAS("spi:ad9832");