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Merge tag 'pci-v3.15-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaa...
[deliverable/linux.git] / drivers / staging / iio / impedance-analyzer / ad5933.c
CommitLineData
f94aa354
MH		 1/*
2 * AD5933 AD5934 Impedance Converter, Network Analyzer
3 *
4 * Copyright 2011 Analog Devices Inc.
5 *
6 * Licensed under the GPL-2.
7 */
8
9#include <linux/interrupt.h>
10#include <linux/device.h>
11#include <linux/kernel.h>
12#include <linux/sysfs.h>
13#include <linux/i2c.h>
14#include <linux/regulator/consumer.h>
15#include <linux/slab.h>
16#include <linux/types.h>
17#include <linux/err.h>
18#include <linux/delay.h>
748b636c 19#include <linux/module.h>
f94aa354
MH		 20#include <asm/div64.h>
21
06458e27
JC		 22#include <linux/iio/iio.h>
23#include <linux/iio/sysfs.h>
24#include <linux/iio/buffer.h>
032658a4 25#include <linux/iio/kfifo_buf.h>
f94aa354
MH		 26
27#include "ad5933.h"
28
29/* AD5933/AD5934 Registers */
30#define AD5933_REG_CONTROL_HB 0x80 /* R/W, 2 bytes */
31#define AD5933_REG_CONTROL_LB 0x81 /* R/W, 2 bytes */
32#define AD5933_REG_FREQ_START 0x82 /* R/W, 3 bytes */
33#define AD5933_REG_FREQ_INC 0x85 /* R/W, 3 bytes */
34#define AD5933_REG_INC_NUM 0x88 /* R/W, 2 bytes, 9 bit */
35#define AD5933_REG_SETTLING_CYCLES 0x8A /* R/W, 2 bytes */
36#define AD5933_REG_STATUS 0x8F /* R, 1 byte */
37#define AD5933_REG_TEMP_DATA 0x92 /* R, 2 bytes*/
38#define AD5933_REG_REAL_DATA 0x94 /* R, 2 bytes*/
39#define AD5933_REG_IMAG_DATA 0x96 /* R, 2 bytes*/
40
41/* AD5933_REG_CONTROL_HB Bits */
42#define AD5933_CTRL_INIT_START_FREQ (0x1 << 4)
43#define AD5933_CTRL_START_SWEEP (0x2 << 4)
44#define AD5933_CTRL_INC_FREQ (0x3 << 4)
45#define AD5933_CTRL_REPEAT_FREQ (0x4 << 4)
46#define AD5933_CTRL_MEASURE_TEMP (0x9 << 4)
47#define AD5933_CTRL_POWER_DOWN (0xA << 4)
48#define AD5933_CTRL_STANDBY (0xB << 4)
49
50#define AD5933_CTRL_RANGE_2000mVpp (0x0 << 1)
51#define AD5933_CTRL_RANGE_200mVpp (0x1 << 1)
52#define AD5933_CTRL_RANGE_400mVpp (0x2 << 1)
53#define AD5933_CTRL_RANGE_1000mVpp (0x3 << 1)
54#define AD5933_CTRL_RANGE(x) ((x) << 1)
55
56#define AD5933_CTRL_PGA_GAIN_1 (0x1 << 0)
57#define AD5933_CTRL_PGA_GAIN_5 (0x0 << 0)
58
59/* AD5933_REG_CONTROL_LB Bits */
60#define AD5933_CTRL_RESET (0x1 << 4)
61#define AD5933_CTRL_INT_SYSCLK (0x0 << 3)
62#define AD5933_CTRL_EXT_SYSCLK (0x1 << 3)
63
64/* AD5933_REG_STATUS Bits */
65#define AD5933_STAT_TEMP_VALID (0x1 << 0)
66#define AD5933_STAT_DATA_VALID (0x1 << 1)
67#define AD5933_STAT_SWEEP_DONE (0x1 << 2)
68
69/* I2C Block Commands */
70#define AD5933_I2C_BLOCK_WRITE 0xA0
71#define AD5933_I2C_BLOCK_READ 0xA1
72#define AD5933_I2C_ADDR_POINTER 0xB0
73
74/* Device Specs */
75#define AD5933_INT_OSC_FREQ_Hz 16776000
76#define AD5933_MAX_OUTPUT_FREQ_Hz 100000
77#define AD5933_MAX_RETRIES 100
78
79#define AD5933_OUT_RANGE 1
80#define AD5933_OUT_RANGE_AVAIL 2
81#define AD5933_OUT_SETTLING_CYCLES 3
82#define AD5933_IN_PGA_GAIN 4
83#define AD5933_IN_PGA_GAIN_AVAIL 5
84#define AD5933_FREQ_POINTS 6
85
86#define AD5933_POLL_TIME_ms 10
87#define AD5933_INIT_EXCITATION_TIME_ms 100
88
89struct ad5933_state {
90 struct i2c_client *client;
91 struct regulator *reg;
92 struct ad5933_platform_data *pdata;
93 struct delayed_work work;
94 unsigned long mclk_hz;
95 unsigned char ctrl_hb;
96 unsigned char ctrl_lb;
97 unsigned range_avail[4];
98 unsigned short vref_mv;
99 unsigned short settling_cycles;
100 unsigned short freq_points;
101 unsigned freq_start;
102 unsigned freq_inc;
103 unsigned state;
104 unsigned poll_time_jiffies;
105};
106
107static struct ad5933_platform_data ad5933_default_pdata = {
108 .vref_mv = 3300,
109};
110
f4e4b955 111static const struct iio_chan_spec ad5933_channels[] = {
cdacc05b
JC		 112 {
113 .type = IIO_TEMP,
114 .indexed = 1,
cdacc05b 115 .channel = 0,
da200c2b 116 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED),
cdacc05b
JC		 117 .address = AD5933_REG_TEMP_DATA,
118 .scan_type = {
119 .sign = 's',
120 .realbits = 14,
121 .storagebits = 16,
122 },
123 }, { /* Ring Channels */
124 .type = IIO_VOLTAGE,
125 .indexed = 1,
126 .channel = 0,
127 .extend_name = "real_raw",
da200c2b
JC		 128 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
129 BIT(IIO_CHAN_INFO_SCALE),
cdacc05b
JC		 130 .address = AD5933_REG_REAL_DATA,
131 .scan_index = 0,
132 .scan_type = {
133 .sign = 's',
134 .realbits = 16,
135 .storagebits = 16,
136 },
137 }, {
138 .type = IIO_VOLTAGE,
139 .indexed = 1,
140 .channel = 0,
141 .extend_name = "imag_raw",
da200c2b
JC		 142 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
143 BIT(IIO_CHAN_INFO_SCALE),
cdacc05b
JC		 144 .address = AD5933_REG_IMAG_DATA,
145 .scan_index = 1,
146 .scan_type = {
147 .sign = 's',
148 .realbits = 16,
149 .storagebits = 16,
150 },
151 },
f94aa354
MH		 152};
153
154static int ad5933_i2c_write(struct i2c_client *client,
155 u8 reg, u8 len, u8 *data)
156{
157 int ret;
158
159 while (len--) {
160 ret = i2c_smbus_write_byte_data(client, reg++, *data++);
161 if (ret < 0) {
162 dev_err(&client->dev, "I2C write error\n");
163 return ret;
164 }
165 }
166 return 0;
167}
168
169static int ad5933_i2c_read(struct i2c_client *client,
170 u8 reg, u8 len, u8 *data)
171{
172 int ret;
173
174 while (len--) {
175 ret = i2c_smbus_read_byte_data(client, reg++);
176 if (ret < 0) {
177 dev_err(&client->dev, "I2C read error\n");
178 return ret;
179 }
180 *data++ = ret;
181 }
182 return 0;
183}
184
185static int ad5933_cmd(struct ad5933_state *st, unsigned char cmd)
186{
187 unsigned char dat = st->ctrl_hb | cmd;
188
189 return ad5933_i2c_write(st->client,
190 AD5933_REG_CONTROL_HB, 1, &dat);
191}
192
193static int ad5933_reset(struct ad5933_state *st)
194{
195 unsigned char dat = st->ctrl_lb | AD5933_CTRL_RESET;
196 return ad5933_i2c_write(st->client,
197 AD5933_REG_CONTROL_LB, 1, &dat);
198}
199
200static int ad5933_wait_busy(struct ad5933_state *st, unsigned char event)
201{
202 unsigned char val, timeout = AD5933_MAX_RETRIES;
203 int ret;
204
205 while (timeout--) {
206 ret = ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &val);
207 if (ret < 0)
208 return ret;
209 if (val & event)
210 return val;
211 cpu_relax();
212 mdelay(1);
213 }
214
215 return -EAGAIN;
216}
217
218static int ad5933_set_freq(struct ad5933_state *st,
219 unsigned reg, unsigned long freq)
220{
221 unsigned long long freqreg;
222 union {
223 u32 d32;
224 u8 d8[4];
225 } dat;
226
227 freqreg = (u64) freq * (u64) (1 << 27);
228 do_div(freqreg, st->mclk_hz / 4);
229
230 switch (reg) {
231 case AD5933_REG_FREQ_START:
232 st->freq_start = freq;
233 break;
234 case AD5933_REG_FREQ_INC:
235 st->freq_inc = freq;
236 break;
237 default:
238 return -EINVAL;
239 }
240
241 dat.d32 = cpu_to_be32(freqreg);
242 return ad5933_i2c_write(st->client, reg, 3, &dat.d8[1]);
243}
244
245static int ad5933_setup(struct ad5933_state *st)
246{
247 unsigned short dat;
248 int ret;
249
250 ret = ad5933_reset(st);
251 if (ret < 0)
252 return ret;
253
254 ret = ad5933_set_freq(st, AD5933_REG_FREQ_START, 10000);
255 if (ret < 0)
256 return ret;
257
258 ret = ad5933_set_freq(st, AD5933_REG_FREQ_INC, 200);
259 if (ret < 0)
260 return ret;
261
262 st->settling_cycles = 10;
263 dat = cpu_to_be16(st->settling_cycles);
264
265 ret = ad5933_i2c_write(st->client,
266 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
267 if (ret < 0)
268 return ret;
269
270 st->freq_points = 100;
271 dat = cpu_to_be16(st->freq_points);
272
273 return ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2, (u8 *)&dat);
274}
275
276static void ad5933_calc_out_ranges(struct ad5933_state *st)
277{
278 int i;
279 unsigned normalized_3v3[4] = {1980, 198, 383, 970};
280
281 for (i = 0; i < 4; i++)
282 st->range_avail[i] = normalized_3v3[i] * st->vref_mv / 3300;
283
284}
285
286/*
287 * handles: AD5933_REG_FREQ_START and AD5933_REG_FREQ_INC
288 */
289
290static ssize_t ad5933_show_frequency(struct device *dev,
291 struct device_attribute *attr,
292 char *buf)
293{
ba86dc46 294 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
638e59fc 295 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 296 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
297 int ret;
298 unsigned long long freqreg;
299 union {
300 u32 d32;
301 u8 d8[4];
302 } dat;
303
638e59fc 304 mutex_lock(&indio_dev->mlock);
f94aa354 305 ret = ad5933_i2c_read(st->client, this_attr->address, 3, &dat.d8[1]);
638e59fc 306 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 307 if (ret < 0)
308 return ret;
309
310 freqreg = be32_to_cpu(dat.d32) & 0xFFFFFF;
311
312 freqreg = (u64) freqreg * (u64) (st->mclk_hz / 4);
313 do_div(freqreg, 1 << 27);
314
315 return sprintf(buf, "%d\n", (int) freqreg);
316}
317
318static ssize_t ad5933_store_frequency(struct device *dev,
319 struct device_attribute *attr,
320 const char *buf,
321 size_t len)
322{
ba86dc46 323 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
638e59fc 324 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354 325 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
e5e26dd5 326 unsigned long val;
f94aa354
MH		 327 int ret;
328
e5e26dd5 329 ret = kstrtoul(buf, 10, &val);
f94aa354
MH		 330 if (ret)
331 return ret;
332
333 if (val > AD5933_MAX_OUTPUT_FREQ_Hz)
334 return -EINVAL;
335
638e59fc 336 mutex_lock(&indio_dev->mlock);
f94aa354 337 ret = ad5933_set_freq(st, this_attr->address, val);
638e59fc 338 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 339
340 return ret ? ret : len;
341}
342
322c9563 343static IIO_DEVICE_ATTR(out_voltage0_freq_start, S_IRUGO | S_IWUSR,
f94aa354
MH		 344 ad5933_show_frequency,
345 ad5933_store_frequency,
346 AD5933_REG_FREQ_START);
347
322c9563 348static IIO_DEVICE_ATTR(out_voltage0_freq_increment, S_IRUGO | S_IWUSR,
f94aa354
MH		 349 ad5933_show_frequency,
350 ad5933_store_frequency,
351 AD5933_REG_FREQ_INC);
352
353static ssize_t ad5933_show(struct device *dev,
354 struct device_attribute *attr,
355 char *buf)
356{
ba86dc46 357 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
638e59fc 358 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 359 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
360 int ret = 0, len = 0;
361
638e59fc 362 mutex_lock(&indio_dev->mlock);
e15fbc91 363 switch ((u32) this_attr->address) {
f94aa354
MH		 364 case AD5933_OUT_RANGE:
365 len = sprintf(buf, "%d\n",
366 st->range_avail[(st->ctrl_hb >> 1) & 0x3]);
367 break;
368 case AD5933_OUT_RANGE_AVAIL:
369 len = sprintf(buf, "%d %d %d %d\n", st->range_avail[0],
370 st->range_avail[3], st->range_avail[2],
371 st->range_avail[1]);
372 break;
373 case AD5933_OUT_SETTLING_CYCLES:
374 len = sprintf(buf, "%d\n", st->settling_cycles);
375 break;
376 case AD5933_IN_PGA_GAIN:
377 len = sprintf(buf, "%s\n",
378 (st->ctrl_hb & AD5933_CTRL_PGA_GAIN_1) ?
379 "1" : "0.2");
380 break;
381 case AD5933_IN_PGA_GAIN_AVAIL:
382 len = sprintf(buf, "1 0.2\n");
383 break;
384 case AD5933_FREQ_POINTS:
385 len = sprintf(buf, "%d\n", st->freq_points);
386 break;
387 default:
388 ret = -EINVAL;
389 }
390
638e59fc 391 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 392 return ret ? ret : len;
393}
394
395static ssize_t ad5933_store(struct device *dev,
396 struct device_attribute *attr,
397 const char *buf,
398 size_t len)
399{
ba86dc46 400 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
638e59fc 401 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354 402 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
e5e26dd5 403 u16 val;
f94aa354
MH		 404 int i, ret = 0;
405 unsigned short dat;
406
407 if (this_attr->address != AD5933_IN_PGA_GAIN) {
e5e26dd5 408 ret = kstrtou16(buf, 10, &val);
f94aa354
MH		 409 if (ret)
410 return ret;
411 }
412
638e59fc 413 mutex_lock(&indio_dev->mlock);
e15fbc91 414 switch ((u32) this_attr->address) {
f94aa354
MH		 415 case AD5933_OUT_RANGE:
416 for (i = 0; i < 4; i++)
417 if (val == st->range_avail[i]) {
418 st->ctrl_hb &= ~AD5933_CTRL_RANGE(0x3);
419 st->ctrl_hb |= AD5933_CTRL_RANGE(i);
420 ret = ad5933_cmd(st, 0);
421 break;
422 }
423 ret = -EINVAL;
424 break;
425 case AD5933_IN_PGA_GAIN:
426 if (sysfs_streq(buf, "1")) {
427 st->ctrl_hb |= AD5933_CTRL_PGA_GAIN_1;
428 } else if (sysfs_streq(buf, "0.2")) {
429 st->ctrl_hb &= ~AD5933_CTRL_PGA_GAIN_1;
430 } else {
431 ret = -EINVAL;
432 break;
433 }
434 ret = ad5933_cmd(st, 0);
435 break;
436 case AD5933_OUT_SETTLING_CYCLES:
e5e26dd5 437 val = clamp(val, (u16)0, (u16)0x7FF);
f94aa354
MH		 438 st->settling_cycles = val;
439
440 /* 2x, 4x handling, see datasheet */
441 if (val > 511)
442 val = (val >> 1) | (1 << 9);
443 else if (val > 1022)
444 val = (val >> 2) | (3 << 9);
445
446 dat = cpu_to_be16(val);
447 ret = ad5933_i2c_write(st->client,
448 AD5933_REG_SETTLING_CYCLES, 2, (u8 *)&dat);
449 break;
450 case AD5933_FREQ_POINTS:
e5e26dd5 451 val = clamp(val, (u16)0, (u16)511);
f94aa354
MH		 452 st->freq_points = val;
453
454 dat = cpu_to_be16(val);
455 ret = ad5933_i2c_write(st->client, AD5933_REG_INC_NUM, 2,
456 (u8 *)&dat);
457 break;
458 default:
459 ret = -EINVAL;
460 }
461
638e59fc 462 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 463 return ret ? ret : len;
464}
465
322c9563 466static IIO_DEVICE_ATTR(out_voltage0_scale, S_IRUGO | S_IWUSR,
f94aa354
MH		 467 ad5933_show,
468 ad5933_store,
469 AD5933_OUT_RANGE);
470
322c9563 471static IIO_DEVICE_ATTR(out_voltage0_scale_available, S_IRUGO,
f94aa354
MH		 472 ad5933_show,
473 NULL,
474 AD5933_OUT_RANGE_AVAIL);
475
322c9563 476static IIO_DEVICE_ATTR(in_voltage0_scale, S_IRUGO | S_IWUSR,
f94aa354
MH		 477 ad5933_show,
478 ad5933_store,
479 AD5933_IN_PGA_GAIN);
480
322c9563 481static IIO_DEVICE_ATTR(in_voltage0_scale_available, S_IRUGO,
f94aa354
MH		 482 ad5933_show,
483 NULL,
484 AD5933_IN_PGA_GAIN_AVAIL);
485
322c9563 486static IIO_DEVICE_ATTR(out_voltage0_freq_points, S_IRUGO | S_IWUSR,
f94aa354
MH		 487 ad5933_show,
488 ad5933_store,
489 AD5933_FREQ_POINTS);
490
322c9563 491static IIO_DEVICE_ATTR(out_voltage0_settling_cycles, S_IRUGO | S_IWUSR,
f94aa354
MH		 492 ad5933_show,
493 ad5933_store,
494 AD5933_OUT_SETTLING_CYCLES);
495
496/* note:
497 * ideally we would handle the scale attributes via the iio_info
498 * (read|write)_raw methods, however this part is a untypical since we
499 * don't create dedicated sysfs channel attributes for out0 and in0.
500 */
501static struct attribute *ad5933_attributes[] = {
322c9563
JC		 502 &iio_dev_attr_out_voltage0_scale.dev_attr.attr,
503 &iio_dev_attr_out_voltage0_scale_available.dev_attr.attr,
504 &iio_dev_attr_out_voltage0_freq_start.dev_attr.attr,
505 &iio_dev_attr_out_voltage0_freq_increment.dev_attr.attr,
506 &iio_dev_attr_out_voltage0_freq_points.dev_attr.attr,
507 &iio_dev_attr_out_voltage0_settling_cycles.dev_attr.attr,
508 &iio_dev_attr_in_voltage0_scale.dev_attr.attr,
509 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
f94aa354
MH		 510 NULL
511};
512
513static const struct attribute_group ad5933_attribute_group = {
514 .attrs = ad5933_attributes,
515};
516
638e59fc 517static int ad5933_read_raw(struct iio_dev *indio_dev,
f94aa354
MH		 518 struct iio_chan_spec const *chan,
519 int *val,
520 int *val2,
521 long m)
522{
638e59fc 523 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 524 unsigned short dat;
525 int ret = -EINVAL;
526
638e59fc 527 mutex_lock(&indio_dev->mlock);
f94aa354 528 switch (m) {
967d3fe0
JC		 529 case IIO_CHAN_INFO_RAW:
530 case IIO_CHAN_INFO_PROCESSED:
638e59fc 531 if (iio_buffer_enabled(indio_dev)) {
f94aa354
MH		 532 ret = -EBUSY;
533 goto out;
534 }
535 ret = ad5933_cmd(st, AD5933_CTRL_MEASURE_TEMP);
536 if (ret < 0)
537 goto out;
538 ret = ad5933_wait_busy(st, AD5933_STAT_TEMP_VALID);
539 if (ret < 0)
540 goto out;
541
542 ret = ad5933_i2c_read(st->client,
543 AD5933_REG_TEMP_DATA, 2,
544 (u8 *)&dat);
545 if (ret < 0)
546 goto out;
638e59fc 547 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 548 ret = be16_to_cpu(dat);
549 /* Temp in Milli degrees Celsius */
550 if (ret < 8192)
551 *val = ret * 1000 / 32;
552 else
553 *val = (ret - 16384) * 1000 / 32;
554
555 return IIO_VAL_INT;
556 }
557
558out:
638e59fc 559 mutex_unlock(&indio_dev->mlock);
f94aa354
MH		 560 return ret;
561}
562
563static const struct iio_info ad5933_info = {
564 .read_raw = &ad5933_read_raw,
565 .attrs = &ad5933_attribute_group,
566 .driver_module = THIS_MODULE,
567};
568
569static int ad5933_ring_preenable(struct iio_dev *indio_dev)
570{
571 struct ad5933_state *st = iio_priv(indio_dev);
f94aa354
MH		 572 int ret;
573
550268ca 574 if (bitmap_empty(indio_dev->active_scan_mask, indio_dev->masklength))
f94aa354
MH		 575 return -EINVAL;
576
f94aa354
MH		 577 ret = ad5933_reset(st);
578 if (ret < 0)
579 return ret;
580
581 ret = ad5933_cmd(st, AD5933_CTRL_STANDBY);
582 if (ret < 0)
583 return ret;
584
585 ret = ad5933_cmd(st, AD5933_CTRL_INIT_START_FREQ);
586 if (ret < 0)
587 return ret;
588
589 st->state = AD5933_CTRL_INIT_START_FREQ;
590
591 return 0;
592}
593
594static int ad5933_ring_postenable(struct iio_dev *indio_dev)
595{
596 struct ad5933_state *st = iio_priv(indio_dev);
597
598 /* AD5933_CTRL_INIT_START_FREQ:
599 * High Q complex circuits require a long time to reach steady state.
600 * To facilitate the measurement of such impedances, this mode allows
601 * the user full control of the settling time requirement before
602 * entering start frequency sweep mode where the impedance measurement
603 * takes place. In this mode the impedance is excited with the
604 * programmed start frequency (ad5933_ring_preenable),
605 * but no measurement takes place.
606 */
607
608 schedule_delayed_work(&st->work,
609 msecs_to_jiffies(AD5933_INIT_EXCITATION_TIME_ms));
610 return 0;
611}
612
613static int ad5933_ring_postdisable(struct iio_dev *indio_dev)
614{
615 struct ad5933_state *st = iio_priv(indio_dev);
616
617 cancel_delayed_work_sync(&st->work);
618 return ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
619}
620
14555b14 621static const struct iio_buffer_setup_ops ad5933_ring_setup_ops = {
f94aa354
MH		 622 .preenable = &ad5933_ring_preenable,
623 .postenable = &ad5933_ring_postenable,
624 .postdisable = &ad5933_ring_postdisable,
625};
626
627static int ad5933_register_ring_funcs_and_init(struct iio_dev *indio_dev)
628{
9e69c935
LPC		 629 struct iio_buffer *buffer;
630
631 buffer = iio_kfifo_allocate(indio_dev);
e9ed104d 632 if (!buffer)
f94aa354
MH		 633 return -ENOMEM;
634
9e69c935
LPC		 635 iio_device_attach_buffer(indio_dev, buffer);
636
f94aa354 637 /* Ring buffer functions - here trigger setup related */
1612244f 638 indio_dev->setup_ops = &ad5933_ring_setup_ops;
f94aa354 639
ec3afa40 640 indio_dev->modes |= INDIO_BUFFER_HARDWARE;
f94aa354
MH		 641
642 return 0;
643}
644
645static void ad5933_work(struct work_struct *work)
646{
647 struct ad5933_state *st = container_of(work,
648 struct ad5933_state, work.work);
649 struct iio_dev *indio_dev = i2c_get_clientdata(st->client);
f94aa354
MH		 650 signed short buf[2];
651 unsigned char status;
652
653 mutex_lock(&indio_dev->mlock);
654 if (st->state == AD5933_CTRL_INIT_START_FREQ) {
655 /* start sweep */
656 ad5933_cmd(st, AD5933_CTRL_START_SWEEP);
657 st->state = AD5933_CTRL_START_SWEEP;
658 schedule_delayed_work(&st->work, st->poll_time_jiffies);
659 mutex_unlock(&indio_dev->mlock);
660 return;
661 }
662
663 ad5933_i2c_read(st->client, AD5933_REG_STATUS, 1, &status);
664
665 if (status & AD5933_STAT_DATA_VALID) {
550268ca
JC		 666 int scan_count = bitmap_weight(indio_dev->active_scan_mask,
667 indio_dev->masklength);
f94aa354 668 ad5933_i2c_read(st->client,
550268ca 669 test_bit(1, indio_dev->active_scan_mask) ?
f94aa354 670 AD5933_REG_REAL_DATA : AD5933_REG_IMAG_DATA,
550268ca 671 scan_count * 2, (u8 *)buf);
f94aa354 672
550268ca 673 if (scan_count == 2) {
f94aa354
MH		 674 buf[0] = be16_to_cpu(buf[0]);
675 buf[1] = be16_to_cpu(buf[1]);
676 } else {
677 buf[0] = be16_to_cpu(buf[0]);
678 }
2432e1ae 679 iio_push_to_buffers(indio_dev, buf);
f94aa354
MH		 680 } else {
681 /* no data available - try again later */
682 schedule_delayed_work(&st->work, st->poll_time_jiffies);
683 mutex_unlock(&indio_dev->mlock);
684 return;
685 }
686
687 if (status & AD5933_STAT_SWEEP_DONE) {
688 /* last sample received - power down do nothing until
689 * the ring enable is toggled */
690 ad5933_cmd(st, AD5933_CTRL_POWER_DOWN);
691 } else {
692 /* we just received a valid datum, move on to the next */
693 ad5933_cmd(st, AD5933_CTRL_INC_FREQ);
694 schedule_delayed_work(&st->work, st->poll_time_jiffies);
695 }
696
697 mutex_unlock(&indio_dev->mlock);
698}
699
4ae1c61f 700static int ad5933_probe(struct i2c_client *client,
f94aa354
MH		 701 const struct i2c_device_id *id)
702{
26d25ae3 703 int ret, voltage_uv = 0;
f94aa354
MH		 704 struct ad5933_platform_data *pdata = client->dev.platform_data;
705 struct ad5933_state *st;
53703a49
SK		 706 struct iio_dev *indio_dev;
707
708 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*st));
f94aa354
MH		 709 if (indio_dev == NULL)
710 return -ENOMEM;
711
712 st = iio_priv(indio_dev);
713 i2c_set_clientdata(client, indio_dev);
714 st->client = client;
715
716 if (!pdata)
717 st->pdata = &ad5933_default_pdata;
718 else
719 st->pdata = pdata;
720
53703a49 721 st->reg = devm_regulator_get(&client->dev, "vcc");
f94aa354
MH		 722 if (!IS_ERR(st->reg)) {
723 ret = regulator_enable(st->reg);
724 if (ret)
53703a49 725 return ret;
f94aa354
MH		 726 voltage_uv = regulator_get_voltage(st->reg);
727 }
728
729 if (voltage_uv)
730 st->vref_mv = voltage_uv / 1000;
731 else
732 st->vref_mv = st->pdata->vref_mv;
733
734 if (st->pdata->ext_clk_Hz) {
735 st->mclk_hz = st->pdata->ext_clk_Hz;
736 st->ctrl_lb = AD5933_CTRL_EXT_SYSCLK;
737 } else {
738 st->mclk_hz = AD5933_INT_OSC_FREQ_Hz;
739 st->ctrl_lb = AD5933_CTRL_INT_SYSCLK;
740 }
741
742 ad5933_calc_out_ranges(st);
743 INIT_DELAYED_WORK(&st->work, ad5933_work);
744 st->poll_time_jiffies = msecs_to_jiffies(AD5933_POLL_TIME_ms);
745
746 indio_dev->dev.parent = &client->dev;
747 indio_dev->info = &ad5933_info;
748 indio_dev->name = id->name;
749 indio_dev->modes = INDIO_DIRECT_MODE;
750 indio_dev->channels = ad5933_channels;
751 indio_dev->num_channels = 1; /* only register temp0_input */
752
753 ret = ad5933_register_ring_funcs_and_init(indio_dev);
754 if (ret)
755 goto error_disable_reg;
756
f94aa354 757 /* skip temp0_input, register in0_(real|imag)_raw */
14555b14 758 ret = iio_buffer_register(indio_dev, &ad5933_channels[1], 2);
f94aa354
MH		 759 if (ret)
760 goto error_unreg_ring;
761
762 /* enable both REAL and IMAG channels by default */
f79a9098
JC		 763 iio_scan_mask_set(indio_dev, indio_dev->buffer, 0);
764 iio_scan_mask_set(indio_dev, indio_dev->buffer, 1);
f94aa354
MH		 765
766 ret = ad5933_setup(st);
767 if (ret)
768 goto error_uninitialize_ring;
769
26d25ae3
JC		 770 ret = iio_device_register(indio_dev);
771 if (ret)
772 goto error_uninitialize_ring;
773
f94aa354
MH		 774 return 0;
775
776error_uninitialize_ring:
14555b14 777 iio_buffer_unregister(indio_dev);
f94aa354 778error_unreg_ring:
032658a4 779 iio_kfifo_free(indio_dev->buffer);
f94aa354
MH		 780error_disable_reg:
781 if (!IS_ERR(st->reg))
782 regulator_disable(st->reg);
f94aa354
MH		 783
784 return ret;
785}
786
447d4f29 787static int ad5933_remove(struct i2c_client *client)
f94aa354
MH		 788{
789 struct iio_dev *indio_dev = i2c_get_clientdata(client);
790 struct ad5933_state *st = iio_priv(indio_dev);
791
d2fffd6c 792 iio_device_unregister(indio_dev);
14555b14 793 iio_buffer_unregister(indio_dev);
032658a4 794 iio_kfifo_free(indio_dev->buffer);
53703a49 795 if (!IS_ERR(st->reg))
f94aa354 796 regulator_disable(st->reg);
f94aa354
MH		 797
798 return 0;
799}
800
801static const struct i2c_device_id ad5933_id[] = {
802 { "ad5933", 0 },
803 { "ad5934", 0 },
804 {}
805};
806
807MODULE_DEVICE_TABLE(i2c, ad5933_id);
808
809static struct i2c_driver ad5933_driver = {
810 .driver = {
811 .name = "ad5933",
812 },
813 .probe = ad5933_probe,
e543acf0 814 .remove = ad5933_remove,
f94aa354
MH		 815 .id_table = ad5933_id,
816};
6e5af184 817module_i2c_driver(ad5933_driver);
f94aa354
MH		 818
819MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
820MODULE_DESCRIPTION("Analog Devices AD5933 Impedance Conv. Network Analyzer");
821MODULE_LICENSE("GPL v2");
Linux kernel - Deliverables
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