Commit | Line | Data |
---|---|---|
ac4c1a9b SH |
1 | /* |
2 | * i.MX drm driver - LVDS display bridge | |
3 | * | |
4 | * Copyright (C) 2012 Sascha Hauer, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
18 | * MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/module.h> | |
22 | #include <linux/clk.h> | |
17b5001b | 23 | #include <linux/component.h> |
ac4c1a9b SH |
24 | #include <drm/drmP.h> |
25 | #include <drm/drm_fb_helper.h> | |
26 | #include <drm/drm_crtc_helper.h> | |
27 | #include <linux/mfd/syscon.h> | |
28 | #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> | |
29 | #include <linux/of_address.h> | |
30 | #include <linux/of_device.h> | |
31 | #include <video/of_videomode.h> | |
32 | #include <linux/regmap.h> | |
33 | #include <linux/videodev2.h> | |
34 | ||
35 | #include "imx-drm.h" | |
36 | ||
37 | #define DRIVER_NAME "imx-ldb" | |
38 | ||
39 | #define LDB_CH0_MODE_EN_TO_DI0 (1 << 0) | |
40 | #define LDB_CH0_MODE_EN_TO_DI1 (3 << 0) | |
41 | #define LDB_CH0_MODE_EN_MASK (3 << 0) | |
42 | #define LDB_CH1_MODE_EN_TO_DI0 (1 << 2) | |
43 | #define LDB_CH1_MODE_EN_TO_DI1 (3 << 2) | |
44 | #define LDB_CH1_MODE_EN_MASK (3 << 2) | |
45 | #define LDB_SPLIT_MODE_EN (1 << 4) | |
46 | #define LDB_DATA_WIDTH_CH0_24 (1 << 5) | |
47 | #define LDB_BIT_MAP_CH0_JEIDA (1 << 6) | |
48 | #define LDB_DATA_WIDTH_CH1_24 (1 << 7) | |
49 | #define LDB_BIT_MAP_CH1_JEIDA (1 << 8) | |
50 | #define LDB_DI0_VS_POL_ACT_LOW (1 << 9) | |
51 | #define LDB_DI1_VS_POL_ACT_LOW (1 << 10) | |
52 | #define LDB_BGREF_RMODE_INT (1 << 15) | |
53 | ||
54 | #define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector) | |
55 | #define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder) | |
56 | ||
57 | struct imx_ldb; | |
58 | ||
59 | struct imx_ldb_channel { | |
60 | struct imx_ldb *ldb; | |
61 | struct drm_connector connector; | |
ac4c1a9b | 62 | struct drm_encoder encoder; |
1b3f7675 | 63 | struct device_node *child; |
ac4c1a9b SH |
64 | int chno; |
65 | void *edid; | |
66 | int edid_len; | |
67 | struct drm_display_mode mode; | |
68 | int mode_valid; | |
69 | }; | |
70 | ||
71 | struct bus_mux { | |
72 | int reg; | |
73 | int shift; | |
74 | int mask; | |
75 | }; | |
76 | ||
77 | struct imx_ldb { | |
78 | struct regmap *regmap; | |
79 | struct device *dev; | |
80 | struct imx_ldb_channel channel[2]; | |
81 | struct clk *clk[2]; /* our own clock */ | |
82 | struct clk *clk_sel[4]; /* parent of display clock */ | |
83 | struct clk *clk_pll[2]; /* upstream clock we can adjust */ | |
84 | u32 ldb_ctrl; | |
85 | const struct bus_mux *lvds_mux; | |
86 | }; | |
87 | ||
88 | static enum drm_connector_status imx_ldb_connector_detect( | |
89 | struct drm_connector *connector, bool force) | |
90 | { | |
91 | return connector_status_connected; | |
92 | } | |
93 | ||
ac4c1a9b SH |
94 | static int imx_ldb_connector_get_modes(struct drm_connector *connector) |
95 | { | |
96 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
97 | int num_modes = 0; | |
98 | ||
99 | if (imx_ldb_ch->edid) { | |
100 | drm_mode_connector_update_edid_property(connector, | |
101 | imx_ldb_ch->edid); | |
102 | num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid); | |
103 | } | |
104 | ||
105 | if (imx_ldb_ch->mode_valid) { | |
106 | struct drm_display_mode *mode; | |
107 | ||
108 | mode = drm_mode_create(connector->dev); | |
109 | drm_mode_copy(mode, &imx_ldb_ch->mode); | |
110 | mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED; | |
111 | drm_mode_probed_add(connector, mode); | |
112 | num_modes++; | |
113 | } | |
114 | ||
115 | return num_modes; | |
116 | } | |
117 | ||
ac4c1a9b SH |
118 | static struct drm_encoder *imx_ldb_connector_best_encoder( |
119 | struct drm_connector *connector) | |
120 | { | |
121 | struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector); | |
122 | ||
123 | return &imx_ldb_ch->encoder; | |
124 | } | |
125 | ||
126 | static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode) | |
127 | { | |
128 | } | |
129 | ||
130 | static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder, | |
131 | const struct drm_display_mode *mode, | |
132 | struct drm_display_mode *adjusted_mode) | |
133 | { | |
134 | return true; | |
135 | } | |
136 | ||
137 | static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno, | |
138 | unsigned long serial_clk, unsigned long di_clk) | |
139 | { | |
140 | int ret; | |
141 | ||
142 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
143 | clk_get_rate(ldb->clk_pll[chno]), serial_clk); | |
144 | clk_set_rate(ldb->clk_pll[chno], serial_clk); | |
145 | ||
146 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
147 | clk_get_rate(ldb->clk_pll[chno])); | |
148 | ||
149 | dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__, | |
150 | clk_get_rate(ldb->clk[chno]), | |
151 | (long int)di_clk); | |
152 | clk_set_rate(ldb->clk[chno], di_clk); | |
153 | ||
154 | dev_dbg(ldb->dev, "%s after: %ld\n", __func__, | |
155 | clk_get_rate(ldb->clk[chno])); | |
156 | ||
157 | /* set display clock mux to LDB input clock */ | |
158 | ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]); | |
49f4a9c8 | 159 | if (ret) |
ac4c1a9b | 160 | dev_err(ldb->dev, "unable to set di%d parent clock to ldb_di%d\n", mux, chno); |
ac4c1a9b SH |
161 | } |
162 | ||
163 | static void imx_ldb_encoder_prepare(struct drm_encoder *encoder) | |
164 | { | |
165 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
166 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
167 | struct drm_display_mode *mode = &encoder->crtc->mode; | |
000d73fc | 168 | u32 pixel_fmt; |
ac4c1a9b SH |
169 | unsigned long serial_clk; |
170 | unsigned long di_clk = mode->clock * 1000; | |
e76171b0 | 171 | int mux = imx_drm_encoder_get_mux_id(encoder); |
ac4c1a9b SH |
172 | |
173 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { | |
174 | /* dual channel LVDS mode */ | |
175 | serial_clk = 3500UL * mode->clock; | |
176 | imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk); | |
177 | imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk); | |
178 | } else { | |
179 | serial_clk = 7000UL * mode->clock; | |
180 | imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk, di_clk); | |
181 | } | |
182 | ||
000d73fc MN |
183 | switch (imx_ldb_ch->chno) { |
184 | case 0: | |
185 | pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH0_24) ? | |
186 | V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; | |
187 | break; | |
188 | case 1: | |
189 | pixel_fmt = (ldb->ldb_ctrl & LDB_DATA_WIDTH_CH1_24) ? | |
190 | V4L2_PIX_FMT_RGB24 : V4L2_PIX_FMT_BGR666; | |
191 | break; | |
192 | default: | |
193 | dev_err(ldb->dev, "unable to config di%d panel format\n", | |
194 | imx_ldb_ch->chno); | |
195 | pixel_fmt = V4L2_PIX_FMT_RGB24; | |
196 | } | |
197 | ||
f2d66aad | 198 | imx_drm_panel_format(encoder, pixel_fmt); |
ac4c1a9b SH |
199 | } |
200 | ||
201 | static void imx_ldb_encoder_commit(struct drm_encoder *encoder) | |
202 | { | |
203 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
204 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
205 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
e76171b0 | 206 | int mux = imx_drm_encoder_get_mux_id(encoder); |
ac4c1a9b SH |
207 | |
208 | if (dual) { | |
209 | clk_prepare_enable(ldb->clk[0]); | |
210 | clk_prepare_enable(ldb->clk[1]); | |
211 | } | |
212 | ||
213 | if (imx_ldb_ch == &ldb->channel[0] || dual) { | |
214 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
215 | if (mux == 0 || ldb->lvds_mux) | |
216 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0; | |
217 | else if (mux == 1) | |
218 | ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1; | |
219 | } | |
220 | if (imx_ldb_ch == &ldb->channel[1] || dual) { | |
221 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
222 | if (mux == 1 || ldb->lvds_mux) | |
223 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1; | |
224 | else if (mux == 0) | |
225 | ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0; | |
226 | } | |
227 | ||
228 | if (ldb->lvds_mux) { | |
229 | const struct bus_mux *lvds_mux = NULL; | |
230 | ||
231 | if (imx_ldb_ch == &ldb->channel[0]) | |
232 | lvds_mux = &ldb->lvds_mux[0]; | |
233 | else if (imx_ldb_ch == &ldb->channel[1]) | |
234 | lvds_mux = &ldb->lvds_mux[1]; | |
235 | ||
236 | regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask, | |
237 | mux << lvds_mux->shift); | |
238 | } | |
239 | ||
240 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
241 | } | |
242 | ||
243 | static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder, | |
244 | struct drm_display_mode *mode, | |
245 | struct drm_display_mode *adjusted_mode) | |
246 | { | |
247 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
248 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
249 | int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN; | |
250 | ||
251 | if (mode->clock > 170000) { | |
252 | dev_warn(ldb->dev, | |
253 | "%s: mode exceeds 170 MHz pixel clock\n", __func__); | |
254 | } | |
255 | if (mode->clock > 85000 && !dual) { | |
256 | dev_warn(ldb->dev, | |
257 | "%s: mode exceeds 85 MHz pixel clock\n", __func__); | |
258 | } | |
259 | ||
260 | /* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */ | |
261 | if (imx_ldb_ch == &ldb->channel[0]) { | |
262 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
263 | ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; | |
264 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
265 | ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW; | |
266 | } | |
267 | if (imx_ldb_ch == &ldb->channel[1]) { | |
268 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) | |
269 | ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; | |
270 | else if (mode->flags & DRM_MODE_FLAG_PVSYNC) | |
271 | ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW; | |
272 | } | |
273 | } | |
274 | ||
275 | static void imx_ldb_encoder_disable(struct drm_encoder *encoder) | |
276 | { | |
277 | struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder); | |
278 | struct imx_ldb *ldb = imx_ldb_ch->ldb; | |
279 | ||
280 | /* | |
281 | * imx_ldb_encoder_disable is called by | |
282 | * drm_helper_disable_unused_functions without | |
283 | * the encoder being enabled before. | |
284 | */ | |
285 | if (imx_ldb_ch == &ldb->channel[0] && | |
286 | (ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0) | |
287 | return; | |
288 | else if (imx_ldb_ch == &ldb->channel[1] && | |
289 | (ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0) | |
290 | return; | |
291 | ||
292 | if (imx_ldb_ch == &ldb->channel[0]) | |
293 | ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; | |
294 | else if (imx_ldb_ch == &ldb->channel[1]) | |
295 | ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; | |
296 | ||
297 | regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl); | |
298 | ||
299 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { | |
300 | clk_disable_unprepare(ldb->clk[0]); | |
301 | clk_disable_unprepare(ldb->clk[1]); | |
302 | } | |
303 | } | |
304 | ||
ac4c1a9b SH |
305 | static struct drm_connector_funcs imx_ldb_connector_funcs = { |
306 | .dpms = drm_helper_connector_dpms, | |
307 | .fill_modes = drm_helper_probe_single_connector_modes, | |
308 | .detect = imx_ldb_connector_detect, | |
1b3f7675 | 309 | .destroy = imx_drm_connector_destroy, |
ac4c1a9b SH |
310 | }; |
311 | ||
312 | static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = { | |
313 | .get_modes = imx_ldb_connector_get_modes, | |
314 | .best_encoder = imx_ldb_connector_best_encoder, | |
baa68c4b | 315 | .mode_valid = imx_drm_connector_mode_valid, |
ac4c1a9b SH |
316 | }; |
317 | ||
318 | static struct drm_encoder_funcs imx_ldb_encoder_funcs = { | |
1b3f7675 | 319 | .destroy = imx_drm_encoder_destroy, |
ac4c1a9b SH |
320 | }; |
321 | ||
322 | static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = { | |
323 | .dpms = imx_ldb_encoder_dpms, | |
324 | .mode_fixup = imx_ldb_encoder_mode_fixup, | |
325 | .prepare = imx_ldb_encoder_prepare, | |
326 | .commit = imx_ldb_encoder_commit, | |
327 | .mode_set = imx_ldb_encoder_mode_set, | |
328 | .disable = imx_ldb_encoder_disable, | |
329 | }; | |
330 | ||
331 | static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno) | |
332 | { | |
333 | char clkname[16]; | |
334 | ||
335 | sprintf(clkname, "di%d", chno); | |
336 | ldb->clk[chno] = devm_clk_get(ldb->dev, clkname); | |
337 | if (IS_ERR(ldb->clk[chno])) | |
338 | return PTR_ERR(ldb->clk[chno]); | |
339 | ||
340 | sprintf(clkname, "di%d_pll", chno); | |
341 | ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname); | |
ac4c1a9b | 342 | |
1f933fa8 | 343 | return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]); |
ac4c1a9b SH |
344 | } |
345 | ||
1b3f7675 RK |
346 | static int imx_ldb_register(struct drm_device *drm, |
347 | struct imx_ldb_channel *imx_ldb_ch) | |
ac4c1a9b | 348 | { |
ac4c1a9b | 349 | struct imx_ldb *ldb = imx_ldb_ch->ldb; |
1b3f7675 RK |
350 | int ret; |
351 | ||
352 | ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder, | |
353 | imx_ldb_ch->child); | |
354 | if (ret) | |
355 | return ret; | |
ac4c1a9b SH |
356 | |
357 | ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno); | |
358 | if (ret) | |
359 | return ret; | |
1b3f7675 | 360 | |
ac4c1a9b | 361 | if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) { |
1b3f7675 | 362 | ret = imx_ldb_get_clk(ldb, 1); |
ac4c1a9b SH |
363 | if (ret) |
364 | return ret; | |
365 | } | |
366 | ||
ac4c1a9b SH |
367 | drm_encoder_helper_add(&imx_ldb_ch->encoder, |
368 | &imx_ldb_encoder_helper_funcs); | |
1b3f7675 RK |
369 | drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs, |
370 | DRM_MODE_ENCODER_LVDS); | |
ac4c1a9b SH |
371 | |
372 | drm_connector_helper_add(&imx_ldb_ch->connector, | |
373 | &imx_ldb_connector_helper_funcs); | |
1b3f7675 RK |
374 | drm_connector_init(drm, &imx_ldb_ch->connector, |
375 | &imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS); | |
ac4c1a9b SH |
376 | |
377 | drm_mode_connector_attach_encoder(&imx_ldb_ch->connector, | |
378 | &imx_ldb_ch->encoder); | |
379 | ||
380 | return 0; | |
381 | } | |
382 | ||
383 | enum { | |
384 | LVDS_BIT_MAP_SPWG, | |
385 | LVDS_BIT_MAP_JEIDA | |
386 | }; | |
387 | ||
5354cb64 | 388 | static const char * const imx_ldb_bit_mappings[] = { |
ac4c1a9b SH |
389 | [LVDS_BIT_MAP_SPWG] = "spwg", |
390 | [LVDS_BIT_MAP_JEIDA] = "jeida", | |
391 | }; | |
392 | ||
d78b1406 | 393 | static const int of_get_data_mapping(struct device_node *np) |
ac4c1a9b SH |
394 | { |
395 | const char *bm; | |
396 | int ret, i; | |
397 | ||
398 | ret = of_property_read_string(np, "fsl,data-mapping", &bm); | |
399 | if (ret < 0) | |
400 | return ret; | |
401 | ||
402 | for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) | |
403 | if (!strcasecmp(bm, imx_ldb_bit_mappings[i])) | |
404 | return i; | |
405 | ||
406 | return -EINVAL; | |
407 | } | |
408 | ||
409 | static struct bus_mux imx6q_lvds_mux[2] = { | |
410 | { | |
411 | .reg = IOMUXC_GPR3, | |
412 | .shift = 6, | |
413 | .mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK, | |
414 | }, { | |
415 | .reg = IOMUXC_GPR3, | |
416 | .shift = 8, | |
417 | .mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK, | |
418 | } | |
419 | }; | |
420 | ||
421 | /* | |
422 | * For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb", | |
423 | * of_match_device will walk through this list and take the first entry | |
424 | * matching any of its compatible values. Therefore, the more generic | |
425 | * entries (in this case fsl,imx53-ldb) need to be ordered last. | |
426 | */ | |
427 | static const struct of_device_id imx_ldb_dt_ids[] = { | |
428 | { .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, }, | |
429 | { .compatible = "fsl,imx53-ldb", .data = NULL, }, | |
430 | { } | |
431 | }; | |
432 | MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids); | |
433 | ||
17b5001b | 434 | static int imx_ldb_bind(struct device *dev, struct device *master, void *data) |
ac4c1a9b | 435 | { |
1b3f7675 | 436 | struct drm_device *drm = data; |
17b5001b | 437 | struct device_node *np = dev->of_node; |
ac4c1a9b | 438 | const struct of_device_id *of_id = |
17b5001b | 439 | of_match_device(imx_ldb_dt_ids, dev); |
ac4c1a9b SH |
440 | struct device_node *child; |
441 | const u8 *edidp; | |
442 | struct imx_ldb *imx_ldb; | |
443 | int datawidth; | |
444 | int mapping; | |
445 | int dual; | |
446 | int ret; | |
447 | int i; | |
448 | ||
17b5001b | 449 | imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); |
ac4c1a9b SH |
450 | if (!imx_ldb) |
451 | return -ENOMEM; | |
452 | ||
453 | imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); | |
454 | if (IS_ERR(imx_ldb->regmap)) { | |
17b5001b | 455 | dev_err(dev, "failed to get parent regmap\n"); |
ac4c1a9b SH |
456 | return PTR_ERR(imx_ldb->regmap); |
457 | } | |
458 | ||
17b5001b | 459 | imx_ldb->dev = dev; |
ac4c1a9b SH |
460 | |
461 | if (of_id) | |
462 | imx_ldb->lvds_mux = of_id->data; | |
463 | ||
464 | dual = of_property_read_bool(np, "fsl,dual-channel"); | |
465 | if (dual) | |
466 | imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; | |
467 | ||
468 | /* | |
4599934d | 469 | * There are three different possible clock mux configurations: |
ac4c1a9b SH |
470 | * i.MX53: ipu1_di0_sel, ipu1_di1_sel |
471 | * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel | |
472 | * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel | |
473 | * Map them all to di0_sel...di3_sel. | |
474 | */ | |
475 | for (i = 0; i < 4; i++) { | |
476 | char clkname[16]; | |
477 | ||
478 | sprintf(clkname, "di%d_sel", i); | |
479 | imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); | |
480 | if (IS_ERR(imx_ldb->clk_sel[i])) { | |
481 | ret = PTR_ERR(imx_ldb->clk_sel[i]); | |
482 | imx_ldb->clk_sel[i] = NULL; | |
483 | break; | |
484 | } | |
485 | } | |
486 | if (i == 0) | |
487 | return ret; | |
488 | ||
489 | for_each_child_of_node(np, child) { | |
490 | struct imx_ldb_channel *channel; | |
491 | ||
492 | ret = of_property_read_u32(child, "reg", &i); | |
493 | if (ret || i < 0 || i > 1) | |
494 | return -EINVAL; | |
495 | ||
496 | if (dual && i > 0) { | |
17b5001b | 497 | dev_warn(dev, "dual-channel mode, ignoring second output\n"); |
ac4c1a9b SH |
498 | continue; |
499 | } | |
500 | ||
501 | if (!of_device_is_available(child)) | |
502 | continue; | |
503 | ||
504 | channel = &imx_ldb->channel[i]; | |
505 | channel->ldb = imx_ldb; | |
506 | channel->chno = i; | |
1b3f7675 | 507 | channel->child = child; |
ac4c1a9b SH |
508 | |
509 | edidp = of_get_property(child, "edid", &channel->edid_len); | |
510 | if (edidp) { | |
511 | channel->edid = kmemdup(edidp, channel->edid_len, | |
512 | GFP_KERNEL); | |
513 | } else { | |
514 | ret = of_get_drm_display_mode(child, &channel->mode, 0); | |
515 | if (!ret) | |
516 | channel->mode_valid = 1; | |
517 | } | |
518 | ||
519 | ret = of_property_read_u32(child, "fsl,data-width", &datawidth); | |
520 | if (ret) | |
521 | datawidth = 0; | |
522 | else if (datawidth != 18 && datawidth != 24) | |
523 | return -EINVAL; | |
524 | ||
525 | mapping = of_get_data_mapping(child); | |
526 | switch (mapping) { | |
527 | case LVDS_BIT_MAP_SPWG: | |
528 | if (datawidth == 24) { | |
529 | if (i == 0 || dual) | |
530 | imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; | |
531 | if (i == 1 || dual) | |
532 | imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; | |
533 | } | |
534 | break; | |
535 | case LVDS_BIT_MAP_JEIDA: | |
536 | if (datawidth == 18) { | |
17b5001b | 537 | dev_err(dev, "JEIDA standard only supported in 24 bit\n"); |
ac4c1a9b SH |
538 | return -EINVAL; |
539 | } | |
540 | if (i == 0 || dual) | |
541 | imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | LDB_BIT_MAP_CH0_JEIDA; | |
542 | if (i == 1 || dual) | |
543 | imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | LDB_BIT_MAP_CH1_JEIDA; | |
544 | break; | |
545 | default: | |
17b5001b | 546 | dev_err(dev, "data mapping not specified or invalid\n"); |
ac4c1a9b SH |
547 | return -EINVAL; |
548 | } | |
549 | ||
1b3f7675 | 550 | ret = imx_ldb_register(drm, channel); |
ac4c1a9b SH |
551 | if (ret) |
552 | return ret; | |
ac4c1a9b SH |
553 | } |
554 | ||
17b5001b | 555 | dev_set_drvdata(dev, imx_ldb); |
ac4c1a9b SH |
556 | |
557 | return 0; | |
558 | } | |
559 | ||
17b5001b RK |
560 | static void imx_ldb_unbind(struct device *dev, struct device *master, |
561 | void *data) | |
ac4c1a9b | 562 | { |
17b5001b | 563 | struct imx_ldb *imx_ldb = dev_get_drvdata(dev); |
ac4c1a9b SH |
564 | int i; |
565 | ||
566 | for (i = 0; i < 2; i++) { | |
567 | struct imx_ldb_channel *channel = &imx_ldb->channel[i]; | |
ac4c1a9b | 568 | |
1b3f7675 RK |
569 | channel->connector.funcs->destroy(&channel->connector); |
570 | channel->encoder.funcs->destroy(&channel->encoder); | |
ac4c1a9b | 571 | } |
17b5001b | 572 | } |
ac4c1a9b | 573 | |
17b5001b RK |
574 | static const struct component_ops imx_ldb_ops = { |
575 | .bind = imx_ldb_bind, | |
576 | .unbind = imx_ldb_unbind, | |
577 | }; | |
578 | ||
579 | static int imx_ldb_probe(struct platform_device *pdev) | |
580 | { | |
581 | return component_add(&pdev->dev, &imx_ldb_ops); | |
582 | } | |
583 | ||
584 | static int imx_ldb_remove(struct platform_device *pdev) | |
585 | { | |
586 | component_del(&pdev->dev, &imx_ldb_ops); | |
ac4c1a9b SH |
587 | return 0; |
588 | } | |
589 | ||
590 | static struct platform_driver imx_ldb_driver = { | |
591 | .probe = imx_ldb_probe, | |
592 | .remove = imx_ldb_remove, | |
593 | .driver = { | |
594 | .of_match_table = imx_ldb_dt_ids, | |
595 | .name = DRIVER_NAME, | |
596 | .owner = THIS_MODULE, | |
597 | }, | |
598 | }; | |
599 | ||
600 | module_platform_driver(imx_ldb_driver); | |
601 | ||
602 | MODULE_DESCRIPTION("i.MX LVDS driver"); | |
603 | MODULE_AUTHOR("Sascha Hauer, Pengutronix"); | |
604 | MODULE_LICENSE("GPL"); | |
bc627387 | 605 | MODULE_ALIAS("platform:" DRIVER_NAME); |