Commit | Line | Data |
---|---|---|
fcbc51e5 PZ |
1 | /* |
2 | * i.MX drm driver - Television Encoder (TVEv2) | |
3 | * | |
4 | * Copyright (C) 2013 Philipp Zabel, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
18 | * MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/clk-provider.h> | |
23 | #include <linux/module.h> | |
24 | #include <linux/of_i2c.h> | |
fcbc51e5 PZ |
25 | #include <linux/regmap.h> |
26 | #include <linux/regulator/consumer.h> | |
27 | #include <linux/spinlock.h> | |
28 | #include <linux/videodev2.h> | |
29 | #include <drm/drmP.h> | |
30 | #include <drm/drm_fb_helper.h> | |
31 | #include <drm/drm_crtc_helper.h> | |
32 | ||
33 | #include "imx-drm.h" | |
34 | ||
35 | #define TVE_COM_CONF_REG 0x00 | |
36 | #define TVE_TVDAC0_CONT_REG 0x28 | |
37 | #define TVE_TVDAC1_CONT_REG 0x2c | |
38 | #define TVE_TVDAC2_CONT_REG 0x30 | |
39 | #define TVE_CD_CONT_REG 0x34 | |
40 | #define TVE_INT_CONT_REG 0x64 | |
41 | #define TVE_STAT_REG 0x68 | |
42 | #define TVE_TST_MODE_REG 0x6c | |
43 | #define TVE_MV_CONT_REG 0xdc | |
44 | ||
45 | /* TVE_COM_CONF_REG */ | |
46 | #define TVE_SYNC_CH_2_EN BIT(22) | |
47 | #define TVE_SYNC_CH_1_EN BIT(21) | |
48 | #define TVE_SYNC_CH_0_EN BIT(20) | |
49 | #define TVE_TV_OUT_MODE_MASK (0x7 << 12) | |
50 | #define TVE_TV_OUT_DISABLE (0x0 << 12) | |
51 | #define TVE_TV_OUT_CVBS_0 (0x1 << 12) | |
52 | #define TVE_TV_OUT_CVBS_2 (0x2 << 12) | |
53 | #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12) | |
54 | #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12) | |
55 | #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12) | |
56 | #define TVE_TV_OUT_YPBPR (0x6 << 12) | |
57 | #define TVE_TV_OUT_RGB (0x7 << 12) | |
58 | #define TVE_TV_STAND_MASK (0xf << 8) | |
59 | #define TVE_TV_STAND_HD_1080P30 (0xc << 8) | |
60 | #define TVE_P2I_CONV_EN BIT(7) | |
61 | #define TVE_INP_VIDEO_FORM BIT(6) | |
62 | #define TVE_INP_YCBCR_422 (0x0 << 6) | |
63 | #define TVE_INP_YCBCR_444 (0x1 << 6) | |
64 | #define TVE_DATA_SOURCE_MASK (0x3 << 4) | |
65 | #define TVE_DATA_SOURCE_BUS1 (0x0 << 4) | |
66 | #define TVE_DATA_SOURCE_BUS2 (0x1 << 4) | |
67 | #define TVE_DATA_SOURCE_EXT (0x2 << 4) | |
68 | #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4) | |
69 | #define TVE_IPU_CLK_EN_OFS 3 | |
70 | #define TVE_IPU_CLK_EN BIT(3) | |
71 | #define TVE_DAC_SAMP_RATE_OFS 1 | |
72 | #define TVE_DAC_SAMP_RATE_WIDTH 2 | |
73 | #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1) | |
74 | #define TVE_DAC_FULL_RATE (0x0 << 1) | |
75 | #define TVE_DAC_DIV2_RATE (0x1 << 1) | |
76 | #define TVE_DAC_DIV4_RATE (0x2 << 1) | |
77 | #define TVE_EN BIT(0) | |
78 | ||
79 | /* TVE_TVDACx_CONT_REG */ | |
80 | #define TVE_TVDAC_GAIN_MASK (0x3f << 0) | |
81 | ||
82 | /* TVE_CD_CONT_REG */ | |
83 | #define TVE_CD_CH_2_SM_EN BIT(22) | |
84 | #define TVE_CD_CH_1_SM_EN BIT(21) | |
85 | #define TVE_CD_CH_0_SM_EN BIT(20) | |
86 | #define TVE_CD_CH_2_LM_EN BIT(18) | |
87 | #define TVE_CD_CH_1_LM_EN BIT(17) | |
88 | #define TVE_CD_CH_0_LM_EN BIT(16) | |
89 | #define TVE_CD_CH_2_REF_LVL BIT(10) | |
90 | #define TVE_CD_CH_1_REF_LVL BIT(9) | |
91 | #define TVE_CD_CH_0_REF_LVL BIT(8) | |
92 | #define TVE_CD_EN BIT(0) | |
93 | ||
94 | /* TVE_INT_CONT_REG */ | |
95 | #define TVE_FRAME_END_IEN BIT(13) | |
96 | #define TVE_CD_MON_END_IEN BIT(2) | |
97 | #define TVE_CD_SM_IEN BIT(1) | |
98 | #define TVE_CD_LM_IEN BIT(0) | |
99 | ||
100 | /* TVE_TST_MODE_REG */ | |
101 | #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0) | |
102 | ||
103 | #define con_to_tve(x) container_of(x, struct imx_tve, connector) | |
104 | #define enc_to_tve(x) container_of(x, struct imx_tve, encoder) | |
105 | ||
106 | enum { | |
107 | TVE_MODE_TVOUT, | |
108 | TVE_MODE_VGA, | |
109 | }; | |
110 | ||
111 | struct imx_tve { | |
112 | struct drm_connector connector; | |
113 | struct imx_drm_connector *imx_drm_connector; | |
114 | struct drm_encoder encoder; | |
115 | struct imx_drm_encoder *imx_drm_encoder; | |
116 | struct device *dev; | |
117 | spinlock_t enable_lock; /* serializes tve_enable/disable */ | |
118 | spinlock_t lock; /* register lock */ | |
119 | bool enabled; | |
120 | int mode; | |
121 | ||
122 | struct regmap *regmap; | |
123 | struct regulator *dac_reg; | |
124 | struct i2c_adapter *ddc; | |
125 | struct clk *clk; | |
126 | struct clk *di_sel_clk; | |
127 | struct clk_hw clk_hw_di; | |
128 | struct clk *di_clk; | |
129 | int vsync_pin; | |
130 | int hsync_pin; | |
131 | }; | |
132 | ||
133 | static void tve_lock(void *__tve) | |
5d78bf80 | 134 | __acquires(&tve->lock) |
fcbc51e5 PZ |
135 | { |
136 | struct imx_tve *tve = __tve; | |
137 | spin_lock(&tve->lock); | |
138 | } | |
139 | ||
140 | static void tve_unlock(void *__tve) | |
5d78bf80 | 141 | __releases(&tve->lock) |
fcbc51e5 PZ |
142 | { |
143 | struct imx_tve *tve = __tve; | |
144 | spin_unlock(&tve->lock); | |
145 | } | |
146 | ||
147 | static void tve_enable(struct imx_tve *tve) | |
148 | { | |
149 | unsigned long flags; | |
150 | int ret; | |
151 | ||
152 | spin_lock_irqsave(&tve->enable_lock, flags); | |
153 | if (!tve->enabled) { | |
154 | tve->enabled = 1; | |
155 | clk_prepare_enable(tve->clk); | |
156 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, | |
157 | TVE_IPU_CLK_EN | TVE_EN, | |
158 | TVE_IPU_CLK_EN | TVE_EN); | |
159 | } | |
160 | ||
161 | /* clear interrupt status register */ | |
162 | regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); | |
163 | ||
164 | /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */ | |
165 | if (tve->mode == TVE_MODE_VGA) | |
166 | regmap_write(tve->regmap, TVE_INT_CONT_REG, 0); | |
167 | else | |
168 | regmap_write(tve->regmap, TVE_INT_CONT_REG, | |
169 | TVE_CD_SM_IEN | TVE_CD_LM_IEN | TVE_CD_MON_END_IEN); | |
170 | spin_unlock_irqrestore(&tve->enable_lock, flags); | |
171 | } | |
172 | ||
173 | static void tve_disable(struct imx_tve *tve) | |
174 | { | |
175 | unsigned long flags; | |
176 | int ret; | |
177 | ||
178 | spin_lock_irqsave(&tve->enable_lock, flags); | |
179 | if (tve->enabled) { | |
180 | tve->enabled = 0; | |
181 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, | |
182 | TVE_IPU_CLK_EN | TVE_EN, 0); | |
183 | clk_disable_unprepare(tve->clk); | |
184 | } | |
185 | spin_unlock_irqrestore(&tve->enable_lock, flags); | |
186 | } | |
187 | ||
188 | static int tve_setup_tvout(struct imx_tve *tve) | |
189 | { | |
190 | return -ENOTSUPP; | |
191 | } | |
192 | ||
193 | static int tve_setup_vga(struct imx_tve *tve) | |
194 | { | |
195 | unsigned int mask; | |
196 | unsigned int val; | |
197 | int ret; | |
198 | ||
199 | /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */ | |
200 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG, | |
201 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
202 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG, | |
203 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
204 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG, | |
205 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
206 | ||
207 | /* set configuration register */ | |
208 | mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; | |
209 | val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444; | |
210 | mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN; | |
211 | val |= TVE_TV_STAND_HD_1080P30 | 0; | |
212 | mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; | |
213 | val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; | |
214 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); | |
215 | if (ret < 0) { | |
216 | dev_err(tve->dev, "failed to set configuration: %d\n", ret); | |
217 | return ret; | |
218 | } | |
219 | ||
220 | /* set test mode (as documented) */ | |
221 | ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, | |
222 | TVE_TVDAC_TEST_MODE_MASK, 1); | |
223 | ||
224 | return 0; | |
225 | } | |
226 | ||
227 | static enum drm_connector_status imx_tve_connector_detect( | |
228 | struct drm_connector *connector, bool force) | |
229 | { | |
230 | return connector_status_connected; | |
231 | } | |
232 | ||
233 | static void imx_tve_connector_destroy(struct drm_connector *connector) | |
234 | { | |
235 | /* do not free here */ | |
236 | } | |
237 | ||
238 | static int imx_tve_connector_get_modes(struct drm_connector *connector) | |
239 | { | |
240 | struct imx_tve *tve = con_to_tve(connector); | |
241 | struct edid *edid; | |
242 | int ret = 0; | |
243 | ||
244 | if (!tve->ddc) | |
245 | return 0; | |
246 | ||
247 | edid = drm_get_edid(connector, tve->ddc); | |
248 | if (edid) { | |
249 | drm_mode_connector_update_edid_property(connector, edid); | |
250 | ret = drm_add_edid_modes(connector, edid); | |
251 | kfree(edid); | |
252 | } | |
253 | ||
254 | return ret; | |
255 | } | |
256 | ||
257 | static int imx_tve_connector_mode_valid(struct drm_connector *connector, | |
258 | struct drm_display_mode *mode) | |
259 | { | |
260 | struct imx_tve *tve = con_to_tve(connector); | |
261 | unsigned long rate; | |
262 | ||
263 | /* pixel clock with 2x oversampling */ | |
264 | rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; | |
265 | if (rate == mode->clock) | |
266 | return MODE_OK; | |
267 | ||
268 | /* pixel clock without oversampling */ | |
269 | rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; | |
270 | if (rate == mode->clock) | |
271 | return MODE_OK; | |
272 | ||
273 | dev_warn(tve->dev, "ignoring mode %dx%d\n", | |
274 | mode->hdisplay, mode->vdisplay); | |
275 | ||
276 | return MODE_BAD; | |
277 | } | |
278 | ||
279 | static struct drm_encoder *imx_tve_connector_best_encoder( | |
280 | struct drm_connector *connector) | |
281 | { | |
282 | struct imx_tve *tve = con_to_tve(connector); | |
283 | ||
284 | return &tve->encoder; | |
285 | } | |
286 | ||
287 | static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode) | |
288 | { | |
289 | struct imx_tve *tve = enc_to_tve(encoder); | |
290 | int ret; | |
291 | ||
292 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, | |
293 | TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE); | |
294 | if (ret < 0) | |
295 | dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret); | |
296 | } | |
297 | ||
298 | static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder, | |
299 | const struct drm_display_mode *mode, | |
300 | struct drm_display_mode *adjusted_mode) | |
301 | { | |
302 | return true; | |
303 | } | |
304 | ||
305 | static void imx_tve_encoder_prepare(struct drm_encoder *encoder) | |
306 | { | |
307 | struct imx_tve *tve = enc_to_tve(encoder); | |
308 | ||
309 | tve_disable(tve); | |
310 | ||
311 | switch (tve->mode) { | |
312 | case TVE_MODE_VGA: | |
313 | imx_drm_crtc_panel_format_pins(encoder->crtc, | |
314 | DRM_MODE_ENCODER_DAC, IPU_PIX_FMT_GBR24, | |
315 | tve->hsync_pin, tve->vsync_pin); | |
316 | break; | |
317 | case TVE_MODE_TVOUT: | |
318 | imx_drm_crtc_panel_format(encoder->crtc, DRM_MODE_ENCODER_TVDAC, | |
319 | V4L2_PIX_FMT_YUV444); | |
320 | break; | |
321 | } | |
322 | } | |
323 | ||
324 | static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, | |
325 | struct drm_display_mode *mode, | |
326 | struct drm_display_mode *adjusted_mode) | |
327 | { | |
328 | struct imx_tve *tve = enc_to_tve(encoder); | |
329 | unsigned long rounded_rate; | |
330 | unsigned long rate; | |
331 | int div = 1; | |
332 | int ret; | |
333 | ||
334 | /* | |
335 | * FIXME | |
336 | * we should try 4k * mode->clock first, | |
337 | * and enable 4x oversampling for lower resolutions | |
338 | */ | |
339 | rate = 2000UL * mode->clock; | |
340 | clk_set_rate(tve->clk, rate); | |
341 | rounded_rate = clk_get_rate(tve->clk); | |
342 | if (rounded_rate >= rate) | |
343 | div = 2; | |
344 | clk_set_rate(tve->di_clk, rounded_rate / div); | |
345 | ||
346 | ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); | |
347 | if (ret < 0) { | |
348 | dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", | |
349 | ret); | |
350 | } | |
351 | ||
352 | if (tve->mode == TVE_MODE_VGA) | |
353 | tve_setup_vga(tve); | |
354 | else | |
355 | tve_setup_tvout(tve); | |
356 | } | |
357 | ||
358 | static void imx_tve_encoder_commit(struct drm_encoder *encoder) | |
359 | { | |
360 | struct imx_tve *tve = enc_to_tve(encoder); | |
361 | ||
362 | tve_enable(tve); | |
363 | } | |
364 | ||
365 | static void imx_tve_encoder_disable(struct drm_encoder *encoder) | |
366 | { | |
367 | struct imx_tve *tve = enc_to_tve(encoder); | |
368 | ||
369 | tve_disable(tve); | |
370 | } | |
371 | ||
372 | static void imx_tve_encoder_destroy(struct drm_encoder *encoder) | |
373 | { | |
374 | /* do not free here */ | |
375 | } | |
376 | ||
377 | static struct drm_connector_funcs imx_tve_connector_funcs = { | |
378 | .dpms = drm_helper_connector_dpms, | |
379 | .fill_modes = drm_helper_probe_single_connector_modes, | |
380 | .detect = imx_tve_connector_detect, | |
381 | .destroy = imx_tve_connector_destroy, | |
382 | }; | |
383 | ||
384 | static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = { | |
385 | .get_modes = imx_tve_connector_get_modes, | |
386 | .best_encoder = imx_tve_connector_best_encoder, | |
387 | .mode_valid = imx_tve_connector_mode_valid, | |
388 | }; | |
389 | ||
390 | static struct drm_encoder_funcs imx_tve_encoder_funcs = { | |
391 | .destroy = imx_tve_encoder_destroy, | |
392 | }; | |
393 | ||
394 | static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = { | |
395 | .dpms = imx_tve_encoder_dpms, | |
396 | .mode_fixup = imx_tve_encoder_mode_fixup, | |
397 | .prepare = imx_tve_encoder_prepare, | |
398 | .mode_set = imx_tve_encoder_mode_set, | |
399 | .commit = imx_tve_encoder_commit, | |
400 | .disable = imx_tve_encoder_disable, | |
401 | }; | |
402 | ||
403 | static irqreturn_t imx_tve_irq_handler(int irq, void *data) | |
404 | { | |
405 | struct imx_tve *tve = data; | |
406 | unsigned int val; | |
407 | ||
408 | regmap_read(tve->regmap, TVE_STAT_REG, &val); | |
409 | ||
410 | /* clear interrupt status register */ | |
411 | regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); | |
412 | ||
413 | return IRQ_HANDLED; | |
414 | } | |
415 | ||
416 | static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw, | |
417 | unsigned long parent_rate) | |
418 | { | |
419 | struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); | |
420 | unsigned int val; | |
421 | int ret; | |
422 | ||
423 | ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); | |
424 | if (ret < 0) | |
425 | return 0; | |
426 | ||
427 | switch (val & TVE_DAC_SAMP_RATE_MASK) { | |
428 | case TVE_DAC_DIV4_RATE: | |
429 | return parent_rate / 4; | |
430 | case TVE_DAC_DIV2_RATE: | |
431 | return parent_rate / 2; | |
432 | case TVE_DAC_FULL_RATE: | |
433 | default: | |
434 | return parent_rate; | |
435 | } | |
436 | ||
437 | return 0; | |
438 | } | |
439 | ||
440 | static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate, | |
441 | unsigned long *prate) | |
442 | { | |
443 | unsigned long div; | |
444 | ||
445 | div = *prate / rate; | |
446 | if (div >= 4) | |
447 | return *prate / 4; | |
448 | else if (div >= 2) | |
449 | return *prate / 2; | |
450 | else | |
451 | return *prate; | |
452 | } | |
453 | ||
454 | static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate, | |
455 | unsigned long parent_rate) | |
456 | { | |
457 | struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); | |
458 | unsigned long div; | |
459 | u32 val; | |
460 | int ret; | |
461 | ||
462 | div = parent_rate / rate; | |
463 | if (div >= 4) | |
464 | val = TVE_DAC_DIV4_RATE; | |
465 | else if (div >= 2) | |
466 | val = TVE_DAC_DIV2_RATE; | |
467 | else | |
468 | val = TVE_DAC_FULL_RATE; | |
469 | ||
470 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, TVE_DAC_SAMP_RATE_MASK, val); | |
471 | if (ret < 0) { | |
472 | dev_err(tve->dev, "failed to set divider: %d\n", ret); | |
473 | return ret; | |
474 | } | |
475 | ||
476 | return 0; | |
477 | } | |
478 | ||
479 | static struct clk_ops clk_tve_di_ops = { | |
480 | .round_rate = clk_tve_di_round_rate, | |
481 | .set_rate = clk_tve_di_set_rate, | |
482 | .recalc_rate = clk_tve_di_recalc_rate, | |
483 | }; | |
484 | ||
485 | static int tve_clk_init(struct imx_tve *tve, void __iomem *base) | |
486 | { | |
487 | const char *tve_di_parent[1]; | |
488 | struct clk_init_data init = { | |
489 | .name = "tve_di", | |
490 | .ops = &clk_tve_di_ops, | |
491 | .num_parents = 1, | |
492 | .flags = 0, | |
493 | }; | |
494 | ||
495 | tve_di_parent[0] = __clk_get_name(tve->clk); | |
496 | init.parent_names = (const char **)&tve_di_parent; | |
497 | ||
498 | tve->clk_hw_di.init = &init; | |
499 | tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di); | |
500 | if (IS_ERR(tve->di_clk)) { | |
501 | dev_err(tve->dev, "failed to register TVE output clock: %ld\n", | |
502 | PTR_ERR(tve->di_clk)); | |
503 | return PTR_ERR(tve->di_clk); | |
504 | } | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
509 | static int imx_tve_register(struct imx_tve *tve) | |
510 | { | |
511 | int ret; | |
512 | ||
513 | tve->connector.funcs = &imx_tve_connector_funcs; | |
514 | tve->encoder.funcs = &imx_tve_encoder_funcs; | |
515 | ||
516 | tve->encoder.encoder_type = DRM_MODE_ENCODER_NONE; | |
517 | tve->connector.connector_type = DRM_MODE_CONNECTOR_VGA; | |
518 | ||
519 | drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs); | |
520 | ret = imx_drm_add_encoder(&tve->encoder, &tve->imx_drm_encoder, | |
521 | THIS_MODULE); | |
522 | if (ret) { | |
523 | dev_err(tve->dev, "adding encoder failed with %d\n", ret); | |
524 | return ret; | |
525 | } | |
526 | ||
527 | drm_connector_helper_add(&tve->connector, | |
528 | &imx_tve_connector_helper_funcs); | |
529 | ||
530 | ret = imx_drm_add_connector(&tve->connector, | |
531 | &tve->imx_drm_connector, THIS_MODULE); | |
532 | if (ret) { | |
533 | imx_drm_remove_encoder(tve->imx_drm_encoder); | |
534 | dev_err(tve->dev, "adding connector failed with %d\n", ret); | |
535 | return ret; | |
536 | } | |
537 | ||
538 | drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder); | |
539 | ||
540 | return 0; | |
541 | } | |
542 | ||
543 | static bool imx_tve_readable_reg(struct device *dev, unsigned int reg) | |
544 | { | |
545 | return (reg % 4 == 0) && (reg <= 0xdc); | |
546 | } | |
547 | ||
548 | static struct regmap_config tve_regmap_config = { | |
549 | .reg_bits = 32, | |
550 | .val_bits = 32, | |
551 | .reg_stride = 4, | |
552 | ||
553 | .readable_reg = imx_tve_readable_reg, | |
554 | ||
555 | .lock = tve_lock, | |
556 | .unlock = tve_unlock, | |
557 | ||
558 | .max_register = 0xdc, | |
559 | }; | |
560 | ||
561 | static const char *imx_tve_modes[] = { | |
562 | [TVE_MODE_TVOUT] = "tvout", | |
563 | [TVE_MODE_VGA] = "vga", | |
564 | }; | |
565 | ||
566 | const int of_get_tve_mode(struct device_node *np) | |
567 | { | |
568 | const char *bm; | |
569 | int ret, i; | |
570 | ||
571 | ret = of_property_read_string(np, "fsl,tve-mode", &bm); | |
572 | if (ret < 0) | |
573 | return ret; | |
574 | ||
575 | for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++) | |
576 | if (!strcasecmp(bm, imx_tve_modes[i])) | |
577 | return i; | |
578 | ||
579 | return -EINVAL; | |
580 | } | |
581 | ||
582 | static int imx_tve_probe(struct platform_device *pdev) | |
583 | { | |
584 | struct device_node *np = pdev->dev.of_node; | |
585 | struct device_node *ddc_node; | |
586 | struct imx_tve *tve; | |
587 | struct resource *res; | |
588 | void __iomem *base; | |
589 | unsigned int val; | |
590 | int irq; | |
591 | int ret; | |
592 | ||
593 | tve = devm_kzalloc(&pdev->dev, sizeof(*tve), GFP_KERNEL); | |
594 | if (!tve) | |
595 | return -ENOMEM; | |
596 | ||
597 | tve->dev = &pdev->dev; | |
598 | spin_lock_init(&tve->lock); | |
599 | spin_lock_init(&tve->enable_lock); | |
600 | ||
601 | ddc_node = of_parse_phandle(np, "ddc", 0); | |
602 | if (ddc_node) { | |
603 | tve->ddc = of_find_i2c_adapter_by_node(ddc_node); | |
604 | of_node_put(ddc_node); | |
605 | } | |
606 | ||
607 | tve->mode = of_get_tve_mode(np); | |
608 | if (tve->mode != TVE_MODE_VGA) { | |
609 | dev_err(&pdev->dev, "only VGA mode supported, currently\n"); | |
610 | return -EINVAL; | |
611 | } | |
612 | ||
613 | if (tve->mode == TVE_MODE_VGA) { | |
fcbc51e5 PZ |
614 | ret = of_property_read_u32(np, "fsl,hsync-pin", &tve->hsync_pin); |
615 | if (ret < 0) { | |
616 | dev_err(&pdev->dev, "failed to get vsync pin\n"); | |
617 | return ret; | |
618 | } | |
619 | ||
620 | ret |= of_property_read_u32(np, "fsl,vsync-pin", &tve->vsync_pin); | |
621 | if (ret < 0) { | |
622 | dev_err(&pdev->dev, "failed to get vsync pin\n"); | |
623 | return ret; | |
624 | } | |
625 | } | |
626 | ||
627 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
628 | if (!res) { | |
629 | dev_err(&pdev->dev, "failed to get memory region\n"); | |
630 | return -ENOENT; | |
631 | } | |
632 | ||
9b43b56f LN |
633 | base = devm_ioremap_resource(&pdev->dev, res); |
634 | if (IS_ERR(base)) | |
635 | return PTR_ERR(base); | |
fcbc51e5 PZ |
636 | |
637 | tve_regmap_config.lock_arg = tve; | |
638 | tve->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "tve", base, | |
639 | &tve_regmap_config); | |
640 | if (IS_ERR(tve->regmap)) { | |
641 | dev_err(&pdev->dev, "failed to init regmap: %ld\n", | |
642 | PTR_ERR(tve->regmap)); | |
643 | return PTR_ERR(tve->regmap); | |
644 | } | |
645 | ||
646 | irq = platform_get_irq(pdev, 0); | |
647 | if (irq < 0) { | |
648 | dev_err(&pdev->dev, "failed to get irq\n"); | |
649 | return irq; | |
650 | } | |
651 | ||
652 | ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, | |
653 | imx_tve_irq_handler, IRQF_ONESHOT, | |
654 | "imx-tve", tve); | |
655 | if (ret < 0) { | |
656 | dev_err(&pdev->dev, "failed to request irq: %d\n", ret); | |
657 | return ret; | |
658 | } | |
659 | ||
660 | tve->dac_reg = devm_regulator_get(&pdev->dev, "dac"); | |
661 | if (!IS_ERR(tve->dac_reg)) { | |
662 | regulator_set_voltage(tve->dac_reg, 2750000, 2750000); | |
c7b0cf3e FE |
663 | ret = regulator_enable(tve->dac_reg); |
664 | if (ret) | |
665 | return ret; | |
fcbc51e5 PZ |
666 | } |
667 | ||
668 | tve->clk = devm_clk_get(&pdev->dev, "tve"); | |
669 | if (IS_ERR(tve->clk)) { | |
670 | dev_err(&pdev->dev, "failed to get high speed tve clock: %ld\n", | |
671 | PTR_ERR(tve->clk)); | |
672 | return PTR_ERR(tve->clk); | |
673 | } | |
674 | ||
675 | /* this is the IPU DI clock input selector, can be parented to tve_di */ | |
676 | tve->di_sel_clk = devm_clk_get(&pdev->dev, "di_sel"); | |
677 | if (IS_ERR(tve->di_sel_clk)) { | |
678 | dev_err(&pdev->dev, "failed to get ipu di mux clock: %ld\n", | |
679 | PTR_ERR(tve->di_sel_clk)); | |
680 | return PTR_ERR(tve->di_sel_clk); | |
681 | } | |
682 | ||
683 | ret = tve_clk_init(tve, base); | |
684 | if (ret < 0) | |
685 | return ret; | |
686 | ||
687 | ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); | |
688 | if (ret < 0) { | |
689 | dev_err(&pdev->dev, "failed to read configuration register: %d\n", ret); | |
690 | return ret; | |
691 | } | |
692 | if (val != 0x00100000) { | |
693 | dev_err(&pdev->dev, "configuration register default value indicates this is not a TVEv2\n"); | |
694 | return -ENODEV; | |
695 | }; | |
696 | ||
697 | /* disable cable detection for VGA mode */ | |
698 | ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0); | |
699 | ||
700 | ret = imx_tve_register(tve); | |
701 | if (ret) | |
702 | return ret; | |
703 | ||
704 | ret = imx_drm_encoder_add_possible_crtcs(tve->imx_drm_encoder, np); | |
705 | ||
706 | platform_set_drvdata(pdev, tve); | |
707 | ||
708 | return 0; | |
709 | } | |
710 | ||
711 | static int imx_tve_remove(struct platform_device *pdev) | |
712 | { | |
713 | struct imx_tve *tve = platform_get_drvdata(pdev); | |
714 | struct drm_connector *connector = &tve->connector; | |
715 | struct drm_encoder *encoder = &tve->encoder; | |
716 | ||
717 | drm_mode_connector_detach_encoder(connector, encoder); | |
718 | ||
719 | imx_drm_remove_connector(tve->imx_drm_connector); | |
720 | imx_drm_remove_encoder(tve->imx_drm_encoder); | |
721 | ||
722 | if (!IS_ERR(tve->dac_reg)) | |
723 | regulator_disable(tve->dac_reg); | |
724 | ||
725 | return 0; | |
726 | } | |
727 | ||
728 | static const struct of_device_id imx_tve_dt_ids[] = { | |
729 | { .compatible = "fsl,imx53-tve", }, | |
730 | { /* sentinel */ } | |
731 | }; | |
732 | ||
733 | static struct platform_driver imx_tve_driver = { | |
734 | .probe = imx_tve_probe, | |
735 | .remove = imx_tve_remove, | |
736 | .driver = { | |
737 | .of_match_table = imx_tve_dt_ids, | |
738 | .name = "imx-tve", | |
739 | .owner = THIS_MODULE, | |
740 | }, | |
741 | }; | |
742 | ||
743 | module_platform_driver(imx_tve_driver); | |
744 | ||
745 | MODULE_DESCRIPTION("i.MX Television Encoder driver"); | |
746 | MODULE_AUTHOR("Philipp Zabel, Pengutronix"); | |
747 | MODULE_LICENSE("GPL"); |