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imx-drm: imx-hdmi: Fix DDC I2C bus property
[deliverable/linux.git] / drivers / staging / imx-drm / imx-tve.c
CommitLineData
fcbc51e5
PZ		 1/*
2 * i.MX drm driver - Television Encoder (TVEv2)
3 *
4 * Copyright (C) 2013 Philipp Zabel, Pengutronix
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
18 * MA 02110-1301, USA.
19 */
20
21#include <linux/clk.h>
22#include <linux/clk-provider.h>
17b5001b 23#include <linux/component.h>
fcbc51e5 24#include <linux/module.h>
687b81d0 25#include <linux/i2c.h>
fcbc51e5
PZ		 26#include <linux/regmap.h>
27#include <linux/regulator/consumer.h>
28#include <linux/spinlock.h>
29#include <linux/videodev2.h>
30#include <drm/drmP.h>
31#include <drm/drm_fb_helper.h>
32#include <drm/drm_crtc_helper.h>
33
34#include "imx-drm.h"
35
36#define TVE_COM_CONF_REG 0x00
37#define TVE_TVDAC0_CONT_REG 0x28
38#define TVE_TVDAC1_CONT_REG 0x2c
39#define TVE_TVDAC2_CONT_REG 0x30
40#define TVE_CD_CONT_REG 0x34
41#define TVE_INT_CONT_REG 0x64
42#define TVE_STAT_REG 0x68
43#define TVE_TST_MODE_REG 0x6c
44#define TVE_MV_CONT_REG 0xdc
45
46/* TVE_COM_CONF_REG */
47#define TVE_SYNC_CH_2_EN BIT(22)
48#define TVE_SYNC_CH_1_EN BIT(21)
49#define TVE_SYNC_CH_0_EN BIT(20)
50#define TVE_TV_OUT_MODE_MASK (0x7 << 12)
51#define TVE_TV_OUT_DISABLE (0x0 << 12)
52#define TVE_TV_OUT_CVBS_0 (0x1 << 12)
53#define TVE_TV_OUT_CVBS_2 (0x2 << 12)
54#define TVE_TV_OUT_CVBS_0_2 (0x3 << 12)
55#define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12)
56#define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12)
57#define TVE_TV_OUT_YPBPR (0x6 << 12)
58#define TVE_TV_OUT_RGB (0x7 << 12)
59#define TVE_TV_STAND_MASK (0xf << 8)
60#define TVE_TV_STAND_HD_1080P30 (0xc << 8)
61#define TVE_P2I_CONV_EN BIT(7)
62#define TVE_INP_VIDEO_FORM BIT(6)
63#define TVE_INP_YCBCR_422 (0x0 << 6)
64#define TVE_INP_YCBCR_444 (0x1 << 6)
65#define TVE_DATA_SOURCE_MASK (0x3 << 4)
66#define TVE_DATA_SOURCE_BUS1 (0x0 << 4)
67#define TVE_DATA_SOURCE_BUS2 (0x1 << 4)
68#define TVE_DATA_SOURCE_EXT (0x2 << 4)
69#define TVE_DATA_SOURCE_TESTGEN (0x3 << 4)
70#define TVE_IPU_CLK_EN_OFS 3
71#define TVE_IPU_CLK_EN BIT(3)
72#define TVE_DAC_SAMP_RATE_OFS 1
73#define TVE_DAC_SAMP_RATE_WIDTH 2
74#define TVE_DAC_SAMP_RATE_MASK (0x3 << 1)
75#define TVE_DAC_FULL_RATE (0x0 << 1)
76#define TVE_DAC_DIV2_RATE (0x1 << 1)
77#define TVE_DAC_DIV4_RATE (0x2 << 1)
78#define TVE_EN BIT(0)
79
80/* TVE_TVDACx_CONT_REG */
81#define TVE_TVDAC_GAIN_MASK (0x3f << 0)
82
83/* TVE_CD_CONT_REG */
84#define TVE_CD_CH_2_SM_EN BIT(22)
85#define TVE_CD_CH_1_SM_EN BIT(21)
86#define TVE_CD_CH_0_SM_EN BIT(20)
87#define TVE_CD_CH_2_LM_EN BIT(18)
88#define TVE_CD_CH_1_LM_EN BIT(17)
89#define TVE_CD_CH_0_LM_EN BIT(16)
90#define TVE_CD_CH_2_REF_LVL BIT(10)
91#define TVE_CD_CH_1_REF_LVL BIT(9)
92#define TVE_CD_CH_0_REF_LVL BIT(8)
93#define TVE_CD_EN BIT(0)
94
95/* TVE_INT_CONT_REG */
96#define TVE_FRAME_END_IEN BIT(13)
97#define TVE_CD_MON_END_IEN BIT(2)
98#define TVE_CD_SM_IEN BIT(1)
99#define TVE_CD_LM_IEN BIT(0)
100
101/* TVE_TST_MODE_REG */
102#define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0)
103
104#define con_to_tve(x) container_of(x, struct imx_tve, connector)
105#define enc_to_tve(x) container_of(x, struct imx_tve, encoder)
106
107enum {
108 TVE_MODE_TVOUT,
109 TVE_MODE_VGA,
110};
111
112struct imx_tve {
113 struct drm_connector connector;
fcbc51e5 114 struct drm_encoder encoder;
fcbc51e5 115 struct device *dev;
fcbc51e5
PZ		 116 spinlock_t lock; /* register lock */
117 bool enabled;
118 int mode;
119
120 struct regmap *regmap;
121 struct regulator *dac_reg;
122 struct i2c_adapter *ddc;
123 struct clk *clk;
124 struct clk *di_sel_clk;
125 struct clk_hw clk_hw_di;
126 struct clk *di_clk;
127 int vsync_pin;
128 int hsync_pin;
129};
130
131static void tve_lock(void *__tve)
5d78bf80 132__acquires(&tve->lock)
fcbc51e5
PZ		 133{
134 struct imx_tve *tve = __tve;
135 spin_lock(&tve->lock);
136}
137
138static void tve_unlock(void *__tve)
5d78bf80 139__releases(&tve->lock)
fcbc51e5
PZ		 140{
141 struct imx_tve *tve = __tve;
142 spin_unlock(&tve->lock);
143}
144
145static void tve_enable(struct imx_tve *tve)
146{
fcbc51e5
PZ		 147 int ret;
148
fcbc51e5 149 if (!tve->enabled) {
89bc5be7 150 tve->enabled = true;
fcbc51e5
PZ		 151 clk_prepare_enable(tve->clk);
152 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
153 TVE_IPU_CLK_EN | TVE_EN,
154 TVE_IPU_CLK_EN | TVE_EN);
155 }
156
157 /* clear interrupt status register */
158 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
159
160 /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */
161 if (tve->mode == TVE_MODE_VGA)
162 regmap_write(tve->regmap, TVE_INT_CONT_REG, 0);
163 else
164 regmap_write(tve->regmap, TVE_INT_CONT_REG,
89911e58
AW		 165 TVE_CD_SM_IEN |
166 TVE_CD_LM_IEN |
167 TVE_CD_MON_END_IEN);
fcbc51e5
PZ		 168}
169
170static void tve_disable(struct imx_tve *tve)
171{
fcbc51e5
PZ		 172 int ret;
173
fcbc51e5 174 if (tve->enabled) {
89bc5be7 175 tve->enabled = false;
fcbc51e5
PZ		 176 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
177 TVE_IPU_CLK_EN | TVE_EN, 0);
178 clk_disable_unprepare(tve->clk);
179 }
fcbc51e5
PZ		 180}
181
182static int tve_setup_tvout(struct imx_tve *tve)
183{
184 return -ENOTSUPP;
185}
186
187static int tve_setup_vga(struct imx_tve *tve)
188{
189 unsigned int mask;
190 unsigned int val;
191 int ret;
192
193 /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */
194 ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG,
195 TVE_TVDAC_GAIN_MASK, 0x0a);
196 ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG,
197 TVE_TVDAC_GAIN_MASK, 0x0a);
198 ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG,
199 TVE_TVDAC_GAIN_MASK, 0x0a);
200
201 /* set configuration register */
202 mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM;
203 val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444;
204 mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN;
205 val |= TVE_TV_STAND_HD_1080P30 | 0;
206 mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN;
207 val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN;
208 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val);
209 if (ret < 0) {
210 dev_err(tve->dev, "failed to set configuration: %d\n", ret);
211 return ret;
212 }
213
214 /* set test mode (as documented) */
215 ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG,
216 TVE_TVDAC_TEST_MODE_MASK, 1);
217
218 return 0;
219}
220
221static enum drm_connector_status imx_tve_connector_detect(
222 struct drm_connector *connector, bool force)
223{
224 return connector_status_connected;
225}
226
fcbc51e5
PZ		 227static int imx_tve_connector_get_modes(struct drm_connector *connector)
228{
229 struct imx_tve *tve = con_to_tve(connector);
230 struct edid *edid;
231 int ret = 0;
232
233 if (!tve->ddc)
234 return 0;
235
236 edid = drm_get_edid(connector, tve->ddc);
237 if (edid) {
238 drm_mode_connector_update_edid_property(connector, edid);
239 ret = drm_add_edid_modes(connector, edid);
240 kfree(edid);
241 }
242
243 return ret;
244}
245
246static int imx_tve_connector_mode_valid(struct drm_connector *connector,
247 struct drm_display_mode *mode)
248{
249 struct imx_tve *tve = con_to_tve(connector);
250 unsigned long rate;
baa68c4b
RK		 251 int ret;
252
253 ret = imx_drm_connector_mode_valid(connector, mode);
254 if (ret != MODE_OK)
255 return ret;
fcbc51e5
PZ		 256
257 /* pixel clock with 2x oversampling */
258 rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000;
259 if (rate == mode->clock)
260 return MODE_OK;
261
262 /* pixel clock without oversampling */
263 rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000;
264 if (rate == mode->clock)
265 return MODE_OK;
266
267 dev_warn(tve->dev, "ignoring mode %dx%d\n",
268 mode->hdisplay, mode->vdisplay);
269
270 return MODE_BAD;
271}
272
273static struct drm_encoder *imx_tve_connector_best_encoder(
274 struct drm_connector *connector)
275{
276 struct imx_tve *tve = con_to_tve(connector);
277
278 return &tve->encoder;
279}
280
281static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode)
282{
283 struct imx_tve *tve = enc_to_tve(encoder);
284 int ret;
285
286 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
287 TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE);
288 if (ret < 0)
289 dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret);
290}
291
292static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder,
293 const struct drm_display_mode *mode,
294 struct drm_display_mode *adjusted_mode)
295{
296 return true;
297}
298
299static void imx_tve_encoder_prepare(struct drm_encoder *encoder)
300{
301 struct imx_tve *tve = enc_to_tve(encoder);
302
303 tve_disable(tve);
304
305 switch (tve->mode) {
306 case TVE_MODE_VGA:
f2d66aad 307 imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24,
fcbc51e5
PZ		 308 tve->hsync_pin, tve->vsync_pin);
309 break;
310 case TVE_MODE_TVOUT:
f2d66aad 311 imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444);
fcbc51e5
PZ		 312 break;
313 }
314}
315
316static void imx_tve_encoder_mode_set(struct drm_encoder *encoder,
317 struct drm_display_mode *mode,
318 struct drm_display_mode *adjusted_mode)
319{
320 struct imx_tve *tve = enc_to_tve(encoder);
321 unsigned long rounded_rate;
322 unsigned long rate;
323 int div = 1;
324 int ret;
325
326 /*
327 * FIXME
328 * we should try 4k * mode->clock first,
329 * and enable 4x oversampling for lower resolutions
330 */
331 rate = 2000UL * mode->clock;
332 clk_set_rate(tve->clk, rate);
333 rounded_rate = clk_get_rate(tve->clk);
334 if (rounded_rate >= rate)
335 div = 2;
336 clk_set_rate(tve->di_clk, rounded_rate / div);
337
338 ret = clk_set_parent(tve->di_sel_clk, tve->di_clk);
339 if (ret < 0) {
340 dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n",
341 ret);
342 }
343
344 if (tve->mode == TVE_MODE_VGA)
345 tve_setup_vga(tve);
346 else
347 tve_setup_tvout(tve);
348}
349
350static void imx_tve_encoder_commit(struct drm_encoder *encoder)
351{
352 struct imx_tve *tve = enc_to_tve(encoder);
353
354 tve_enable(tve);
355}
356
357static void imx_tve_encoder_disable(struct drm_encoder *encoder)
358{
359 struct imx_tve *tve = enc_to_tve(encoder);
360
361 tve_disable(tve);
362}
363
fcbc51e5
PZ		 364static struct drm_connector_funcs imx_tve_connector_funcs = {
365 .dpms = drm_helper_connector_dpms,
366 .fill_modes = drm_helper_probe_single_connector_modes,
367 .detect = imx_tve_connector_detect,
1b3f7675 368 .destroy = imx_drm_connector_destroy,
fcbc51e5
PZ		 369};
370
371static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = {
372 .get_modes = imx_tve_connector_get_modes,
373 .best_encoder = imx_tve_connector_best_encoder,
374 .mode_valid = imx_tve_connector_mode_valid,
375};
376
377static struct drm_encoder_funcs imx_tve_encoder_funcs = {
1b3f7675 378 .destroy = imx_drm_encoder_destroy,
fcbc51e5
PZ		 379};
380
381static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = {
382 .dpms = imx_tve_encoder_dpms,
383 .mode_fixup = imx_tve_encoder_mode_fixup,
384 .prepare = imx_tve_encoder_prepare,
385 .mode_set = imx_tve_encoder_mode_set,
386 .commit = imx_tve_encoder_commit,
387 .disable = imx_tve_encoder_disable,
388};
389
390static irqreturn_t imx_tve_irq_handler(int irq, void *data)
391{
392 struct imx_tve *tve = data;
393 unsigned int val;
394
395 regmap_read(tve->regmap, TVE_STAT_REG, &val);
396
397 /* clear interrupt status register */
398 regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff);
399
400 return IRQ_HANDLED;
401}
402
403static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw,
404 unsigned long parent_rate)
405{
406 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
407 unsigned int val;
408 int ret;
409
410 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
411 if (ret < 0)
412 return 0;
413
414 switch (val & TVE_DAC_SAMP_RATE_MASK) {
415 case TVE_DAC_DIV4_RATE:
416 return parent_rate / 4;
417 case TVE_DAC_DIV2_RATE:
418 return parent_rate / 2;
419 case TVE_DAC_FULL_RATE:
420 default:
421 return parent_rate;
422 }
423
424 return 0;
425}
426
427static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate,
428 unsigned long *prate)
429{
430 unsigned long div;
431
432 div = *prate / rate;
433 if (div >= 4)
434 return *prate / 4;
435 else if (div >= 2)
436 return *prate / 2;
437 else
438 return *prate;
439}
440
441static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate,
442 unsigned long parent_rate)
443{
444 struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di);
445 unsigned long div;
446 u32 val;
447 int ret;
448
449 div = parent_rate / rate;
450 if (div >= 4)
451 val = TVE_DAC_DIV4_RATE;
452 else if (div >= 2)
453 val = TVE_DAC_DIV2_RATE;
454 else
455 val = TVE_DAC_FULL_RATE;
456
89911e58
AW		 457 ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG,
458 TVE_DAC_SAMP_RATE_MASK, val);
459
fcbc51e5
PZ		 460 if (ret < 0) {
461 dev_err(tve->dev, "failed to set divider: %d\n", ret);
462 return ret;
463 }
464
465 return 0;
466}
467
468static struct clk_ops clk_tve_di_ops = {
469 .round_rate = clk_tve_di_round_rate,
470 .set_rate = clk_tve_di_set_rate,
471 .recalc_rate = clk_tve_di_recalc_rate,
472};
473
474static int tve_clk_init(struct imx_tve *tve, void __iomem *base)
475{
476 const char *tve_di_parent[1];
477 struct clk_init_data init = {
478 .name = "tve_di",
479 .ops = &clk_tve_di_ops,
480 .num_parents = 1,
481 .flags = 0,
482 };
483
484 tve_di_parent[0] = __clk_get_name(tve->clk);
485 init.parent_names = (const char **)&tve_di_parent;
486
487 tve->clk_hw_di.init = &init;
488 tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di);
489 if (IS_ERR(tve->di_clk)) {
490 dev_err(tve->dev, "failed to register TVE output clock: %ld\n",
491 PTR_ERR(tve->di_clk));
492 return PTR_ERR(tve->di_clk);
493 }
494
495 return 0;
496}
497
1b3f7675 498static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve)
fcbc51e5 499{
f2d66aad 500 int encoder_type;
fcbc51e5
PZ		 501 int ret;
502
f2d66aad
RK		 503 encoder_type = tve->mode == TVE_MODE_VGA ?
504 DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
505
1b3f7675
RK		 506 ret = imx_drm_encoder_parse_of(drm, &tve->encoder,
507 tve->dev->of_node);
508 if (ret)
509 return ret;
fcbc51e5
PZ		 510
511 drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
1b3f7675
RK		 512 drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs,
513 encoder_type);
fcbc51e5
PZ		 514
515 drm_connector_helper_add(&tve->connector,
516 &imx_tve_connector_helper_funcs);
1b3f7675
RK		 517 drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs,
518 DRM_MODE_CONNECTOR_VGA);
fcbc51e5
PZ		 519
520 drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
521
522 return 0;
523}
524
525static bool imx_tve_readable_reg(struct device *dev, unsigned int reg)
526{
527 return (reg % 4 == 0) && (reg <= 0xdc);
528}
529
530static struct regmap_config tve_regmap_config = {
531 .reg_bits = 32,
532 .val_bits = 32,
533 .reg_stride = 4,
534
535 .readable_reg = imx_tve_readable_reg,
536
537 .lock = tve_lock,
538 .unlock = tve_unlock,
539
540 .max_register = 0xdc,
541};
542
543static const char *imx_tve_modes[] = {
544 [TVE_MODE_TVOUT] = "tvout",
545 [TVE_MODE_VGA] = "vga",
546};
547
7fc6cb28 548static const int of_get_tve_mode(struct device_node *np)
fcbc51e5
PZ		 549{
550 const char *bm;
551 int ret, i;
552
553 ret = of_property_read_string(np, "fsl,tve-mode", &bm);
554 if (ret < 0)
555 return ret;
556
557 for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++)
558 if (!strcasecmp(bm, imx_tve_modes[i]))
559 return i;
560
561 return -EINVAL;
562}
563
17b5001b 564static int imx_tve_bind(struct device *dev, struct device *master, void *data)
fcbc51e5 565{
17b5001b 566 struct platform_device *pdev = to_platform_device(dev);
1b3f7675 567 struct drm_device *drm = data;
17b5001b 568 struct device_node *np = dev->of_node;
fcbc51e5
PZ		 569 struct device_node *ddc_node;
570 struct imx_tve *tve;
571 struct resource *res;
572 void __iomem *base;
573 unsigned int val;
574 int irq;
575 int ret;
576
17b5001b 577 tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
fcbc51e5
PZ		 578 if (!tve)
579 return -ENOMEM;
580
17b5001b 581 tve->dev = dev;
fcbc51e5 582 spin_lock_init(&tve->lock);
fcbc51e5
PZ		 583
584 ddc_node = of_parse_phandle(np, "ddc", 0);
585 if (ddc_node) {
586 tve->ddc = of_find_i2c_adapter_by_node(ddc_node);
587 of_node_put(ddc_node);
588 }
589
590 tve->mode = of_get_tve_mode(np);
591 if (tve->mode != TVE_MODE_VGA) {
17b5001b 592 dev_err(dev, "only VGA mode supported, currently\n");
fcbc51e5
PZ		 593 return -EINVAL;
594 }
595
596 if (tve->mode == TVE_MODE_VGA) {
89911e58
AW		 597 ret = of_property_read_u32(np, "fsl,hsync-pin",
598 &tve->hsync_pin);
599
fcbc51e5 600 if (ret < 0) {
17b5001b 601 dev_err(dev, "failed to get vsync pin\n");
fcbc51e5
PZ		 602 return ret;
603 }
604
89911e58
AW		 605 ret |= of_property_read_u32(np, "fsl,vsync-pin",
606 &tve->vsync_pin);
607
fcbc51e5 608 if (ret < 0) {
17b5001b 609 dev_err(dev, "failed to get vsync pin\n");
fcbc51e5
PZ		 610 return ret;
611 }
612 }
613
614 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
17b5001b 615 base = devm_ioremap_resource(dev, res);
9b43b56f
LN		 616 if (IS_ERR(base))
617 return PTR_ERR(base);
fcbc51e5
PZ		 618
619 tve_regmap_config.lock_arg = tve;
17b5001b 620 tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base,
fcbc51e5
PZ		 621 &tve_regmap_config);
622 if (IS_ERR(tve->regmap)) {
17b5001b 623 dev_err(dev, "failed to init regmap: %ld\n",
fcbc51e5
PZ		 624 PTR_ERR(tve->regmap));
625 return PTR_ERR(tve->regmap);
626 }
627
628 irq = platform_get_irq(pdev, 0);
629 if (irq < 0) {
17b5001b 630 dev_err(dev, "failed to get irq\n");
fcbc51e5
PZ		 631 return irq;
632 }
633
17b5001b 634 ret = devm_request_threaded_irq(dev, irq, NULL,
fcbc51e5
PZ		 635 imx_tve_irq_handler, IRQF_ONESHOT,
636 "imx-tve", tve);
637 if (ret < 0) {
17b5001b 638 dev_err(dev, "failed to request irq: %d\n", ret);
fcbc51e5
PZ		 639 return ret;
640 }
641
17b5001b 642 tve->dac_reg = devm_regulator_get(dev, "dac");
fcbc51e5
PZ		 643 if (!IS_ERR(tve->dac_reg)) {
644 regulator_set_voltage(tve->dac_reg, 2750000, 2750000);
c7b0cf3e
FE		 645 ret = regulator_enable(tve->dac_reg);
646 if (ret)
647 return ret;
fcbc51e5
PZ		 648 }
649
17b5001b 650 tve->clk = devm_clk_get(dev, "tve");
fcbc51e5 651 if (IS_ERR(tve->clk)) {
17b5001b 652 dev_err(dev, "failed to get high speed tve clock: %ld\n",
fcbc51e5
PZ		 653 PTR_ERR(tve->clk));
654 return PTR_ERR(tve->clk);
655 }
656
657 /* this is the IPU DI clock input selector, can be parented to tve_di */
17b5001b 658 tve->di_sel_clk = devm_clk_get(dev, "di_sel");
fcbc51e5 659 if (IS_ERR(tve->di_sel_clk)) {
17b5001b 660 dev_err(dev, "failed to get ipu di mux clock: %ld\n",
fcbc51e5
PZ		 661 PTR_ERR(tve->di_sel_clk));
662 return PTR_ERR(tve->di_sel_clk);
663 }
664
665 ret = tve_clk_init(tve, base);
666 if (ret < 0)
667 return ret;
668
669 ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val);
670 if (ret < 0) {
17b5001b 671 dev_err(dev, "failed to read configuration register: %d\n", ret);
fcbc51e5
PZ		 672 return ret;
673 }
674 if (val != 0x00100000) {
17b5001b 675 dev_err(dev, "configuration register default value indicates this is not a TVEv2\n");
fcbc51e5 676 return -ENODEV;
a22526e4 677 }
fcbc51e5
PZ		 678
679 /* disable cable detection for VGA mode */
680 ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0);
681
1b3f7675 682 ret = imx_tve_register(drm, tve);
fcbc51e5
PZ		 683 if (ret)
684 return ret;
685
17b5001b 686 dev_set_drvdata(dev, tve);
fcbc51e5
PZ		 687
688 return 0;
689}
690
17b5001b
RK		 691static void imx_tve_unbind(struct device *dev, struct device *master,
692 void *data)
fcbc51e5 693{
17b5001b 694 struct imx_tve *tve = dev_get_drvdata(dev);
fcbc51e5 695
1b3f7675
RK		 696 tve->connector.funcs->destroy(&tve->connector);
697 tve->encoder.funcs->destroy(&tve->encoder);
fcbc51e5
PZ		 698
699 if (!IS_ERR(tve->dac_reg))
700 regulator_disable(tve->dac_reg);
17b5001b 701}
fcbc51e5 702
17b5001b
RK		 703static const struct component_ops imx_tve_ops = {
704 .bind = imx_tve_bind,
705 .unbind = imx_tve_unbind,
706};
707
708static int imx_tve_probe(struct platform_device *pdev)
709{
710 return component_add(&pdev->dev, &imx_tve_ops);
711}
712
713static int imx_tve_remove(struct platform_device *pdev)
714{
715 component_del(&pdev->dev, &imx_tve_ops);
fcbc51e5
PZ		 716 return 0;
717}
718
719static const struct of_device_id imx_tve_dt_ids[] = {
720 { .compatible = "fsl,imx53-tve", },
721 { /* sentinel */ }
722};
723
724static struct platform_driver imx_tve_driver = {
725 .probe = imx_tve_probe,
726 .remove = imx_tve_remove,
727 .driver = {
728 .of_match_table = imx_tve_dt_ids,
729 .name = "imx-tve",
730 .owner = THIS_MODULE,
731 },
732};
733
734module_platform_driver(imx_tve_driver);
735
736MODULE_DESCRIPTION("i.MX Television Encoder driver");
737MODULE_AUTHOR("Philipp Zabel, Pengutronix");
738MODULE_LICENSE("GPL");
52db752c 739MODULE_ALIAS("platform:imx-tve");
Linux kernel - Deliverables
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