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fcbc51e5 PZ |
1 | /* |
2 | * i.MX drm driver - Television Encoder (TVEv2) | |
3 | * | |
4 | * Copyright (C) 2013 Philipp Zabel, Pengutronix | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version 2 | |
9 | * of the License, or (at your option) any later version. | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, | |
18 | * MA 02110-1301, USA. | |
19 | */ | |
20 | ||
21 | #include <linux/clk.h> | |
22 | #include <linux/clk-provider.h> | |
17b5001b | 23 | #include <linux/component.h> |
fcbc51e5 | 24 | #include <linux/module.h> |
687b81d0 | 25 | #include <linux/i2c.h> |
fcbc51e5 PZ |
26 | #include <linux/regmap.h> |
27 | #include <linux/regulator/consumer.h> | |
28 | #include <linux/spinlock.h> | |
29 | #include <linux/videodev2.h> | |
30 | #include <drm/drmP.h> | |
31 | #include <drm/drm_fb_helper.h> | |
32 | #include <drm/drm_crtc_helper.h> | |
33 | ||
7f4392aa | 34 | #include "ipu-v3/imx-ipu-v3.h" |
fcbc51e5 PZ |
35 | #include "imx-drm.h" |
36 | ||
37 | #define TVE_COM_CONF_REG 0x00 | |
38 | #define TVE_TVDAC0_CONT_REG 0x28 | |
39 | #define TVE_TVDAC1_CONT_REG 0x2c | |
40 | #define TVE_TVDAC2_CONT_REG 0x30 | |
41 | #define TVE_CD_CONT_REG 0x34 | |
42 | #define TVE_INT_CONT_REG 0x64 | |
43 | #define TVE_STAT_REG 0x68 | |
44 | #define TVE_TST_MODE_REG 0x6c | |
45 | #define TVE_MV_CONT_REG 0xdc | |
46 | ||
47 | /* TVE_COM_CONF_REG */ | |
48 | #define TVE_SYNC_CH_2_EN BIT(22) | |
49 | #define TVE_SYNC_CH_1_EN BIT(21) | |
50 | #define TVE_SYNC_CH_0_EN BIT(20) | |
51 | #define TVE_TV_OUT_MODE_MASK (0x7 << 12) | |
52 | #define TVE_TV_OUT_DISABLE (0x0 << 12) | |
53 | #define TVE_TV_OUT_CVBS_0 (0x1 << 12) | |
54 | #define TVE_TV_OUT_CVBS_2 (0x2 << 12) | |
55 | #define TVE_TV_OUT_CVBS_0_2 (0x3 << 12) | |
56 | #define TVE_TV_OUT_SVIDEO_0_1 (0x4 << 12) | |
57 | #define TVE_TV_OUT_SVIDEO_0_1_CVBS2_2 (0x5 << 12) | |
58 | #define TVE_TV_OUT_YPBPR (0x6 << 12) | |
59 | #define TVE_TV_OUT_RGB (0x7 << 12) | |
60 | #define TVE_TV_STAND_MASK (0xf << 8) | |
61 | #define TVE_TV_STAND_HD_1080P30 (0xc << 8) | |
62 | #define TVE_P2I_CONV_EN BIT(7) | |
63 | #define TVE_INP_VIDEO_FORM BIT(6) | |
64 | #define TVE_INP_YCBCR_422 (0x0 << 6) | |
65 | #define TVE_INP_YCBCR_444 (0x1 << 6) | |
66 | #define TVE_DATA_SOURCE_MASK (0x3 << 4) | |
67 | #define TVE_DATA_SOURCE_BUS1 (0x0 << 4) | |
68 | #define TVE_DATA_SOURCE_BUS2 (0x1 << 4) | |
69 | #define TVE_DATA_SOURCE_EXT (0x2 << 4) | |
70 | #define TVE_DATA_SOURCE_TESTGEN (0x3 << 4) | |
71 | #define TVE_IPU_CLK_EN_OFS 3 | |
72 | #define TVE_IPU_CLK_EN BIT(3) | |
73 | #define TVE_DAC_SAMP_RATE_OFS 1 | |
74 | #define TVE_DAC_SAMP_RATE_WIDTH 2 | |
75 | #define TVE_DAC_SAMP_RATE_MASK (0x3 << 1) | |
76 | #define TVE_DAC_FULL_RATE (0x0 << 1) | |
77 | #define TVE_DAC_DIV2_RATE (0x1 << 1) | |
78 | #define TVE_DAC_DIV4_RATE (0x2 << 1) | |
79 | #define TVE_EN BIT(0) | |
80 | ||
81 | /* TVE_TVDACx_CONT_REG */ | |
82 | #define TVE_TVDAC_GAIN_MASK (0x3f << 0) | |
83 | ||
84 | /* TVE_CD_CONT_REG */ | |
85 | #define TVE_CD_CH_2_SM_EN BIT(22) | |
86 | #define TVE_CD_CH_1_SM_EN BIT(21) | |
87 | #define TVE_CD_CH_0_SM_EN BIT(20) | |
88 | #define TVE_CD_CH_2_LM_EN BIT(18) | |
89 | #define TVE_CD_CH_1_LM_EN BIT(17) | |
90 | #define TVE_CD_CH_0_LM_EN BIT(16) | |
91 | #define TVE_CD_CH_2_REF_LVL BIT(10) | |
92 | #define TVE_CD_CH_1_REF_LVL BIT(9) | |
93 | #define TVE_CD_CH_0_REF_LVL BIT(8) | |
94 | #define TVE_CD_EN BIT(0) | |
95 | ||
96 | /* TVE_INT_CONT_REG */ | |
97 | #define TVE_FRAME_END_IEN BIT(13) | |
98 | #define TVE_CD_MON_END_IEN BIT(2) | |
99 | #define TVE_CD_SM_IEN BIT(1) | |
100 | #define TVE_CD_LM_IEN BIT(0) | |
101 | ||
102 | /* TVE_TST_MODE_REG */ | |
103 | #define TVE_TVDAC_TEST_MODE_MASK (0x7 << 0) | |
104 | ||
105 | #define con_to_tve(x) container_of(x, struct imx_tve, connector) | |
106 | #define enc_to_tve(x) container_of(x, struct imx_tve, encoder) | |
107 | ||
108 | enum { | |
109 | TVE_MODE_TVOUT, | |
110 | TVE_MODE_VGA, | |
111 | }; | |
112 | ||
113 | struct imx_tve { | |
114 | struct drm_connector connector; | |
fcbc51e5 | 115 | struct drm_encoder encoder; |
fcbc51e5 | 116 | struct device *dev; |
fcbc51e5 PZ |
117 | spinlock_t lock; /* register lock */ |
118 | bool enabled; | |
119 | int mode; | |
120 | ||
121 | struct regmap *regmap; | |
122 | struct regulator *dac_reg; | |
123 | struct i2c_adapter *ddc; | |
124 | struct clk *clk; | |
125 | struct clk *di_sel_clk; | |
126 | struct clk_hw clk_hw_di; | |
127 | struct clk *di_clk; | |
128 | int vsync_pin; | |
129 | int hsync_pin; | |
130 | }; | |
131 | ||
132 | static void tve_lock(void *__tve) | |
5d78bf80 | 133 | __acquires(&tve->lock) |
fcbc51e5 PZ |
134 | { |
135 | struct imx_tve *tve = __tve; | |
136 | spin_lock(&tve->lock); | |
137 | } | |
138 | ||
139 | static void tve_unlock(void *__tve) | |
5d78bf80 | 140 | __releases(&tve->lock) |
fcbc51e5 PZ |
141 | { |
142 | struct imx_tve *tve = __tve; | |
143 | spin_unlock(&tve->lock); | |
144 | } | |
145 | ||
146 | static void tve_enable(struct imx_tve *tve) | |
147 | { | |
fcbc51e5 PZ |
148 | int ret; |
149 | ||
fcbc51e5 | 150 | if (!tve->enabled) { |
89bc5be7 | 151 | tve->enabled = true; |
fcbc51e5 PZ |
152 | clk_prepare_enable(tve->clk); |
153 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, | |
154 | TVE_IPU_CLK_EN | TVE_EN, | |
155 | TVE_IPU_CLK_EN | TVE_EN); | |
156 | } | |
157 | ||
158 | /* clear interrupt status register */ | |
159 | regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); | |
160 | ||
161 | /* cable detection irq disabled in VGA mode, enabled in TVOUT mode */ | |
162 | if (tve->mode == TVE_MODE_VGA) | |
163 | regmap_write(tve->regmap, TVE_INT_CONT_REG, 0); | |
164 | else | |
165 | regmap_write(tve->regmap, TVE_INT_CONT_REG, | |
89911e58 AW |
166 | TVE_CD_SM_IEN | |
167 | TVE_CD_LM_IEN | | |
168 | TVE_CD_MON_END_IEN); | |
fcbc51e5 PZ |
169 | } |
170 | ||
171 | static void tve_disable(struct imx_tve *tve) | |
172 | { | |
fcbc51e5 PZ |
173 | int ret; |
174 | ||
fcbc51e5 | 175 | if (tve->enabled) { |
89bc5be7 | 176 | tve->enabled = false; |
fcbc51e5 PZ |
177 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, |
178 | TVE_IPU_CLK_EN | TVE_EN, 0); | |
179 | clk_disable_unprepare(tve->clk); | |
180 | } | |
fcbc51e5 PZ |
181 | } |
182 | ||
183 | static int tve_setup_tvout(struct imx_tve *tve) | |
184 | { | |
185 | return -ENOTSUPP; | |
186 | } | |
187 | ||
188 | static int tve_setup_vga(struct imx_tve *tve) | |
189 | { | |
190 | unsigned int mask; | |
191 | unsigned int val; | |
192 | int ret; | |
193 | ||
194 | /* set gain to (1 + 10/128) to provide 0.7V peak-to-peak amplitude */ | |
195 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC0_CONT_REG, | |
196 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
197 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC1_CONT_REG, | |
198 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
199 | ret = regmap_update_bits(tve->regmap, TVE_TVDAC2_CONT_REG, | |
200 | TVE_TVDAC_GAIN_MASK, 0x0a); | |
201 | ||
202 | /* set configuration register */ | |
203 | mask = TVE_DATA_SOURCE_MASK | TVE_INP_VIDEO_FORM; | |
204 | val = TVE_DATA_SOURCE_BUS2 | TVE_INP_YCBCR_444; | |
205 | mask |= TVE_TV_STAND_MASK | TVE_P2I_CONV_EN; | |
206 | val |= TVE_TV_STAND_HD_1080P30 | 0; | |
207 | mask |= TVE_TV_OUT_MODE_MASK | TVE_SYNC_CH_0_EN; | |
208 | val |= TVE_TV_OUT_RGB | TVE_SYNC_CH_0_EN; | |
209 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, mask, val); | |
210 | if (ret < 0) { | |
211 | dev_err(tve->dev, "failed to set configuration: %d\n", ret); | |
212 | return ret; | |
213 | } | |
214 | ||
215 | /* set test mode (as documented) */ | |
216 | ret = regmap_update_bits(tve->regmap, TVE_TST_MODE_REG, | |
217 | TVE_TVDAC_TEST_MODE_MASK, 1); | |
218 | ||
219 | return 0; | |
220 | } | |
221 | ||
222 | static enum drm_connector_status imx_tve_connector_detect( | |
223 | struct drm_connector *connector, bool force) | |
224 | { | |
225 | return connector_status_connected; | |
226 | } | |
227 | ||
fcbc51e5 PZ |
228 | static int imx_tve_connector_get_modes(struct drm_connector *connector) |
229 | { | |
230 | struct imx_tve *tve = con_to_tve(connector); | |
231 | struct edid *edid; | |
232 | int ret = 0; | |
233 | ||
234 | if (!tve->ddc) | |
235 | return 0; | |
236 | ||
237 | edid = drm_get_edid(connector, tve->ddc); | |
238 | if (edid) { | |
239 | drm_mode_connector_update_edid_property(connector, edid); | |
240 | ret = drm_add_edid_modes(connector, edid); | |
241 | kfree(edid); | |
242 | } | |
243 | ||
244 | return ret; | |
245 | } | |
246 | ||
247 | static int imx_tve_connector_mode_valid(struct drm_connector *connector, | |
248 | struct drm_display_mode *mode) | |
249 | { | |
250 | struct imx_tve *tve = con_to_tve(connector); | |
251 | unsigned long rate; | |
baa68c4b RK |
252 | int ret; |
253 | ||
fcbc51e5 PZ |
254 | /* pixel clock with 2x oversampling */ |
255 | rate = clk_round_rate(tve->clk, 2000UL * mode->clock) / 2000; | |
256 | if (rate == mode->clock) | |
257 | return MODE_OK; | |
258 | ||
259 | /* pixel clock without oversampling */ | |
260 | rate = clk_round_rate(tve->clk, 1000UL * mode->clock) / 1000; | |
261 | if (rate == mode->clock) | |
262 | return MODE_OK; | |
263 | ||
264 | dev_warn(tve->dev, "ignoring mode %dx%d\n", | |
265 | mode->hdisplay, mode->vdisplay); | |
266 | ||
267 | return MODE_BAD; | |
268 | } | |
269 | ||
270 | static struct drm_encoder *imx_tve_connector_best_encoder( | |
271 | struct drm_connector *connector) | |
272 | { | |
273 | struct imx_tve *tve = con_to_tve(connector); | |
274 | ||
275 | return &tve->encoder; | |
276 | } | |
277 | ||
278 | static void imx_tve_encoder_dpms(struct drm_encoder *encoder, int mode) | |
279 | { | |
280 | struct imx_tve *tve = enc_to_tve(encoder); | |
281 | int ret; | |
282 | ||
283 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, | |
284 | TVE_TV_OUT_MODE_MASK, TVE_TV_OUT_DISABLE); | |
285 | if (ret < 0) | |
286 | dev_err(tve->dev, "failed to disable TVOUT: %d\n", ret); | |
287 | } | |
288 | ||
289 | static bool imx_tve_encoder_mode_fixup(struct drm_encoder *encoder, | |
290 | const struct drm_display_mode *mode, | |
291 | struct drm_display_mode *adjusted_mode) | |
292 | { | |
293 | return true; | |
294 | } | |
295 | ||
296 | static void imx_tve_encoder_prepare(struct drm_encoder *encoder) | |
297 | { | |
298 | struct imx_tve *tve = enc_to_tve(encoder); | |
299 | ||
300 | tve_disable(tve); | |
301 | ||
302 | switch (tve->mode) { | |
303 | case TVE_MODE_VGA: | |
f2d66aad | 304 | imx_drm_panel_format_pins(encoder, IPU_PIX_FMT_GBR24, |
fcbc51e5 PZ |
305 | tve->hsync_pin, tve->vsync_pin); |
306 | break; | |
307 | case TVE_MODE_TVOUT: | |
f2d66aad | 308 | imx_drm_panel_format(encoder, V4L2_PIX_FMT_YUV444); |
fcbc51e5 PZ |
309 | break; |
310 | } | |
311 | } | |
312 | ||
313 | static void imx_tve_encoder_mode_set(struct drm_encoder *encoder, | |
314 | struct drm_display_mode *mode, | |
315 | struct drm_display_mode *adjusted_mode) | |
316 | { | |
317 | struct imx_tve *tve = enc_to_tve(encoder); | |
318 | unsigned long rounded_rate; | |
319 | unsigned long rate; | |
320 | int div = 1; | |
321 | int ret; | |
322 | ||
323 | /* | |
324 | * FIXME | |
325 | * we should try 4k * mode->clock first, | |
326 | * and enable 4x oversampling for lower resolutions | |
327 | */ | |
328 | rate = 2000UL * mode->clock; | |
329 | clk_set_rate(tve->clk, rate); | |
330 | rounded_rate = clk_get_rate(tve->clk); | |
331 | if (rounded_rate >= rate) | |
332 | div = 2; | |
333 | clk_set_rate(tve->di_clk, rounded_rate / div); | |
334 | ||
335 | ret = clk_set_parent(tve->di_sel_clk, tve->di_clk); | |
336 | if (ret < 0) { | |
337 | dev_err(tve->dev, "failed to set di_sel parent to tve_di: %d\n", | |
338 | ret); | |
339 | } | |
340 | ||
341 | if (tve->mode == TVE_MODE_VGA) | |
342 | tve_setup_vga(tve); | |
343 | else | |
344 | tve_setup_tvout(tve); | |
345 | } | |
346 | ||
347 | static void imx_tve_encoder_commit(struct drm_encoder *encoder) | |
348 | { | |
349 | struct imx_tve *tve = enc_to_tve(encoder); | |
350 | ||
351 | tve_enable(tve); | |
352 | } | |
353 | ||
354 | static void imx_tve_encoder_disable(struct drm_encoder *encoder) | |
355 | { | |
356 | struct imx_tve *tve = enc_to_tve(encoder); | |
357 | ||
358 | tve_disable(tve); | |
359 | } | |
360 | ||
fcbc51e5 PZ |
361 | static struct drm_connector_funcs imx_tve_connector_funcs = { |
362 | .dpms = drm_helper_connector_dpms, | |
363 | .fill_modes = drm_helper_probe_single_connector_modes, | |
364 | .detect = imx_tve_connector_detect, | |
1b3f7675 | 365 | .destroy = imx_drm_connector_destroy, |
fcbc51e5 PZ |
366 | }; |
367 | ||
368 | static struct drm_connector_helper_funcs imx_tve_connector_helper_funcs = { | |
369 | .get_modes = imx_tve_connector_get_modes, | |
370 | .best_encoder = imx_tve_connector_best_encoder, | |
371 | .mode_valid = imx_tve_connector_mode_valid, | |
372 | }; | |
373 | ||
374 | static struct drm_encoder_funcs imx_tve_encoder_funcs = { | |
1b3f7675 | 375 | .destroy = imx_drm_encoder_destroy, |
fcbc51e5 PZ |
376 | }; |
377 | ||
378 | static struct drm_encoder_helper_funcs imx_tve_encoder_helper_funcs = { | |
379 | .dpms = imx_tve_encoder_dpms, | |
380 | .mode_fixup = imx_tve_encoder_mode_fixup, | |
381 | .prepare = imx_tve_encoder_prepare, | |
382 | .mode_set = imx_tve_encoder_mode_set, | |
383 | .commit = imx_tve_encoder_commit, | |
384 | .disable = imx_tve_encoder_disable, | |
385 | }; | |
386 | ||
387 | static irqreturn_t imx_tve_irq_handler(int irq, void *data) | |
388 | { | |
389 | struct imx_tve *tve = data; | |
390 | unsigned int val; | |
391 | ||
392 | regmap_read(tve->regmap, TVE_STAT_REG, &val); | |
393 | ||
394 | /* clear interrupt status register */ | |
395 | regmap_write(tve->regmap, TVE_STAT_REG, 0xffffffff); | |
396 | ||
397 | return IRQ_HANDLED; | |
398 | } | |
399 | ||
400 | static unsigned long clk_tve_di_recalc_rate(struct clk_hw *hw, | |
401 | unsigned long parent_rate) | |
402 | { | |
403 | struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); | |
404 | unsigned int val; | |
405 | int ret; | |
406 | ||
407 | ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); | |
408 | if (ret < 0) | |
409 | return 0; | |
410 | ||
411 | switch (val & TVE_DAC_SAMP_RATE_MASK) { | |
412 | case TVE_DAC_DIV4_RATE: | |
413 | return parent_rate / 4; | |
414 | case TVE_DAC_DIV2_RATE: | |
415 | return parent_rate / 2; | |
416 | case TVE_DAC_FULL_RATE: | |
417 | default: | |
418 | return parent_rate; | |
419 | } | |
420 | ||
421 | return 0; | |
422 | } | |
423 | ||
424 | static long clk_tve_di_round_rate(struct clk_hw *hw, unsigned long rate, | |
425 | unsigned long *prate) | |
426 | { | |
427 | unsigned long div; | |
428 | ||
429 | div = *prate / rate; | |
430 | if (div >= 4) | |
431 | return *prate / 4; | |
432 | else if (div >= 2) | |
433 | return *prate / 2; | |
434 | else | |
435 | return *prate; | |
436 | } | |
437 | ||
438 | static int clk_tve_di_set_rate(struct clk_hw *hw, unsigned long rate, | |
439 | unsigned long parent_rate) | |
440 | { | |
441 | struct imx_tve *tve = container_of(hw, struct imx_tve, clk_hw_di); | |
442 | unsigned long div; | |
443 | u32 val; | |
444 | int ret; | |
445 | ||
446 | div = parent_rate / rate; | |
447 | if (div >= 4) | |
448 | val = TVE_DAC_DIV4_RATE; | |
449 | else if (div >= 2) | |
450 | val = TVE_DAC_DIV2_RATE; | |
451 | else | |
452 | val = TVE_DAC_FULL_RATE; | |
453 | ||
89911e58 AW |
454 | ret = regmap_update_bits(tve->regmap, TVE_COM_CONF_REG, |
455 | TVE_DAC_SAMP_RATE_MASK, val); | |
456 | ||
fcbc51e5 PZ |
457 | if (ret < 0) { |
458 | dev_err(tve->dev, "failed to set divider: %d\n", ret); | |
459 | return ret; | |
460 | } | |
461 | ||
462 | return 0; | |
463 | } | |
464 | ||
465 | static struct clk_ops clk_tve_di_ops = { | |
466 | .round_rate = clk_tve_di_round_rate, | |
467 | .set_rate = clk_tve_di_set_rate, | |
468 | .recalc_rate = clk_tve_di_recalc_rate, | |
469 | }; | |
470 | ||
471 | static int tve_clk_init(struct imx_tve *tve, void __iomem *base) | |
472 | { | |
473 | const char *tve_di_parent[1]; | |
474 | struct clk_init_data init = { | |
475 | .name = "tve_di", | |
476 | .ops = &clk_tve_di_ops, | |
477 | .num_parents = 1, | |
478 | .flags = 0, | |
479 | }; | |
480 | ||
481 | tve_di_parent[0] = __clk_get_name(tve->clk); | |
482 | init.parent_names = (const char **)&tve_di_parent; | |
483 | ||
484 | tve->clk_hw_di.init = &init; | |
485 | tve->di_clk = clk_register(tve->dev, &tve->clk_hw_di); | |
486 | if (IS_ERR(tve->di_clk)) { | |
487 | dev_err(tve->dev, "failed to register TVE output clock: %ld\n", | |
488 | PTR_ERR(tve->di_clk)); | |
489 | return PTR_ERR(tve->di_clk); | |
490 | } | |
491 | ||
492 | return 0; | |
493 | } | |
494 | ||
1b3f7675 | 495 | static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve) |
fcbc51e5 | 496 | { |
f2d66aad | 497 | int encoder_type; |
fcbc51e5 PZ |
498 | int ret; |
499 | ||
f2d66aad RK |
500 | encoder_type = tve->mode == TVE_MODE_VGA ? |
501 | DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC; | |
502 | ||
1b3f7675 RK |
503 | ret = imx_drm_encoder_parse_of(drm, &tve->encoder, |
504 | tve->dev->of_node); | |
505 | if (ret) | |
506 | return ret; | |
fcbc51e5 PZ |
507 | |
508 | drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs); | |
1b3f7675 RK |
509 | drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs, |
510 | encoder_type); | |
fcbc51e5 PZ |
511 | |
512 | drm_connector_helper_add(&tve->connector, | |
513 | &imx_tve_connector_helper_funcs); | |
1b3f7675 RK |
514 | drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs, |
515 | DRM_MODE_CONNECTOR_VGA); | |
fcbc51e5 PZ |
516 | |
517 | drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder); | |
518 | ||
519 | return 0; | |
520 | } | |
521 | ||
522 | static bool imx_tve_readable_reg(struct device *dev, unsigned int reg) | |
523 | { | |
524 | return (reg % 4 == 0) && (reg <= 0xdc); | |
525 | } | |
526 | ||
527 | static struct regmap_config tve_regmap_config = { | |
528 | .reg_bits = 32, | |
529 | .val_bits = 32, | |
530 | .reg_stride = 4, | |
531 | ||
532 | .readable_reg = imx_tve_readable_reg, | |
533 | ||
534 | .lock = tve_lock, | |
535 | .unlock = tve_unlock, | |
536 | ||
537 | .max_register = 0xdc, | |
538 | }; | |
539 | ||
540 | static const char *imx_tve_modes[] = { | |
541 | [TVE_MODE_TVOUT] = "tvout", | |
542 | [TVE_MODE_VGA] = "vga", | |
543 | }; | |
544 | ||
7fc6cb28 | 545 | static const int of_get_tve_mode(struct device_node *np) |
fcbc51e5 PZ |
546 | { |
547 | const char *bm; | |
548 | int ret, i; | |
549 | ||
550 | ret = of_property_read_string(np, "fsl,tve-mode", &bm); | |
551 | if (ret < 0) | |
552 | return ret; | |
553 | ||
554 | for (i = 0; i < ARRAY_SIZE(imx_tve_modes); i++) | |
555 | if (!strcasecmp(bm, imx_tve_modes[i])) | |
556 | return i; | |
557 | ||
558 | return -EINVAL; | |
559 | } | |
560 | ||
17b5001b | 561 | static int imx_tve_bind(struct device *dev, struct device *master, void *data) |
fcbc51e5 | 562 | { |
17b5001b | 563 | struct platform_device *pdev = to_platform_device(dev); |
1b3f7675 | 564 | struct drm_device *drm = data; |
17b5001b | 565 | struct device_node *np = dev->of_node; |
fcbc51e5 PZ |
566 | struct device_node *ddc_node; |
567 | struct imx_tve *tve; | |
568 | struct resource *res; | |
569 | void __iomem *base; | |
570 | unsigned int val; | |
571 | int irq; | |
572 | int ret; | |
573 | ||
17b5001b | 574 | tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL); |
fcbc51e5 PZ |
575 | if (!tve) |
576 | return -ENOMEM; | |
577 | ||
17b5001b | 578 | tve->dev = dev; |
fcbc51e5 | 579 | spin_lock_init(&tve->lock); |
fcbc51e5 | 580 | |
62e3879a | 581 | ddc_node = of_parse_phandle(np, "i2c-ddc-bus", 0); |
fcbc51e5 PZ |
582 | if (ddc_node) { |
583 | tve->ddc = of_find_i2c_adapter_by_node(ddc_node); | |
584 | of_node_put(ddc_node); | |
585 | } | |
586 | ||
587 | tve->mode = of_get_tve_mode(np); | |
588 | if (tve->mode != TVE_MODE_VGA) { | |
17b5001b | 589 | dev_err(dev, "only VGA mode supported, currently\n"); |
fcbc51e5 PZ |
590 | return -EINVAL; |
591 | } | |
592 | ||
593 | if (tve->mode == TVE_MODE_VGA) { | |
89911e58 AW |
594 | ret = of_property_read_u32(np, "fsl,hsync-pin", |
595 | &tve->hsync_pin); | |
596 | ||
fcbc51e5 | 597 | if (ret < 0) { |
17b5001b | 598 | dev_err(dev, "failed to get vsync pin\n"); |
fcbc51e5 PZ |
599 | return ret; |
600 | } | |
601 | ||
89911e58 AW |
602 | ret |= of_property_read_u32(np, "fsl,vsync-pin", |
603 | &tve->vsync_pin); | |
604 | ||
fcbc51e5 | 605 | if (ret < 0) { |
17b5001b | 606 | dev_err(dev, "failed to get vsync pin\n"); |
fcbc51e5 PZ |
607 | return ret; |
608 | } | |
609 | } | |
610 | ||
611 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
17b5001b | 612 | base = devm_ioremap_resource(dev, res); |
9b43b56f LN |
613 | if (IS_ERR(base)) |
614 | return PTR_ERR(base); | |
fcbc51e5 PZ |
615 | |
616 | tve_regmap_config.lock_arg = tve; | |
17b5001b | 617 | tve->regmap = devm_regmap_init_mmio_clk(dev, "tve", base, |
fcbc51e5 PZ |
618 | &tve_regmap_config); |
619 | if (IS_ERR(tve->regmap)) { | |
17b5001b | 620 | dev_err(dev, "failed to init regmap: %ld\n", |
fcbc51e5 PZ |
621 | PTR_ERR(tve->regmap)); |
622 | return PTR_ERR(tve->regmap); | |
623 | } | |
624 | ||
625 | irq = platform_get_irq(pdev, 0); | |
626 | if (irq < 0) { | |
17b5001b | 627 | dev_err(dev, "failed to get irq\n"); |
fcbc51e5 PZ |
628 | return irq; |
629 | } | |
630 | ||
17b5001b | 631 | ret = devm_request_threaded_irq(dev, irq, NULL, |
fcbc51e5 PZ |
632 | imx_tve_irq_handler, IRQF_ONESHOT, |
633 | "imx-tve", tve); | |
634 | if (ret < 0) { | |
17b5001b | 635 | dev_err(dev, "failed to request irq: %d\n", ret); |
fcbc51e5 PZ |
636 | return ret; |
637 | } | |
638 | ||
17b5001b | 639 | tve->dac_reg = devm_regulator_get(dev, "dac"); |
fcbc51e5 PZ |
640 | if (!IS_ERR(tve->dac_reg)) { |
641 | regulator_set_voltage(tve->dac_reg, 2750000, 2750000); | |
c7b0cf3e FE |
642 | ret = regulator_enable(tve->dac_reg); |
643 | if (ret) | |
644 | return ret; | |
fcbc51e5 PZ |
645 | } |
646 | ||
17b5001b | 647 | tve->clk = devm_clk_get(dev, "tve"); |
fcbc51e5 | 648 | if (IS_ERR(tve->clk)) { |
17b5001b | 649 | dev_err(dev, "failed to get high speed tve clock: %ld\n", |
fcbc51e5 PZ |
650 | PTR_ERR(tve->clk)); |
651 | return PTR_ERR(tve->clk); | |
652 | } | |
653 | ||
654 | /* this is the IPU DI clock input selector, can be parented to tve_di */ | |
17b5001b | 655 | tve->di_sel_clk = devm_clk_get(dev, "di_sel"); |
fcbc51e5 | 656 | if (IS_ERR(tve->di_sel_clk)) { |
17b5001b | 657 | dev_err(dev, "failed to get ipu di mux clock: %ld\n", |
fcbc51e5 PZ |
658 | PTR_ERR(tve->di_sel_clk)); |
659 | return PTR_ERR(tve->di_sel_clk); | |
660 | } | |
661 | ||
662 | ret = tve_clk_init(tve, base); | |
663 | if (ret < 0) | |
664 | return ret; | |
665 | ||
666 | ret = regmap_read(tve->regmap, TVE_COM_CONF_REG, &val); | |
667 | if (ret < 0) { | |
17b5001b | 668 | dev_err(dev, "failed to read configuration register: %d\n", ret); |
fcbc51e5 PZ |
669 | return ret; |
670 | } | |
671 | if (val != 0x00100000) { | |
17b5001b | 672 | dev_err(dev, "configuration register default value indicates this is not a TVEv2\n"); |
fcbc51e5 | 673 | return -ENODEV; |
a22526e4 | 674 | } |
fcbc51e5 PZ |
675 | |
676 | /* disable cable detection for VGA mode */ | |
677 | ret = regmap_write(tve->regmap, TVE_CD_CONT_REG, 0); | |
678 | ||
1b3f7675 | 679 | ret = imx_tve_register(drm, tve); |
fcbc51e5 PZ |
680 | if (ret) |
681 | return ret; | |
682 | ||
17b5001b | 683 | dev_set_drvdata(dev, tve); |
fcbc51e5 PZ |
684 | |
685 | return 0; | |
686 | } | |
687 | ||
17b5001b RK |
688 | static void imx_tve_unbind(struct device *dev, struct device *master, |
689 | void *data) | |
fcbc51e5 | 690 | { |
17b5001b | 691 | struct imx_tve *tve = dev_get_drvdata(dev); |
fcbc51e5 | 692 | |
1b3f7675 RK |
693 | tve->connector.funcs->destroy(&tve->connector); |
694 | tve->encoder.funcs->destroy(&tve->encoder); | |
fcbc51e5 PZ |
695 | |
696 | if (!IS_ERR(tve->dac_reg)) | |
697 | regulator_disable(tve->dac_reg); | |
17b5001b | 698 | } |
fcbc51e5 | 699 | |
17b5001b RK |
700 | static const struct component_ops imx_tve_ops = { |
701 | .bind = imx_tve_bind, | |
702 | .unbind = imx_tve_unbind, | |
703 | }; | |
704 | ||
705 | static int imx_tve_probe(struct platform_device *pdev) | |
706 | { | |
707 | return component_add(&pdev->dev, &imx_tve_ops); | |
708 | } | |
709 | ||
710 | static int imx_tve_remove(struct platform_device *pdev) | |
711 | { | |
712 | component_del(&pdev->dev, &imx_tve_ops); | |
fcbc51e5 PZ |
713 | return 0; |
714 | } | |
715 | ||
716 | static const struct of_device_id imx_tve_dt_ids[] = { | |
717 | { .compatible = "fsl,imx53-tve", }, | |
718 | { /* sentinel */ } | |
719 | }; | |
720 | ||
721 | static struct platform_driver imx_tve_driver = { | |
722 | .probe = imx_tve_probe, | |
723 | .remove = imx_tve_remove, | |
724 | .driver = { | |
725 | .of_match_table = imx_tve_dt_ids, | |
726 | .name = "imx-tve", | |
727 | .owner = THIS_MODULE, | |
728 | }, | |
729 | }; | |
730 | ||
731 | module_platform_driver(imx_tve_driver); | |
732 | ||
733 | MODULE_DESCRIPTION("i.MX Television Encoder driver"); | |
734 | MODULE_AUTHOR("Philipp Zabel, Pengutronix"); | |
735 | MODULE_LICENSE("GPL"); | |
52db752c | 736 | MODULE_ALIAS("platform:imx-tve"); |