[deliverable/linux.git] / drivers / staging / imx-drm / ipu-v3 / ipu-dc.c

/*
 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * for more details.
 */

#include <linux/export.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/errno.h>
#include <linux/delay.h>
#include <linux/io.h>

#include "../imx-drm.h"
#include "imx-ipu-v3.h"
#include "ipu-prv.h"

#define DC_MAP_CONF_PTR(n)	(0x108 + ((n) & ~0x1) * 2)
#define DC_MAP_CONF_VAL(n)	(0x144 + ((n) & ~0x1) * 2)

#define DC_EVT_NF		0
#define DC_EVT_NL		1
#define DC_EVT_EOF		2
#define DC_EVT_NFIELD		3
#define DC_EVT_EOL		4
#define DC_EVT_EOFIELD		5
#define DC_EVT_NEW_ADDR		6
#define DC_EVT_NEW_CHAN		7
#define DC_EVT_NEW_DATA		8

#define DC_EVT_NEW_ADDR_W_0	0
#define DC_EVT_NEW_ADDR_W_1	1
#define DC_EVT_NEW_CHAN_W_0	2
#define DC_EVT_NEW_CHAN_W_1	3
#define DC_EVT_NEW_DATA_W_0	4
#define DC_EVT_NEW_DATA_W_1	5
#define DC_EVT_NEW_ADDR_R_0	6
#define DC_EVT_NEW_ADDR_R_1	7
#define DC_EVT_NEW_CHAN_R_0	8
#define DC_EVT_NEW_CHAN_R_1	9
#define DC_EVT_NEW_DATA_R_0	10
#define DC_EVT_NEW_DATA_R_1	11

#define DC_WR_CH_CONF		0x0
#define DC_WR_CH_ADDR		0x4
#define DC_RL_CH(evt)		(8 + ((evt) & ~0x1) * 2)

#define DC_GEN			0xd4
#define DC_DISP_CONF1(disp)	(0xd8 + (disp) * 4)
#define DC_DISP_CONF2(disp)	(0xe8 + (disp) * 4)
#define DC_STAT			0x1c8

#define WROD(lf)		(0x18 | ((lf) << 1))
#define WRG			0x01
#define WCLK			0xc9

#define SYNC_WAVE 0
#define NULL_WAVE (-1)

#define DC_GEN_SYNC_1_6_SYNC	(2 << 1)
#define DC_GEN_SYNC_PRIORITY_1	(1 << 7)

#define DC_WR_CH_CONF_WORD_SIZE_8		(0 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_16		(1 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_24		(2 << 0)
#define DC_WR_CH_CONF_WORD_SIZE_32		(3 << 0)
#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i)	(((i) & 0x1) << 3)
#define DC_WR_CH_CONF_DISP_ID_SERIAL		(2 << 3)
#define DC_WR_CH_CONF_DISP_ID_ASYNC		(3 << 4)
#define DC_WR_CH_CONF_FIELD_MODE		(1 << 9)
#define DC_WR_CH_CONF_PROG_TYPE_NORMAL		(4 << 5)
#define DC_WR_CH_CONF_PROG_TYPE_MASK		(7 << 5)
#define DC_WR_CH_CONF_PROG_DI_ID		(1 << 2)
#define DC_WR_CH_CONF_PROG_DISP_ID(i)		(((i) & 0x1) << 3)

#define IPU_DC_NUM_CHANNELS	10

struct ipu_dc_priv;

enum ipu_dc_map {
	IPU_DC_MAP_RGB24,
	IPU_DC_MAP_RGB565,
	IPU_DC_MAP_GBR24, /* TVEv2 */
};

struct ipu_dc {
	/* The display interface number assigned to this dc channel */
	unsigned int		di;
	void __iomem		*base;
	struct ipu_dc_priv	*priv;
	int			chno;
	bool			in_use;
};

struct ipu_dc_priv {
	void __iomem		*dc_reg;
	void __iomem		*dc_tmpl_reg;
	struct ipu_soc		*ipu;
	struct device		*dev;
	struct ipu_dc		channels[IPU_DC_NUM_CHANNELS];
	struct mutex		mutex;
};

static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
{
	u32 reg;

	reg = readl(dc->base + DC_RL_CH(event));
	reg &= ~(0xffff << (16 * (event & 0x1)));
	reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
	writel(reg, dc->base + DC_RL_CH(event));
}

static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
		int map, int wave, int glue, int sync, int stop)
{
	struct ipu_dc_priv *priv = dc->priv;
	u32 reg1, reg2;

	if (opcode == WCLK) {
		reg1 = (operand << 20) & 0xfff00000;
		reg2 = operand >> 12 | opcode << 1 | stop << 9;
	} else if (opcode == WRG) {
		reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
		reg2 = operand >> 17 | opcode << 7 | stop << 9;
	} else {
		reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
		reg2 = operand >> 12 | opcode << 4 | stop << 9;
	}
	writel(reg1, priv->dc_tmpl_reg + word * 8);
	writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
}

static int ipu_pixfmt_to_map(u32 fmt)
{
	switch (fmt) {
	case V4L2_PIX_FMT_RGB24:
		return IPU_DC_MAP_RGB24;
	case V4L2_PIX_FMT_RGB565:
		return IPU_DC_MAP_RGB565;
	case IPU_PIX_FMT_GBR24:
		return IPU_DC_MAP_GBR24;
	default:
		return -EINVAL;
	}
}

int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
		u32 pixel_fmt, u32 width)
{
	struct ipu_dc_priv *priv = dc->priv;
	u32 reg = 0, map;

	dc->di = ipu_di_get_num(di);

	map = ipu_pixfmt_to_map(pixel_fmt);
	if (map < 0) {
		dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
		return -EINVAL;
	}

	if (interlaced) {
		dc_link_event(dc, DC_EVT_NL, 0, 3);
		dc_link_event(dc, DC_EVT_EOL, 0, 2);
		dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);

		/* Init template microcode */
		dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
	} else {
		if (dc->di) {
			dc_link_event(dc, DC_EVT_NL, 2, 3);
			dc_link_event(dc, DC_EVT_EOL, 3, 2);
			dc_link_event(dc, DC_EVT_NEW_DATA, 4, 1);
			/* Init template microcode */
			dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
			dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 1);
			dc_write_tmpl(dc, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
		} else {
			dc_link_event(dc, DC_EVT_NL, 5, 3);
			dc_link_event(dc, DC_EVT_EOL, 6, 2);
			dc_link_event(dc, DC_EVT_NEW_DATA, 7, 1);
			/* Init template microcode */
			dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
			dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 1);
			dc_write_tmpl(dc, 7, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
		}
	}
	dc_link_event(dc, DC_EVT_NF, 0, 0);
	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
	dc_link_event(dc, DC_EVT_EOF, 0, 0);
	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);

	reg = readl(dc->base + DC_WR_CH_CONF);
	if (interlaced)
		reg |= DC_WR_CH_CONF_FIELD_MODE;
	else
		reg &= ~DC_WR_CH_CONF_FIELD_MODE;
	writel(reg, dc->base + DC_WR_CH_CONF);

	writel(0x0, dc->base + DC_WR_CH_ADDR);
	writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));

	ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);

	return 0;
}
EXPORT_SYMBOL_GPL(ipu_dc_init_sync);

void ipu_dc_enable_channel(struct ipu_dc *dc)
{
	int di;
	u32 reg;

	di = dc->di;

	reg = readl(dc->base + DC_WR_CH_CONF);
	reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
	writel(reg, dc->base + DC_WR_CH_CONF);
}
EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);

void ipu_dc_disable_channel(struct ipu_dc *dc)
{
	struct ipu_dc_priv *priv = dc->priv;
	u32 val;
	int irq = 0, timeout = 50;

	if (dc->chno == 1)
		irq = IPU_IRQ_DC_FC_1;
	else if (dc->chno == 5)
		irq = IPU_IRQ_DP_SF_END;
	else
		return;

	/* should wait for the interrupt here */
	mdelay(50);

	if (dc->di == 0)
		val = 0x00000002;
	else
		val = 0x00000020;

	/* Wait for DC triple buffer to empty */
	while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
		msleep(2);
		timeout -= 2;
		if (timeout <= 0)
			break;
	}

	val = readl(dc->base + DC_WR_CH_CONF);
	val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
	writel(val, dc->base + DC_WR_CH_CONF);
}
EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);

static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
		int byte_num, int offset, int mask)
{
	int ptr = map * 3 + byte_num;
	u32 reg;

	reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
	reg &= ~(0xffff << (16 * (ptr & 0x1)));
	reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
	writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));

	reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
	reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
	writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
}

static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
{
	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));

	writel(reg & ~(0xffff << (16 * (map & 0x1))),
		     priv->dc_reg + DC_MAP_CONF_PTR(map));
}

struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
{
	struct ipu_dc_priv *priv = ipu->dc_priv;
	struct ipu_dc *dc;

	if (channel >= IPU_DC_NUM_CHANNELS)
		return ERR_PTR(-ENODEV);

	dc = &priv->channels[channel];

	mutex_lock(&priv->mutex);

	if (dc->in_use) {
		mutex_unlock(&priv->mutex);
		return ERR_PTR(-EBUSY);
	}

	dc->in_use = 1;

	mutex_unlock(&priv->mutex);

	return dc;
}
EXPORT_SYMBOL_GPL(ipu_dc_get);

void ipu_dc_put(struct ipu_dc *dc)
{
	struct ipu_dc_priv *priv = dc->priv;

	mutex_lock(&priv->mutex);
	dc->in_use = 0;
	mutex_unlock(&priv->mutex);
}
EXPORT_SYMBOL_GPL(ipu_dc_put);

int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
		unsigned long base, unsigned long template_base)
{
	struct ipu_dc_priv *priv;
	static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
		0x78, 0, 0x94, 0xb4};
	int i;

	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
	if (!priv)
		return -ENOMEM;

	mutex_init(&priv->mutex);

	priv->dev = dev;
	priv->ipu = ipu;
	priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
	priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
	if (!priv->dc_reg || !priv->dc_tmpl_reg)
		return -ENOMEM;

	for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
		priv->channels[i].chno = i;
		priv->channels[i].priv = priv;
		priv->channels[i].base = priv->dc_reg + channel_offsets[i];
	}

	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
			DC_WR_CH_CONF_PROG_DI_ID,
			priv->channels[1].base + DC_WR_CH_CONF);
	writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
			priv->channels[5].base + DC_WR_CH_CONF);

	writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1, priv->dc_reg + DC_GEN);

	ipu->dc_priv = priv;

	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
			base, template_base);

	/* rgb24 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */

	/* rgb565 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */

	/* gbr24 */
	ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */

	return 0;
}

void ipu_dc_exit(struct ipu_soc *ipu)
{
}
Commit	Line	Data
aecfbdb1 SH	1	/*
	2	* Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
	3	* Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
	4	*
	5	* This program is free software; you can redistribute it and/or modify it
	6	* under the terms of the GNU General Public License as published by the
	7	* Free Software Foundation; either version 2 of the License, or (at your
	8	* option) any later version.
	9	*
	10	* This program is distributed in the hope that it will be useful, but
	11	* WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
	12	* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
	13	* for more details.
	14	*/
	15
	16	#include <linux/export.h>
	17	#include <linux/module.h>
	18	#include <linux/types.h>
	19	#include <linux/errno.h>
	20	#include <linux/delay.h>
	21	#include <linux/io.h>
	22
eeb14ec8	23	#include "../imx-drm.h"
aecfbdb1 SH	24	#include "imx-ipu-v3.h"
	25	#include "ipu-prv.h"
	26
	27	#define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
	28	#define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
	29
	30	#define DC_EVT_NF 0
	31	#define DC_EVT_NL 1
	32	#define DC_EVT_EOF 2
	33	#define DC_EVT_NFIELD 3
	34	#define DC_EVT_EOL 4
	35	#define DC_EVT_EOFIELD 5
	36	#define DC_EVT_NEW_ADDR 6
	37	#define DC_EVT_NEW_CHAN 7
	38	#define DC_EVT_NEW_DATA 8
	39
	40	#define DC_EVT_NEW_ADDR_W_0 0
	41	#define DC_EVT_NEW_ADDR_W_1 1
	42	#define DC_EVT_NEW_CHAN_W_0 2
	43	#define DC_EVT_NEW_CHAN_W_1 3
	44	#define DC_EVT_NEW_DATA_W_0 4
	45	#define DC_EVT_NEW_DATA_W_1 5
	46	#define DC_EVT_NEW_ADDR_R_0 6
	47	#define DC_EVT_NEW_ADDR_R_1 7
	48	#define DC_EVT_NEW_CHAN_R_0 8
	49	#define DC_EVT_NEW_CHAN_R_1 9
	50	#define DC_EVT_NEW_DATA_R_0 10
	51	#define DC_EVT_NEW_DATA_R_1 11
	52
	53	#define DC_WR_CH_CONF 0x0
	54	#define DC_WR_CH_ADDR 0x4
	55	#define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
	56
	57	#define DC_GEN 0xd4
	58	#define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
	59	#define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
	60	#define DC_STAT 0x1c8
	61
	62	#define WROD(lf) (0x18 \| ((lf) << 1))
	63	#define WRG 0x01
85eacb06	64	#define WCLK 0xc9
aecfbdb1 SH	65
aecfbdb1 SH	66	#define SYNC_WAVE 0
85eacb06	67	#define NULL_WAVE (-1)
aecfbdb1 SH	68
	69	#define DC_GEN_SYNC_1_6_SYNC (2 << 1)
	70	#define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
	71
	72	#define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
	73	#define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
	74	#define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
	75	#define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
	76	#define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
	77	#define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
	78	#define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
	79	#define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
	80	#define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
	81	#define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
	82	#define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
	83	#define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
	84
	85	#define IPU_DC_NUM_CHANNELS 10
	86
	87	struct ipu_dc_priv;
	88
	89	enum ipu_dc_map {
	90	IPU_DC_MAP_RGB24,
	91	IPU_DC_MAP_RGB565,
eeb14ec8	92	IPU_DC_MAP_GBR24, /* TVEv2 */
aecfbdb1 SH	93	};
	94
	95	struct ipu_dc {
	96	/* The display interface number assigned to this dc channel */
	97	unsigned int di;
	98	void __iomem *base;
	99	struct ipu_dc_priv *priv;
	100	int chno;
	101	bool in_use;
	102	};
	103
	104	struct ipu_dc_priv {
	105	void __iomem *dc_reg;
	106	void __iomem *dc_tmpl_reg;
	107	struct ipu_soc *ipu;
	108	struct device *dev;
	109	struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
	110	struct mutex mutex;
	111	};
	112
	113	static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
	114	{
	115	u32 reg;
	116
	117	reg = readl(dc->base + DC_RL_CH(event));
	118	reg &= ~(0xffff << (16 * (event & 0x1)));
	119	reg \|= ((addr << 8) \| priority) << (16 * (event & 0x1));
	120	writel(reg, dc->base + DC_RL_CH(event));
	121	}
	122
	123	static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
85eacb06	124	int map, int wave, int glue, int sync, int stop)
aecfbdb1 SH	125	{
aecfbdb1 SH	126	struct ipu_dc_priv *priv = dc->priv;
85eacb06 PZ	127	u32 reg1, reg2;
	128
	129	if (opcode == WCLK) {
	130	reg1 = (operand << 20) & 0xfff00000;
	131	reg2 = operand >> 12 \| opcode << 1 \| stop << 9;
	132	} else if (opcode == WRG) {
	133	reg1 = sync \| glue << 4 \| ++wave << 11 \| ((operand << 15) & 0xffff8000);
	134	reg2 = operand >> 17 \| opcode << 7 \| stop << 9;
	135	} else {
	136	reg1 = sync \| glue << 4 \| ++wave << 11 \| ++map << 15 \| ((operand << 20) & 0xfff00000);
	137	reg2 = operand >> 12 \| opcode << 4 \| stop << 9;
	138	}
	139	writel(reg1, priv->dc_tmpl_reg + word * 8);
	140	writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
aecfbdb1 SH	141	}
	142
	143	static int ipu_pixfmt_to_map(u32 fmt)
	144	{
	145	switch (fmt) {
	146	case V4L2_PIX_FMT_RGB24:
	147	return IPU_DC_MAP_RGB24;
	148	case V4L2_PIX_FMT_RGB565:
	149	return IPU_DC_MAP_RGB565;
eeb14ec8 PZ	150	case IPU_PIX_FMT_GBR24:
eeb14ec8 PZ	151	return IPU_DC_MAP_GBR24;
aecfbdb1 SH	152	default:
	153	return -EINVAL;
	154	}
	155	}
	156
	157	int ipu_dc_init_sync(struct ipu_dc dc, struct ipu_di di, bool interlaced,
	158	u32 pixel_fmt, u32 width)
	159	{
	160	struct ipu_dc_priv *priv = dc->priv;
	161	u32 reg = 0, map;
	162
	163	dc->di = ipu_di_get_num(di);
	164
	165	map = ipu_pixfmt_to_map(pixel_fmt);
	166	if (map < 0) {
	167	dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
	168	return -EINVAL;
	169	}
	170
	171	if (interlaced) {
	172	dc_link_event(dc, DC_EVT_NL, 0, 3);
	173	dc_link_event(dc, DC_EVT_EOL, 0, 2);
	174	dc_link_event(dc, DC_EVT_NEW_DATA, 0, 1);
	175
	176	/* Init template microcode */
85eacb06	177	dc_write_tmpl(dc, 0, WROD(0), 0, map, SYNC_WAVE, 0, 8, 1);
aecfbdb1 SH	178	} else {
	179	if (dc->di) {
	180	dc_link_event(dc, DC_EVT_NL, 2, 3);
	181	dc_link_event(dc, DC_EVT_EOL, 3, 2);
	182	dc_link_event(dc, DC_EVT_NEW_DATA, 4, 1);
	183	/* Init template microcode */
85eacb06 PZ	184	dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
	185	dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 1);
	186	dc_write_tmpl(dc, 4, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
aecfbdb1 SH	187	} else {
	188	dc_link_event(dc, DC_EVT_NL, 5, 3);
	189	dc_link_event(dc, DC_EVT_EOL, 6, 2);
	190	dc_link_event(dc, DC_EVT_NEW_DATA, 7, 1);
	191	/* Init template microcode */
85eacb06 PZ	192	dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
	193	dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 1);
	194	dc_write_tmpl(dc, 7, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
aecfbdb1 SH	195	}
	196	}
	197	dc_link_event(dc, DC_EVT_NF, 0, 0);
	198	dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
	199	dc_link_event(dc, DC_EVT_EOF, 0, 0);
	200	dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
	201	dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
	202	dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
	203
	204	reg = readl(dc->base + DC_WR_CH_CONF);
	205	if (interlaced)
	206	reg \|= DC_WR_CH_CONF_FIELD_MODE;
	207	else
	208	reg &= ~DC_WR_CH_CONF_FIELD_MODE;
	209	writel(reg, dc->base + DC_WR_CH_CONF);
	210
	211	writel(0x0, dc->base + DC_WR_CH_ADDR);
	212	writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
	213
	214	ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
	215
	216	return 0;
	217	}
	218	EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
	219
	220	void ipu_dc_enable_channel(struct ipu_dc *dc)
	221	{
	222	int di;
	223	u32 reg;
	224
	225	di = dc->di;
	226
	227	reg = readl(dc->base + DC_WR_CH_CONF);
	228	reg \|= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
	229	writel(reg, dc->base + DC_WR_CH_CONF);
	230	}
	231	EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
	232
	233	void ipu_dc_disable_channel(struct ipu_dc *dc)
	234	{
	235	struct ipu_dc_priv *priv = dc->priv;
	236	u32 val;
	237	int irq = 0, timeout = 50;
	238
	239	if (dc->chno == 1)
	240	irq = IPU_IRQ_DC_FC_1;
	241	else if (dc->chno == 5)
	242	irq = IPU_IRQ_DP_SF_END;
	243	else
	244	return;
	245
	246	/* should wait for the interrupt here */
	247	mdelay(50);
	248
	249	if (dc->di == 0)
	250	val = 0x00000002;
	251	else
	252	val = 0x00000020;
	253
	254	/* Wait for DC triple buffer to empty */
	255	while ((readl(priv->dc_reg + DC_STAT) & val) != val) {
	256	msleep(2);
	257	timeout -= 2;
	258	if (timeout <= 0)
259	break;
260	}
261
262	val = readl(dc->base + DC_WR_CH_CONF);
263	val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
264	writel(val, dc->base + DC_WR_CH_CONF);
265	}
266	EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
267
268	static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
269	int byte_num, int offset, int mask)
270	{
271	int ptr = map * 3 + byte_num;
272	u32 reg;
273
274	reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
275	reg &= ~(0xffff << (16 * (ptr & 0x1)));
276	reg \|= ((offset << 8) \| mask) << (16 * (ptr & 0x1));
277	writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
278
279	reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
280	reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
281	reg \|= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
282	writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
283	}
284
285	static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
286	{
287	u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
288
289	writel(reg & ~(0xffff << (16 * (map & 0x1))),
290	priv->dc_reg + DC_MAP_CONF_PTR(map));
291	}
292
293	struct ipu_dc ipu_dc_get(struct ipu_soc ipu, int channel)
294	{
295	struct ipu_dc_priv *priv = ipu->dc_priv;
296	struct ipu_dc *dc;
297
298	if (channel >= IPU_DC_NUM_CHANNELS)
299	return ERR_PTR(-ENODEV);
300
301	dc = &priv->channels[channel];
302
303	mutex_lock(&priv->mutex);
304
305	if (dc->in_use) {
306	mutex_unlock(&priv->mutex);
307	return ERR_PTR(-EBUSY);
308	}
309
310	dc->in_use = 1;
311
312	mutex_unlock(&priv->mutex);
313
314	return dc;
315	}
316	EXPORT_SYMBOL_GPL(ipu_dc_get);
317
318	void ipu_dc_put(struct ipu_dc *dc)
319	{
320	struct ipu_dc_priv *priv = dc->priv;
321
322	mutex_lock(&priv->mutex);
323	dc->in_use = 0;
324	mutex_unlock(&priv->mutex);
325	}
326	EXPORT_SYMBOL_GPL(ipu_dc_put);
327
328	int ipu_dc_init(struct ipu_soc ipu, struct device dev,
329	unsigned long base, unsigned long template_base)
330	{
331	struct ipu_dc_priv *priv;
332	static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
333	0x78, 0, 0x94, 0xb4};
334	int i;
335
336	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
337	if (!priv)
338	return -ENOMEM;
339
340	mutex_init(&priv->mutex);
341
342	priv->dev = dev;
343	priv->ipu = ipu;
344	priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
345	priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
346	if (!priv->dc_reg \|\| !priv->dc_tmpl_reg)
347	return -ENOMEM;
348
349	for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
350	priv->channels[i].chno = i;
351	priv->channels[i].priv = priv;
352	priv->channels[i].base = priv->dc_reg + channel_offsets[i];
353	}
354
355	writel(DC_WR_CH_CONF_WORD_SIZE_24 \| DC_WR_CH_CONF_DISP_ID_PARALLEL(1) \|
356	DC_WR_CH_CONF_PROG_DI_ID,
357	priv->channels[1].base + DC_WR_CH_CONF);
358	writel(DC_WR_CH_CONF_WORD_SIZE_24 \| DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
359	priv->channels[5].base + DC_WR_CH_CONF);
360
361	writel(DC_GEN_SYNC_1_6_SYNC \| DC_GEN_SYNC_PRIORITY_1, priv->dc_reg + DC_GEN);
362
363	ipu->dc_priv = priv;
364
365	dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
366	base, template_base);
367
368	/* rgb24 */
369	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
370	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
371	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
372	ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
373
374	/* rgb565 */
375	ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
376	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
377	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
378	ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
379
eeb14ec8 PZ	380	/* gbr24 */
	381	ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
	382	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
	383	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
	384	ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
	385
aecfbdb1 SH	386	return 0;
	387	}
	388
	389	void ipu_dc_exit(struct ipu_soc *ipu)
	390	{
	391	}